OpenCores
URL https://opencores.org/ocsvn/pcie_sg_dma/pcie_sg_dma/trunk

Subversion Repositories pcie_sg_dma

[/] [pcie_sg_dma/] [branches/] [Virtex6/] [ML605_ISE12.3/] [MyUserLogic/] [top_level_1_PCIe_UserLogic_00_USER_LOGIC/] [sysgen/] [synopsis.2] - Blame information for rev 11

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Line No. Rev Author Line
1 11 barabba 
{
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        'data_in_x9' => 'data_in_x9_net',
7167 
        'data_out' => 'data_out_net',
7168 
        'data_out_x0' => 'data_out_x0_net',
7169 
        'data_out_x1' => 'data_out_x1_net',
7170 
        'data_out_x10' => 'data_out_x10_net',
7171 
        'data_out_x11' => 'data_out_x11_net',
7172 
        'data_out_x12' => 'data_out_x12_net',
7173 
        'data_out_x13' => 'data_out_x13_net',
7174 
        'data_out_x14' => 'data_out_x14_net',
7175 
        'data_out_x15' => 'data_out_x15_net',
7176 
        'data_out_x16' => 'data_out_x16_net',
7177 
        'data_out_x17' => 'data_out_x17_net',
7178 
        'data_out_x18' => 'data_out_x18_net',
7179 
        'data_out_x19' => 'data_out_x19_net',
7180 
        'data_out_x2' => 'data_out_x2_net',
7181 
        'data_out_x20' => 'data_out_x20_net',
7182 
        'data_out_x21' => 'data_out_x21_net',
7183 
        'data_out_x22' => 'data_out_x22_net',
7184 
        'data_out_x23' => 'data_out_x23_net',
7185 
        'data_out_x24' => 'data_out_x24_net',
7186 
        'data_out_x25' => 'data_out_x25_net',
7187 
        'data_out_x26' => 'data_out_x26_net',
7188 
        'data_out_x27' => 'data_out_x27_net',
7189 
        'data_out_x28' => 'data_out_x28_net',
7190 
        'data_out_x3' => 'data_out_x3_net',
7191 
        'data_out_x6' => 'data_out_x6_net',
7192 
        'data_out_x7' => 'data_out_x7_net',
7193 
        'data_out_x8' => 'data_out_x8_net',
7194 
        'data_out_x9' => 'data_out_x9_net',
7195 
        'en' => 'constant6_op_net_x0',
7196 
        'en_x0' => 'constant6_op_net_x1',
7197 
        'en_x1' => 'constant6_op_net_x2',
7198 
        'en_x10' => 'constant6_op_net_x11',
7199 
        'en_x11' => 'constant6_op_net_x12',
7200 
        'en_x12' => 'constant6_op_net_x13',
7201 
        'en_x13' => 'constant6_op_net_x14',
7202 
        'en_x14' => 'constant6_op_net_x15',
7203 
        'en_x15' => 'constant6_op_net_x16',
7204 
        'en_x16' => 'constant6_op_net_x17',
7205 
        'en_x17' => 'constant6_op_net_x18',
7206 
        'en_x18' => 'constant6_op_net_x19',
7207 
        'en_x19' => 'constant6_op_net_x20',
7208 
        'en_x2' => 'constant6_op_net_x3',
7209 
        'en_x20' => 'constant6_op_net_x21',
7210 
        'en_x21' => 'constant6_op_net_x22',
7211 
        'en_x22' => 'constant6_op_net_x23',
7212 
        'en_x23' => 'constant6_op_net_x24',
7213 
        'en_x24' => 'constant6_op_net_x25',
7214 
        'en_x25' => 'constant6_op_net_x26',
7215 
        'en_x26' => 'constant6_op_net_x27',
7216 
        'en_x3' => 'constant6_op_net_x4',
7217 
        'en_x4' => 'constant6_op_net_x5',
7218 
        'en_x5' => 'constant6_op_net_x6',
7219 
        'en_x6' => 'constant6_op_net_x7',
7220 
        'en_x7' => 'constant6_op_net_x8',
7221 
        'en_x8' => 'constant6_op_net_x9',
7222 
        'en_x9' => 'constant6_op_net_x10',
7223 
        'fifo_rd_count' => 'fifo_rd_count_net',
7224 
        'fifo_rd_dout' => 'fifo_rd_dout_net',
7225 
        'fifo_rd_empty' => 'fifo_rd_empty_net',
7226 
        'fifo_rd_en' => 'fifo_rd_en_net',
7227 
        'fifo_rd_pempty' => 'fifo_rd_pempty_net',
7228 
        'fifo_rd_valid' => 'fifo_rd_valid_net',
7229 
        'fifo_wr_count' => 'fifo_wr_count_net',
7230 
        'fifo_wr_din' => 'fifo_wr_din_net',
7231 
        'fifo_wr_en' => 'fifo_wr_en_net',
7232 
        'fifo_wr_full' => 'fifo_wr_full_net',
7233 
        'fifo_wr_pfull' => 'fifo_wr_pfull_net',
7234 
        'rst_i' => 'rst_i_net',
7235 
        'rst_o' => 'rst_o_net',
7236 
        'user_int_1o' => 'user_int_1o_net',
7237 
        'user_int_2o' => 'user_int_2o_net',
7238 
        'user_int_3o' => 'user_int_3o_net',
7239 
      },
7240 
      'entity' => {
7241 
        'attributes' => {
7242 
          'entityAlreadyNetlisted' => 1,
7243 
          'hdlKind' => 'vhdl',
7244 
          'isDesign' => 1,
7245 
          'simulinkName' => 'USER_LOGIC',
7246 
        },
7247 
        'entityName' => 'user_logic',
7248 
        'ports' => {
7249 
          'bram_rd_addr' => {
7250 
            'attributes' => {
7251 
              'bin_pt' => 0,
7252 
              'inputFile' => 'pcie_userlogic_00_user_logic_bram_rd_addr.dat',
7253 
              'is_floating_block' => 1,
7254 
              'is_gateway_port' => 1,
7255 
              'must_be_hdl_vector' => 1,
7256 
              'period' => 1,
7257 
              'port_id' => 15,
7258 
              'simulinkName' => 'USER_LOGIC/BRAM_rd_addr',
7259 
              'source_block' => 'USER_LOGIC',
7260 
              'timingConstraint' => 'none',
7261 
              'type' => 'UFix_12_0',
7262 
            },
7263 
            'direction' => 'out',
7264 
            'hdlType' => 'std_logic_vector(11 downto 0)',
7265 
            'width' => 12,
7266 
          },
7267 
          'bram_rd_dout' => {
7268 
            'attributes' => {
7269 
              'bin_pt' => 0,
7270 
              'inputFile' => 'pcie_userlogic_00_user_logic_bram_rd_dout.dat',
7271 
              'is_floating_block' => 1,
7272 
              'is_gateway_port' => 1,
7273 
              'must_be_hdl_vector' => 1,
7274 
              'period' => 1,
7275 
              'port_id' => 0,
7276 
              'simulinkName' => 'USER_LOGIC/BRAM_rd_dout',
7277 
              'source_block' => 'USER_LOGIC',
7278 
              'timingConstraint' => 'none',
7279 
              'type' => 'UFix_64_0',
7280 
            },
7281 
            'direction' => 'in',
7282 
            'hdlType' => 'std_logic_vector(63 downto 0)',
7283 
            'width' => 64,
7284 
          },
7285 
          'bram_wr_addr' => {
7286 
            'attributes' => {
7287 
              'bin_pt' => 0,
7288 
              'inputFile' => 'pcie_userlogic_00_user_logic_bram_wr_addr.dat',
7289 
              'is_floating_block' => 1,
7290 
              'is_gateway_port' => 1,
7291 
              'must_be_hdl_vector' => 1,
7292 
              'period' => 1,
7293 
              'port_id' => 16,
7294 
              'simulinkName' => 'USER_LOGIC/BRAM_wr_addr',
7295 
              'source_block' => 'USER_LOGIC',
7296 
              'timingConstraint' => 'none',
7297 
              'type' => 'UFix_12_0',
7298 
            },
7299 
            'direction' => 'out',
7300 
            'hdlType' => 'std_logic_vector(11 downto 0)',
7301 
            'width' => 12,
7302 
          },
7303 
          'bram_wr_din' => {
7304 
            'attributes' => {
7305 
              'bin_pt' => 0,
7306 
              'inputFile' => 'pcie_userlogic_00_user_logic_bram_wr_din.dat',
7307 
              'is_floating_block' => 1,
7308 
              'is_gateway_port' => 1,
7309 
              'must_be_hdl_vector' => 1,
7310 
              'period' => 1,
7311 
              'port_id' => 18,
7312 
              'simulinkName' => 'USER_LOGIC/BRAM_wr_din',
7313 
              'source_block' => 'USER_LOGIC',
7314 
              'timingConstraint' => 'none',
7315 
              'type' => 'UFix_64_0',
7316 
            },
7317 
            'direction' => 'out',
7318 
            'hdlType' => 'std_logic_vector(63 downto 0)',
7319 
            'width' => 64,
7320 
          },
7321 
          'bram_wr_en' => {
7322 
            'attributes' => {
7323 
              'bin_pt' => 0,
7324 
              'inputFile' => 'pcie_userlogic_00_user_logic_bram_wr_en.dat',
7325 
              'is_floating_block' => 1,
7326 
              'is_gateway_port' => 1,
7327 
              'must_be_hdl_vector' => 1,
7328 
              'period' => 1,
7329 
              'port_id' => 23,
7330 
              'simulinkName' => 'USER_LOGIC/BRAM_wr_en',
7331 
              'source_block' => 'USER_LOGIC',
7332 
              'timingConstraint' => 'none',
7333 
              'type' => 'UFix_8_0',
7334 
            },
7335 
            'direction' => 'out',
7336 
            'hdlType' => 'std_logic_vector(7 downto 0)',
7337 
            'width' => 8,
7338 
          },
7339 
          'ce_1' => {
7340 
            'attributes' => {
7341 
              'domain' => '',
7342 
              'group' => 1,
7343 
              'isCe' => 1,
7344 
              'is_subsys_port' => 1,
7345 
              'period' => 1,
7346 
              'subsys_port_index' => 0,
7347 
              'type' => 'logic',
7348 
            },
7349 
            'direction' => 'in',
7350 
            'hdlType' => 'std_logic',
7351 
            'width' => 1,
7352 
          },
7353 
          'clk_1' => {
7354 
            'attributes' => {
7355 
              'domain' => '',
7356 
              'group' => 1,
7357 
              'isClk' => 1,
7358 
              'is_subsys_port' => 1,
7359 
              'period' => 1,
7360 
              'subsys_port_index' => 0,
7361 
              'type' => 'logic',
7362 
            },
7363 
            'direction' => 'in',
7364 
            'hdlType' => 'std_logic',
7365 
            'width' => 1,
7366 
          },
7367 
          'data_in' => {
7368 
            'attributes' => {
7369 
              'bin_pt' => 0,
7370 
              'is_floating_block' => 1,
7371 
              'must_be_hdl_vector' => 1,
7372 
              'period' => 1,
7373 
              'port_id' => 17,
7374 
              'simulinkName' => 'USER_LOGIC/tx_en_in2',
7375 
              'type' => 'UFix_32_0',
7376 
            },
7377 
            'direction' => 'out',
7378 
            'hdlType' => 'std_logic_vector(31 downto 0)',
7379 
            'width' => 32,
7380 
          },
7381 
          'data_in_x0' => {
7382 
            'attributes' => {
7383 
              'bin_pt' => 0,
7384 
              'is_floating_block' => 1,
7385 
              'must_be_hdl_vector' => 1,
7386 
              'period' => 1,
7387 
              'port_id' => 1,
7388 
              'simulinkName' => 'USER_LOGIC/tx_en_in1',
7389 
              'type' => 'Bool',
7390 
            },
7391 
            'direction' => 'out',
7392 
            'hdlType' => 'std_logic',
7393 
            'width' => 1,
7394 
          },
7395 
          'data_in_x1' => {
7396 
            'attributes' => {
7397 
              'bin_pt' => 0,
7398 
              'is_floating_block' => 1,
7399 
              'must_be_hdl_vector' => 1,
7400 
              'period' => 1,
7401 
              'port_id' => 36,
7402 
              'simulinkName' => 'USER_LOGIC/tx_en_in96',
7403 
              'type' => 'Bool',
7404 
            },
7405 
            'direction' => 'out',
7406 
            'hdlType' => 'std_logic',
7407 
            'width' => 1,
7408 
          },
7409 
          'data_in_x10' => {
7410 
            'attributes' => {
7411 
              'bin_pt' => 0,
7412 
              'is_floating_block' => 1,
7413 
              'must_be_hdl_vector' => 1,
7414 
              'period' => 1,
7415 
              'port_id' => 33,
7416 
              'simulinkName' => 'USER_LOGIC/tx_en_in91',
7417 
              'type' => 'UFix_32_0',
7418 
            },
7419 
            'direction' => 'out',
7420 
            'hdlType' => 'std_logic_vector(31 downto 0)',
7421 
            'width' => 32,
7422 
          },
7423 
          'data_in_x11' => {
7424 
            'attributes' => {
7425 
              'bin_pt' => 0,
7426 
              'is_floating_block' => 1,
7427 
              'must_be_hdl_vector' => 1,
7428 
              'period' => 1,
7429 
              'port_id' => 21,
7430 
              'simulinkName' => 'USER_LOGIC/tx_en_in33',
7431 
              'type' => 'UFix_32_0',
7432 
            },
7433 
            'direction' => 'out',
7434 
            'hdlType' => 'std_logic_vector(31 downto 0)',
7435 
            'width' => 32,
7436 
          },
7437 
          'data_in_x12' => {
7438 
            'attributes' => {
7439 
              'bin_pt' => 0,
7440 
              'is_floating_block' => 1,
7441 
              'must_be_hdl_vector' => 1,
7442 
              'period' => 1,
7443 
              'port_id' => 6,
7444 
              'simulinkName' => 'USER_LOGIC/tx_en_in113',
7445 
              'type' => 'Bool',
7446 
            },
7447 
            'direction' => 'out',
7448 
            'hdlType' => 'std_logic',
7449 
            'width' => 1,
7450 
          },
7451 
          'data_in_x13' => {
7452 
            'attributes' => {
7453 
              'bin_pt' => 0,
7454 
              'is_floating_block' => 1,
7455 
              'must_be_hdl_vector' => 1,
7456 
              'period' => 1,
7457 
              'port_id' => 8,
7458 
              'simulinkName' => 'USER_LOGIC/tx_en_in115',
7459 
              'type' => 'UFix_32_0',
7460 
            },
7461 
            'direction' => 'out',
7462 
            'hdlType' => 'std_logic_vector(31 downto 0)',
7463 
            'width' => 32,
7464 
          },
7465 
          'data_in_x14' => {
7466 
            'attributes' => {
7467 
              'bin_pt' => 0,
7468 
              'is_floating_block' => 1,
7469 
              'must_be_hdl_vector' => 1,
7470 
              'period' => 1,
7471 
              'port_id' => 7,
7472 
              'simulinkName' => 'USER_LOGIC/tx_en_in114',
7473 
              'type' => 'Bool',
7474 
            },
7475 
            'direction' => 'out',
7476 
            'hdlType' => 'std_logic',
7477 
            'width' => 1,
7478 
          },
7479 
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7480 
            'attributes' => {
7481 
              'bin_pt' => 0,
7482 
              'is_floating_block' => 1,
7483 
              'must_be_hdl_vector' => 1,
7484 
              'period' => 1,
7485 
              'port_id' => 9,
7486 
              'simulinkName' => 'USER_LOGIC/tx_en_in118',
7487 
              'type' => 'UFix_32_0',
7488 
            },
7489 
            'direction' => 'out',
7490 
            'hdlType' => 'std_logic_vector(31 downto 0)',
7491 
            'width' => 32,
7492 
          },
7493 
          'data_in_x16' => {
7494 
            'attributes' => {
7495 
              'bin_pt' => 0,
7496 
              'is_floating_block' => 1,
7497 
              'must_be_hdl_vector' => 1,
7498 
              'period' => 1,
7499 
              'port_id' => 10,
7500 
              'simulinkName' => 'USER_LOGIC/tx_en_in121',
7501 
              'type' => 'Bool',
7502 
            },
7503 
            'direction' => 'out',
7504 
            'hdlType' => 'std_logic',
7505 
            'width' => 1,
7506 
          },
7507 
          'data_in_x17' => {
7508 
            'attributes' => {
7509 
              'bin_pt' => 0,
7510 
              'is_floating_block' => 1,
7511 
              'must_be_hdl_vector' => 1,
7512 
              'period' => 1,
7513 
              'port_id' => 11,
7514 
              'simulinkName' => 'USER_LOGIC/tx_en_in122',
7515 
              'type' => 'UFix_32_0',
7516 
            },
7517 
            'direction' => 'out',
7518 
            'hdlType' => 'std_logic_vector(31 downto 0)',
7519 
            'width' => 32,
7520 
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7521 
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7522 
            'attributes' => {
7523 
              'bin_pt' => 0,
7524 
              'is_floating_block' => 1,
7525 
              'must_be_hdl_vector' => 1,
7526 
              'period' => 1,
7527 
              'port_id' => 12,
7528 
              'simulinkName' => 'USER_LOGIC/tx_en_in125',
7529 
              'type' => 'Bool',
7530 
            },
7531 
            'direction' => 'out',
7532 
            'hdlType' => 'std_logic',
7533 
            'width' => 1,
7534 
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7535 
          'data_in_x19' => {
7536 
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7537 
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7538 
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7539 
              'must_be_hdl_vector' => 1,
7540 
              'period' => 1,
7541 
              'port_id' => 13,
7542 
              'simulinkName' => 'USER_LOGIC/tx_en_in126',
7543 
              'type' => 'UFix_32_0',
7544 
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7545 
            'direction' => 'out',
7546 
            'hdlType' => 'std_logic_vector(31 downto 0)',
7547 
            'width' => 32,
7548 
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7549 
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7550 
            'attributes' => {
7551 
              'bin_pt' => 0,
7552 
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7553 
              'must_be_hdl_vector' => 1,
7554 
              'period' => 1,
7555 
              'port_id' => 37,
7556 
              'simulinkName' => 'USER_LOGIC/tx_en_in97',
7557 
              'type' => 'Bool',
7558 
            },
7559 
            'direction' => 'out',
7560 
            'hdlType' => 'std_logic',
7561 
            'width' => 1,
7562 
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7563 
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7564 
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7565 
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7566 
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7567 
              'must_be_hdl_vector' => 1,
7568 
              'period' => 1,
7569 
              'port_id' => 2,
7570 
              'simulinkName' => 'USER_LOGIC/tx_en_in10',
7571 
              'type' => 'UFix_32_0',
7572 
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7573 
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7574 
            'hdlType' => 'std_logic_vector(31 downto 0)',
7575 
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7576 
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7577 
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7578 
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7579 
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7580 
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7581 
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7582 
              'period' => 1,
7583 
              'port_id' => 34,
7584 
              'simulinkName' => 'USER_LOGIC/tx_en_in94',
7585 
              'type' => 'Bool',
7586 
            },
7587 
            'direction' => 'out',
7588 
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7589 
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7590 
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7591 
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7592 
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7593 
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7594 
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7595 
              'must_be_hdl_vector' => 1,
7596 
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7597 
              'port_id' => 29,
7598 
              'simulinkName' => 'USER_LOGIC/tx_en_in7',
7599 
              'type' => 'Bool',
7600 
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7601 
            'direction' => 'out',
7602 
            'hdlType' => 'std_logic',
7603 
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7604 
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7605 
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7606 
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7607 
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7608 
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7609 
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7610 
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7611 
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7612 
              'simulinkName' => 'USER_LOGIC/tx_en_in50',
7613 
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7614 
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7615 
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7616 
            'hdlType' => 'std_logic_vector(31 downto 0)',
7617 
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7618 
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7619 
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7620 
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7621 
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7622 
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7623 
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7624 
              'period' => 1,
7625 
              'port_id' => 35,
7626 
              'simulinkName' => 'USER_LOGIC/tx_en_in95',
7627 
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7628 
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7629 
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7630 
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7631 
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7632 
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7633 
          'data_in_x25' => {
7634 
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7635 
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7636 
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7637 
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7638 
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7639 
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}

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