Subversion Repositories pcie_sg_dma

#

# Created by System Generator     Thu Mar 22 15:51:30 2012

#

# Note: This file is produced automatically, and will be overwritten the next

# time you press "Generate" in System Generator.

#

source SgIseProject.tcl

namespace eval ::xilinx::dsptool::iseproject::param {

    set Project {user_logic_cw}

    set Family {Virtex6}

    set Device {xc6vlx240t}

    set Package {ff784}

    set Speed {-3}

    set HDLLanguage {vhdl}

    set SynthesisTool {XST}

    set Simulator {Modelsim-SE}

    set ReadCores {False}

    set MapEffortLevel {High}

    set ParEffortLevel {High}

    set Frequency {200}

    set ProjectFiles {

        {{user_logic_cw.vhd} -view All}

        {{user_logic.vhd} -view All}

        {{user_logic_cw.ucf}}

        {{C:\Temp\Xilinx PCI Express\pcie-v6-ml605_ISE12_OpenCores\MySysGen\PCIe_UserLogic_00.mdl}}

    }

    set TopLevelModule {user_logic_cw}

    set SynthesisConstraintsFile {user_logic_cw.xcf}

    set ImplementationStopView {Structural}

    set ProjectGenerator {SysgenDSP}

}

::xilinx::dsptool::iseproject::create