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[/] [pcie_sg_dma/] [branches/] [Virtex6/] [ML605_ISE12.3/] [Registers.vhd] - Blame information for rev 11

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Line No. Rev Author Line
1 11 barabba 
----------------------------------------------------------------------------------
2 
-- Company:
3 
-- Engineer:
4 
--
5 
-- Design Name:
6 
-- Module Name:    Regs_Group - Behavioral
7 
-- Project Name:
8 
-- Target Devices:
9 
-- Tool versions:
10 
-- Description:
11 
--
12 
-- Dependencies:
13 
--
14 
-- Revision:
15 
--
16 
-- Revision 1.10 - Readability improved by FOR-LOOP used  19.03.2007
17 
--
18 
-- Revision 1.00 - File Created  06.02.2007
19 
--
20 
-- Additional Comments:
21 
--
22 
----------------------------------------------------------------------------------
23 
 
24 
library IEEE;
25 
use IEEE.STD_LOGIC_1164.ALL;
26 
use IEEE.STD_LOGIC_ARITH.ALL;
27 
use IEEE.STD_LOGIC_UNSIGNED.ALL;
28 
 
29 
 
30 
library work;
31 
use work.abb64Package.all;
32 
 
33 
---- Uncomment the following library declaration if instantiating
34 
---- any Xilinx primitives in this code.
35 
library UNISIM;
36 
use UNISIM.VComponents.all;
37 
 
38 
entity Regs_Group is
39 
    port (
40 
 
41 
      -- DCB protocol interface
42 
      protocol_link_act        : IN  std_logic_vector(2-1 downto 0);
43 
      protocol_rst             : OUT std_logic;
44 
 
45 
      -- Fabric side: CTL Rx
46 
      ctl_rv                   : OUT std_logic;
47 
      ctl_rd                   : OUT std_logic_vector(C_DBUS_WIDTH/2-1 downto 0);
48 
 
49 
      -- Fabric side: CTL Tx
50 
      ctl_ttake                : OUT std_logic;
51 
      ctl_tv                   : IN  std_logic;
52 
      ctl_td                   : IN  std_logic_vector(C_DBUS_WIDTH/2-1 downto 0);
53 
      ctl_tstop                : OUT std_logic;
54 
 
55 
      ctl_reset                : OUT std_logic;
56 
      ctl_status               : IN  std_logic_vector(C_DBUS_WIDTH/2-1 downto 0);
57 
 
58 
      -- Fabric side: DLM Rx
59 
      dlm_tv                   : OUT std_logic;
60 
      dlm_td                   : OUT std_logic_vector(C_DBUS_WIDTH/2-1 downto 0);
61 
 
62 
      -- Fabric side: DLM Tx
63 
      dlm_rv                   : IN  std_logic;
64 
      dlm_rd                   : IN  std_logic_vector(C_DBUS_WIDTH/2-1 downto 0);
65 
 
66 
      -- Event Buffer status + reset
67 
      eb_FIFO_Status           : IN  std_logic_vector(C_DBUS_WIDTH-1 downto 0);
68 
      eb_FIFO_Rst              : OUT std_logic;
69 
      eb_FIFO_ow               : IN  std_logic;
70 
           H2B_FIFO_Status                       : IN std_logic_VECTOR(C_DBUS_WIDTH-1 downto 0);
71 
           B2H_FIFO_Status                       : IN std_logic_VECTOR(C_DBUS_WIDTH-1 downto 0);
72 
 
73 
      -- Write interface
74 
      Regs_WrEnA               : IN  std_logic;
75 
      Regs_WrMaskA             : IN  std_logic_vector(2-1 downto 0);
76 
      Regs_WrAddrA             : IN  std_logic_vector(C_EP_AWIDTH-1 downto 0);
77 
      Regs_WrDinA              : IN  std_logic_vector(C_DBUS_WIDTH-1 downto 0);
78 
 
79 
      Regs_WrEnB               : IN  std_logic;
80 
      Regs_WrMaskB             : IN  std_logic_vector(2-1 downto 0);
81 
      Regs_WrAddrB             : IN  std_logic_vector(C_EP_AWIDTH-1 downto 0);
82 
      Regs_WrDinB              : IN  std_logic_vector(C_DBUS_WIDTH-1 downto 0);
83 
 
84 
      -- Register Read interface
85 
      Regs_RdAddr              : IN  std_logic_vector(C_EP_AWIDTH-1 downto 0);
86 
      Regs_RdQout              : OUT std_logic_vector(C_DBUS_WIDTH-1 downto 0);
87 
 
88 
      -- Downstream DMA transferred bytes count up
89 
      ds_DMA_Bytes_Add         : IN  std_logic;
90 
      ds_DMA_Bytes             : IN  std_logic_vector(C_TLP_FLD_WIDTH_OF_LENG+2 downto 0);
91 
 
92 
     -- Registers to/from Downstream Engine
93 
      DMA_ds_PA                : OUT std_logic_vector(C_DBUS_WIDTH-1 downto 0);
94 
      DMA_ds_HA                : OUT std_logic_vector(C_DBUS_WIDTH-1 downto 0);
95 
      DMA_ds_BDA               : OUT std_logic_vector(C_DBUS_WIDTH-1 downto 0);
96 
      DMA_ds_Length            : OUT std_logic_vector(C_DBUS_WIDTH-1 downto 0);
97 
      DMA_ds_Control           : OUT std_logic_vector(C_DBUS_WIDTH-1 downto 0);
98 
      dsDMA_BDA_eq_Null        : OUT std_logic;      -- obsolete
99 
      DMA_ds_Status            : IN  std_logic_vector(C_DBUS_WIDTH-1 downto 0);
100 
      DMA_ds_Done              : IN  std_logic;
101 
      DMA_ds_Tout              : IN  std_logic;
102 
 
103 
      -- Calculation in advance, for better timing
104 
      dsHA_is_64b              : OUT std_logic;
105 
      dsBDA_is_64b             : OUT std_logic;
106 
 
107 
      -- Calculation in advance, for better timing
108 
      dsLeng_Hi19b_True        : OUT std_logic;
109 
      dsLeng_Lo7b_True         : OUT std_logic;
110 
 
111 
      -- Downstream Control Signals
112 
      dsDMA_Start              : OUT std_logic;
113 
      dsDMA_Stop               : OUT std_logic;
114 
      dsDMA_Start2             : OUT std_logic;
115 
      dsDMA_Stop2              : OUT std_logic;
116 
      dsDMA_Channel_Rst        : OUT std_logic;
117 
      dsDMA_Cmd_Ack            : IN  std_logic;
118 
 
119 
 
120 
      -- Upstream DMA transferred bytes count up
121 
      us_DMA_Bytes_Add         : IN  std_logic;
122 
      us_DMA_Bytes             : IN  std_logic_vector(C_TLP_FLD_WIDTH_OF_LENG+2 downto 0);
123 
 
124 
      -- Registers to/from Upstream Engine
125 
      DMA_us_PA                : OUT std_logic_vector(C_DBUS_WIDTH-1 downto 0);
126 
      DMA_us_HA                : OUT std_logic_vector(C_DBUS_WIDTH-1 downto 0);
127 
      DMA_us_BDA               : OUT std_logic_vector(C_DBUS_WIDTH-1 downto 0);
128 
      DMA_us_Length            : OUT std_logic_vector(C_DBUS_WIDTH-1 downto 0);
129 
      DMA_us_Control           : OUT std_logic_vector(C_DBUS_WIDTH-1 downto 0);
130 
      usDMA_BDA_eq_Null        : OUT std_logic;      -- obsolete
131 
      us_MWr_Param_Vec         : OUT std_logic_vector(6-1 downto 0);
132 
      DMA_us_Status            : IN  std_logic_vector(C_DBUS_WIDTH-1 downto 0);
133 
      DMA_us_Done              : IN  std_logic;
134 
      DMA_us_Tout              : IN  std_logic;
135 
 
136 
      -- Calculation in advance, for better timing
137 
      usHA_is_64b              : OUT std_logic;
138 
      usBDA_is_64b             : OUT std_logic;
139 
 
140 
      -- Calculation in advance, for better timing
141 
      usLeng_Hi19b_True        : OUT std_logic;
142 
      usLeng_Lo7b_True         : OUT std_logic;
143 
 
144 
      -- Upstream Control Signals
145 
      usDMA_Start              : OUT std_logic;
146 
      usDMA_Stop               : OUT std_logic;
147 
      usDMA_Start2             : OUT std_logic;
148 
      usDMA_Stop2              : OUT std_logic;
149 
      usDMA_Channel_Rst        : OUT std_logic;
150 
      usDMA_Cmd_Ack            : IN  std_logic;
151 
 
152 
      -- MRd Channel Reset
153 
      MRd_Channel_Rst          : OUT std_logic;
154 
 
155 
      -- Tx module reset
156 
      Tx_Reset                 : OUT std_logic;
157 
 
158 
                -- to Interrupts Module
159 
      Sys_IRQ                  : OUT std_logic_vector(C_DBUS_WIDTH-1 downto 0);
160 
      DAQ_irq                  : IN  std_logic;
161 
      CTL_irq                  : IN  std_logic;
162 
      DLM_irq                  : IN  std_logic;
163 
 
164 
      -- System error and info
165 
      Tx_TimeOut               : IN  std_logic;
166 
      Tx_eb_TimeOut            : IN  std_logic;
167 
      Msg_Routing              : OUT std_logic_vector(C_GCR_MSG_ROUT_BIT_TOP-C_GCR_MSG_ROUT_BIT_BOT downto 0);
168 
      pcie_link_width          : IN  std_logic_vector(CINT_BIT_LWIDTH_IN_GSR_TOP-CINT_BIT_LWIDTH_IN_GSR_BOT downto 0);
169 
      cfg_dcommand             : IN  std_logic_vector(16-1 downto 0);
170 
 
171 
      -- Interrupt Generation Signals
172 
      IG_Reset                 : OUT std_logic;
173 
      IG_Host_Clear            : OUT std_logic;
174 
      IG_Latency               : OUT std_logic_vector(C_DBUS_WIDTH-1 downto 0);
175 
      IG_Num_Assert            : IN  std_logic_vector(C_DBUS_WIDTH-1 downto 0);
176 
      IG_Num_Deassert          : IN  std_logic_vector(C_DBUS_WIDTH-1 downto 0);
177 
      IG_Asserting             : IN  std_logic;
178 
 
179 
      -- Data generator control
180 
      DG_is_Running            : IN  std_logic;
181 
      DG_Reset                 : OUT std_logic;
182 
      DG_Mask                  : OUT std_logic;
183 
 
184 
      -- SIMONE Register: PC-->FPGA
185 
      reg01_tv                   : OUT std_logic;
186 
      reg01_td                   : OUT std_logic_vector(C_DBUS_WIDTH/2-1 downto 0);
187 
      reg02_tv                   : OUT std_logic;
188 
      reg02_td                   : OUT std_logic_vector(C_DBUS_WIDTH/2-1 downto 0);
189 
      reg03_tv                   : OUT std_logic;
190 
      reg03_td                   : OUT std_logic_vector(C_DBUS_WIDTH/2-1 downto 0);
191 
      reg04_tv                   : OUT std_logic;
192 
      reg04_td                   : OUT std_logic_vector(C_DBUS_WIDTH/2-1 downto 0);
193 
      reg05_tv                   : OUT std_logic;
194 
      reg05_td                   : OUT std_logic_vector(C_DBUS_WIDTH/2-1 downto 0);
195 
      reg06_tv                   : OUT std_logic;
196 
      reg06_td                   : OUT std_logic_vector(C_DBUS_WIDTH/2-1 downto 0);
197 
      reg07_tv                   : OUT std_logic;
198 
      reg07_td                   : OUT std_logic_vector(C_DBUS_WIDTH/2-1 downto 0);
199 
      reg08_tv                   : OUT std_logic;
200 
      reg08_td                   : OUT std_logic_vector(C_DBUS_WIDTH/2-1 downto 0);
201 
      reg09_tv                   : OUT std_logic;
202 
      reg09_td                   : OUT std_logic_vector(C_DBUS_WIDTH/2-1 downto 0);
203 
      reg10_tv                   : OUT std_logic;
204 
      reg10_td                   : OUT std_logic_vector(C_DBUS_WIDTH/2-1 downto 0);
205 
      reg11_tv                   : OUT std_logic;
206 
      reg11_td                   : OUT std_logic_vector(C_DBUS_WIDTH/2-1 downto 0);
207 
      reg12_tv                   : OUT std_logic;
208 
      reg12_td                   : OUT std_logic_vector(C_DBUS_WIDTH/2-1 downto 0);
209 
      reg13_tv                   : OUT std_logic;
210 
      reg13_td                   : OUT std_logic_vector(C_DBUS_WIDTH/2-1 downto 0);
211 
      reg14_tv                   : OUT std_logic;
212 
      reg14_td                   : OUT std_logic_vector(C_DBUS_WIDTH/2-1 downto 0);
213 
 
214 
      -- SIMONE Register: FPGA-->PC
215 
      reg01_rv                   : IN  std_logic;
216 
      reg01_rd                   : IN  std_logic_vector(C_DBUS_WIDTH/2-1 downto 0);
217 
      reg02_rv                   : IN  std_logic;
218 
      reg02_rd                   : IN  std_logic_vector(C_DBUS_WIDTH/2-1 downto 0);
219 
      reg03_rv                   : IN  std_logic;
220 
      reg03_rd                   : IN  std_logic_vector(C_DBUS_WIDTH/2-1 downto 0);
221 
      reg04_rv                   : IN  std_logic;
222 
      reg04_rd                   : IN  std_logic_vector(C_DBUS_WIDTH/2-1 downto 0);
223 
      reg05_rv                   : IN  std_logic;
224 
      reg05_rd                   : IN  std_logic_vector(C_DBUS_WIDTH/2-1 downto 0);
225 
      reg06_rv                   : IN  std_logic;
226 
      reg06_rd                   : IN  std_logic_vector(C_DBUS_WIDTH/2-1 downto 0);
227 
      reg07_rv                   : IN  std_logic;
228 
      reg07_rd                   : IN  std_logic_vector(C_DBUS_WIDTH/2-1 downto 0);
229 
      reg08_rv                   : IN  std_logic;
230 
      reg08_rd                   : IN  std_logic_vector(C_DBUS_WIDTH/2-1 downto 0);
231 
      reg09_rv                   : IN  std_logic;
232 
      reg09_rd                   : IN  std_logic_vector(C_DBUS_WIDTH/2-1 downto 0);
233 
      reg10_rv                   : IN  std_logic;
234 
      reg10_rd                   : IN  std_logic_vector(C_DBUS_WIDTH/2-1 downto 0);
235 
      reg11_rv                   : IN  std_logic;
236 
      reg11_rd                   : IN  std_logic_vector(C_DBUS_WIDTH/2-1 downto 0);
237 
      reg12_rv                   : IN  std_logic;
238 
      reg12_rd                   : IN  std_logic_vector(C_DBUS_WIDTH/2-1 downto 0);
239 
      reg13_rv                   : IN  std_logic;
240 
      reg13_rd                   : IN  std_logic_vector(C_DBUS_WIDTH/2-1 downto 0);
241 
      reg14_rv                   : IN  std_logic;
242 
      reg14_rd                   : IN  std_logic_vector(C_DBUS_WIDTH/2-1 downto 0);
243 
 
244 
      --SIMONE debug signals
245 
                debug_in_1i                                             : OUT std_logic_vector(31 downto 0);
246 
      debug_in_2i                                               : OUT std_logic_vector(31 downto 0);
247 
      debug_in_3i                                               : OUT std_logic_vector(31 downto 0);
248 
      debug_in_4i                                               : OUT std_logic_vector(31 downto 0);
249 
 
250 
      -- Clock and reset
251 
      trn_clk                  : IN  std_logic;
252 
      trn_lnk_up_n             : IN  std_logic;
253 
      trn_reset_n              : IN  std_logic
254 
 
255 
    );
256 
end Regs_Group;
257 
 
258 
 
259 
architecture Behavioral of Regs_Group is
260 
 
261 
  type    icapStates is        ( icapST_Reset
262 
                               , icapST_Idle
263 
                               , icapST_Access
264 
                               , icapST_Abort
265 
                               );
266 
 
267 
  -- State variables of ICAP
268 
  signal  FSM_icap             : icapStates;
269 
 
270 
 
271 
  ----------------------------------------------------------------------------
272 
  ----------------------------------------------------------------------------
273 
  signal  Regs_WrDin_i         : std_logic_vector(C_DBUS_WIDTH-1   downto 0);
274 
  signal  Regs_WrAddr_i        : std_logic_vector(C_EP_AWIDTH-1   downto 0);
275 
  signal  Regs_WrMask_i        : std_logic_vector(2-1   downto 0);
276 
 
277 
  ------  Delay signals
278 
  signal  Regs_WrEn_r1         : std_logic;
279 
  signal  Regs_WrAddr_r1       : std_logic_vector(C_EP_AWIDTH-1   downto 0);
280 
  signal  Regs_WrMask_r1       : std_logic_vector(2-1   downto 0);
281 
  signal  Regs_WrDin_r1        : std_logic_vector(C_DBUS_WIDTH-1   downto 0);
282 
  signal  Regs_WrEn_r2         : std_logic;
283 
  signal  Regs_WrDin_r2        : std_logic_vector(C_DBUS_WIDTH-1   downto 0);
284 
  signal  Regs_Wr_dma_V_hi_r2     : std_logic;
285 
  signal  Regs_Wr_dma_nV_hi_r2    : std_logic;
286 
  signal  Regs_Wr_dma_V_nE_hi_r2  : std_logic;
287 
  signal  Regs_Wr_dma_V_lo_r2     : std_logic;
288 
  signal  Regs_Wr_dma_nV_lo_r2    : std_logic;
289 
  signal  Regs_Wr_dma_V_nE_lo_r2  : std_logic;
290 
  signal  WrDin_r1_not_Zero_Hi    : std_logic_vector(4-1 downto 0);
291 
  signal  WrDin_r2_not_Zero_Hi    : std_logic;
292 
  signal  WrDin_r1_not_Zero_Lo    : std_logic_vector(4-1 downto 0);
293 
  signal  WrDin_r2_not_Zero_Lo    : std_logic;
294 
 
295 
  --      Calculation in advance, just for better timing
296 
  signal  Regs_WrDin_Hi19b_True_hq_r2 : std_logic;
297 
  signal  Regs_WrDin_Lo7b_True_hq_r2  : std_logic;
298 
  signal  Regs_WrDin_Hi19b_True_lq_r2 : std_logic;
299 
  signal  Regs_WrDin_Lo7b_True_lq_r2  : std_logic;
300 
 
301 
  signal  Regs_WrEnA_r1           : std_logic;
302 
  signal  Regs_WrEnB_r1           : std_logic;
303 
  signal  Regs_WrEnA_r2           : std_logic;
304 
  signal  Regs_WrEnB_r2           : std_logic;
305 
 
306 
  --      Register write mux signals
307 
  signal  Reg_WrMuxer_Hi          : std_logic_vector(C_NUM_OF_ADDRESSES-1 downto 0);
308 
  signal  Reg_WrMuxer_Lo          : std_logic_vector(C_NUM_OF_ADDRESSES-1 downto 0);
309 
 
310 
 
311 
  -- Signals for Tx reading
312 
  signal  Regs_RdAddr_i           : std_logic_vector(C_EP_AWIDTH-1   downto 0);
313 
  signal  Regs_RdQout_i           : std_logic_vector(C_DBUS_WIDTH-1   downto 0);
314 
 
315 
  --      Register read mux signals
316 
  signal  Reg_RdMuxer_Hi          : std_logic_vector(C_NUM_OF_ADDRESSES-1 downto 0);
317 
  signal  Reg_RdMuxer_Lo          : std_logic_vector(C_NUM_OF_ADDRESSES-1 downto 0);
318 
 
319 
  -- Optical Link status
320 
  signal  Opto_Link_Status_i      : std_logic_vector(C_DBUS_WIDTH-1 downto 0);
321 
  signal  Opto_Link_Status_o_Hi   : std_logic_vector(C_DBUS_WIDTH-1 downto 0);
322 
  signal  Opto_Link_Status_o_Lo   : std_logic_vector(C_DBUS_WIDTH-1 downto 0);
323 
  -- Event Buffer
324 
  signal  eb_FIFO_Status_r1       : std_logic_vector(C_DBUS_WIDTH-1 downto 0);
325 
  signal  eb_FIFO_Status_o_Hi     : std_logic_vector(C_DBUS_WIDTH-1 downto 0);
326 
  signal  eb_FIFO_Status_o_Lo     : std_logic_vector(C_DBUS_WIDTH-1 downto 0);
327 
  signal  H2B_FIFO_Status_r1       : std_logic_vector(C_DBUS_WIDTH-1 downto 0);
328 
  signal  H2B_FIFO_Status_o_Hi     : std_logic_vector(C_DBUS_WIDTH-1 downto 0);
329 
  signal  H2B_FIFO_Status_o_Lo     : std_logic_vector(C_DBUS_WIDTH-1 downto 0);
330 
  signal  B2H_FIFO_Status_r1       : std_logic_vector(C_DBUS_WIDTH-1 downto 0);
331 
  signal  B2H_FIFO_Status_o_Hi     : std_logic_vector(C_DBUS_WIDTH-1 downto 0);
332 
  signal  B2H_FIFO_Status_o_Lo     : std_logic_vector(C_DBUS_WIDTH-1 downto 0);
333 
  signal  eb_FIFO_Rst_i           : std_logic;
334 
  signal  eb_FIFO_Rst_b1          : std_logic;
335 
  signal  eb_FIFO_Rst_b2          : std_logic;
336 
  signal  eb_FIFO_Rst_b3          : std_logic;
337 
  signal  eb_FIFO_OverWritten     : std_logic;
338 
 
339 
  -- Downstream DMA registers
340 
  signal  DMA_ds_PA_o_Hi          : std_logic_vector(C_DBUS_WIDTH-1 downto 0);
341 
  signal  DMA_ds_HA_o_Hi          : std_logic_vector(C_DBUS_WIDTH-1 downto 0);
342 
  signal  DMA_ds_BDA_o_Hi         : std_logic_vector(C_DBUS_WIDTH-1 downto 0);
343 
  signal  DMA_ds_Length_o_Hi      : std_logic_vector(C_DBUS_WIDTH-1 downto 0);
344 
  signal  DMA_ds_Control_o_Hi     : std_logic_vector(C_DBUS_WIDTH-1 downto 0);
345 
  signal  DMA_ds_Status_o_Hi      : std_logic_vector(C_DBUS_WIDTH-1 downto 0);
346 
  signal  DMA_ds_Transf_Bytes_o_Hi      : std_logic_vector(C_DBUS_WIDTH-1 downto 0);
347 
  signal  DMA_ds_PA_o_Lo          : std_logic_vector(C_DBUS_WIDTH-1 downto 0);
348 
  signal  DMA_ds_HA_o_Lo          : std_logic_vector(C_DBUS_WIDTH-1 downto 0);
349 
  signal  DMA_ds_BDA_o_Lo         : std_logic_vector(C_DBUS_WIDTH-1 downto 0);
350 
  signal  DMA_ds_Length_o_Lo      : std_logic_vector(C_DBUS_WIDTH-1 downto 0);
351 
  signal  DMA_ds_Control_o_Lo     : std_logic_vector(C_DBUS_WIDTH-1 downto 0);
352 
  signal  DMA_ds_Status_o_Lo      : std_logic_vector(C_DBUS_WIDTH-1 downto 0);
353 
  signal  DMA_ds_Transf_Bytes_o_Lo      : std_logic_vector(C_DBUS_WIDTH-1 downto 0);
354 
 
355 
  -- Upstream DMA registers
356 
  signal  DMA_us_PA_o_Hi          : std_logic_vector(C_DBUS_WIDTH-1 downto 0);
357 
  signal  DMA_us_HA_o_Hi          : std_logic_vector(C_DBUS_WIDTH-1 downto 0);
358 
  signal  DMA_us_BDA_o_Hi         : std_logic_vector(C_DBUS_WIDTH-1 downto 0);
359 
  signal  DMA_us_Length_o_Hi      : std_logic_vector(C_DBUS_WIDTH-1 downto 0);
360 
  signal  DMA_us_Control_o_Hi     : std_logic_vector(C_DBUS_WIDTH-1 downto 0);
361 
  signal  DMA_us_Status_o_Hi      : std_logic_vector(C_DBUS_WIDTH-1 downto 0);
362 
  signal  DMA_us_Transf_Bytes_o_Hi      : std_logic_vector(C_DBUS_WIDTH-1 downto 0);
363 
  signal  DMA_us_PA_o_Lo          : std_logic_vector(C_DBUS_WIDTH-1 downto 0);
364 
  signal  DMA_us_HA_o_Lo          : std_logic_vector(C_DBUS_WIDTH-1 downto 0);
365 
  signal  DMA_us_BDA_o_Lo         : std_logic_vector(C_DBUS_WIDTH-1 downto 0);
366 
  signal  DMA_us_Length_o_Lo      : std_logic_vector(C_DBUS_WIDTH-1 downto 0);
367 
  signal  DMA_us_Control_o_Lo     : std_logic_vector(C_DBUS_WIDTH-1 downto 0);
368 
  signal  DMA_us_Status_o_Lo      : std_logic_vector(C_DBUS_WIDTH-1 downto 0);
369 
  signal  DMA_us_Transf_Bytes_o_Lo      : std_logic_vector(C_DBUS_WIDTH-1 downto 0);
370 
 
371 
 
372 
  -- System Interrupt Status/Control
373 
  signal  Sys_IRQ_i               : std_logic_vector(C_DBUS_WIDTH-1 downto 0);
374 
  signal  Sys_Int_Status_i        : std_logic_vector(C_DBUS_WIDTH-1 downto 0);
375 
  signal  Sys_Int_Status_o_Hi     : std_logic_vector(C_DBUS_WIDTH-1 downto 0);
376 
  signal  Sys_Int_Status_o_Lo     : std_logic_vector(C_DBUS_WIDTH-1 downto 0);
377 
 
378 
  signal  Sys_Int_Enable_i        : std_logic_vector(C_DBUS_WIDTH-1 downto 0);
379 
  signal  Sys_Int_Enable_o_Hi     : std_logic_vector(C_DBUS_WIDTH-1 downto 0);
380 
  signal  Sys_Int_Enable_o_Lo     : std_logic_vector(C_DBUS_WIDTH-1 downto 0);
381 
 
382 
 
383 
  -- Data generator control
384 
  signal  DG_Reset_i              : std_logic;
385 
  signal  DG_Mask_i               : std_logic;
386 
  signal  DG_is_Available         : std_logic;
387 
  signal  DG_Rst_Counter          : std_logic_vector(8-1 downto 0);
388 
  signal  DG_Status_i             : std_logic_vector(C_DBUS_WIDTH-1 downto 0);
389 
  signal  DG_Status_o_Hi          : std_logic_vector(C_DBUS_WIDTH-1 downto 0);
390 
  signal  DG_Status_o_Lo          : std_logic_vector(C_DBUS_WIDTH-1 downto 0);
391 
 
392 
  -- General Control and Status
393 
  signal  Sys_Error_i             : std_logic_vector(C_DBUS_WIDTH-1   downto 0);
394 
  signal  Sys_Error_o_Hi          : std_logic_vector(C_DBUS_WIDTH-1   downto 0);
395 
  signal  Sys_Error_o_Lo          : std_logic_vector(C_DBUS_WIDTH-1   downto 0);
396 
 
397 
  signal  General_Control_i       : std_logic_vector(C_DBUS_WIDTH-1   downto 0);
398 
  signal  General_Control_o_Hi    : std_logic_vector(C_DBUS_WIDTH-1   downto 0);
399 
  signal  General_Control_o_Lo    : std_logic_vector(C_DBUS_WIDTH-1   downto 0);
400 
 
401 
  signal  General_Status_i        : std_logic_vector(C_DBUS_WIDTH-1   downto 0);
402 
  signal  General_Status_o_Hi     : std_logic_vector(C_DBUS_WIDTH-1   downto 0);
403 
  signal  General_Status_o_Lo     : std_logic_vector(C_DBUS_WIDTH-1   downto 0);
404 
 
405 
  -- Hardward version
406 
  signal  HW_Version_o_Hi         : std_logic_vector(C_DBUS_WIDTH-1   downto 0);
407 
  signal  HW_Version_o_Lo         : std_logic_vector(C_DBUS_WIDTH-1   downto 0);
408 
 
409 
  -- Signal as the source of interrupts
410 
  signal  IG_Host_Clear_i         : std_logic;
411 
  signal  IG_Reset_i              : std_logic;
412 
 
413 
  -- Interrupt Generator Control
414 
  signal  IG_Control_i            : std_logic_vector(C_DBUS_WIDTH-1   downto 0);
415 
 
416 
  -- Interrupt Generator Latency
417 
  signal  IG_Latency_i            : std_logic_vector(C_DBUS_WIDTH-1   downto 0);
418 
  signal  IG_Latency_o_Hi         : std_logic_vector(C_DBUS_WIDTH-1   downto 0);
419 
  signal  IG_Latency_o_Lo         : std_logic_vector(C_DBUS_WIDTH-1   downto 0);
420 
 
421 
  -- Interrupt Generator Statistic: Assert number
422 
  signal  IG_Num_Assert_i         : std_logic_vector(C_DBUS_WIDTH-1   downto 0);
423 
  signal  IG_Num_Assert_o_Hi      : std_logic_vector(C_DBUS_WIDTH-1   downto 0);
424 
  signal  IG_Num_Assert_o_Lo      : std_logic_vector(C_DBUS_WIDTH-1   downto 0);
425 
 
426 
  -- Interrupt Generator Statistic: Deassert number
427 
  signal  IG_Num_Deassert_i       : std_logic_vector(C_DBUS_WIDTH-1   downto 0);
428 
  signal  IG_Num_Deassert_o_Hi    : std_logic_vector(C_DBUS_WIDTH-1   downto 0);
429 
  signal  IG_Num_Deassert_o_Lo    : std_logic_vector(C_DBUS_WIDTH-1   downto 0);
430 
 
431 
  -- IntClr character is written
432 
  signal  Command_is_Host_iClr_Hi : std_logic;
433 
  signal  Command_is_Host_iClr_Lo : std_logic;
434 
 
435 
  -- Downstream Registers
436 
  signal  DMA_ds_PA_i          : std_logic_vector(C_DBUS_WIDTH-1 downto 0);
437 
  signal  DMA_ds_HA_i          : std_logic_vector(C_DBUS_WIDTH-1 downto 0);
438 
  signal  DMA_ds_BDA_i         : std_logic_vector(C_DBUS_WIDTH-1 downto 0);
439 
  signal  DMA_ds_Length_i      : std_logic_vector(C_DBUS_WIDTH-1   downto 0);
440 
  signal  DMA_ds_Control_i     : std_logic_vector(C_DBUS_WIDTH-1   downto 0);
441 
  signal  DMA_ds_Status_i      : std_logic_vector(C_DBUS_WIDTH-1   downto 0);
442 
  signal  DMA_ds_Transf_Bytes_i      : std_logic_vector(C_DBUS_WIDTH-1   downto 0);
443 
 
444 
  signal  Last_Ctrl_Word_ds    : std_logic_vector(C_DBUS_WIDTH-1   downto 0);
445 
 
446 
  -- Calculation in advance, for better timing
447 
  signal  dsHA_is_64b_i        : std_logic;
448 
  signal  dsBDA_is_64b_i       : std_logic;
449 
 
450 
  -- Calculation in advance, for better timing
451 
  signal  dsLeng_Hi19b_True_i  : std_logic;
452 
  signal  dsLeng_Lo7b_True_i   : std_logic;
453 
 
454 
  -- Downstream Control Signals
455 
  signal  dsDMA_Start_i        : std_logic;
456 
  signal  dsDMA_Stop_i         : std_logic;
457 
  signal  dsDMA_Start2_i       : std_logic;
458 
  signal  dsDMA_Start2_r1      : std_logic;
459 
  signal  dsDMA_Stop2_i        : std_logic;
460 
  signal  dsDMA_Channel_Rst_i  : std_logic;
461 
  signal  ds_Param_Modified    : std_logic;
462 
 
463 
 
464 
  -- Upstream Registers
465 
  signal  DMA_us_PA_i          : std_logic_vector(C_DBUS_WIDTH-1 downto 0);
466 
  signal  DMA_us_HA_i          : std_logic_vector(C_DBUS_WIDTH-1 downto 0);
467 
  signal  DMA_us_BDA_i         : std_logic_vector(C_DBUS_WIDTH-1 downto 0);
468 
  signal  DMA_us_Length_i      : std_logic_vector(C_DBUS_WIDTH-1   downto 0);
469 
  signal  DMA_us_Control_i     : std_logic_vector(C_DBUS_WIDTH-1   downto 0);
470 
  signal  DMA_us_Status_i      : std_logic_vector(C_DBUS_WIDTH-1   downto 0);
471 
  signal  DMA_us_Transf_Bytes_i      : std_logic_vector(C_DBUS_WIDTH-1   downto 0);
472 
 
473 
  signal  Last_Ctrl_Word_us    : std_logic_vector(C_DBUS_WIDTH-1   downto 0);
474 
 
475 
  -- Calculation in advance, for better timing
476 
  signal  usHA_is_64b_i        : std_logic;
477 
  signal  usBDA_is_64b_i       : std_logic;
478 
 
479 
  -- Calculation in advance, for better timing
480 
  signal  usLeng_Hi19b_True_i  : std_logic;
481 
  signal  usLeng_Lo7b_True_i   : std_logic;
482 
 
483 
 
484 
  -- Upstream Control Signals
485 
  signal  usDMA_Start_i        : std_logic;
486 
  signal  usDMA_Stop_i         : std_logic;
487 
  signal  usDMA_Start2_i       : std_logic;
488 
  signal  usDMA_Start2_r1      : std_logic;
489 
  signal  usDMA_Stop2_i        : std_logic;
490 
  signal  usDMA_Channel_Rst_i  : std_logic;
491 
  signal  us_Param_Modified    : std_logic;
492 
 
493 
  -- Reset character is written
494 
  signal  Command_is_Reset_Hi  : std_logic;
495 
  signal  Command_is_Reset_Lo  : std_logic;
496 
 
497 
  -- MRd channel reset
498 
  signal  MRd_Channel_Rst_i    : std_logic;
499 
 
500 
  -- Tx module reset
501 
  signal  Tx_Reset_i           : std_logic;
502 
 
503 
 
504 
  -- ICAP
505 
  signal  icap_CLK             : std_logic;
506 
  signal  icap_I               : std_logic_vector(C_DBUS_WIDTH-1 downto 0);
507 
  signal  icap_CE              : std_logic;
508 
  signal  icap_Write           : std_logic;
509 
  signal  icap_O               : std_logic_vector(C_DBUS_WIDTH-1 downto 0);
510 
  signal  icap_O_o_Hi          : std_logic_vector(C_DBUS_WIDTH-1 downto 0);
511 
  signal  icap_O_o_Lo          : std_logic_vector(C_DBUS_WIDTH-1 downto 0);
512 
  signal  icap_BUSY            : std_logic;
513 
 
514 
  -- DCB protocol interface
515 
  signal  protocol_rst_i       : std_logic;
516 
  signal  protocol_rst_b1      : std_logic;
517 
  signal  protocol_rst_b2      : std_logic;
518 
 
519 
  -- Protocol : CTL
520 
  signal  ctl_rv_i             : std_logic;
521 
  signal  ctl_rd_i             : std_logic_vector(C_DBUS_WIDTH/2-1 downto 0);
522 
 
523 
  signal  class_CTL_Status_i   : std_logic_vector(C_DBUS_WIDTH-1 downto 0);
524 
  signal  class_CTL_Status_o_Hi: std_logic_vector(C_DBUS_WIDTH-1 downto 0);
525 
  signal  class_CTL_Status_o_Lo: std_logic_vector(C_DBUS_WIDTH-1 downto 0);
526 
 
527 
  signal  ctl_td_o_Hi          : std_logic_vector(C_DBUS_WIDTH/2-1 downto 0);
528 
  signal  ctl_td_o_Lo          : std_logic_vector(C_DBUS_WIDTH/2-1 downto 0);
529 
  signal  ctl_td_r             : std_logic_vector(C_DBUS_WIDTH/2-1 downto 0);
530 
 
531 
  signal  ctl_reset_i          : std_logic;
532 
  signal  ctl_ttake_i          : std_logic;
533 
  signal  ctl_tstop_i          : std_logic;
534 
  signal  ctl_t_read_Hi_r1     : std_logic;
535 
  signal  ctl_t_read_Lo_r1     : std_logic;
536 
  signal  CTL_read_counter     : std_logic_vector(6-1 downto 0);
537 
 
538 
  -- Protocol : DLM
539 
  signal  dlm_tv_i             : std_logic;
540 
  signal  dlm_td_i             : std_logic_vector(C_DBUS_WIDTH/2-1 downto 0);
541 
 
542 
  signal  dlm_rd_o_Hi          : std_logic_vector(C_DBUS_WIDTH/2-1 downto 0);
543 
  signal  dlm_rd_o_Lo          : std_logic_vector(C_DBUS_WIDTH/2-1 downto 0);
544 
  signal  dlm_rd_r             : std_logic_vector(C_DBUS_WIDTH/2-1 downto 0);
545 
 
546 
 
547 
  -- SIMONE Register: PC-->FPGA
548 
  signal  reg01_tv_i            : std_logic;
549 
  signal  reg01_td_i            : std_logic_vector(C_DBUS_WIDTH/2-1 downto 0);
550 
  signal  reg02_tv_i            : std_logic;
551 
  signal  reg02_td_i            : std_logic_vector(C_DBUS_WIDTH/2-1 downto 0);
552 
  signal  reg03_tv_i            : std_logic;
553 
  signal  reg03_td_i            : std_logic_vector(C_DBUS_WIDTH/2-1 downto 0);
554 
  signal  reg04_tv_i            : std_logic;
555 
  signal  reg04_td_i            : std_logic_vector(C_DBUS_WIDTH/2-1 downto 0);
556 
  signal  reg05_tv_i            : std_logic;
557 
  signal  reg05_td_i            : std_logic_vector(C_DBUS_WIDTH/2-1 downto 0);
558 
  signal  reg06_tv_i            : std_logic;
559 
  signal  reg06_td_i            : std_logic_vector(C_DBUS_WIDTH/2-1 downto 0);
560 
  signal  reg07_tv_i            : std_logic;
561 
  signal  reg07_td_i            : std_logic_vector(C_DBUS_WIDTH/2-1 downto 0);
562 
  signal  reg08_tv_i            : std_logic;
563 
  signal  reg08_td_i            : std_logic_vector(C_DBUS_WIDTH/2-1 downto 0);
564 
  signal  reg09_tv_i            : std_logic;
565 
  signal  reg09_td_i            : std_logic_vector(C_DBUS_WIDTH/2-1 downto 0);
566 
  signal  reg10_tv_i            : std_logic;
567 
  signal  reg10_td_i            : std_logic_vector(C_DBUS_WIDTH/2-1 downto 0);
568 
  signal  reg11_tv_i            : std_logic;
569 
  signal  reg11_td_i            : std_logic_vector(C_DBUS_WIDTH/2-1 downto 0);
570 
  signal  reg12_tv_i            : std_logic;
571 
  signal  reg12_td_i            : std_logic_vector(C_DBUS_WIDTH/2-1 downto 0);
572 
  signal  reg13_tv_i            : std_logic;
573 
  signal  reg13_td_i            : std_logic_vector(C_DBUS_WIDTH/2-1 downto 0);
574 
  signal  reg14_tv_i            : std_logic;
575 
  signal  reg14_td_i            : std_logic_vector(C_DBUS_WIDTH/2-1 downto 0);
576 
   -- SIMONE Register: FPGA-->PC
577 
  signal  reg01_rd_o_Hi         : std_logic_vector(C_DBUS_WIDTH/2-1 downto 0);
578 
  signal  reg01_rd_o_Lo         : std_logic_vector(C_DBUS_WIDTH/2-1 downto 0);
579 
  signal  reg01_rd_r            : std_logic_vector(C_DBUS_WIDTH/2-1 downto 0);
580 
  signal  reg02_rd_o_Hi         : std_logic_vector(C_DBUS_WIDTH/2-1 downto 0);
581 
  signal  reg02_rd_o_Lo         : std_logic_vector(C_DBUS_WIDTH/2-1 downto 0);
582 
  signal  reg02_rd_r            : std_logic_vector(C_DBUS_WIDTH/2-1 downto 0);
583 
  signal  reg03_rd_o_Hi         : std_logic_vector(C_DBUS_WIDTH/2-1 downto 0);
584 
  signal  reg03_rd_o_Lo         : std_logic_vector(C_DBUS_WIDTH/2-1 downto 0);
585 
  signal  reg03_rd_r            : std_logic_vector(C_DBUS_WIDTH/2-1 downto 0);
586 
  signal  reg04_rd_o_Hi         : std_logic_vector(C_DBUS_WIDTH/2-1 downto 0);
587 
  signal  reg04_rd_o_Lo         : std_logic_vector(C_DBUS_WIDTH/2-1 downto 0);
588 
  signal  reg04_rd_r            : std_logic_vector(C_DBUS_WIDTH/2-1 downto 0);
589 
  signal  reg05_rd_o_Hi         : std_logic_vector(C_DBUS_WIDTH/2-1 downto 0);
590 
  signal  reg05_rd_o_Lo         : std_logic_vector(C_DBUS_WIDTH/2-1 downto 0);
591 
  signal  reg05_rd_r            : std_logic_vector(C_DBUS_WIDTH/2-1 downto 0);
592 
  signal  reg06_rd_o_Hi         : std_logic_vector(C_DBUS_WIDTH/2-1 downto 0);
593 
  signal  reg06_rd_o_Lo         : std_logic_vector(C_DBUS_WIDTH/2-1 downto 0);
594 
  signal  reg06_rd_r            : std_logic_vector(C_DBUS_WIDTH/2-1 downto 0);
595 
  signal  reg07_rd_o_Hi         : std_logic_vector(C_DBUS_WIDTH/2-1 downto 0);
596 
  signal  reg07_rd_o_Lo         : std_logic_vector(C_DBUS_WIDTH/2-1 downto 0);
597 
  signal  reg07_rd_r            : std_logic_vector(C_DBUS_WIDTH/2-1 downto 0);
598 
  signal  reg08_rd_o_Hi         : std_logic_vector(C_DBUS_WIDTH/2-1 downto 0);
599 
  signal  reg08_rd_o_Lo         : std_logic_vector(C_DBUS_WIDTH/2-1 downto 0);
600 
  signal  reg08_rd_r            : std_logic_vector(C_DBUS_WIDTH/2-1 downto 0);
601 
  signal  reg09_rd_o_Hi         : std_logic_vector(C_DBUS_WIDTH/2-1 downto 0);
602 
  signal  reg09_rd_o_Lo         : std_logic_vector(C_DBUS_WIDTH/2-1 downto 0);
603 
  signal  reg09_rd_r            : std_logic_vector(C_DBUS_WIDTH/2-1 downto 0);
604 
  signal  reg10_rd_o_Hi         : std_logic_vector(C_DBUS_WIDTH/2-1 downto 0);
605 
  signal  reg10_rd_o_Lo         : std_logic_vector(C_DBUS_WIDTH/2-1 downto 0);
606 
  signal  reg10_rd_r            : std_logic_vector(C_DBUS_WIDTH/2-1 downto 0);
607 
  signal  reg11_rd_o_Hi         : std_logic_vector(C_DBUS_WIDTH/2-1 downto 0);
608 
  signal  reg11_rd_o_Lo         : std_logic_vector(C_DBUS_WIDTH/2-1 downto 0);
609 
  signal  reg11_rd_r            : std_logic_vector(C_DBUS_WIDTH/2-1 downto 0);
610 
  signal  reg12_rd_o_Hi         : std_logic_vector(C_DBUS_WIDTH/2-1 downto 0);
611 
  signal  reg12_rd_o_Lo         : std_logic_vector(C_DBUS_WIDTH/2-1 downto 0);
612 
  signal  reg12_rd_r            : std_logic_vector(C_DBUS_WIDTH/2-1 downto 0);
613 
  signal  reg13_rd_o_Hi         : std_logic_vector(C_DBUS_WIDTH/2-1 downto 0);
614 
  signal  reg13_rd_o_Lo         : std_logic_vector(C_DBUS_WIDTH/2-1 downto 0);
615 
  signal  reg13_rd_r            : std_logic_vector(C_DBUS_WIDTH/2-1 downto 0);
616 
  signal  reg14_rd_o_Hi         : std_logic_vector(C_DBUS_WIDTH/2-1 downto 0);
617 
  signal  reg14_rd_o_Lo         : std_logic_vector(C_DBUS_WIDTH/2-1 downto 0);
618 
  signal  reg14_rd_r            : std_logic_vector(C_DBUS_WIDTH/2-1 downto 0);
619 
  --signal  debug_in_1i           : std_logic_vector(31 downto 0);
620 
  --signal  debug_in_2i           : std_logic_vector(31 downto 0);
621 
  --signal  debug_in_3i           : std_logic_vector(31 downto 0);
622 
 
623 
 
624 
 
625 
begin
626 
 
627 
   DG_Available_Bit: if IMP_DATA_GENERATOR generate
628 
      DG_is_Available   <= '1';
629 
   end generate;
630 
 
631 
   DG_Unavailable_Bit: if not IMP_DATA_GENERATOR generate
632 
      DG_is_Available   <= '0';
633 
   end generate;
634 
 
635 
   -- SIMONE Register: PC-->FPGA
636 
   reg01_tv             <= reg01_tv_i;
637 
   reg01_td             <= reg01_td_i;
638 
   reg02_tv             <= reg02_tv_i;
639 
   reg02_td             <= reg02_td_i;
640 
   reg03_tv             <= reg03_tv_i;
641 
   reg03_td             <= reg03_td_i;
642 
   reg04_tv             <= reg04_tv_i;
643 
   reg04_td             <= reg04_td_i;
644 
   reg05_tv             <= reg05_tv_i;
645 
   reg05_td             <= reg05_td_i;
646 
   reg06_tv             <= reg06_tv_i;
647 
   reg06_td             <= reg06_td_i;
648 
   reg07_tv             <= reg07_tv_i;
649 
   reg07_td             <= reg07_td_i;
650 
   reg08_tv             <= reg08_tv_i;
651 
   reg08_td             <= reg08_td_i;
652 
   reg09_tv             <= reg09_tv_i;
653 
   reg09_td             <= reg09_td_i;
654 
   reg10_tv             <= reg10_tv_i;
655 
   reg10_td             <= reg10_td_i;
656 
   reg11_tv             <= reg11_tv_i;
657 
   reg11_td             <= reg11_td_i;
658 
   reg12_tv             <= reg12_tv_i;
659 
   reg12_td             <= reg12_td_i;
660 
   reg13_tv             <= reg13_tv_i;
661 
   reg13_td             <= reg13_td_i;
662 
   reg14_tv             <= reg14_tv_i;
663 
   reg14_td             <= reg14_td_i;
664 
 
665 
 
666 
   -- protocol interface reset
667 
   protocol_rst         <= protocol_rst_i;
668 
 
669 
   ctl_rv               <= ctl_rv_i;
670 
   ctl_rd               <= ctl_rd_i;
671 
 
672 
   ctl_ttake            <= ctl_ttake_i;
673 
   ctl_tstop            <= ctl_tstop_i;
674 
   ctl_reset            <= ctl_reset_i;
675 
 
676 
   ctl_tstop_i          <= '0';   -- ???
677 
 
678 
   dlm_tv               <= dlm_tv_i;
679 
   dlm_td               <= dlm_td_i;
680 
 
681 
   -- Data generator control
682 
   DG_Reset             <= DG_Reset_i;
683 
   DG_Mask              <= DG_Mask_i;
684 
 
685 
   -- Event buffer reset
686 
   eb_FIFO_Rst          <= eb_FIFO_Rst_i;
687 
 
688 
   -- MRd channel reset
689 
   MRd_Channel_Rst      <= MRd_Channel_Rst_i;
690 
 
691 
   -- Tx module reset
692 
   Tx_Reset             <= Tx_Reset_i;
693 
 
694 
   -- Upstream DMA engine reset
695 
   usDMA_Channel_Rst    <= usDMA_Channel_Rst_i;
696 
 
697 
   -- Downstream DMA engine reset
698 
   dsDMA_Channel_Rst    <= dsDMA_Channel_Rst_i;
699 
 
700 
 
701 
   -- Upstream DMA registers
702 
   DMA_us_PA            <= DMA_us_PA_i;
703 
   DMA_us_HA            <= DMA_us_HA_i;
704 
   DMA_us_BDA           <= DMA_us_BDA_i;
705 
   DMA_us_Length        <= DMA_us_Length_i;
706 
   DMA_us_Control       <= DMA_us_Control_i;
707 
   usDMA_BDA_eq_Null    <= '0';
708 
   DMA_us_Status_i      <= DMA_us_Status;
709 
 
710 
   usHA_is_64b          <= usHA_is_64b_i;
711 
   usBDA_is_64b         <= usBDA_is_64b_i;
712 
 
713 
   usLeng_Hi19b_True    <= usLeng_Hi19b_True_i;
714 
   usLeng_Lo7b_True     <= usLeng_Lo7b_True_i;
715 
 
716 
   usDMA_Start          <= usDMA_Start_i;
717 
   usDMA_Stop           <= usDMA_Stop_i;
718 
   usDMA_Start2         <= usDMA_Start2_r1;
719 
--   usDMA_Start2         <= usDMA_Start2_i;
720 
   usDMA_Stop2          <= usDMA_Stop2_i;
721 
 
722 
   -- Downstream DMA registers
723 
   DMA_ds_PA            <= DMA_ds_PA_i;
724 
   DMA_ds_HA            <= DMA_ds_HA_i;
725 
   DMA_ds_BDA           <= DMA_ds_BDA_i;
726 
   DMA_ds_Length        <= DMA_ds_Length_i;
727 
   DMA_ds_Control       <= DMA_ds_Control_i;
728 
   dsDMA_BDA_eq_Null    <= '0';
729 
   DMA_ds_Status_i      <= DMA_ds_Status;
730 
 
731 
   dsHA_is_64b          <= dsHA_is_64b_i;
732 
   dsBDA_is_64b         <= dsBDA_is_64b_i;
733 
 
734 
   dsLeng_Hi19b_True    <= dsLeng_Hi19b_True_i;
735 
   dsLeng_Lo7b_True     <= dsLeng_Lo7b_True_i;
736 
 
737 
   dsDMA_Start          <= dsDMA_Start_i;
738 
   dsDMA_Stop           <= dsDMA_Stop_i;
739 
   dsDMA_Start2         <= dsDMA_Start2_r1;
740 
--   dsDMA_Start2         <= dsDMA_Start2_i;
741 
   dsDMA_Stop2          <= dsDMA_Stop2_i;
742 
 
743 
 
744 
   -- Register to Interrupt handler module
745 
   Sys_IRQ              <= Sys_IRQ_i;
746 
 
747 
   -- Message routing method
748 
   Msg_Routing          <= General_Control_i(C_GCR_MSG_ROUT_BIT_TOP downto C_GCR_MSG_ROUT_BIT_BOT);
749 
 
750 
   -- us_MWr_TLP_Param
751 
   us_MWr_Param_Vec     <= General_Control_i(13 downto 8);
752 
 
753 
 
754 
   -- -------------   Interrupt generator generation    ----------------------
755 
   Gen_IG:  if IMP_INT_GENERATOR generate
756 
 
757 
   IG_Reset             <= IG_Reset_i;
758 
   IG_Host_Clear        <= IG_Host_Clear_i;  -- and Sys_Int_Enable_i(CINT_BIT_INTGEN_IN_ISR);
759 
   IG_Latency           <= IG_Latency_i;
760 
   IG_Num_Assert_i      <= IG_Num_Assert;
761 
   IG_Num_Deassert_i    <= IG_Num_Deassert;
762 
 
763 
 
764 
-- -----------------------------------------------
765 
-- Synchronous Registered: IG_Control_i
766 
   SysReg_IntGen_Control:
767 
   process ( trn_clk, trn_lnk_up_n)
768 
   begin
769 
      if trn_lnk_up_n = '1' then
770 
         IG_Control_i          <= (OTHERS => '0');
771 
         IG_Reset_i            <= '1';
772 
         IG_Host_Clear_i       <= '0';
773 
 
774 
      elsif trn_clk'event and trn_clk = '1' then
775 
 
776 
        if Regs_WrEn_r2='1'
777 
                    and Reg_WrMuxer_Hi(CINT_ADDR_IG_CONTROL)='1'
778 
                         then
779 
            IG_Control_i(32-1 downto 0)       <=  Regs_WrDin_r2(64-1 downto 32);
780 
            IG_Reset_i         <=  Command_is_Reset_Hi;
781 
            IG_Host_Clear_i    <=  Command_is_Host_iClr_Hi;
782 
        elsif Regs_WrEn_r2='1'
783 
                    and Reg_WrMuxer_Lo(CINT_ADDR_IG_CONTROL)='1'
784 
                         then
785 
            IG_Control_i(32-1 downto 0)       <=  Regs_WrDin_r2(32-1 downto 0);
786 
            IG_Reset_i         <=  Command_is_Reset_Lo;
787 
            IG_Host_Clear_i    <=  Command_is_Host_iClr_Lo;
788 
        else
789 
            IG_Control_i       <=  IG_Control_i;
790 
            IG_Reset_i         <=  '0';
791 
            IG_Host_Clear_i    <=  '0';
792 
        end if;
793 
 
794 
      end if;
795 
   end process;
796 
 
797 
 
798 
-- -----------------------------------------------
799 
-- Synchronous Registered: IG_Latency_i
800 
   SysReg_IntGen_Latency:
801 
   process ( trn_clk, trn_lnk_up_n)
802 
   begin
803 
      if trn_lnk_up_n = '1' then
804 
         IG_Latency_i       <= (OTHERS => '0');
805 
 
806 
      elsif trn_clk'event and trn_clk = '1' then
807 
 
808 
        if IG_Reset_i='1' then
809 
            IG_Latency_i    <=  (OTHERS => '0');
810 
        elsif Regs_WrEn_r2='1'
811 
                    and Reg_WrMuxer_Hi(CINT_ADDR_IG_LATENCY)='1'
812 
                         then
813 
            IG_Latency_i(32-1 downto 0)    <=  Regs_WrDin_r2(64-1 downto 32);
814 
        elsif Regs_WrEn_r2='1'
815 
                    and Reg_WrMuxer_Lo(CINT_ADDR_IG_LATENCY)='1'
816 
                         then
817 
            IG_Latency_i(32-1 downto 0)    <=  Regs_WrDin_r2(32-1 downto 0);
818 
        else
819 
            IG_Latency_i    <=  IG_Latency_i;
820 
        end if;
821 
 
822 
      end if;
823 
   end process;
824 
 
825 
   end generate;
826 
 
827 
   NotGen_IG:  if not IMP_INT_GENERATOR generate
828 
 
829 
   IG_Reset             <= '0';
830 
   IG_Host_Clear        <= '0';
831 
   IG_Latency           <= (OTHERS=>'0');
832 
   IG_Num_Assert_i      <= (OTHERS=>'0');
833 
   IG_Num_Deassert_i    <= (OTHERS=>'0');
834 
 
835 
   IG_Control_i         <= (OTHERS=>'0');
836 
   IG_Reset_i           <= '0';
837 
   IG_Host_Clear_i      <= '0';
838 
   IG_Latency_i         <= (OTHERS=>'0');
839 
 
840 
   end generate;
841 
 
842 
 
843 
 
844 
-- ----------------------------------------------
845 
-- Synchronous Delay : Sys_IRQ_i
846 
--
847 
   Synch_Delay_Sys_IRQ:
848 
   process ( trn_clk, trn_lnk_up_n )
849 
   begin
850 
      if trn_lnk_up_n = '1' then
851 
         Sys_IRQ_i   <=  (OTHERS=>'0');
852 
 
853 
      elsif trn_clk'event and trn_clk = '1' then
854 
         Sys_IRQ_i(C_NUM_OF_INTERRUPTS-1 downto 0)
855 
                     <= Sys_Int_Enable_i(C_NUM_OF_INTERRUPTS-1 downto 0)
856 
                    and Sys_Int_Status_i(C_NUM_OF_INTERRUPTS-1 downto 0);
857 
 
858 
      end if;
859 
   end process;
860 
 
861 
 
862 
-- ----------------------------------------------
863 
-- Registers writing
864 
--
865 
   Regs_WrAddr_i        <= Regs_WrAddrA and Regs_WrAddrB;
866 
   Regs_WrMask_i        <= Regs_WrMaskA or  Regs_WrMaskB;
867 
   Regs_WrDin_i         <= Regs_WrDinA  or  Regs_WrDinB;
868 
 
869 
-- ----------------------------------------------
870 
-- Registers reading
871 
--
872 
   Regs_RdAddr_i        <= Regs_RdAddr;
873 
   Regs_RdQout          <= Regs_RdQout_i;
874 
 
875 
-- ----------------------------------------------
876 
-- Synchronous Delay : Regs_WrEn
877 
--
878 
   Synch_Delay_Regs_WrEn:
879 
   process ( trn_clk )
880 
   begin
881 
      if trn_clk'event and trn_clk = '1' then
882 
         Regs_WrEn_r1   <= Regs_WrEnA or Regs_WrEnB;
883 
         Regs_WrEn_r2   <= Regs_WrEn_r1;
884 
 
885 
         Regs_WrEnA_r1  <= Regs_WrEnA;
886 
         Regs_WrEnA_r2  <= Regs_WrEnA_r1;
887 
 
888 
         Regs_WrEnB_r1  <= Regs_WrEnB;
889 
         Regs_WrEnB_r2  <= Regs_WrEnB_r1;
890 
 
891 
      end if;
892 
   end process;
893 
 
894 
-- ----------------------------------------------
895 
-- Synchronous Delay : Opto_Link_Status
896 
--
897 
   Synch_Delay_Opto_Link_Status:
898 
   process ( trn_clk )
899 
   begin
900 
      if trn_clk'event and trn_clk = '1' then
901 
         Opto_Link_Status_i(C_DBUS_WIDTH-1 downto 2)   <= (OTHERS=>'0');
902 
         Opto_Link_Status_i(2-1 downto 0)   <= protocol_link_act;
903 
      end if;
904 
   end process;
905 
 
906 
-- ----------------------------------------------
907 
-- Synchronous Delay : eb_FIFO_Status
908 
--
909 
   Synch_Delay_eb_FIFO_Status:
910 
   process ( trn_clk )
911 
   begin
912 
      if trn_clk'event and trn_clk = '1' then
913 
         eb_FIFO_Status_r1   <= eb_FIFO_Status;
914 
      end if;
915 
   end process;
916 
   Synch_Delay_H2B_FIFO_Status:
917 
   process ( trn_clk )
918 
   begin
919 
      if trn_clk'event and trn_clk = '1' then
920 
         H2B_FIFO_Status_r1   <= H2B_FIFO_Status;
921 
      end if;
922 
   end process;
923 
   Synch_Delay_B2H_FIFO_Status:
924 
   process ( trn_clk )
925 
   begin
926 
      if trn_clk'event and trn_clk = '1' then
927 
         B2H_FIFO_Status_r1   <= B2H_FIFO_Status;
928 
      end if;
929 
   end process;
930 
 
931 
-- ----------------------------------------------
932 
-- Synchronous Delay : Regs_WrAddr
933 
--
934 
   Synch_Delay_Regs_WrAddr:
935 
   process ( trn_clk )
936 
   begin
937 
      if trn_clk'event and trn_clk = '1' then
938 
         Regs_WrAddr_r1   <= Regs_WrAddr_i;
939 
         Regs_WrMask_r1   <= Regs_WrMask_i;
940 
      end if;
941 
   end process;
942 
 
943 
-- ----------------------------------------------------
944 
-- Synchronous Delay : dsDMA_Start2
945 
--                     usDMA_Start2
946 
--   (Special recipe for 64-bit successive descriptors)
947 
--
948 
   Synch_Delay_DMA_Start2:
949 
   process ( trn_clk )
950 
   begin
951 
      if trn_clk'event and trn_clk = '1' then
952 
         dsDMA_Start2_r1   <= dsDMA_Start2_i and not dsDMA_Cmd_Ack;
953 
         usDMA_Start2_r1   <= usDMA_Start2_i and not usDMA_Cmd_Ack;
954 
      end if;
955 
   end process;
956 
 
957 
 
958 
-- ----------------------------------------------
959 
-- Synchronous Delay : Regs_WrDin_i
960 
--
961 
   Synch_Delay_Regs_WrDin:
962 
   process ( trn_clk )
963 
   begin
964 
      if trn_clk'event and trn_clk = '1' then
965 
         Regs_WrDin_r1   <= Regs_WrDin_i;
966 
         Regs_WrDin_r2   <= Regs_WrDin_r1;
967 
 
968 
         if Regs_WrDin_i(31+32 downto 24+32) = C_ALL_ZEROS(31+32 downto 24+32) then
969 
            WrDin_r1_not_Zero_Hi(3) <= '0';
970 
         else
971 
            WrDin_r1_not_Zero_Hi(3) <= '1';
972 
         end if;
973 
         if Regs_WrDin_i(23+32 downto 16+32) = C_ALL_ZEROS(23+32 downto 16+32) then
974 
            WrDin_r1_not_Zero_Hi(2) <= '0';
975 
         else
976 
            WrDin_r1_not_Zero_Hi(2) <= '1';
977 
         end if;
978 
         if Regs_WrDin_i(15+32 downto 8+32) = C_ALL_ZEROS(15+32 downto 8+32) then
979 
            WrDin_r1_not_Zero_Hi(1) <= '0';
980 
         else
981 
            WrDin_r1_not_Zero_Hi(1) <= '1';
982 
         end if;
983 
         if Regs_WrDin_i(7+32 downto 0+32) = C_ALL_ZEROS(7+32 downto 0+32) then
984 
            WrDin_r1_not_Zero_Hi(0) <= '0';
985 
         else
986 
            WrDin_r1_not_Zero_Hi(0) <= '1';
987 
         end if;
988 
 
989 
         if WrDin_r1_not_Zero_Hi = C_ALL_ZEROS(3 downto 0) then
990 
            WrDin_r2_not_Zero_Hi <= '0';
991 
         else
992 
            WrDin_r2_not_Zero_Hi <= '1';
993 
         end if;
994 
 
995 
 
996 
         if Regs_WrDin_i(31 downto 24) = C_ALL_ZEROS(31 downto 24) then
997 
            WrDin_r1_not_Zero_Lo(3) <= '0';
998 
         else
999 
            WrDin_r1_not_Zero_Lo(3) <= '1';
1000 
         end if;
1001 
         if Regs_WrDin_i(23 downto 16) = C_ALL_ZEROS(23 downto 16) then
1002 
            WrDin_r1_not_Zero_Lo(2) <= '0';
1003 
         else
1004 
            WrDin_r1_not_Zero_Lo(2) <= '1';
1005 
         end if;
1006 
         if Regs_WrDin_i(15 downto 8) = C_ALL_ZEROS(15 downto 8) then
1007 
            WrDin_r1_not_Zero_Lo(1) <= '0';
1008 
         else
1009 
            WrDin_r1_not_Zero_Lo(1) <= '1';
1010 
         end if;
1011 
         if Regs_WrDin_i(7 downto 0) = C_ALL_ZEROS(7 downto 0) then
1012 
            WrDin_r1_not_Zero_Lo(0) <= '0';
1013 
         else
1014 
            WrDin_r1_not_Zero_Lo(0) <= '1';
1015 
         end if;
1016 
 
1017 
         if WrDin_r1_not_Zero_Lo = C_ALL_ZEROS(3 downto 0) then
1018 
            WrDin_r2_not_Zero_Lo <= '0';
1019 
         else
1020 
            WrDin_r2_not_Zero_Lo <= '1';
1021 
         end if;
1022 
      end if;
1023 
   end process;
1024 
 
1025 
 
1026 
-- -----------------------------------------------------------
1027 
-- Synchronous Delay : DMA Commands Write Valid and not End
1028 
--
1029 
   Synch_Delay_dmaCmd_Wr_Valid_and_End:
1030 
   process ( trn_clk )
1031 
   begin
1032 
      if trn_clk'event and trn_clk = '1' then
1033 
         Regs_Wr_dma_V_hi_r2      <= Regs_WrEn_r1
1034 
                               and Regs_WrDin_r1(CINT_BIT_DMA_CTRL_VALID+32)
1035 
                               ;
1036 
         Regs_Wr_dma_nV_hi_r2     <= Regs_WrEn_r1
1037 
                               and not Regs_WrDin_r1(CINT_BIT_DMA_CTRL_VALID+32)
1038 
                               ;
1039 
         Regs_Wr_dma_V_nE_hi_r2   <= Regs_WrEn_r1
1040 
                               and Regs_WrDin_r1(CINT_BIT_DMA_CTRL_VALID+32)
1041 
                               and not Regs_WrDin_r1(CINT_BIT_DMA_CTRL_END+32)
1042 
                               ;
1043 
 
1044 
 
1045 
         Regs_Wr_dma_V_lo_r2      <= Regs_WrEn_r1
1046 
                               and Regs_WrDin_r1(CINT_BIT_DMA_CTRL_VALID)
1047 
                               ;
1048 
         Regs_Wr_dma_nV_lo_r2     <= Regs_WrEn_r1
1049 
                               and not Regs_WrDin_r1(CINT_BIT_DMA_CTRL_VALID)
1050 
                               ;
1051 
         Regs_Wr_dma_V_nE_lo_r2   <= Regs_WrEn_r1
1052 
                               and Regs_WrDin_r1(CINT_BIT_DMA_CTRL_VALID)
1053 
                               and not Regs_WrDin_r1(CINT_BIT_DMA_CTRL_END)
1054 
                               ;
1055 
      end if;
1056 
   end process;
1057 
 
1058 
 
1059 
 
1060 
-- ------------------------------------------------
1061 
-- Synchronous Delay : Regs_WrDin_Hi19b_True_r2 x2
1062 
--                     Regs_WrDin_Lo7b_True_r2 x2
1063 
--
1064 
   Synch_Delay_Regs_WrDin_Hi19b_and_Lo7b_True:
1065 
   process ( trn_clk )
1066 
   begin
1067 
      if trn_clk'event and trn_clk = '1' then
1068 
 
1069 
         if Regs_WrDin_r1(C_DBUS_WIDTH-1 downto C_MAXSIZE_FLD_BIT_TOP+1+32)
1070 
            = C_ALL_ZEROS(C_DBUS_WIDTH-1 downto C_MAXSIZE_FLD_BIT_TOP+1+32)
1071 
            then
1072 
            Regs_WrDin_Hi19b_True_hq_r2  <= '0';
1073 
         else
1074 
            Regs_WrDin_Hi19b_True_hq_r2  <= '1';
1075 
         end if;
1076 
 
1077 
         if Regs_WrDin_r1(C_MAXSIZE_FLD_BIT_BOT-1+32 downto 2+32)
1078 
            = C_ALL_ZEROS(C_MAXSIZE_FLD_BIT_BOT-1+32 downto 2+32)
1079 
            then                               -- ! Lowest 2 bits ignored !
1080 
            Regs_WrDin_Lo7b_True_hq_r2  <= '0';
1081 
         else
1082 
            Regs_WrDin_Lo7b_True_hq_r2  <= '1';
1083 
         end if;
1084 
 
1085 
         if Regs_WrDin_r1(C_DBUS_WIDTH-1-32 downto C_MAXSIZE_FLD_BIT_TOP+1)
1086 
            = C_ALL_ZEROS(C_DBUS_WIDTH-1-32 downto C_MAXSIZE_FLD_BIT_TOP+1)
1087 
            then
1088 
            Regs_WrDin_Hi19b_True_lq_r2  <= '0';
1089 
         else
1090 
            Regs_WrDin_Hi19b_True_lq_r2  <= '1';
1091 
         end if;
1092 
 
1093 
         if Regs_WrDin_r1(C_MAXSIZE_FLD_BIT_BOT-1 downto 2)
1094 
            = C_ALL_ZEROS(C_MAXSIZE_FLD_BIT_BOT-1 downto 2)
1095 
            then                               -- ! Lowest 2 bits ignored !
1096 
            Regs_WrDin_Lo7b_True_lq_r2  <= '0';
1097 
         else
1098 
            Regs_WrDin_Lo7b_True_lq_r2  <= '1';
1099 
         end if;
1100 
 
1101 
      end if;
1102 
   end process;
1103 
 
1104 
 
1105 
 
1106 
-- ---------------------------------------
1107 
--
1108 
   Write_DMA_Registers_Mux:
1109 
   process ( trn_clk, trn_lnk_up_n)
1110 
   begin
1111 
      if trn_lnk_up_n = '1' then
1112 
         Reg_WrMuxer_Hi <= (Others => '0');
1113 
         Reg_WrMuxer_Lo <= (Others => '0');
1114 
 
1115 
      elsif trn_clk'event and trn_clk = '1' then
1116 
 
1117 
         if -- Regs_WrAddr_r1(C_DECODE_BIT_TOP downto C_DECODE_BIT_BOT)=C_REGS_BASE_ADDR(C_DECODE_BIT_TOP downto C_DECODE_BIT_BOT)
1118 
            -- and
1119 
            Regs_WrAddr_r1(C_DECODE_BIT_BOT-1 downto 2)=CONV_STD_LOGIC_VECTOR(0, C_DECODE_BIT_BOT-2)
1120 
            -- and Regs_WrAddr_r1(2-1 downto 0)="00"
1121 
            then
1122 
            Reg_WrMuxer_Hi(0)   <= not Regs_WrMask_r1(1);
1123 
         else
1124 
            Reg_WrMuxer_Hi(0)   <= '0';
1125 
         end if;
1126 
 
1127 
         FOR k IN 1 TO C_NUM_OF_ADDRESSES-1 LOOP
1128 
 
1129 
            if -- Regs_WrAddr_r1(C_DECODE_BIT_TOP downto C_DECODE_BIT_BOT)=C_REGS_BASE_ADDR(C_DECODE_BIT_TOP downto C_DECODE_BIT_BOT)
1130 
               -- and
1131 
               Regs_WrAddr_r1(C_DECODE_BIT_BOT-1 downto 2)=CONV_STD_LOGIC_VECTOR(k, C_DECODE_BIT_BOT-2)
1132 
               -- and Regs_WrAddr_r1(2-1 downto 0)="00"
1133 
               then
1134 
               Reg_WrMuxer_Hi(k)   <= not Regs_WrMask_r1(1);
1135 
            else
1136 
               Reg_WrMuxer_Hi(k)   <= '0';
1137 
            end if;
1138 
 
1139 
            if -- Regs_WrAddr_r1(C_DECODE_BIT_TOP downto C_DECODE_BIT_BOT)=C_REGS_BASE_ADDR(C_DECODE_BIT_TOP downto C_DECODE_BIT_BOT)
1140 
               -- and
1141 
               Regs_WrAddr_r1(C_DECODE_BIT_BOT-1 downto 2)=CONV_STD_LOGIC_VECTOR(k-1, C_DECODE_BIT_BOT-2)
1142 
               -- and Regs_WrAddr_r1(2-1 downto 0)="00"
1143 
               then
1144 
               Reg_WrMuxer_Lo(k)   <= not Regs_WrMask_r1(0);
1145 
            else
1146 
               Reg_WrMuxer_Lo(k)   <= '0';
1147 
            end if;
1148 
 
1149 
         END LOOP;
1150 
 
1151 
      end if;
1152 
   end process;
1153 
 
1154 
 
1155 
 
1156 
--  -----------------------------------------------
1157 
--  System Interrupt Status Control
1158 
--  -----------------------------------------------
1159 
 
1160 
-- -------------------------------------------------------
1161 
-- Synchronous Registered: Sys_Int_Enable_i
1162 
   SysReg_Sys_Int_Enable:
1163 
   process ( trn_clk, trn_lnk_up_n)
1164 
   begin
1165 
      if trn_lnk_up_n = '1' then
1166 
         Sys_Int_Enable_i     <= (OTHERS => '0');
1167 
      elsif trn_clk'event and trn_clk = '1' then
1168 
 
1169 
        if Regs_WrEn_r2='1'
1170 
                    and Reg_WrMuxer_Hi(CINT_ADDR_IRQ_EN)='1'
1171 
                         then
1172 
            Sys_Int_Enable_i(32-1 downto 0) <=  Regs_WrDin_r2(64-1 downto 32);
1173 
        elsif Regs_WrEn_r2='1'
1174 
                    and Reg_WrMuxer_Lo(CINT_ADDR_IRQ_EN)='1'
1175 
                         then
1176 
            Sys_Int_Enable_i(32-1 downto 0) <=  Regs_WrDin_r2(32-1 downto 0);
1177 
        else
1178 
            Sys_Int_Enable_i <=  Sys_Int_Enable_i;
1179 
        end if;
1180 
 
1181 
 
1182 
      end if;
1183 
   end process;
1184 
 
1185 
 
1186 
--  -----------------------------------------------
1187 
--    System General Control Register
1188 
--  -----------------------------------------------
1189 
-- -----------------------------------------------
1190 
-- Synchronous Registered: General_Control
1191 
   SysReg_General_Control:
1192 
   process ( trn_clk, trn_lnk_up_n)
1193 
   begin
1194 
      if trn_lnk_up_n = '1' then
1195 
         General_Control_i     <= (OTHERS => '0');
1196 
         General_Control_i(C_GCR_MSG_ROUT_BIT_TOP downto C_GCR_MSG_ROUT_BIT_BOT)
1197 
                               <= C_TYPE_OF_MSG(C_TLP_TYPE_BIT_BOT+C_GCR_MSG_ROUT_BIT_TOP-C_GCR_MSG_ROUT_BIT_BOT
1198 
                                  downto C_TLP_TYPE_BIT_BOT);
1199 
 
1200 
      elsif trn_clk'event and trn_clk = '1' then
1201 
 
1202 
        if Regs_WrEn_r2='1'
1203 
           and Reg_WrMuxer_Hi(CINT_ADDR_CONTROL)='1'
1204 
           then
1205 
            General_Control_i(32-1 downto 0)  <=  Regs_WrDin_r2(64-1 downto 32);
1206 
        elsif Regs_WrEn_r2='1'
1207 
           and Reg_WrMuxer_Lo(CINT_ADDR_CONTROL)='1'
1208 
           then
1209 
            General_Control_i(32-1 downto 0)  <=  Regs_WrDin_r2(32-1 downto 0);
1210 
        else
1211 
            General_Control_i  <=  General_Control_i;
1212 
        end if;
1213 
 
1214 
      end if;
1215 
   end process;
1216 
 
1217 
-- -----------------------------------------------
1218 
-- Synchronous Registered: DG_Reset_i
1219 
   SysReg_DGen_Reset:
1220 
   process ( trn_clk, trn_lnk_up_n)
1221 
   begin
1222 
      if trn_lnk_up_n = '1' then
1223 
         DG_Reset_i            <= '1';
1224 
         DG_Rst_Counter        <= (OTHERS=>'0');
1225 
 
1226 
      elsif trn_clk'event and trn_clk = '1' then
1227 
 
1228 
        if DG_Rst_Counter=X"FF" then
1229 
           DG_Rst_Counter  <= DG_Rst_Counter;
1230 
        else
1231 
           DG_Rst_Counter  <= DG_Rst_Counter + '1';
1232 
        end if;
1233 
 
1234 
        if DG_Rst_Counter(7)='0' then
1235 
            DG_Reset_i         <=  '1';
1236 
        elsif Regs_WrEn_r2='1'
1237 
                    and Reg_WrMuxer_Hi(CINT_ADDR_DG_CTRL)='1'
1238 
                         then
1239 
            DG_Reset_i         <=  Command_is_Reset_Hi;
1240 
        elsif Regs_WrEn_r2='1'
1241 
                    and Reg_WrMuxer_Lo(CINT_ADDR_DG_CTRL)='1'
1242 
                         then
1243 
            DG_Reset_i         <=  Command_is_Reset_Lo;
1244 
        else
1245 
            DG_Reset_i         <=  '0';
1246 
        end if;
1247 
 
1248 
      end if;
1249 
   end process;
1250 
 
1251 
-- -----------------------------------------------
1252 
-- Synchronous Registered: DG_Mask_i
1253 
   SysReg_DGen_Mask:
1254 
   process ( trn_clk, trn_lnk_up_n)
1255 
   begin
1256 
      if trn_lnk_up_n = '1' then
1257 
         DG_Mask_i     <= '0';
1258 
      elsif trn_clk'event and trn_clk = '1' then
1259 
 
1260 
        if Regs_WrEn_r2='1'
1261 
           and Reg_WrMuxer_Hi(CINT_ADDR_DG_CTRL)='1'
1262 
           then
1263 
           DG_Mask_i  <=  Regs_WrDin_r2(32+CINT_BIT_DG_MASK);
1264 
        elsif Regs_WrEn_r2='1'
1265 
           and Reg_WrMuxer_Lo(CINT_ADDR_DG_CTRL)='1'
1266 
           then
1267 
           DG_Mask_i  <=  Regs_WrDin_r2(CINT_BIT_DG_MASK);
1268 
        else
1269 
           DG_Mask_i  <=  DG_Mask_i;
1270 
        end if;
1271 
 
1272 
      end if;
1273 
   end process;
1274 
 
1275 
--------------------------------------------------------------------------
1276 
--  Data generator status
1277 
--
1278 
   Synch_DG_Status_i:
1279 
   process ( trn_clk, DG_Reset_i )
1280 
   begin
1281 
     if DG_Reset_i = '1' then
1282 
        DG_Status_i    <= (OTHERS=>'0');
1283 
     elsif trn_clk'event and trn_clk = '1' then
1284 
        DG_Status_i(CINT_BIT_DG_MASK)    <= DG_Mask_i;
1285 
        DG_Status_i(CINT_BIT_DG_BUSY)    <= DG_is_Running;
1286 
     end if;
1287 
   end process;
1288 
 
1289 
-- -----------------------------------------------
1290 
-- Synchronous Registered: IG_Control_i
1291 
   SysReg_IntGen_Control:
1292 
   process ( trn_clk, trn_lnk_up_n)
1293 
   begin
1294 
      if trn_lnk_up_n = '1' then
1295 
         IG_Control_i          <= (OTHERS => '0');
1296 
         IG_Reset_i            <= '1';
1297 
         IG_Host_Clear_i       <= '0';
1298 
 
1299 
      elsif trn_clk'event and trn_clk = '1' then
1300 
 
1301 
        if Regs_WrEn_r2='1'
1302 
                    and Reg_WrMuxer_Hi(CINT_ADDR_IG_CONTROL)='1'
1303 
                         then
1304 
            IG_Control_i(32-1 downto 0)       <=  Regs_WrDin_r2(64-1 downto 32);
1305 
            IG_Reset_i         <=  Command_is_Reset_Hi;
1306 
            IG_Host_Clear_i    <=  Command_is_Host_iClr_Hi;
1307 
        elsif Regs_WrEn_r2='1'
1308 
                    and Reg_WrMuxer_Lo(CINT_ADDR_IG_CONTROL)='1'
1309 
                         then
1310 
            IG_Control_i(32-1 downto 0)       <=  Regs_WrDin_r2(32-1 downto 0);
1311 
            IG_Reset_i         <=  Command_is_Reset_Lo;
1312 
            IG_Host_Clear_i    <=  Command_is_Host_iClr_Lo;
1313 
        else
1314 
            IG_Control_i       <=  IG_Control_i;
1315 
            IG_Reset_i         <=  '0';
1316 
            IG_Host_Clear_i    <=  '0';
1317 
        end if;
1318 
 
1319 
      end if;
1320 
   end process;
1321 
 
1322 
 
1323 
-- -----------------------------------------------
1324 
-- Synchronous Registered: IG_Latency_i
1325 
   SysReg_IntGen_Latency:
1326 
   process ( trn_clk, trn_lnk_up_n)
1327 
   begin
1328 
      if trn_lnk_up_n = '1' then
1329 
         IG_Latency_i       <= (OTHERS => '0');
1330 
 
1331 
      elsif trn_clk'event and trn_clk = '1' then
1332 
 
1333 
        if IG_Reset_i='1' then
1334 
            IG_Latency_i    <=  (OTHERS => '0');
1335 
        elsif Regs_WrEn_r2='1'
1336 
                    and Reg_WrMuxer_Hi(CINT_ADDR_IG_LATENCY)='1'
1337 
                         then
1338 
            IG_Latency_i(32-1 downto 0)    <=  Regs_WrDin_r2(64-1 downto 32);
1339 
        elsif Regs_WrEn_r2='1'
1340 
                    and Reg_WrMuxer_Lo(CINT_ADDR_IG_LATENCY)='1'
1341 
                         then
1342 
            IG_Latency_i(32-1 downto 0)    <=  Regs_WrDin_r2(32-1 downto 0);
1343 
        else
1344 
            IG_Latency_i    <=  IG_Latency_i;
1345 
        end if;
1346 
 
1347 
      end if;
1348 
   end process;
1349 
 
1350 
 
1351 
 
1352 
 
1353 
--  ------------------------------------------------------
1354 
--      Protocol CTL interface
1355 
--  ------------------------------------------------------
1356 
 
1357 
-- -------------------------------------------------------
1358 
-- Synchronous Registered: ctl_rd
1359 
   Syn_CTL_rd:
1360 
   process ( trn_clk, trn_lnk_up_n)
1361 
   begin
1362 
      if trn_lnk_up_n = '1' then
1363 
         ctl_rd_i     <= (OTHERS => '0');
1364 
         ctl_rv_i     <= '0';
1365 
      elsif trn_clk'event and trn_clk = '1' then
1366 
 
1367 
         if Regs_WrEn_r2='1' and Reg_WrMuxer_Hi(CINT_ADDR_CTL_CLASS)='1' then
1368 
            ctl_rd_i     <= Regs_WrDin_r2(C_DBUS_WIDTH-1 downto 32);
1369 
            ctl_rv_i     <= '1';
1370 
         elsif Regs_WrEn_r2='1' and Reg_WrMuxer_Lo(CINT_ADDR_CTL_CLASS)='1' then
1371 
            ctl_rd_i     <= Regs_WrDin_r2(32-1 downto 0);
1372 
            ctl_rv_i     <= '1';
1373 
         else
1374 
            ctl_rd_i     <= ctl_rd_i;
1375 
            ctl_rv_i     <= '0';
1376 
         end if;
1377 
 
1378 
      end if;
1379 
   end process;
1380 
 
1381 
 
1382 
-- -----------------------------------------------
1383 
-- Synchronous Registered: ctl_reset
1384 
   SysReg_ctl_reset:
1385 
   process ( trn_clk, trn_lnk_up_n)
1386 
   begin
1387 
      if trn_lnk_up_n = '1' then
1388 
         ctl_reset_i            <= '1';
1389 
 
1390 
      elsif trn_clk'event and trn_clk = '1' then
1391 
 
1392 
        if Regs_WrEn_r2='1'
1393 
                    and Reg_WrMuxer_Hi(CINT_ADDR_TC_STATUS)='1'
1394 
                         then
1395 
            ctl_reset_i         <=  Command_is_Reset_Hi;
1396 
        elsif Regs_WrEn_r2='1'
1397 
                    and Reg_WrMuxer_Lo(CINT_ADDR_TC_STATUS)='1'
1398 
                         then
1399 
            ctl_reset_i         <=  Command_is_Reset_Lo;
1400 
        else
1401 
            ctl_reset_i         <=  '0';
1402 
        end if;
1403 
 
1404 
      end if;
1405 
   end process;
1406 
 
1407 
 
1408 
 
1409 
-- -------------------------------------------------------
1410 
-- Synchronous Registered: ctl_td
1411 
--    ++++++++++++ INT triggering  ++++++++++++++++++
1412 
   Syn_CTL_td:
1413 
   process ( trn_clk, trn_lnk_up_n)
1414 
   begin
1415 
      if trn_lnk_up_n = '1' then
1416 
         ctl_td_r     <= (OTHERS => '0');
1417 
      elsif trn_clk'event and trn_clk = '1' then
1418 
 
1419 
         if ctl_tv='1' then
1420 
            ctl_td_r     <= ctl_td;
1421 
         else
1422 
            ctl_td_r     <= ctl_td_r;
1423 
         end if;
1424 
 
1425 
      end if;
1426 
   end process;
1427 
 
1428 
 
1429 
 
1430 
 
1431 
--  ------------------------------------------------------
1432 
--      SIMONE USER REGISTER td
1433 
--  ------------------------------------------------------
1434 
   SIMONE_Reg01_td:
1435 
   process ( trn_clk, trn_lnk_up_n)
1436 
   begin
1437 
      if trn_lnk_up_n = '1' then
1438 
         reg01_td_i     <= (OTHERS => '0');
1439 
         reg01_tv_i     <= '0';
1440 
      elsif trn_clk'event and trn_clk = '1' then
1441 
         if Regs_WrEn_r2='1' and Reg_WrMuxer_Hi(CINT_ADDR_REG01)='1' then
1442 
            reg01_td_i     <= Regs_WrDin_r2(C_DBUS_WIDTH-1 downto 32);
1443 
            reg01_tv_i     <= '1';
1444 
         elsif Regs_WrEn_r2='1' and Reg_WrMuxer_Lo(CINT_ADDR_REG01)='1' then
1445 
            reg01_td_i     <= Regs_WrDin_r2(32-1 downto 0);
1446 
            reg01_tv_i     <= '1';
1447 
         else
1448 
            reg01_td_i     <= reg01_td_i;
1449 
            reg01_tv_i     <= '0';
1450 
         end if;
1451 
      end if;
1452 
   end process;
1453 
 
1454 
   SIMONE_Reg02_td:
1455 
   process ( trn_clk, trn_lnk_up_n)
1456 
   begin
1457 
      if trn_lnk_up_n = '1' then
1458 
         reg02_td_i     <= (OTHERS => '0');
1459 
         reg02_tv_i     <= '0';
1460 
      elsif trn_clk'event and trn_clk = '1' then
1461 
         if Regs_WrEn_r2='1' and Reg_WrMuxer_Hi(CINT_ADDR_REG02)='1' then
1462 
            reg02_td_i     <= Regs_WrDin_r2(C_DBUS_WIDTH-1 downto 32);
1463 
            reg02_tv_i     <= '1';
1464 
         elsif Regs_WrEn_r2='1' and Reg_WrMuxer_Lo(CINT_ADDR_REG02)='1' then
1465 
            reg02_td_i     <= Regs_WrDin_r2(32-1 downto 0);
1466 
            reg02_tv_i     <= '1';
1467 
         else
1468 
            reg02_td_i     <= reg02_td_i;
1469 
            reg02_tv_i     <= '0';
1470 
         end if;
1471 
      end if;
1472 
   end process;
1473 
 
1474 
   SIMONE_Reg03_td:
1475 
   process ( trn_clk, trn_lnk_up_n)
1476 
   begin
1477 
      if trn_lnk_up_n = '1' then
1478 
         reg03_td_i     <= (OTHERS => '0');
1479 
         reg03_tv_i     <= '0';
1480 
      elsif trn_clk'event and trn_clk = '1' then
1481 
         if Regs_WrEn_r2='1' and Reg_WrMuxer_Hi(CINT_ADDR_REG03)='1' then
1482 
            reg03_td_i     <= Regs_WrDin_r2(C_DBUS_WIDTH-1 downto 32);
1483 
            reg03_tv_i     <= '1';
1484 
         elsif Regs_WrEn_r2='1' and Reg_WrMuxer_Lo(CINT_ADDR_REG03)='1' then
1485 
            reg03_td_i     <= Regs_WrDin_r2(32-1 downto 0);
1486 
            reg03_tv_i     <= '1';
1487 
         else
1488 
            reg03_td_i     <= reg03_td_i;
1489 
            reg03_tv_i     <= '0';
1490 
         end if;
1491 
      end if;
1492 
   end process;
1493 
 
1494 
 
1495 
 
1496 
--------
1497 
 
1498 
   SIMONE_Reg04_td:
1499 
   process ( trn_clk, trn_lnk_up_n)
1500 
   begin
1501 
      if trn_lnk_up_n = '1' then
1502 
         reg04_td_i     <= (OTHERS => '0');
1503 
         reg04_tv_i     <= '0';
1504 
      elsif trn_clk'event and trn_clk = '1' then
1505 
         if Regs_WrEn_r2='1' and Reg_WrMuxer_Hi(CINT_ADDR_REG04)='1' then
1506 
            reg04_td_i     <= Regs_WrDin_r2(C_DBUS_WIDTH-1 downto 32);
1507 
            reg04_tv_i     <= '1';
1508 
         elsif Regs_WrEn_r2='1' and Reg_WrMuxer_Lo(CINT_ADDR_REG04)='1' then
1509 
            reg04_td_i     <= Regs_WrDin_r2(32-1 downto 0);
1510 
            reg04_tv_i     <= '1';
1511 
         else
1512 
            reg04_td_i     <= reg04_td_i;
1513 
            reg04_tv_i     <= '0';
1514 
         end if;
1515 
      end if;
1516 
   end process;
1517 
 
1518 
           SIMONE_Reg05_td:
1519 
   process ( trn_clk, trn_lnk_up_n)
1520 
   begin
1521 
      if trn_lnk_up_n = '1' then
1522 
         reg05_td_i     <= (OTHERS => '0');
1523 
         reg05_tv_i     <= '0';
1524 
      elsif trn_clk'event and trn_clk = '1' then
1525 
         if Regs_WrEn_r2='1' and Reg_WrMuxer_Hi(CINT_ADDR_REG05)='1' then
1526 
            reg05_td_i     <= Regs_WrDin_r2(C_DBUS_WIDTH-1 downto 32);
1527 
            reg05_tv_i     <= '1';
1528 
         elsif Regs_WrEn_r2='1' and Reg_WrMuxer_Lo(CINT_ADDR_REG05)='1' then
1529 
            reg05_td_i     <= Regs_WrDin_r2(32-1 downto 0);
1530 
            reg05_tv_i     <= '1';
1531 
         else
1532 
            reg05_td_i     <= reg05_td_i;
1533 
            reg05_tv_i     <= '0';
1534 
         end if;
1535 
      end if;
1536 
   end process;
1537 
 
1538 
           SIMONE_Reg06_td:
1539 
   process ( trn_clk, trn_lnk_up_n)
1540 
   begin
1541 
      if trn_lnk_up_n = '1' then
1542 
         reg06_td_i     <= (OTHERS => '0');
1543 
         reg06_tv_i     <= '0';
1544 
      elsif trn_clk'event and trn_clk = '1' then
1545 
         if Regs_WrEn_r2='1' and Reg_WrMuxer_Hi(CINT_ADDR_REG06)='1' then
1546 
            reg06_td_i     <= Regs_WrDin_r2(C_DBUS_WIDTH-1 downto 32);
1547 
            reg06_tv_i     <= '1';
1548 
         elsif Regs_WrEn_r2='1' and Reg_WrMuxer_Lo(CINT_ADDR_REG06)='1' then
1549 
            reg06_td_i     <= Regs_WrDin_r2(32-1 downto 0);
1550 
            reg06_tv_i     <= '1';
1551 
         else
1552 
            reg06_td_i     <= reg06_td_i;
1553 
            reg06_tv_i     <= '0';
1554 
         end if;
1555 
      end if;
1556 
   end process;
1557 
 
1558 
           SIMONE_Reg07_td:
1559 
   process ( trn_clk, trn_lnk_up_n)
1560 
   begin
1561 
      if trn_lnk_up_n = '1' then
1562 
         reg07_td_i     <= (OTHERS => '0');
1563 
         reg07_tv_i     <= '0';
1564 
      elsif trn_clk'event and trn_clk = '1' then
1565 
         if Regs_WrEn_r2='1' and Reg_WrMuxer_Hi(CINT_ADDR_REG07)='1' then
1566 
            reg07_td_i     <= Regs_WrDin_r2(C_DBUS_WIDTH-1 downto 32);
1567 
            reg07_tv_i     <= '1';
1568 
         elsif Regs_WrEn_r2='1' and Reg_WrMuxer_Lo(CINT_ADDR_REG07)='1' then
1569 
            reg07_td_i     <= Regs_WrDin_r2(32-1 downto 0);
1570 
            reg07_tv_i     <= '1';
1571 
         else
1572 
            reg07_td_i     <= reg07_td_i;
1573 
            reg07_tv_i     <= '0';
1574 
         end if;
1575 
      end if;
1576 
   end process;
1577 
 
1578 
           SIMONE_Reg08_td:
1579 
   process ( trn_clk, trn_lnk_up_n)
1580 
   begin
1581 
      if trn_lnk_up_n = '1' then
1582 
         reg08_td_i     <= (OTHERS => '0');
1583 
         reg08_tv_i     <= '0';
1584 
      elsif trn_clk'event and trn_clk = '1' then
1585 
         if Regs_WrEn_r2='1' and Reg_WrMuxer_Hi(CINT_ADDR_REG08)='1' then
1586 
            reg08_td_i     <= Regs_WrDin_r2(C_DBUS_WIDTH-1 downto 32);
1587 
            reg08_tv_i     <= '1';
1588 
         elsif Regs_WrEn_r2='1' and Reg_WrMuxer_Lo(CINT_ADDR_REG08)='1' then
1589 
            reg08_td_i     <= Regs_WrDin_r2(32-1 downto 0);
1590 
            reg08_tv_i     <= '1';
1591 
         else
1592 
            reg08_td_i     <= reg08_td_i;
1593 
            reg08_tv_i     <= '0';
1594 
         end if;
1595 
      end if;
1596 
   end process;
1597 
 
1598 
                   SIMONE_Reg09_td:
1599 
   process ( trn_clk, trn_lnk_up_n)
1600 
   begin
1601 
      if trn_lnk_up_n = '1' then
1602 
         reg09_td_i     <= (OTHERS => '0');
1603 
         reg09_tv_i     <= '0';
1604 
      elsif trn_clk'event and trn_clk = '1' then
1605 
         if Regs_WrEn_r2='1' and Reg_WrMuxer_Hi(CINT_ADDR_REG09)='1' then
1606 
            reg09_td_i     <= Regs_WrDin_r2(C_DBUS_WIDTH-1 downto 32);
1607 
            reg09_tv_i     <= '1';
1608 
         elsif Regs_WrEn_r2='1' and Reg_WrMuxer_Lo(CINT_ADDR_REG09)='1' then
1609 
            reg09_td_i     <= Regs_WrDin_r2(32-1 downto 0);
1610 
            reg09_tv_i     <= '1';
1611 
         else
1612 
            reg09_td_i     <= reg09_td_i;
1613 
            reg09_tv_i     <= '0';
1614 
         end if;
1615 
      end if;
1616 
   end process;
1617 
 
1618 
                   SIMONE_Reg10_td:
1619 
   process ( trn_clk, trn_lnk_up_n)
1620 
   begin
1621 
      if trn_lnk_up_n = '1' then
1622 
         reg10_td_i     <= (OTHERS => '0');
1623 
         reg10_tv_i     <= '0';
1624 
      elsif trn_clk'event and trn_clk = '1' then
1625 
         if Regs_WrEn_r2='1' and Reg_WrMuxer_Hi(CINT_ADDR_REG10)='1' then
1626 
            reg10_td_i     <= Regs_WrDin_r2(C_DBUS_WIDTH-1 downto 32);
1627 
            reg10_tv_i     <= '1';
1628 
         elsif Regs_WrEn_r2='1' and Reg_WrMuxer_Lo(CINT_ADDR_REG10)='1' then
1629 
            reg10_td_i     <= Regs_WrDin_r2(32-1 downto 0);
1630 
            reg10_tv_i     <= '1';
1631 
         else
1632 
            reg10_td_i     <= reg10_td_i;
1633 
            reg10_tv_i     <= '0';
1634 
         end if;
1635 
      end if;
1636 
   end process;
1637 
 
1638 
 
1639 
 
1640 
                   SIMONE_Reg11_td:
1641 
   process ( trn_clk, trn_lnk_up_n)
1642 
   begin
1643 
      if trn_lnk_up_n = '1' then
1644 
         reg11_td_i     <= (OTHERS => '0');
1645 
         reg11_tv_i     <= '0';
1646 
      elsif trn_clk'event and trn_clk = '1' then
1647 
         if Regs_WrEn_r2='1' and Reg_WrMuxer_Hi(CINT_ADDR_REG11)='1' then
1648 
            reg11_td_i     <= Regs_WrDin_r2(C_DBUS_WIDTH-1 downto 32);
1649 
            reg11_tv_i     <= '1';
1650 
         elsif Regs_WrEn_r2='1' and Reg_WrMuxer_Lo(CINT_ADDR_REG11)='1' then
1651 
            reg11_td_i     <= Regs_WrDin_r2(32-1 downto 0);
1652 
            reg11_tv_i     <= '1';
1653 
         else
1654 
            reg11_td_i     <= reg11_td_i;
1655 
            reg11_tv_i     <= '0';
1656 
         end if;
1657 
      end if;
1658 
   end process;
1659 
                   SIMONE_Reg12_td:
1660 
   process ( trn_clk, trn_lnk_up_n)
1661 
   begin
1662 
      if trn_lnk_up_n = '1' then
1663 
         reg12_td_i     <= (OTHERS => '0');
1664 
         reg12_tv_i     <= '0';
1665 
      elsif trn_clk'event and trn_clk = '1' then
1666 
         if Regs_WrEn_r2='1' and Reg_WrMuxer_Hi(CINT_ADDR_REG12)='1' then
1667 
            reg12_td_i     <= Regs_WrDin_r2(C_DBUS_WIDTH-1 downto 32);
1668 
            reg12_tv_i     <= '1';
1669 
         elsif Regs_WrEn_r2='1' and Reg_WrMuxer_Lo(CINT_ADDR_REG12)='1' then
1670 
            reg12_td_i     <= Regs_WrDin_r2(32-1 downto 0);
1671 
            reg12_tv_i     <= '1';
1672 
         else
1673 
            reg12_td_i     <= reg12_td_i;
1674 
            reg12_tv_i     <= '0';
1675 
         end if;
1676 
      end if;
1677 
   end process;
1678 
                   SIMONE_Reg13_td:
1679 
   process ( trn_clk, trn_lnk_up_n)
1680 
   begin
1681 
      if trn_lnk_up_n = '1' then
1682 
         reg13_td_i     <= (OTHERS => '0');
1683 
         reg13_tv_i     <= '0';
1684 
      elsif trn_clk'event and trn_clk = '1' then
1685 
         if Regs_WrEn_r2='1' and Reg_WrMuxer_Hi(CINT_ADDR_REG13)='1' then
1686 
            reg13_td_i     <= Regs_WrDin_r2(C_DBUS_WIDTH-1 downto 32);
1687 
            reg13_tv_i     <= '1';
1688 
         elsif Regs_WrEn_r2='1' and Reg_WrMuxer_Lo(CINT_ADDR_REG13)='1' then
1689 
            reg13_td_i     <= Regs_WrDin_r2(32-1 downto 0);
1690 
            reg13_tv_i     <= '1';
1691 
         else
1692 
            reg13_td_i     <= reg13_td_i;
1693 
            reg13_tv_i     <= '0';
1694 
         end if;
1695 
      end if;
1696 
   end process;
1697 
                   SIMONE_Reg14_td:
1698 
   process ( trn_clk, trn_lnk_up_n)
1699 
   begin
1700 
      if trn_lnk_up_n = '1' then
1701 
         reg14_td_i     <= (OTHERS => '0');
1702 
         reg14_tv_i     <= '0';
1703 
      elsif trn_clk'event and trn_clk = '1' then
1704 
         if Regs_WrEn_r2='1' and Reg_WrMuxer_Hi(CINT_ADDR_REG14)='1' then
1705 
            reg14_td_i     <= Regs_WrDin_r2(C_DBUS_WIDTH-1 downto 32);
1706 
            reg14_tv_i     <= '1';
1707 
         elsif Regs_WrEn_r2='1' and Reg_WrMuxer_Lo(CINT_ADDR_REG14)='1' then
1708 
            reg14_td_i     <= Regs_WrDin_r2(32-1 downto 0);
1709 
            reg14_tv_i     <= '1';
1710 
         else
1711 
            reg14_td_i     <= reg14_td_i;
1712 
            reg14_tv_i     <= '0';
1713 
         end if;
1714 
      end if;
1715 
   end process;
1716 
--------
1717 
 
1718 
 
1719 
-- -------------------------------------------------------
1720 
 
1721 
 
1722 
-- -------------------------------------------------------
1723 
--      SIMONE USER REGISTER rd
1724 
--  ------------------------------------------------------
1725 
        SIMONE_Reg01_rd:
1726 
   process ( trn_clk, trn_lnk_up_n)
1727 
   begin
1728 
      if trn_lnk_up_n = '1' then
1729 
         reg01_rd_r     <= (OTHERS => '0');
1730 
      elsif trn_clk'event and trn_clk = '1' then
1731 
         if reg01_rv='1' then
1732 
            reg01_rd_r     <= reg01_rd;
1733 
        else
1734 
            reg01_rd_r     <= reg01_rd_r;
1735 
         end if;
1736 
      end if;
1737 
   end process;
1738 
 
1739 
        SIMONE_Reg02_rd:
1740 
   process ( trn_clk, trn_lnk_up_n)
1741 
   begin
1742 
      if trn_lnk_up_n = '1' then
1743 
         reg02_rd_r     <= (OTHERS => '0');
1744 
      elsif trn_clk'event and trn_clk = '1' then
1745 
         if reg02_rv='1' then
1746 
            reg02_rd_r     <= reg02_rd;
1747 
        else
1748 
            reg02_rd_r     <= reg02_rd_r;
1749 
         end if;
1750 
      end if;
1751 
   end process;
1752 
 
1753 
        SIMONE_Reg03_rd:
1754 
   process ( trn_clk, trn_lnk_up_n)
1755 
   begin
1756 
      if trn_lnk_up_n = '1' then
1757 
         reg03_rd_r     <= (OTHERS => '0');
1758 
      elsif trn_clk'event and trn_clk = '1' then
1759 
         if reg03_rv='1' then
1760 
            reg03_rd_r     <= reg03_rd;
1761 
        else
1762 
            reg03_rd_r     <= reg03_rd_r;
1763 
         end if;
1764 
      end if;
1765 
   end process;
1766 
 
1767 
---
1768 
 
1769 
        SIMONE_Reg04_rd:
1770 
   process ( trn_clk, trn_lnk_up_n)
1771 
   begin
1772 
      if trn_lnk_up_n = '1' then
1773 
         reg04_rd_r     <= (OTHERS => '0');
1774 
      elsif trn_clk'event and trn_clk = '1' then
1775 
         if reg04_rv='1' then
1776 
            reg04_rd_r     <= reg04_rd;
1777 
        else
1778 
            reg04_rd_r     <= reg04_rd_r;
1779 
         end if;
1780 
      end if;
1781 
   end process;
1782 
                SIMONE_Reg05_rd:
1783 
   process ( trn_clk, trn_lnk_up_n)
1784 
   begin
1785 
      if trn_lnk_up_n = '1' then
1786 
         reg05_rd_r     <= (OTHERS => '0');
1787 
      elsif trn_clk'event and trn_clk = '1' then
1788 
         if reg05_rv='1' then
1789 
            reg05_rd_r     <= reg05_rd;
1790 
        else
1791 
            reg05_rd_r     <= reg05_rd_r;
1792 
         end if;
1793 
      end if;
1794 
   end process;
1795 
                SIMONE_Reg06_rd:
1796 
   process ( trn_clk, trn_lnk_up_n)
1797 
   begin
1798 
      if trn_lnk_up_n = '1' then
1799 
         reg06_rd_r     <= (OTHERS => '0');
1800 
      elsif trn_clk'event and trn_clk = '1' then
1801 
         if reg06_rv='1' then
1802 
            reg06_rd_r     <= reg06_rd;
1803 
        else
1804 
            reg06_rd_r     <= reg06_rd_r;
1805 
         end if;
1806 
      end if;
1807 
   end process;
1808 
                SIMONE_Reg07_rd:
1809 
   process ( trn_clk, trn_lnk_up_n)
1810 
   begin
1811 
      if trn_lnk_up_n = '1' then
1812 
         reg07_rd_r     <= (OTHERS => '0');
1813 
      elsif trn_clk'event and trn_clk = '1' then
1814 
         if reg07_rv='1' then
1815 
            reg07_rd_r     <= reg07_rd;
1816 
        else
1817 
            reg07_rd_r     <= reg07_rd_r;
1818 
         end if;
1819 
      end if;
1820 
   end process;
1821 
                SIMONE_Reg08_rd:
1822 
   process ( trn_clk, trn_lnk_up_n)
1823 
   begin
1824 
      if trn_lnk_up_n = '1' then
1825 
         reg08_rd_r     <= (OTHERS => '0');
1826 
      elsif trn_clk'event and trn_clk = '1' then
1827 
         if reg08_rv='1' then
1828 
            reg08_rd_r     <= reg08_rd;
1829 
        else
1830 
            reg08_rd_r     <= reg08_rd_r;
1831 
         end if;
1832 
      end if;
1833 
   end process;
1834 
        SIMONE_Reg09_rd:
1835 
   process ( trn_clk, trn_lnk_up_n)
1836 
   begin
1837 
      if trn_lnk_up_n = '1' then
1838 
         reg09_rd_r     <= (OTHERS => '0');
1839 
      elsif trn_clk'event and trn_clk = '1' then
1840 
         if reg09_rv='1' then
1841 
            reg09_rd_r     <= reg09_rd;
1842 
        else
1843 
            reg09_rd_r     <= reg09_rd_r;
1844 
         end if;
1845 
      end if;
1846 
   end process;
1847 
        SIMONE_Reg10_rd:
1848 
   process ( trn_clk, trn_lnk_up_n)
1849 
   begin
1850 
      if trn_lnk_up_n = '1' then
1851 
         reg10_rd_r     <= (OTHERS => '0');
1852 
      elsif trn_clk'event and trn_clk = '1' then
1853 
         if reg10_rv='1' then
1854 
            reg10_rd_r     <= reg10_rd;
1855 
        else
1856 
            reg10_rd_r     <= reg10_rd_r;
1857 
         end if;
1858 
      end if;
1859 
   end process;
1860 
        SIMONE_Reg11_rd:
1861 
   process ( trn_clk, trn_lnk_up_n)
1862 
   begin
1863 
      if trn_lnk_up_n = '1' then
1864 
         reg11_rd_r     <= (OTHERS => '0');
1865 
      elsif trn_clk'event and trn_clk = '1' then
1866 
         if reg11_rv='1' then
1867 
            reg11_rd_r     <= reg11_rd;
1868 
        else
1869 
            reg11_rd_r     <= reg11_rd_r;
1870 
         end if;
1871 
      end if;
1872 
   end process;
1873 
        SIMONE_Reg12_rd:
1874 
   process ( trn_clk, trn_lnk_up_n)
1875 
   begin
1876 
      if trn_lnk_up_n = '1' then
1877 
         reg12_rd_r     <= (OTHERS => '0');
1878 
      elsif trn_clk'event and trn_clk = '1' then
1879 
         if reg12_rv='1' then
1880 
            reg12_rd_r     <= reg12_rd;
1881 
        else
1882 
            reg12_rd_r     <= reg12_rd_r;
1883 
         end if;
1884 
      end if;
1885 
   end process;
1886 
        SIMONE_Reg13_rd:
1887 
   process ( trn_clk, trn_lnk_up_n)
1888 
   begin
1889 
      if trn_lnk_up_n = '1' then
1890 
         reg13_rd_r     <= (OTHERS => '0');
1891 
      elsif trn_clk'event and trn_clk = '1' then
1892 
         if reg13_rv='1' then
1893 
            reg13_rd_r     <= reg13_rd;
1894 
        else
1895 
            reg13_rd_r     <= reg13_rd_r;
1896 
         end if;
1897 
      end if;
1898 
   end process;
1899 
        SIMONE_Reg14_rd:
1900 
   process ( trn_clk, trn_lnk_up_n)
1901 
   begin
1902 
      if trn_lnk_up_n = '1' then
1903 
         reg14_rd_r     <= (OTHERS => '0');
1904 
      elsif trn_clk'event and trn_clk = '1' then
1905 
         if reg14_rv='1' then
1906 
            reg14_rd_r     <= reg14_rd;
1907 
        else
1908 
            reg14_rd_r     <= reg14_rd_r;
1909 
         end if;
1910 
      end if;
1911 
   end process;
1912 
---
1913 
 
1914 
-- -------------------------------------------------------
1915 
 
1916 
 
1917 
 
1918 
 
1919 
 
1920 
 
1921 
 
1922 
 
1923 
 
1924 
 
1925 
--  ------------------------------------------------------
1926 
--      Protocol DLM interface
1927 
--  ------------------------------------------------------
1928 
 
1929 
-- -------------------------------------------------------
1930 
-- Synchronous Registered: dlm_td
1931 
   Syn_DLM_td:
1932 
   process ( trn_clk, trn_lnk_up_n)
1933 
   begin
1934 
      if trn_lnk_up_n = '1' then
1935 
         dlm_td_i     <= (OTHERS => '0');
1936 
         dlm_tv_i     <= '0';
1937 
      elsif trn_clk'event and trn_clk = '1' then
1938 
 
1939 
         if Regs_WrEn_r2='1' and Reg_WrMuxer_Hi(CINT_ADDR_DLM_CLASS)='1' then
1940 
            dlm_td_i     <= Regs_WrDin_r2(C_DBUS_WIDTH-1 downto 32);
1941 
            dlm_tv_i     <= '1';
1942 
         elsif Regs_WrEn_r2='1' and Reg_WrMuxer_Lo(CINT_ADDR_DLM_CLASS)='1' then
1943 
            dlm_td_i     <= Regs_WrDin_r2(32-1 downto 0);
1944 
            dlm_tv_i     <= '1';
1945 
         else
1946 
            dlm_td_i     <= dlm_td_i;
1947 
            dlm_tv_i     <= '0';
1948 
         end if;
1949 
 
1950 
      end if;
1951 
   end process;
1952 
 
1953 
 
1954 
-- -------------------------------------------------------
1955 
-- Synchronous Registered: dlm_rd
1956 
--    ++++++++++++ INT triggering  ++++++++++++++++++
1957 
   Syn_DLM_rd:
1958 
   process ( trn_clk, trn_lnk_up_n)
1959 
   begin
1960 
      if trn_lnk_up_n = '1' then
1961 
         dlm_rd_r     <= (OTHERS => '0');
1962 
      elsif trn_clk'event and trn_clk = '1' then
1963 
 
1964 
         if dlm_rv='1' then
1965 
            dlm_rd_r     <= dlm_rd;
1966 
         else
1967 
            dlm_rd_r     <= dlm_rd_r;
1968 
         end if;
1969 
 
1970 
      end if;
1971 
   end process;
1972 
 
1973 
 
1974 
--  ------------------------------------------------------
1975 
--  DMA Upstream Registers
1976 
--  ------------------------------------------------------
1977 
 
1978 
-- -------------------------------------------------------
1979 
-- Synchronous Registered: DMA_us_PA_i
1980 
   RxTrn_DMA_us_PA:
1981 
   process ( trn_clk, trn_lnk_up_n)
1982 
   begin
1983 
      if trn_lnk_up_n = '1' then
1984 
         DMA_us_PA_i  <= (OTHERS => '0');
1985 
      elsif trn_clk'event and trn_clk = '1' then
1986 
 
1987 
        if usDMA_Channel_Rst_i = '1' then
1988 
            DMA_us_PA_i <= (OTHERS => '0');
1989 
        else
1990 
 
1991 
          if Regs_WrEn_r2='1' and Reg_WrMuxer_Hi(CINT_ADDR_DMA_US_PAH)='1' then
1992 
            DMA_us_PA_i(C_DBUS_WIDTH-1 downto 32)  <= Regs_WrDin_r2(64-1 downto 32);
1993 
          elsif Regs_WrEn_r2='1' and Reg_WrMuxer_Lo(CINT_ADDR_DMA_US_PAH)='1' then
1994 
            DMA_us_PA_i(C_DBUS_WIDTH-1 downto 32)  <= Regs_WrDin_r2(32-1 downto 0);
1995 
          else
1996 
            DMA_us_PA_i(C_DBUS_WIDTH-1 downto 32)  <= DMA_us_PA_i(C_DBUS_WIDTH-1 downto 32);
1997 
          end if;
1998 
 
1999 
          if Regs_WrEn_r2='1' and Reg_WrMuxer_Hi(CINT_ADDR_DMA_US_PAL)='1' then
2000 
            DMA_us_PA_i(32-1 downto 0)  <= Regs_WrDin_r2(64-1 downto 32);
2001 
          elsif Regs_WrEn_r2='1' and Reg_WrMuxer_Lo(CINT_ADDR_DMA_US_PAL)='1' then
2002 
            DMA_us_PA_i(32-1 downto 0)  <= Regs_WrDin_r2(32-1 downto 0);
2003 
          else
2004 
            DMA_us_PA_i(32-1 downto 0)  <= DMA_us_PA_i(32-1 downto 0);
2005 
          end if;
2006 
 
2007 
        end if;
2008 
 
2009 
      end if;
2010 
   end process;
2011 
 
2012 
 
2013 
-- -------------------------------------------------------
2014 
-- Synchronous Registered: DMA_us_HA_i
2015 
   RxTrn_DMA_us_HA:
2016 
   process ( trn_clk, trn_lnk_up_n)
2017 
   begin
2018 
      if trn_lnk_up_n = '1' then
2019 
         DMA_us_HA_i     <= (OTHERS => '1');
2020 
         usHA_is_64b_i   <= '0';
2021 
 
2022 
      elsif trn_clk'event and trn_clk = '1' then
2023 
 
2024 
        if usDMA_Channel_Rst_i = '1' then
2025 
            DMA_us_HA_i <= (OTHERS => '1');
2026 
            usHA_is_64b_i <= '0';
2027 
        else
2028 
 
2029 
          if Regs_WrEn_r2='1' and Reg_WrMuxer_Hi(CINT_ADDR_DMA_US_HAH)='1' then
2030 
            DMA_us_HA_i(C_DBUS_WIDTH-1 downto 32)  <= Regs_WrDin_r2(64-1 downto 32);
2031 
            usHA_is_64b_i   <=  WrDin_r2_not_Zero_Hi;
2032 
          elsif Regs_WrEn_r2='1' and Reg_WrMuxer_Lo(CINT_ADDR_DMA_US_HAH)='1' then
2033 
            DMA_us_HA_i(C_DBUS_WIDTH-1 downto 32)  <= Regs_WrDin_r2(32-1 downto 0);
2034 
            usHA_is_64b_i   <=  WrDin_r2_not_Zero_Lo;
2035 
          else
2036 
            DMA_us_HA_i(C_DBUS_WIDTH-1 downto 32)  <= DMA_us_HA_i(C_DBUS_WIDTH-1 downto 32);
2037 
            usHA_is_64b_i   <=  usHA_is_64b_i;
2038 
          end if;
2039 
 
2040 
          if Regs_WrEn_r2='1' and Reg_WrMuxer_Hi(CINT_ADDR_DMA_US_HAL)='1' then
2041 
            DMA_us_HA_i(32-1 downto 0)  <= Regs_WrDin_r2(64-1 downto 32);
2042 
          elsif Regs_WrEn_r2='1' and Reg_WrMuxer_Lo(CINT_ADDR_DMA_US_HAL)='1' then
2043 
            DMA_us_HA_i(32-1 downto 0)  <= Regs_WrDin_r2(32-1 downto 0);
2044 
          else
2045 
            DMA_us_HA_i(32-1 downto 0)  <= DMA_us_HA_i(32-1 downto 0);
2046 
          end if;
2047 
 
2048 
        end if;
2049 
 
2050 
      end if;
2051 
   end process;
2052 
 
2053 
 
2054 
-- -------------------------------------------------------
2055 
-- Synchronous output: DMA_us_BDA_i
2056 
   Syn_Output_DMA_us_BDA:
2057 
   process ( trn_clk, trn_lnk_up_n)
2058 
   begin
2059 
      if trn_lnk_up_n = '1' then
2060 
         DMA_us_BDA_i    <= (OTHERS =>'0');
2061 
         usBDA_is_64b_i  <= '0';
2062 
      elsif trn_clk'event and trn_clk = '1' then
2063 
 
2064 
        if usDMA_Channel_Rst_i = '1' then
2065 
           DMA_us_BDA_i <= (OTHERS => '0');
2066 
           usBDA_is_64b_i <= '0';
2067 
        else
2068 
 
2069 
          if Regs_WrEn_r2='1' and Reg_WrMuxer_Hi(CINT_ADDR_DMA_US_BDAH)='1' then
2070 
            DMA_us_BDA_i(C_DBUS_WIDTH-1 downto 32)  <= Regs_WrDin_r2(C_DBUS_WIDTH-1 downto 32);
2071 
            usBDA_is_64b_i   <=  WrDin_r2_not_Zero_Hi;
2072 
          elsif Regs_WrEn_r2='1' and Reg_WrMuxer_Lo(CINT_ADDR_DMA_US_BDAH)='1' then
2073 
            DMA_us_BDA_i(C_DBUS_WIDTH-1 downto 32)  <= Regs_WrDin_r2(32-1 downto 0);
2074 
            usBDA_is_64b_i   <=  WrDin_r2_not_Zero_Lo;
2075 
          else
2076 
            DMA_us_BDA_i(C_DBUS_WIDTH-1 downto 32)  <= DMA_us_BDA_i(C_DBUS_WIDTH-1 downto 32);
2077 
            usBDA_is_64b_i   <=  usBDA_is_64b_i;
2078 
          end if;
2079 
 
2080 
          if Regs_WrEn_r2='1' and Reg_WrMuxer_Hi(CINT_ADDR_DMA_US_BDAL)='1' then
2081 
            DMA_us_BDA_i(32-1 downto 0)  <= Regs_WrDin_r2(C_DBUS_WIDTH-1 downto 32);
2082 
          elsif Regs_WrEn_r2='1' and Reg_WrMuxer_Lo(CINT_ADDR_DMA_US_BDAL)='1' then
2083 
            DMA_us_BDA_i(32-1 downto 0)  <= Regs_WrDin_r2(32-1 downto 0);
2084 
          else
2085 
            DMA_us_BDA_i(32-1 downto 0)  <= DMA_us_BDA_i(32-1 downto 0);
2086 
          end if;
2087 
 
2088 
        end if;
2089 
 
2090 
      end if;
2091 
   end process;
2092 
 
2093 
 
2094 
 
2095 
-- -------------------------------------------------------
2096 
-- Synchronous Registered: DMA_us_Length_i
2097 
   RxTrn_DMA_us_Length:
2098 
   process ( trn_clk, trn_lnk_up_n)
2099 
   begin
2100 
      if trn_lnk_up_n = '1' then
2101 
         DMA_us_Length_i     <= (OTHERS => '0');
2102 
         usLeng_Hi19b_True_i <= '0';
2103 
         usLeng_Lo7b_True_i  <= '0';
2104 
      elsif trn_clk'event and trn_clk = '1' then
2105 
 
2106 
         if usDMA_Channel_Rst_i = '1' then
2107 
            DMA_us_Length_i     <= (OTHERS => '0');
2108 
            usLeng_Hi19b_True_i <= '0';
2109 
            usLeng_Lo7b_True_i  <= '0';
2110 
 
2111 
         elsif Regs_WrEn_r2='1' and  Reg_WrMuxer_Hi(CINT_ADDR_DMA_US_LENG)='1' then
2112 
            DMA_us_Length_i(32-1 downto 0)     <= Regs_WrDin_r2(64-1 downto 32);
2113 
            usLeng_Hi19b_True_i <= Regs_WrDin_Hi19b_True_hq_r2;
2114 
            usLeng_Lo7b_True_i  <= Regs_WrDin_Lo7b_True_hq_r2;
2115 
         elsif Regs_WrEn_r2='1' and  Reg_WrMuxer_Lo(CINT_ADDR_DMA_US_LENG)='1' then
2116 
            DMA_us_Length_i(32-1 downto 0)     <= Regs_WrDin_r2(32-1 downto 0);
2117 
            usLeng_Hi19b_True_i <= Regs_WrDin_Hi19b_True_lq_r2;
2118 
            usLeng_Lo7b_True_i  <= Regs_WrDin_Lo7b_True_lq_r2;
2119 
         else
2120 
            DMA_us_Length_i     <= DMA_us_Length_i;
2121 
            usLeng_Hi19b_True_i <= usLeng_Hi19b_True_i;
2122 
            usLeng_Lo7b_True_i  <= usLeng_Lo7b_True_i;
2123 
 
2124 
         end if;
2125 
 
2126 
      end if;
2127 
   end process;
2128 
 
2129 
 
2130 
 
2131 
-- -------------------------------------------------------
2132 
-- Synchronous us_Param_Modified
2133 
   SynReg_us_Param_Modified:
2134 
   process ( trn_clk, trn_lnk_up_n)
2135 
   begin
2136 
      if trn_lnk_up_n = '1' then
2137 
         us_Param_Modified     <= '0';
2138 
 
2139 
      elsif trn_clk'event and trn_clk = '1' then
2140 
 
2141 
        if usDMA_Channel_Rst_i = '1'
2142 
           or usDMA_Start_i = '1'
2143 
           or usDMA_Start2_i = '1'
2144 
           then
2145 
             us_Param_Modified     <= '0';
2146 
        elsif Regs_WrEn_r2='1' and
2147 
                (
2148 
                    Reg_WrMuxer_Hi(CINT_ADDR_DMA_US_PAL) ='1'
2149 
                 or Reg_WrMuxer_Lo(CINT_ADDR_DMA_US_PAL) ='1'
2150 
                 or Reg_WrMuxer_Hi(CINT_ADDR_DMA_US_HAH) ='1'
2151 
                 or Reg_WrMuxer_Lo(CINT_ADDR_DMA_US_HAH) ='1'
2152 
                 or Reg_WrMuxer_Hi(CINT_ADDR_DMA_US_HAL) ='1'
2153 
                 or Reg_WrMuxer_Lo(CINT_ADDR_DMA_US_HAL) ='1'
2154 
                 or Reg_WrMuxer_Hi(CINT_ADDR_DMA_US_BDAH)='1'
2155 
                 or Reg_WrMuxer_Lo(CINT_ADDR_DMA_US_BDAH)='1'
2156 
                 or Reg_WrMuxer_Hi(CINT_ADDR_DMA_US_BDAL)='1'
2157 
                 or Reg_WrMuxer_Lo(CINT_ADDR_DMA_US_BDAL)='1'
2158 
                 or Reg_WrMuxer_Hi(CINT_ADDR_DMA_US_LENG)='1'
2159 
                 or Reg_WrMuxer_Lo(CINT_ADDR_DMA_US_LENG)='1'
2160 
                )
2161 
           then
2162 
             us_Param_Modified     <= '1';
2163 
        else
2164 
             us_Param_Modified     <= us_Param_Modified;
2165 
 
2166 
        end if;
2167 
 
2168 
      end if;
2169 
   end process;
2170 
 
2171 
 
2172 
 
2173 
-- -------------------------------------------------------
2174 
-- Synchronous output: DMA_us_Control_i
2175 
   Syn_Output_DMA_us_Control:
2176 
   process ( trn_clk, trn_lnk_up_n)
2177 
   begin
2178 
      if trn_lnk_up_n = '1' then
2179 
         DMA_us_Control_i <= (OTHERS =>'0');
2180 
      elsif trn_clk'event and trn_clk = '1' then
2181 
 
2182 
         if     Regs_Wr_dma_V_nE_Hi_r2='1'
2183 
            and Reg_WrMuxer_Hi(CINT_ADDR_DMA_US_CTRL)='1'
2184 
--            and Regs_WrDin_r2(CINT_BIT_DMA_CTRL_VALID)='1'
2185 
--            and Regs_WrDin_r2(CINT_BIT_DMA_CTRL_END)='0'
2186 
            and us_Param_Modified='1'
2187 
            and usDMA_Stop_i='0'
2188 
            then
2189 
               DMA_us_Control_i(32-1 downto 0) <= Regs_WrDin_r2(C_DBUS_WIDTH-1 downto 8+32)& X"00";
2190 
         elsif Regs_Wr_dma_V_nE_Lo_r2='1'
2191 
            and Reg_WrMuxer_Lo(CINT_ADDR_DMA_US_CTRL)='1'
2192 
--            and Regs_WrDin_r2(CINT_BIT_DMA_CTRL_VALID)='1'
2193 
--            and Regs_WrDin_r2(CINT_BIT_DMA_CTRL_END)='0'
2194 
            and us_Param_Modified='1'
2195 
            and usDMA_Stop_i='0'
2196 
            then
2197 
               DMA_us_Control_i(32-1 downto 0) <= Regs_WrDin_r2(32-1 downto 8)& X"00";
2198 
         elsif  Regs_Wr_dma_nV_Hi_r2='1'
2199 
            and Reg_WrMuxer_Hi(CINT_ADDR_DMA_US_CTRL)='1'
2200 
--            and Regs_WrDin_r2(CINT_BIT_DMA_CTRL_VALID)='0'
2201 
            then
2202 
               DMA_us_Control_i(32-1 downto 0) <= Last_Ctrl_Word_us(32-1 downto 0);
2203 
         elsif  Regs_Wr_dma_nV_Lo_r2='1'
2204 
            and Reg_WrMuxer_Lo(CINT_ADDR_DMA_US_CTRL)='1'
2205 
--            and Regs_WrDin_r2(CINT_BIT_DMA_CTRL_VALID)='0'
2206 
            then
2207 
               DMA_us_Control_i(32-1 downto 0) <= Last_Ctrl_Word_us(32-1 downto 0);
2208 
         else
2209 
            DMA_us_Control_i  <= DMA_us_Control_i;
2210 
         end if;
2211 
 
2212 
      end if;
2213 
   end process;
2214 
 
2215 
 
2216 
-- -------------------------------------------------------
2217 
-- Synchronous Register: Last_Ctrl_Word_us
2218 
   Hold_Last_Ctrl_Word_us:
2219 
   process ( trn_clk, trn_lnk_up_n)
2220 
   begin
2221 
      if trn_lnk_up_n = '1' then
2222 
         Last_Ctrl_Word_us  <= C_DEF_DMA_CTRL_WORD;
2223 
      elsif trn_clk'event and trn_clk = '1' then
2224 
 
2225 
        if usDMA_Channel_Rst_i = '1' then
2226 
            Last_Ctrl_Word_us <= C_DEF_DMA_CTRL_WORD;
2227 
        elsif Regs_Wr_dma_V_nE_Hi_r2='1'
2228 
          and Reg_WrMuxer_Hi(CINT_ADDR_DMA_US_CTRL)='1'
2229 
--          and Regs_WrDin_r2(CINT_BIT_DMA_CTRL_VALID)='1'
2230 
--          and Regs_WrDin_r2(CINT_BIT_DMA_CTRL_END)='0'
2231 
          and us_Param_Modified='1'
2232 
          and usDMA_Stop_i='0'
2233 
          then
2234 
            Last_Ctrl_Word_us(32-1 downto 0) <= Regs_WrDin_r2(C_DBUS_WIDTH-1 downto 8+32) & X"00";
2235 
        elsif Regs_Wr_dma_V_nE_Lo_r2='1'
2236 
          and Reg_WrMuxer_Lo(CINT_ADDR_DMA_US_CTRL)='1'
2237 
--          and Regs_WrDin_r2(CINT_BIT_DMA_CTRL_VALID)='1'
2238 
--          and Regs_WrDin_r2(CINT_BIT_DMA_CTRL_END)='0'
2239 
          and us_Param_Modified='1'
2240 
          and usDMA_Stop_i='0'
2241 
          then
2242 
            Last_Ctrl_Word_us(32-1 downto 0) <= Regs_WrDin_r2(32-1 downto 8) & X"00";
2243 
        elsif Regs_Wr_dma_V_nE_Hi_r2='1'
2244 
          and Reg_WrMuxer_Hi(CINT_ADDR_DMA_US_CTRL)='1'
2245 
--          and Regs_WrDin_r2(CINT_BIT_DMA_CTRL_VALID)='1'
2246 
--          and Regs_WrDin_r2(CINT_BIT_DMA_CTRL_END)='0'
2247 
          and us_Param_Modified='1'
2248 
          and usDMA_Stop_i='0'
2249 
          then
2250 
            Last_Ctrl_Word_us(32-1 downto 0) <= Regs_WrDin_r2(C_DBUS_WIDTH-1 downto 8+32) & X"00";
2251 
        elsif Regs_Wr_dma_V_nE_Lo_r2='1'
2252 
          and Reg_WrMuxer_Lo(CINT_ADDR_DMA_US_CTRL)='1'
2253 
--          and Regs_WrDin_r2(CINT_BIT_DMA_CTRL_VALID)='1'
2254 
--          and Regs_WrDin_r2(CINT_BIT_DMA_CTRL_END)='0'
2255 
          and us_Param_Modified='1'
2256 
          and usDMA_Stop_i='0'
2257 
          then
2258 
            Last_Ctrl_Word_us(32-1 downto 0) <= Regs_WrDin_r2(32-1 downto 8) & X"00";
2259 
        else
2260 
            Last_Ctrl_Word_us <= Last_Ctrl_Word_us;
2261 
        end if;
2262 
 
2263 
      end if;
2264 
   end process;
2265 
 
2266 
 
2267 
-- -------------------------------------------------------
2268 
-- Synchronous output: DMA_us_Start_Stop
2269 
   Syn_Output_DMA_us_Start_Stop:
2270 
   process ( trn_clk, trn_lnk_up_n)
2271 
   begin
2272 
      if trn_lnk_up_n = '1' then
2273 
         usDMA_Start_i  <= '0';
2274 
         usDMA_Stop_i   <= '0';
2275 
      elsif trn_clk'event and trn_clk = '1' then
2276 
 
2277 
         if     Regs_WrEnA_r2='1'
2278 
            and Reg_WrMuxer_Hi(CINT_ADDR_DMA_US_CTRL)='1'
2279 
            and Regs_WrDin_r2(CINT_BIT_DMA_CTRL_VALID+32)='1'
2280 
            then
2281 
               usDMA_Start_i <= not Regs_WrDin_r2(CINT_BIT_DMA_CTRL_END+32)
2282 
                            and not usDMA_Stop_i
2283 
                            and not Command_is_Reset_Hi
2284 
                            and us_Param_Modified
2285 
                            ;
2286 
               usDMA_Stop_i  <= Regs_WrDin_r2(CINT_BIT_DMA_CTRL_END+32)
2287 
                            and not Command_is_Reset_Hi
2288 
                            ;
2289 
         elsif Regs_WrEnA_r2='1'
2290 
            and Reg_WrMuxer_Lo(CINT_ADDR_DMA_US_CTRL)='1'
2291 
            and Regs_WrDin_r2(CINT_BIT_DMA_CTRL_VALID)='1'
2292 
            then
2293 
               usDMA_Start_i <= not Regs_WrDin_r2(CINT_BIT_DMA_CTRL_END)
2294 
                            and not usDMA_Stop_i
2295 
                            and not Command_is_Reset_Lo
2296 
                            and us_Param_Modified
2297 
                            ;
2298 
               usDMA_Stop_i  <= Regs_WrDin_r2(CINT_BIT_DMA_CTRL_END)
2299 
                            and not Command_is_Reset_Lo
2300 
                            ;
2301 
         elsif  Regs_WrEnA_r2='1'
2302 
            and Reg_WrMuxer_Hi(CINT_ADDR_DMA_US_CTRL)='1'
2303 
            and Regs_WrDin_r2(CINT_BIT_DMA_CTRL_VALID)='0'
2304 
            then
2305 
               usDMA_Start_i <= not Last_Ctrl_Word_us(CINT_BIT_DMA_CTRL_END)
2306 
                            and us_Param_Modified;
2307 
               usDMA_Stop_i  <= Last_Ctrl_Word_us(CINT_BIT_DMA_CTRL_END);
2308 
         elsif  Regs_WrEnA_r2='1'
2309 
            and Reg_WrMuxer_Lo(CINT_ADDR_DMA_US_CTRL)='1'
2310 
            and Regs_WrDin_r2(CINT_BIT_DMA_CTRL_VALID)='0'
2311 
            then
2312 
               usDMA_Start_i <= not Last_Ctrl_Word_us(CINT_BIT_DMA_CTRL_END)
2313 
                            and us_Param_Modified;
2314 
               usDMA_Stop_i  <= Last_Ctrl_Word_us(CINT_BIT_DMA_CTRL_END);
2315 
         elsif usDMA_Cmd_Ack='1'
2316 
            then
2317 
               usDMA_Start_i <= '0';
2318 
               usDMA_Stop_i  <= usDMA_Stop_i;
2319 
         else
2320 
               usDMA_Start_i <= usDMA_Start_i;
2321 
               usDMA_Stop_i  <= usDMA_Stop_i;
2322 
         end if;
2323 
 
2324 
      end if;
2325 
   end process;
2326 
 
2327 
 
2328 
-- -------------------------------------------------------
2329 
-- Synchronous output: DMA_us_Start2_Stop2
2330 
   Syn_Output_DMA_us_Start2_Stop2:
2331 
   process ( trn_clk, trn_lnk_up_n)
2332 
   begin
2333 
      if trn_lnk_up_n = '1' then
2334 
         usDMA_Start2_i <= '0';
2335 
         usDMA_Stop2_i  <= '0';
2336 
      elsif trn_clk'event and trn_clk = '1' then
2337 
 
2338 
         if usDMA_Channel_Rst_i='1' then
2339 
               usDMA_Start2_i <= '0';
2340 
               usDMA_Stop2_i  <= '0';
2341 
         elsif     Regs_WrEnB_r2='1'
2342 
            and Reg_WrMuxer_Hi(CINT_ADDR_DMA_US_CTRL)='1'
2343 
            and Regs_WrDin_r2(CINT_BIT_DMA_CTRL_VALID+32)='1'
2344 
            then
2345 
               usDMA_Start2_i <= not Regs_WrDin_r2(CINT_BIT_DMA_CTRL_END+32) and not Command_is_Reset_Hi;
2346 
               usDMA_Stop2_i  <= Regs_WrDin_r2(CINT_BIT_DMA_CTRL_END+32) and not Command_is_Reset_Lo;
2347 
         elsif  Regs_WrEnB_r2='1'
2348 
            and Reg_WrMuxer_Lo(CINT_ADDR_DMA_US_CTRL)='1'
2349 
            and Regs_WrDin_r2(CINT_BIT_DMA_CTRL_VALID)='1'
2350 
            then
2351 
               usDMA_Start2_i <= not Regs_WrDin_r2(CINT_BIT_DMA_CTRL_END) and not Command_is_Reset_Lo;
2352 
               usDMA_Stop2_i  <= Regs_WrDin_r2(CINT_BIT_DMA_CTRL_END) and not Command_is_Reset_Lo;
2353 
         elsif  Regs_WrEnB_r2='1'
2354 
            and Reg_WrMuxer_Hi(CINT_ADDR_DMA_US_CTRL)='1'
2355 
            and Regs_WrDin_r2(CINT_BIT_DMA_CTRL_VALID+32)='0'
2356 
            then
2357 
               usDMA_Start2_i <= not Last_Ctrl_Word_us(CINT_BIT_DMA_CTRL_END);
2358 
               usDMA_Stop2_i  <= Last_Ctrl_Word_us(CINT_BIT_DMA_CTRL_END);
2359 
         elsif  Regs_WrEnB_r2='1'
2360 
            and Reg_WrMuxer_Lo(CINT_ADDR_DMA_US_CTRL)='1'
2361 
            and Regs_WrDin_r2(CINT_BIT_DMA_CTRL_VALID)='0'
2362 
            then
2363 
               usDMA_Start2_i <= not Last_Ctrl_Word_us(CINT_BIT_DMA_CTRL_END);
2364 
               usDMA_Stop2_i  <= Last_Ctrl_Word_us(CINT_BIT_DMA_CTRL_END);
2365 
         elsif usDMA_Cmd_Ack='1' then
2366 
               usDMA_Start2_i <= '0';
2367 
               usDMA_Stop2_i  <= usDMA_Stop2_i;
2368 
         else
2369 
               usDMA_Start2_i <= usDMA_Start2_i;
2370 
               usDMA_Stop2_i  <= usDMA_Stop2_i;
2371 
         end if;
2372 
 
2373 
      end if;
2374 
   end process;
2375 
 
2376 
 
2377 
--  ------------------------------------------------------
2378 
--  DMA Downstream Registers
2379 
--  ------------------------------------------------------
2380 
 
2381 
-- -------------------------------------------------------
2382 
-- Synchronous Registered: DMA_ds_PA_i
2383 
   RxTrn_DMA_ds_PA:
2384 
   process ( trn_clk, trn_lnk_up_n)
2385 
   begin
2386 
      if trn_lnk_up_n = '1' then
2387 
         DMA_ds_PA_i     <= (OTHERS => '0');
2388 
      elsif trn_clk'event and trn_clk = '1' then
2389 
 
2390 
        if dsDMA_Channel_Rst_i = '1' then
2391 
            DMA_ds_PA_i <= (OTHERS => '0');
2392 
        else
2393 
 
2394 
          if Regs_WrEn_r2='1' and Reg_WrMuxer_Hi(CINT_ADDR_DMA_DS_PAH)='1' then
2395 
            DMA_ds_PA_i(C_DBUS_WIDTH-1 downto 32)  <= Regs_WrDin_r2(C_DBUS_WIDTH-1 downto 32);
2396 
          elsif Regs_WrEn_r2='1' and Reg_WrMuxer_Lo(CINT_ADDR_DMA_DS_PAH)='1' then
2397 
            DMA_ds_PA_i(C_DBUS_WIDTH-1 downto 32)  <= Regs_WrDin_r2(32-1 downto 0);
2398 
          else
2399 
            DMA_ds_PA_i(C_DBUS_WIDTH-1 downto 32)  <= DMA_ds_PA_i(C_DBUS_WIDTH-1 downto 32);
2400 
          end if;
2401 
 
2402 
          if Regs_WrEn_r2='1' and Reg_WrMuxer_Hi(CINT_ADDR_DMA_DS_PAL)='1' then
2403 
            DMA_ds_PA_i(32-1 downto 0)  <= Regs_WrDin_r2(C_DBUS_WIDTH-1 downto 32);
2404 
          elsif Regs_WrEn_r2='1' and Reg_WrMuxer_Lo(CINT_ADDR_DMA_DS_PAL)='1' then
2405 
            DMA_ds_PA_i(32-1 downto 0)  <= Regs_WrDin_r2(32-1 downto 0);
2406 
          else
2407 
            DMA_ds_PA_i(32-1 downto 0)  <= DMA_ds_PA_i(32-1 downto 0);
2408 
          end if;
2409 
 
2410 
        end if;
2411 
 
2412 
      end if;
2413 
   end process;
2414 
 
2415 
 
2416 
-- -------------------------------------------------------
2417 
-- Synchronous Registered: DMA_ds_HA_i
2418 
   RxTrn_DMA_ds_HA:
2419 
   process ( trn_clk, trn_lnk_up_n)
2420 
   begin
2421 
      if trn_lnk_up_n = '1' then
2422 
         DMA_ds_HA_i     <= (OTHERS => '1');
2423 
         dsHA_is_64b_i   <= '0';
2424 
      elsif trn_clk'event and trn_clk = '1' then
2425 
 
2426 
        if dsDMA_Channel_Rst_i = '1' then
2427 
            DMA_ds_HA_i <= (OTHERS => '1');
2428 
            dsHA_is_64b_i <= '0';
2429 
        else
2430 
 
2431 
          if Regs_WrEn_r2='1' and Reg_WrMuxer_Hi(CINT_ADDR_DMA_DS_HAH)='1' then
2432 
            DMA_ds_HA_i(C_DBUS_WIDTH-1 downto 32)  <= Regs_WrDin_r2(C_DBUS_WIDTH-1 downto 32);
2433 
            dsHA_is_64b_i   <=  WrDin_r2_not_Zero_Hi;
2434 
          elsif Regs_WrEn_r2='1' and Reg_WrMuxer_Lo(CINT_ADDR_DMA_DS_HAH)='1' then
2435 
            DMA_ds_HA_i(C_DBUS_WIDTH-1 downto 32)  <= Regs_WrDin_r2(32-1 downto 0);
2436 
            dsHA_is_64b_i   <=  WrDin_r2_not_Zero_Lo;
2437 
          else
2438 
            DMA_ds_HA_i(C_DBUS_WIDTH-1 downto 32)  <= DMA_ds_HA_i(C_DBUS_WIDTH-1 downto 32);
2439 
            dsHA_is_64b_i   <=  dsHA_is_64b_i;
2440 
          end if;
2441 
 
2442 
          if Regs_WrEn_r2='1' and Reg_WrMuxer_Hi(CINT_ADDR_DMA_DS_HAL)='1' then
2443 
            DMA_ds_HA_i(32-1 downto 0)  <= Regs_WrDin_r2(C_DBUS_WIDTH-1 downto 32);
2444 
          elsif Regs_WrEn_r2='1' and Reg_WrMuxer_Lo(CINT_ADDR_DMA_DS_HAL)='1' then
2445 
            DMA_ds_HA_i(32-1 downto 0)  <= Regs_WrDin_r2(32-1 downto 0);
2446 
          else
2447 
            DMA_ds_HA_i(32-1 downto 0)  <= DMA_ds_HA_i(32-1 downto 0);
2448 
          end if;
2449 
 
2450 
        end if;
2451 
 
2452 
      end if;
2453 
   end process;
2454 
 
2455 
 
2456 
-- -------------------------------------------------------
2457 
-- Synchronous output: DMA_ds_BDA_i
2458 
   Syn_Output_DMA_ds_BDA:
2459 
   process ( trn_clk, trn_lnk_up_n)
2460 
   begin
2461 
      if trn_lnk_up_n = '1' then
2462 
         DMA_ds_BDA_i    <= (OTHERS =>'0');
2463 
         dsBDA_is_64b_i  <= '0';
2464 
      elsif trn_clk'event and trn_clk = '1' then
2465 
 
2466 
        if dsDMA_Channel_Rst_i = '1' then
2467 
            DMA_ds_BDA_i <= (OTHERS => '0');
2468 
            dsBDA_is_64b_i <= '0';
2469 
        else
2470 
 
2471 
          if Regs_WrEn_r2='1' and Reg_WrMuxer_Hi(CINT_ADDR_DMA_DS_BDAH)='1' then
2472 
            DMA_ds_BDA_i(C_DBUS_WIDTH-1 downto 32)  <= Regs_WrDin_r2(C_DBUS_WIDTH-1 downto 32);
2473 
            dsBDA_is_64b_i   <=  WrDin_r2_not_Zero_Hi;
2474 
          elsif Regs_WrEn_r2='1' and Reg_WrMuxer_Lo(CINT_ADDR_DMA_DS_BDAH)='1' then
2475 
            DMA_ds_BDA_i(C_DBUS_WIDTH-1 downto 32)  <= Regs_WrDin_r2(32-1 downto 0);
2476 
            dsBDA_is_64b_i   <=  WrDin_r2_not_Zero_Lo;
2477 
          else
2478 
            DMA_ds_BDA_i(C_DBUS_WIDTH-1 downto 32)  <= DMA_ds_BDA_i(C_DBUS_WIDTH-1 downto 32);
2479 
            dsBDA_is_64b_i   <=  dsBDA_is_64b_i;
2480 
          end if;
2481 
 
2482 
          if Regs_WrEn_r2='1' and Reg_WrMuxer_Hi(CINT_ADDR_DMA_DS_BDAL)='1' then
2483 
            DMA_ds_BDA_i(32-1 downto 0)  <= Regs_WrDin_r2(C_DBUS_WIDTH-1 downto 32);
2484 
          elsif Regs_WrEn_r2='1' and Reg_WrMuxer_Lo(CINT_ADDR_DMA_DS_BDAL)='1' then
2485 
            DMA_ds_BDA_i(32-1 downto 0)  <= Regs_WrDin_r2(32-1 downto 0);
2486 
          else
2487 
            DMA_ds_BDA_i(32-1 downto 0)  <= DMA_ds_BDA_i(32-1 downto 0);
2488 
          end if;
2489 
 
2490 
        end if;
2491 
      end if;
2492 
   end process;
2493 
 
2494 
 
2495 
 
2496 
-- Synchronous Registered: DMA_ds_Length_i
2497 
   RxTrn_DMA_ds_Length:
2498 
   process ( trn_clk, trn_lnk_up_n)
2499 
   begin
2500 
      if trn_lnk_up_n = '1' then
2501 
         DMA_ds_Length_i     <= (OTHERS => '0');
2502 
         dsLeng_Hi19b_True_i <= '0';
2503 
         dsLeng_Lo7b_True_i  <= '0';
2504 
      elsif trn_clk'event and trn_clk = '1' then
2505 
 
2506 
         if dsDMA_Channel_Rst_i = '1' then
2507 
            DMA_ds_Length_i <= (OTHERS => '0');
2508 
            dsLeng_Hi19b_True_i <= '0';
2509 
            dsLeng_Lo7b_True_i  <= '0';
2510 
 
2511 
         elsif Regs_WrEn_r2='1' and Reg_WrMuxer_Hi(CINT_ADDR_DMA_DS_LENG)='1' then
2512 
            DMA_ds_Length_i(32-1 downto 0)     <= Regs_WrDin_r2(C_DBUS_WIDTH-1 downto 32);
2513 
            dsLeng_Hi19b_True_i <= Regs_WrDin_Hi19b_True_hq_r2;
2514 
            dsLeng_Lo7b_True_i  <= Regs_WrDin_Lo7b_True_hq_r2;
2515 
         elsif Regs_WrEn_r2='1' and Reg_WrMuxer_Lo(CINT_ADDR_DMA_DS_LENG)='1' then
2516 
            DMA_ds_Length_i(32-1 downto 0)     <= Regs_WrDin_r2(32-1 downto 0);
2517 
            dsLeng_Hi19b_True_i <= Regs_WrDin_Hi19b_True_lq_r2;
2518 
            dsLeng_Lo7b_True_i  <= Regs_WrDin_Lo7b_True_lq_r2;
2519 
         else
2520 
            DMA_ds_Length_i     <= DMA_ds_Length_i;
2521 
            dsLeng_Hi19b_True_i <= dsLeng_Hi19b_True_i;
2522 
            dsLeng_Lo7b_True_i  <= dsLeng_Lo7b_True_i;
2523 
 
2524 
         end if;
2525 
 
2526 
      end if;
2527 
   end process;
2528 
 
2529 
 
2530 
 
2531 
-- -------------------------------------------------------
2532 
-- Synchronous ds_Param_Modified
2533 
   SynReg_ds_Param_Modified:
2534 
   process ( trn_clk, trn_lnk_up_n)
2535 
   begin
2536 
      if trn_lnk_up_n = '1' then
2537 
         ds_Param_Modified     <= '0';
2538 
 
2539 
      elsif trn_clk'event and trn_clk = '1' then
2540 
 
2541 
        if dsDMA_Channel_Rst_i = '1'
2542 
           or dsDMA_Start_i = '1'
2543 
           or dsDMA_Start2_i = '1'
2544 
           then
2545 
             ds_Param_Modified     <= '0';
2546 
        elsif Regs_WrEn_r2='1' and
2547 
                (
2548 
--                    Reg_WrMuxer(CINT_ADDR_DMA_DS_PAH) ='1'
2549 
--                 or
2550 
                    Reg_WrMuxer_Hi(CINT_ADDR_DMA_DS_PAL) ='1'
2551 
                 or Reg_WrMuxer_Lo(CINT_ADDR_DMA_DS_PAL) ='1'
2552 
                 or Reg_WrMuxer_Hi(CINT_ADDR_DMA_DS_HAH) ='1'
2553 
                 or Reg_WrMuxer_Lo(CINT_ADDR_DMA_DS_HAH) ='1'
2554 
                 or Reg_WrMuxer_Hi(CINT_ADDR_DMA_DS_HAL) ='1'
2555 
                 or Reg_WrMuxer_Lo(CINT_ADDR_DMA_DS_HAL) ='1'
2556 
                 or Reg_WrMuxer_Hi(CINT_ADDR_DMA_DS_BDAH)='1'
2557 
                 or Reg_WrMuxer_Lo(CINT_ADDR_DMA_DS_BDAH)='1'
2558 
                 or Reg_WrMuxer_Hi(CINT_ADDR_DMA_DS_BDAL)='1'
2559 
                 or Reg_WrMuxer_Lo(CINT_ADDR_DMA_DS_BDAL)='1'
2560 
                 or Reg_WrMuxer_Hi(CINT_ADDR_DMA_DS_LENG)='1'
2561 
                 or Reg_WrMuxer_Lo(CINT_ADDR_DMA_DS_LENG)='1'
2562 
                )
2563 
           then
2564 
             ds_Param_Modified     <= '1';
2565 
        else
2566 
             ds_Param_Modified     <= ds_Param_Modified;
2567 
 
2568 
        end if;
2569 
 
2570 
      end if;
2571 
   end process;
2572 
 
2573 
 
2574 
 
2575 
-- -------------------------------------------------------
2576 
-- Synchronous output: DMA_ds_Control_i
2577 
   Syn_Output_DMA_ds_Control:
2578 
   process ( trn_clk, trn_lnk_up_n)
2579 
   begin
2580 
      if trn_lnk_up_n = '1' then
2581 
         DMA_ds_Control_i <= (OTHERS =>'0');
2582 
 
2583 
      elsif trn_clk'event and trn_clk = '1' then
2584 
 
2585 
         if     Regs_Wr_dma_V_nE_Hi_r2='1'
2586 
            and Reg_WrMuxer_Hi(CINT_ADDR_DMA_DS_CTRL)='1'
2587 
--            and Regs_WrDin_r2(CINT_BIT_DMA_CTRL_VALID+32)='1'
2588 
--            and Regs_WrDin_r2(CINT_BIT_DMA_CTRL_END+32)='0'
2589 
            and ds_Param_Modified='1'
2590 
            and dsDMA_Stop_i='0'
2591 
            then
2592 
               DMA_ds_Control_i(32-1 downto 0) <= Regs_WrDin_r2(C_DBUS_WIDTH-1 downto 8+32)& X"00";
2593 
         elsif  Regs_Wr_dma_V_nE_Lo_r2='1'
2594 
            and Reg_WrMuxer_Lo(CINT_ADDR_DMA_DS_CTRL)='1'
2595 
--            and Regs_WrDin_r2(CINT_BIT_DMA_CTRL_VALID)='1'
2596 
--            and Regs_WrDin_r2(CINT_BIT_DMA_CTRL_END)='0'
2597 
            and ds_Param_Modified='1'
2598 
            and dsDMA_Stop_i='0'
2599 
            then
2600 
               DMA_ds_Control_i(32-1 downto 0) <= Regs_WrDin_r2(32-1 downto 8)& X"00";
2601 
         elsif  Regs_Wr_dma_nV_Hi_r2='1'
2602 
            and (Reg_WrMuxer_Hi(CINT_ADDR_DMA_DS_CTRL)='1' or Reg_WrMuxer_Lo(CINT_ADDR_DMA_DS_CTRL)='1')
2603 
--            and Regs_WrDin_r2(CINT_BIT_DMA_CTRL_VALID)='0'
2604 
            then
2605 
               DMA_ds_Control_i <= Last_Ctrl_Word_ds;
2606 
         else
2607 
            DMA_ds_Control_i  <= DMA_ds_Control_i;
2608 
         end if;
2609 
 
2610 
      end if;
2611 
   end process;
2612 
 
2613 
 
2614 
-- -------------------------------------------------------
2615 
-- Synchronous Register: Last_Ctrl_Word_ds
2616 
   Hold_Last_Ctrl_Word_ds:
2617 
   process ( trn_clk, trn_lnk_up_n)
2618 
   begin
2619 
      if trn_lnk_up_n = '1' then
2620 
         Last_Ctrl_Word_ds  <= C_DEF_DMA_CTRL_WORD;
2621 
      elsif trn_clk'event and trn_clk = '1' then
2622 
 
2623 
        if dsDMA_Channel_Rst_i = '1' then
2624 
            Last_Ctrl_Word_ds <= C_DEF_DMA_CTRL_WORD;
2625 
        elsif Regs_Wr_dma_V_nE_Hi_r2='1'
2626 
          and Reg_WrMuxer_Hi(CINT_ADDR_DMA_DS_CTRL)='1'
2627 
--          and Regs_WrDin_r2(CINT_BIT_DMA_CTRL_VALID+32)='1'
2628 
--          and Regs_WrDin_r2(CINT_BIT_DMA_CTRL_END+32)='0'
2629 
          and ds_Param_Modified='1'
2630 
          and dsDMA_Stop_i='0'
2631 
          then
2632 
            Last_Ctrl_Word_ds(32-1 downto 0) <= Regs_WrDin_r2(C_DBUS_WIDTH-1 downto 8+32) & X"00";
2633 
        elsif Regs_Wr_dma_V_nE_Lo_r2='1'
2634 
          and Reg_WrMuxer_Lo(CINT_ADDR_DMA_DS_CTRL)='1'
2635 
--          and Regs_WrDin_r2(CINT_BIT_DMA_CTRL_VALID)='1'
2636 
--          and Regs_WrDin_r2(CINT_BIT_DMA_CTRL_END)='0'
2637 
          and ds_Param_Modified='1'
2638 
          and dsDMA_Stop_i='0'
2639 
          then
2640 
            Last_Ctrl_Word_ds(32-1 downto 0) <= Regs_WrDin_r2(32-1 downto 8) & X"00";
2641 
        else
2642 
            Last_Ctrl_Word_ds <= Last_Ctrl_Word_ds;
2643 
        end if;
2644 
 
2645 
      end if;
2646 
   end process;
2647 
 
2648 
 
2649 
-- -------------------------------------------------------
2650 
-- Synchronous output: DMA_ds_Start_Stop
2651 
   Syn_Output_DMA_ds_Start_Stop:
2652 
   process ( trn_clk, trn_lnk_up_n)
2653 
   begin
2654 
      if trn_lnk_up_n = '1' then
2655 
         dsDMA_Start_i  <= '0';
2656 
         dsDMA_Stop_i   <= '0';
2657 
 
2658 
      elsif trn_clk'event and trn_clk = '1' then
2659 
 
2660 
         if     Regs_WrEnA_r2='1'
2661 
            and Reg_WrMuxer_Hi(CINT_ADDR_DMA_DS_CTRL)='1'
2662 
            and Regs_WrDin_r2(CINT_BIT_DMA_CTRL_VALID+32)='1'
2663 
            then
2664 
               dsDMA_Start_i <= not Regs_WrDin_r2(CINT_BIT_DMA_CTRL_END+32)
2665 
                            and not dsDMA_Stop_i
2666 
                            and not Command_is_Reset_Hi
2667 
                            and ds_Param_Modified
2668 
                            ;
2669 
               dsDMA_Stop_i  <= Regs_WrDin_r2(CINT_BIT_DMA_CTRL_END+32)
2670 
                            and not Command_is_Reset_Hi
2671 
                            ;
2672 
         elsif  Regs_WrEnA_r2='1'
2673 
            and Reg_WrMuxer_Lo(CINT_ADDR_DMA_DS_CTRL)='1'
2674 
            and Regs_WrDin_r2(CINT_BIT_DMA_CTRL_VALID)='1'
2675 
            then
2676 
               dsDMA_Start_i <= not Regs_WrDin_r2(CINT_BIT_DMA_CTRL_END)
2677 
                            and not dsDMA_Stop_i
2678 
                            and not Command_is_Reset_Lo
2679 
                            and ds_Param_Modified
2680 
                            ;
2681 
               dsDMA_Stop_i  <= Regs_WrDin_r2(CINT_BIT_DMA_CTRL_END)
2682 
                            and not Command_is_Reset_Lo
2683 
                            ;
2684 
         elsif  Regs_WrEnA_r2='1'
2685 
            and (Reg_WrMuxer_Hi(CINT_ADDR_DMA_DS_CTRL)='1' or Reg_WrMuxer_Lo(CINT_ADDR_DMA_DS_CTRL)='1')
2686 
            and Regs_WrDin_r2(CINT_BIT_DMA_CTRL_VALID+32)='0'
2687 
            then
2688 
               dsDMA_Start_i <= not Last_Ctrl_Word_ds(CINT_BIT_DMA_CTRL_END)
2689 
                            and ds_Param_Modified
2690 
                            ;
2691 
               dsDMA_Stop_i  <= Last_Ctrl_Word_ds(CINT_BIT_DMA_CTRL_END);
2692 
         elsif dsDMA_Cmd_Ack='1'
2693 
            then
2694 
               dsDMA_Start_i <= '0';
2695 
               dsDMA_Stop_i  <= dsDMA_Stop_i;
2696 
         else
2697 
               dsDMA_Start_i <= dsDMA_Start_i;
2698 
               dsDMA_Stop_i  <= dsDMA_Stop_i;
2699 
         end if;
2700 
 
2701 
      end if;
2702 
   end process;
2703 
 
2704 
 
2705 
-- -------------------------------------------------------
2706 
-- Synchronous output: DMA_ds_Start2_Stop2
2707 
   Syn_Output_DMA_ds_Start2_Stop2:
2708 
   process ( trn_clk, trn_lnk_up_n)
2709 
   begin
2710 
      if trn_lnk_up_n = '1' then
2711 
         dsDMA_Start2_i <= '0';
2712 
         dsDMA_Stop2_i  <= '0';
2713 
 
2714 
      elsif trn_clk'event and trn_clk = '1' then
2715 
 
2716 
         if dsDMA_Channel_Rst_i='1' then
2717 
               dsDMA_Start2_i <= '0';
2718 
               dsDMA_Stop2_i  <= '0';
2719 
         elsif     Regs_WrEnB_r2='1'
2720 
            and Reg_WrMuxer_Hi(CINT_ADDR_DMA_DS_CTRL)='1'
2721 
            and Regs_WrDin_r2(CINT_BIT_DMA_CTRL_VALID+32)='1'
2722 
            then
2723 
               dsDMA_Start2_i <= not Regs_WrDin_r2(CINT_BIT_DMA_CTRL_END+32) and not Command_is_Reset_Hi;
2724 
               dsDMA_Stop2_i  <= Regs_WrDin_r2(CINT_BIT_DMA_CTRL_END+32) and not Command_is_Reset_Hi;
2725 
         elsif  Regs_WrEnB_r2='1'
2726 
            and Reg_WrMuxer_Lo(CINT_ADDR_DMA_DS_CTRL)='1'
2727 
            and Regs_WrDin_r2(CINT_BIT_DMA_CTRL_VALID)='1'
2728 
            then
2729 
               dsDMA_Start2_i <= not Regs_WrDin_r2(CINT_BIT_DMA_CTRL_END) and not Command_is_Reset_Lo;
2730 
               dsDMA_Stop2_i  <= Regs_WrDin_r2(CINT_BIT_DMA_CTRL_END) and not Command_is_Reset_Lo;
2731 
         elsif  Regs_WrEnB_r2='1'
2732 
            and Reg_WrMuxer_Hi(CINT_ADDR_DMA_DS_CTRL)='1'
2733 
            and Regs_WrDin_r2(CINT_BIT_DMA_CTRL_VALID+32)='0'
2734 
            then
2735 
               dsDMA_Start2_i <= not Last_Ctrl_Word_ds(CINT_BIT_DMA_CTRL_END);
2736 
               dsDMA_Stop2_i  <= Last_Ctrl_Word_ds(CINT_BIT_DMA_CTRL_END);
2737 
         elsif  Regs_WrEnB_r2='1'
2738 
            and Reg_WrMuxer_Lo(CINT_ADDR_DMA_DS_CTRL)='1'
2739 
            and Regs_WrDin_r2(CINT_BIT_DMA_CTRL_VALID)='0'
2740 
            then
2741 
               dsDMA_Start2_i <= not Last_Ctrl_Word_ds(CINT_BIT_DMA_CTRL_END);
2742 
               dsDMA_Stop2_i  <= Last_Ctrl_Word_ds(CINT_BIT_DMA_CTRL_END);
2743 
         elsif dsDMA_Cmd_Ack='1' then
2744 
               dsDMA_Start2_i <= '0';
2745 
               dsDMA_Stop2_i  <= dsDMA_Stop2_i;
2746 
         else
2747 
               dsDMA_Start2_i <= dsDMA_Start2_i;
2748 
               dsDMA_Stop2_i  <= dsDMA_Stop2_i;
2749 
         end if;
2750 
 
2751 
      end if;
2752 
   end process;
2753 
 
2754 
 
2755 
------------------------------------------------------------------------
2756 
--                          Reset signals                             --
2757 
------------------------------------------------------------------------
2758 
 
2759 
-- --------------------------------------
2760 
-- Identification: Command_is_Reset
2761 
--
2762 
   Synch_Capture_Command_is_Reset:
2763 
   process ( trn_clk, trn_lnk_up_n)
2764 
   begin
2765 
      if trn_lnk_up_n = '1' then
2766 
         Command_is_Reset_Hi    <= '0';
2767 
         Command_is_Reset_Lo    <= '0';
2768 
 
2769 
      elsif trn_clk'event and trn_clk = '1' then
2770 
         if Regs_WrDin_r1(C_FEAT_BITS_WIDTH-1+32 downto 32)=C_CHANNEL_RST_BITS then
2771 
            Command_is_Reset_Hi    <= '1';
2772 
         else
2773 
            Command_is_Reset_Hi    <= '0';
2774 
         end if;
2775 
 
2776 
         if Regs_WrDin_r1(C_FEAT_BITS_WIDTH-1 downto 0)=C_CHANNEL_RST_BITS then
2777 
            Command_is_Reset_Lo    <= '1';
2778 
         else
2779 
            Command_is_Reset_Lo    <= '0';
2780 
         end if;
2781 
      end if;
2782 
   end process;
2783 
 
2784 
 
2785 
-- --------------------------------------
2786 
-- Identification: Command_is_Host_iClr
2787 
--
2788 
   Synch_Capture_Command_is_Host_iClr:
2789 
   process ( trn_clk, trn_lnk_up_n)
2790 
   begin
2791 
      if trn_lnk_up_n = '1' then
2792 
         Command_is_Host_iClr_Hi    <= '0';
2793 
         Command_is_Host_iClr_Lo    <= '0';
2794 
 
2795 
      elsif trn_clk'event and trn_clk = '1' then
2796 
         if Regs_WrDin_r1(C_FEAT_BITS_WIDTH-1+32 downto 32)=C_HOST_ICLR_BITS then
2797 
            Command_is_Host_iClr_Hi    <= '1';
2798 
         else
2799 
            Command_is_Host_iClr_Hi    <= '0';
2800 
         end if;
2801 
 
2802 
         if Regs_WrDin_r1(C_FEAT_BITS_WIDTH-1 downto 0)=C_HOST_ICLR_BITS then
2803 
            Command_is_Host_iClr_Lo    <= '1';
2804 
         else
2805 
            Command_is_Host_iClr_Lo    <= '0';
2806 
         end if;
2807 
      end if;
2808 
   end process;
2809 
 
2810 
-------------------------------------------
2811 
-- Synchronous output: usDMA_Channel_Rst_i
2812 
--
2813 
   Syn_Output_usDMA_Channel_Rst:
2814 
   process ( trn_clk, trn_lnk_up_n)
2815 
   begin
2816 
      if trn_lnk_up_n = '1' then
2817 
         usDMA_Channel_Rst_i <= '1';
2818 
      elsif trn_clk'event and trn_clk = '1' then
2819 
 
2820 
         usDMA_Channel_Rst_i <= (Regs_Wr_dma_V_Hi_r2
2821 
                            and Reg_WrMuxer_Hi(CINT_ADDR_DMA_US_CTRL)
2822 
--                            and Regs_WrDin_r2(CINT_BIT_DMA_CTRL_VALID+32)
2823 
                            and Command_is_Reset_Hi
2824 
                                )
2825 
                            or  (Regs_Wr_dma_V_LO_r2
2826 
                            and Reg_WrMuxer_Lo(CINT_ADDR_DMA_US_CTRL)
2827 
--                            and Regs_WrDin_r2(CINT_BIT_DMA_CTRL_VALID)
2828 
                            and Command_is_Reset_Lo
2829 
                                )
2830 
                            ;
2831 
      end if;
2832 
   end process;
2833 
 
2834 
 
2835 
 
2836 
-------------------------------------------
2837 
-- Synchronous output: dsDMA_Channel_Rst_i
2838 
--
2839 
   Syn_Output_dsDMA_Channel_Rst:
2840 
   process ( trn_clk, trn_lnk_up_n)
2841 
   begin
2842 
      if trn_lnk_up_n = '1' then
2843 
         dsDMA_Channel_Rst_i <= '1';
2844 
      elsif trn_clk'event and trn_clk = '1' then
2845 
 
2846 
         dsDMA_Channel_Rst_i <= (Regs_Wr_dma_V_Hi_r2
2847 
                            and Reg_WrMuxer_Hi(CINT_ADDR_DMA_DS_CTRL)
2848 
--                            and Regs_WrDin_r2(CINT_BIT_DMA_CTRL_VALID+32)
2849 
                            and Command_is_Reset_Hi
2850 
                            )
2851 
                            or
2852 
                           (Regs_Wr_dma_V_Lo_r2
2853 
                            and Reg_WrMuxer_Lo(CINT_ADDR_DMA_DS_CTRL)
2854 
--                            and Regs_WrDin_r2(CINT_BIT_DMA_CTRL_VALID)
2855 
                            and Command_is_Reset_Lo
2856 
                            )
2857 
                            ;
2858 
      end if;
2859 
   end process;
2860 
 
2861 
 
2862 
-- -----------------------------------------------
2863 
-- Synchronous output: MRd_Channel_Rst_i
2864 
--
2865 
   Syn_Output_MRd_Channel_Rst:
2866 
   process ( trn_clk, trn_lnk_up_n)
2867 
   begin
2868 
      if trn_lnk_up_n = '1' then
2869 
         MRd_Channel_Rst_i <= '1';
2870 
      elsif trn_clk'event and trn_clk = '1' then
2871 
 
2872 
         MRd_Channel_Rst_i    <= Regs_WrEn_r2
2873 
                             and (
2874 
                                 (Reg_WrMuxer_Hi(CINT_ADDR_MRD_CTRL)
2875 
                                  and Command_is_Reset_Hi)
2876 
                             or
2877 
                                 (Reg_WrMuxer_Lo(CINT_ADDR_MRD_CTRL)
2878 
                                  and Command_is_Reset_Lo)
2879 
                             )
2880 
                             ;
2881 
      end if;
2882 
   end process;
2883 
 
2884 
 
2885 
-- -----------------------------------------------
2886 
-- Synchronous output: Tx_Reset_i
2887 
--
2888 
   Syn_Output_Tx_Reset:
2889 
   process ( trn_clk, trn_lnk_up_n)
2890 
   begin
2891 
      if trn_lnk_up_n = '1' then
2892 
         Tx_Reset_i   <= '1';
2893 
      elsif trn_clk'event and trn_clk = '1' then
2894 
 
2895 
         Tx_Reset_i   <= Regs_WrEn_r2
2896 
                     and ((Reg_WrMuxer_Hi(CINT_ADDR_TX_CTRL)
2897 
                     and Command_is_Reset_Hi)
2898 
                     or  (Reg_WrMuxer_Lo(CINT_ADDR_TX_CTRL)
2899 
                     and Command_is_Reset_Lo))
2900 
                     ;
2901 
      end if;
2902 
   end process;
2903 
 
2904 
 
2905 
-- -----------------------------------------------
2906 
-- Synchronous output: eb_FIFO_Rst_i
2907 
--
2908 
   Syn_Output_eb_FIFO_Rst:
2909 
   process ( trn_clk, trn_lnk_up_n)
2910 
   begin
2911 
      if trn_lnk_up_n = '1' then
2912 
         eb_FIFO_Rst_i    <= '1';
2913 
         eb_FIFO_Rst_b3   <= '1';
2914 
         eb_FIFO_Rst_b2   <= '1';
2915 
         eb_FIFO_Rst_b1   <= '1';
2916 
      elsif trn_clk'event and trn_clk = '1' then
2917 
 
2918 
         eb_FIFO_Rst_i   <= eb_FIFO_Rst_b1 or eb_FIFO_Rst_b2 or eb_FIFO_Rst_b3;
2919 
         eb_FIFO_Rst_b3  <= eb_FIFO_Rst_b2;
2920 
         eb_FIFO_Rst_b2  <= eb_FIFO_Rst_b1;
2921 
         eb_FIFO_Rst_b1  <= Regs_WrEn_r2
2922 
                         and ((Reg_WrMuxer_Hi(CINT_ADDR_EB_STACON)
2923 
                         and Command_is_Reset_Hi)
2924 
                         or  (Reg_WrMuxer_Lo(CINT_ADDR_EB_STACON)
2925 
                         and Command_is_Reset_Lo))
2926 
                         ;
2927 
      end if;
2928 
   end process;
2929 
 
2930 
 
2931 
-- -----------------------------------------------
2932 
-- Synchronous output: protocol_rst
2933 
--
2934 
--            !!!  reset by trn_reset_n  !!!
2935 
--
2936 
   Syn_Output_protocol_rst:
2937 
   process ( trn_clk, trn_reset_n)
2938 
   begin
2939 
      if trn_reset_n = '0' then
2940 
         protocol_rst_i   <= '1';
2941 
         protocol_rst_b1  <= '1';
2942 
         protocol_rst_b2  <= '1';
2943 
      elsif trn_clk'event and trn_clk = '1' then
2944 
 
2945 
         protocol_rst_i  <= protocol_rst_b1 or protocol_rst_b2;
2946 
         protocol_rst_b1 <= protocol_rst_b2;
2947 
         protocol_rst_b2 <= Regs_WrEn_r2
2948 
                         and ((Reg_WrMuxer_Hi(CINT_ADDR_PROTOCOL_STACON)
2949 
                         and Command_is_Reset_Hi)
2950 
                         or  (Reg_WrMuxer_Lo(CINT_ADDR_PROTOCOL_STACON)
2951 
                         and Command_is_Reset_Lo))
2952 
                         ;
2953 
      end if;
2954 
   end process;
2955 
 
2956 
 
2957 
-- -----------------------------------------------
2958 
-- Synchronous Calculation: DMA_us_Transf_Bytes
2959 
--
2960 
   Syn_Calc_DMA_us_Transf_Bytes:
2961 
   process ( trn_clk, trn_lnk_up_n)
2962 
   begin
2963 
      if trn_lnk_up_n = '1' then
2964 
         DMA_us_Transf_Bytes_i   <= (OTHERS=>'0');
2965 
      elsif trn_clk'event and trn_clk = '1' then
2966 
 
2967 
         if usDMA_Channel_Rst_i='1' then
2968 
            DMA_us_Transf_Bytes_i   <= (OTHERS=>'0');
2969 
         elsif us_DMA_Bytes_Add='1' then
2970 
            DMA_us_Transf_Bytes_i(32-1 downto 0)
2971 
                                    <= DMA_us_Transf_Bytes_i(32-1 downto 0)
2972 
                                    +  us_DMA_Bytes;
2973 
         else
2974 
            DMA_us_Transf_Bytes_i   <= DMA_us_Transf_Bytes_i;
2975 
         end if;
2976 
      end if;
2977 
   end process;
2978 
 
2979 
 
2980 
-- -----------------------------------------------
2981 
-- Synchronous Calculation: DMA_ds_Transf_Bytes
2982 
--
2983 
   Syn_Calc_DMA_ds_Transf_Bytes:
2984 
   process ( trn_clk, trn_lnk_up_n)
2985 
   begin
2986 
      if trn_lnk_up_n = '1' then
2987 
         DMA_ds_Transf_Bytes_i   <= (OTHERS=>'0');
2988 
      elsif trn_clk'event and trn_clk = '1' then
2989 
 
2990 
         if dsDMA_Channel_Rst_i='1' then
2991 
            DMA_ds_Transf_Bytes_i   <= (OTHERS=>'0');
2992 
         elsif ds_DMA_Bytes_Add='1' then
2993 
            DMA_ds_Transf_Bytes_i(32-1 downto 0)
2994 
                                    <= DMA_ds_Transf_Bytes_i(32-1 downto 0)
2995 
                                    +  ds_DMA_Bytes;
2996 
         else
2997 
            DMA_ds_Transf_Bytes_i   <= DMA_ds_Transf_Bytes_i;
2998 
         end if;
2999 
      end if;
3000 
   end process;
3001 
 
3002 
---- -------------------------------------------------------
3003 
---- Synchronous Registers: icap_Write_i
3004 
--   RxTrn_icap_Write:
3005 
--   process ( trn_clk, trn_lnk_up_n)
3006 
--   begin
3007 
--      if trn_lnk_up_n = '1' then
3008 
--         icap_CLK      <= '0';
3009 
--         icap_I        <= (OTHERS => '0');
3010 
--         icap_Write    <= '1';
3011 
--         icap_CE       <= '1';
3012 
--         FSM_icap      <= icapST_Reset;
3013 
--
3014 
--      elsif trn_clk'event and trn_clk = '1' then
3015 
--
3016 
--        case FSM_icap is
3017 
--
3018 
--          when icapST_Reset =>
3019 
--            icap_CLK      <= '0';
3020 
--            icap_I        <= (OTHERS => '0');
3021 
--            icap_Write    <= '1';
3022 
--            icap_CE       <= '1';
3023 
--            FSM_icap      <= icapST_Idle;
3024 
--
3025 
--          when icapST_Idle =>
3026 
--
3027 
--            if Regs_WrEn_r2='1' and  Reg_WrMuxer(CINT_ADDR_ICAP)='1' then
3028 
--               icap_CLK   <= '1';
3029 
--               icap_I     <= Regs_WrDin_r2;
3030 
--               icap_Write <= '0';
3031 
--               icap_CE    <= '0';
3032 
--               FSM_icap   <= icapST_Access;
3033 
--            elsif Reg_RdMuxer(CINT_ADDR_ICAP)='1' then
3034 
--               icap_CLK   <= '1';
3035 
--               icap_I     <= icap_I;
3036 
--               icap_Write <= '1';
3037 
--               icap_CE    <= '0';
3038 
--               FSM_icap   <= icapST_Access;
3039 
--            else
3040 
--               icap_CLK   <= icap_CLK;
3041 
--               icap_I     <= icap_I;
3042 
--               icap_Write <= icap_Write;
3043 
--               icap_CE    <= icap_CE;
3044 
--               FSM_icap   <= icapST_Idle;
3045 
--            end if;
3046 
--
3047 
--
3048 
--          when icapST_Access =>
3049 
--               icap_CLK   <= '1';
3050 
--               icap_I     <= icap_I;
3051 
--               icap_Write <= icap_Write;
3052 
--               icap_CE    <= icap_CE;
3053 
--               FSM_icap   <= icapST_Abort;
3054 
--
3055 
--          when icapST_Abort =>
3056 
--               icap_CLK   <= '0';
3057 
--               icap_I     <= icap_I;
3058 
--               icap_Write <= icap_Write;
3059 
--               icap_CE    <= icap_CE;
3060 
--               FSM_icap   <= icapST_Idle;
3061 
--
3062 
--          when Others =>
3063 
--            icap_CLK      <= '0';
3064 
--            icap_I        <= (OTHERS => '0');
3065 
--            icap_Write    <= '1';
3066 
--            icap_CE       <= '1';
3067 
--            FSM_icap      <= icapST_Idle;
3068 
--
3069 
--        end case;
3070 
--
3071 
--      end if;
3072 
--   end process;
3073 
--
3074 
 
3075 
 
3076 
----------------------------------------------------------
3077 
---------------  Tx reading registers  -------------------
3078 
----------------------------------------------------------
3079 
 
3080 
----------------------------------------------------------
3081 
-- Synch Register:  Read Selection
3082 
--
3083 
   Tx_DMA_Reg_RdMuxer:
3084 
   process ( trn_clk, trn_lnk_up_n)
3085 
   begin
3086 
      if trn_lnk_up_n = '1' then
3087 
           Reg_RdMuxer_Hi     <= (Others =>'0');
3088 
           Reg_RdMuxer_Lo     <= (Others =>'0');
3089 
 
3090 
      elsif trn_clk'event and trn_clk = '1' then
3091 
 
3092 
         FOR k IN 0 TO C_NUM_OF_ADDRESSES-1 LOOP
3093 
            if Regs_RdAddr_i(C_DECODE_BIT_TOP downto C_DECODE_BIT_BOT)= C_REGS_BASE_ADDR(C_DECODE_BIT_TOP downto C_DECODE_BIT_BOT)
3094 
               and Regs_RdAddr_i(C_DECODE_BIT_BOT-1 downto 2)=CONV_STD_LOGIC_VECTOR(k, C_DECODE_BIT_BOT-2)
3095 
               and Regs_RdAddr_i(2-1 downto 0)="00"
3096 
               then
3097 
               Reg_RdMuxer_Hi(k) <= '1';
3098 
            else
3099 
               Reg_RdMuxer_Hi(k) <= '0';
3100 
            end if;
3101 
         END LOOP;
3102 
 
3103 
         if Regs_RdAddr_i(C_DECODE_BIT_TOP downto C_DECODE_BIT_BOT)= C_ALL_ONES(C_DECODE_BIT_TOP downto C_DECODE_BIT_BOT)
3104 
            and Regs_RdAddr_i(C_DECODE_BIT_BOT-1 downto 2)=C_ALL_ONES(C_DECODE_BIT_BOT-1 downto 2)
3105 
            and Regs_RdAddr_i(2-1 downto 0)="00"
3106 
            then
3107 
            Reg_RdMuxer_Lo(0) <= '1';
3108 
         else
3109 
            Reg_RdMuxer_Lo(0) <= '0';
3110 
         end if;
3111 
         FOR k IN 1 TO C_NUM_OF_ADDRESSES-1 LOOP
3112 
            if Regs_RdAddr_i(C_DECODE_BIT_TOP downto C_DECODE_BIT_BOT)= C_REGS_BASE_ADDR(C_DECODE_BIT_TOP downto C_DECODE_BIT_BOT)
3113 
               and Regs_RdAddr_i(C_DECODE_BIT_BOT-1 downto 2)=CONV_STD_LOGIC_VECTOR(k-1, C_DECODE_BIT_BOT-2)
3114 
               and Regs_RdAddr_i(2-1 downto 0)="00"
3115 
               then
3116 
               Reg_RdMuxer_Lo(k) <= '1';
3117 
            else
3118 
               Reg_RdMuxer_Lo(k) <= '0';
3119 
            end if;
3120 
         END LOOP;
3121 
 
3122 
      end if;
3123 
   end process;
3124 
 
3125 
 
3126 
----------------------------------------------------------
3127 
-- Synch Register:  CTL_TTake
3128 
--
3129 
   Syn_CTL_ttake:
3130 
   process ( trn_clk, trn_lnk_up_n)
3131 
   begin
3132 
      if trn_lnk_up_n = '1' then
3133 
         ctl_ttake_i      <= '0';
3134 
         ctl_t_read_Hi_r1 <= '0';
3135 
         ctl_t_read_Lo_r1 <= '0';
3136 
         CTL_read_counter <= (OTHERS=>'0');
3137 
 
3138 
      elsif trn_clk'event and trn_clk = '1' then
3139 
         ctl_t_read_Hi_r1 <= Reg_RdMuxer_Hi(CINT_ADDR_CTL_CLASS);
3140 
         ctl_t_read_Lo_r1 <= Reg_RdMuxer_Lo(CINT_ADDR_CTL_CLASS);
3141 
         ctl_ttake_i  <= (Reg_RdMuxer_Hi(CINT_ADDR_CTL_CLASS) and not ctl_t_read_Hi_r1)
3142 
                      or (Reg_RdMuxer_Lo(CINT_ADDR_CTL_CLASS) and not ctl_t_read_Lo_r1)
3143 
                      ;
3144 
         if ctl_reset_i='1' then
3145 
            CTL_read_counter <= (OTHERS=>'0');
3146 
         else
3147 
            CTL_read_counter <= CTL_read_counter + ctl_ttake_i;
3148 
         end if;
3149 
 
3150 
      end if;
3151 
   end process;
3152 
 
3153 
----------------------------------------------------------
3154 
-- Synch Register:  class_CTL_Status
3155 
--
3156 
   Syn_class_CTL_Status:
3157 
   process ( trn_clk, trn_lnk_up_n)
3158 
   begin
3159 
      if trn_lnk_up_n = '1' then
3160 
         class_CTL_Status_i      <= (OTHERS=>'0');
3161 
 
3162 
      elsif trn_clk'event and trn_clk = '1' then
3163 
         class_CTL_Status_i(C_DBUS_WIDTH/2-1 downto 0)      <= ctl_status;
3164 
 
3165 
      end if;
3166 
   end process;
3167 
 
3168 
 
3169 
-- -------------------------------------------------------
3170 
--
3171 
   Sys_Int_Status_i     <= (
3172 
                            CINT_BIT_DLM_IN_ISR     => DLM_irq     ,
3173 
                            CINT_BIT_CTL_IN_ISR     => CTL_irq     ,
3174 
                            CINT_BIT_DAQ_IN_ISR     => DAQ_irq     ,
3175 
 
3176 
                            CINT_BIT_DSTOUT_IN_ISR  => DMA_ds_Tout ,
3177 
                            CINT_BIT_USTOUT_IN_ISR  => DMA_us_Tout ,
3178 
 
3179 
                            CINT_BIT_INTGEN_IN_ISR  => IG_Asserting,
3180 
                            CINT_BIT_DS_DONE_IN_ISR => DMA_ds_Done ,
3181 
                            CINT_BIT_US_DONE_IN_ISR => DMA_us_Done ,
3182 
                            OTHERS                  => '0'
3183 
                           );
3184 
 
3185 
   --------------------------------------------------------------------------
3186 
   -- Upstream Registers
3187 
   --------------------------------------------------------------------------
3188 
 
3189 
   --  Peripheral Address Start point
3190 
   DMA_us_PA_o_Hi(C_DBUS_WIDTH-1 downto C_DBUS_WIDTH/2)
3191 
      <= DMA_us_PA_i(C_DBUS_WIDTH-1 downto C_DBUS_WIDTH/2) when Reg_RdMuxer_Hi(CINT_ADDR_DMA_US_PAH)='1'
3192 
         else (Others=>'0');
3193 
 
3194 
   DMA_us_PA_o_Hi(C_DBUS_WIDTH/2-1 downto 0)
3195 
      <= DMA_us_PA_i(C_DBUS_WIDTH/2-1 downto 0) when Reg_RdMuxer_Hi(CINT_ADDR_DMA_US_PAL)='1'
3196 
         else (Others=>'0');
3197 
 
3198 
 
3199 
   --  Host Address Start point
3200 
   DMA_us_HA_o_Hi(C_DBUS_WIDTH-1 downto C_DBUS_WIDTH/2)
3201 
      <= DMA_us_HA_i(C_DBUS_WIDTH-1 downto C_DBUS_WIDTH/2) when Reg_RdMuxer_Hi(CINT_ADDR_DMA_US_HAH)='1'
3202 
         else (Others=>'0');
3203 
 
3204 
   DMA_us_HA_o_Hi(C_DBUS_WIDTH/2-1 downto 0)
3205 
      <= DMA_us_HA_i(C_DBUS_WIDTH/2-1 downto 0) when Reg_RdMuxer_Hi(CINT_ADDR_DMA_US_HAL)='1'
3206 
         else (Others=>'0');
3207 
 
3208 
 
3209 
   --  Next Descriptor Address
3210 
   DMA_us_BDA_o_Hi(C_DBUS_WIDTH-1 downto C_DBUS_WIDTH/2)
3211 
      <= DMA_us_BDA_i(C_DBUS_WIDTH-1 downto C_DBUS_WIDTH/2) when Reg_RdMuxer_Hi(CINT_ADDR_DMA_US_BDAH)='1'
3212 
         else (Others=>'0');
3213 
 
3214 
   DMA_us_BDA_o_Hi(C_DBUS_WIDTH/2-1 downto 0)
3215 
      <= DMA_us_BDA_i(C_DBUS_WIDTH/2-1 downto 0) when Reg_RdMuxer_Hi(CINT_ADDR_DMA_US_BDAL)='1'
3216 
         else (Others=>'0');
3217 
 
3218 
   --  Length
3219 
   DMA_us_Length_o_Hi(32-1 downto 0)
3220 
      <= DMA_us_Length_i(32-1 downto 0) when Reg_RdMuxer_Hi(CINT_ADDR_DMA_US_LENG)='1'
3221 
         else (Others=>'0');
3222 
 
3223 
   --  Control word
3224 
   DMA_us_Control_o_Hi(32-1 downto 0)
3225 
      <= DMA_us_Control_i(32-1 downto 0) when Reg_RdMuxer_Hi(CINT_ADDR_DMA_US_CTRL)='1'
3226 
         else (Others=>'0');
3227 
 
3228 
   --  Status (Read only)
3229 
   DMA_us_Status_o_Hi(32-1 downto 0)
3230 
      <= DMA_us_Status_i(32-1 downto 0) when Reg_RdMuxer_Hi(CINT_ADDR_DMA_US_STA)='1'
3231 
         else (Others=>'0');
3232 
 
3233 
   --  Tranferred bytes (Read only)
3234 
   DMA_us_Transf_Bytes_o_Hi(32-1 downto 0)
3235 
      <= DMA_us_Transf_Bytes_i(32-1 downto 0) when Reg_RdMuxer_Hi(CINT_ADDR_US_TRANSF_BC)='1'
3236 
         else (Others=>'0');
3237 
 
3238 
 
3239 
   --  Peripheral Address Start point
3240 
   DMA_us_PA_o_Lo(C_DBUS_WIDTH-1 downto C_DBUS_WIDTH/2)
3241 
      <= DMA_us_PA_i(C_DBUS_WIDTH-1 downto C_DBUS_WIDTH/2) when Reg_RdMuxer_Lo(CINT_ADDR_DMA_US_PAH)='1'
3242 
         else (Others=>'0');
3243 
 
3244 
   DMA_us_PA_o_Lo(C_DBUS_WIDTH/2-1 downto 0)
3245 
      <= DMA_us_PA_i(C_DBUS_WIDTH/2-1 downto 0) when Reg_RdMuxer_Lo(CINT_ADDR_DMA_US_PAL)='1'
3246 
         else (Others=>'0');
3247 
 
3248 
 
3249 
   --  Host Address Start point
3250 
   DMA_us_HA_o_Lo(C_DBUS_WIDTH-1 downto C_DBUS_WIDTH/2)
3251 
      <= DMA_us_HA_i(C_DBUS_WIDTH-1 downto C_DBUS_WIDTH/2) when Reg_RdMuxer_Lo(CINT_ADDR_DMA_US_HAH)='1'
3252 
         else (Others=>'0');
3253 
 
3254 
   DMA_us_HA_o_Lo(C_DBUS_WIDTH/2-1 downto 0)
3255 
      <= DMA_us_HA_i(C_DBUS_WIDTH/2-1 downto 0) when Reg_RdMuxer_Lo(CINT_ADDR_DMA_US_HAL)='1'
3256 
         else (Others=>'0');
3257 
 
3258 
 
3259 
   --  Next Descriptor Address
3260 
   DMA_us_BDA_o_Lo(C_DBUS_WIDTH-1 downto C_DBUS_WIDTH/2)
3261 
      <= DMA_us_BDA_i(C_DBUS_WIDTH-1 downto C_DBUS_WIDTH/2) when Reg_RdMuxer_Lo(CINT_ADDR_DMA_US_BDAH)='1'
3262 
         else (Others=>'0');
3263 
 
3264 
   DMA_us_BDA_o_Lo(C_DBUS_WIDTH/2-1 downto 0)
3265 
      <= DMA_us_BDA_i(C_DBUS_WIDTH/2-1 downto 0) when Reg_RdMuxer_Lo(CINT_ADDR_DMA_US_BDAL)='1'
3266 
         else (Others=>'0');
3267 
 
3268 
   --  Length
3269 
   DMA_us_Length_o_Lo(32-1 downto 0)
3270 
      <= DMA_us_Length_i(32-1 downto 0) when Reg_RdMuxer_Lo(CINT_ADDR_DMA_US_LENG)='1'
3271 
         else (Others=>'0');
3272 
 
3273 
   --  Control word
3274 
   DMA_us_Control_o_Lo(32-1 downto 0)
3275 
      <= DMA_us_Control_i(32-1 downto 0) when Reg_RdMuxer_Lo(CINT_ADDR_DMA_US_CTRL)='1'
3276 
         else (Others=>'0');
3277 
 
3278 
   --  Status (Read only)
3279 
   DMA_us_Status_o_Lo(32-1 downto 0)
3280 
      <= DMA_us_Status_i(32-1 downto 0) when Reg_RdMuxer_Lo(CINT_ADDR_DMA_US_STA)='1'
3281 
         else (Others=>'0');
3282 
 
3283 
   --  Tranferred bytes (Read only)
3284 
   DMA_us_Transf_Bytes_o_Lo(32-1 downto 0)
3285 
      <= DMA_us_Transf_Bytes_i(32-1 downto 0) when Reg_RdMuxer_Lo(CINT_ADDR_US_TRANSF_BC)='1'
3286 
         else (Others=>'0');
3287 
 
3288 
   --------------------------------------------------------------------------
3289 
   -- Downstream Registers
3290 
   --------------------------------------------------------------------------
3291 
 
3292 
   --  Peripheral Address Start point
3293 
   DMA_ds_PA_o_Hi(C_DBUS_WIDTH-1 downto C_DBUS_WIDTH/2)
3294 
      <= DMA_ds_PA_i(C_DBUS_WIDTH-1 downto C_DBUS_WIDTH/2) when Reg_RdMuxer_Hi(CINT_ADDR_DMA_DS_PAH)='1'
3295 
         else (Others=>'0');
3296 
 
3297 
   DMA_ds_PA_o_Hi(C_DBUS_WIDTH/2-1 downto 0)
3298 
      <= DMA_ds_PA_i(C_DBUS_WIDTH/2-1 downto 0) when Reg_RdMuxer_Hi(CINT_ADDR_DMA_DS_PAL)='1'
3299 
         else (Others=>'0');
3300 
 
3301 
   --  Host Address Start point
3302 
   DMA_ds_HA_o_Hi(C_DBUS_WIDTH-1 downto C_DBUS_WIDTH/2)
3303 
      <= DMA_ds_HA_i(C_DBUS_WIDTH-1 downto C_DBUS_WIDTH/2) when Reg_RdMuxer_Hi(CINT_ADDR_DMA_DS_HAH)='1'
3304 
         else (Others=>'0');
3305 
 
3306 
   DMA_ds_HA_o_Hi(C_DBUS_WIDTH/2-1 downto 0)
3307 
      <= DMA_ds_HA_i(C_DBUS_WIDTH/2-1 downto 0) when Reg_RdMuxer_Hi(CINT_ADDR_DMA_DS_HAL)='1'
3308 
         else (Others=>'0');
3309 
 
3310 
   --  Next Descriptor Address
3311 
   DMA_ds_BDA_o_Hi(C_DBUS_WIDTH-1 downto C_DBUS_WIDTH/2)
3312 
      <= DMA_ds_BDA_i(C_DBUS_WIDTH-1 downto C_DBUS_WIDTH/2) when Reg_RdMuxer_Hi(CINT_ADDR_DMA_DS_BDAH)='1'
3313 
         else (Others=>'0');
3314 
 
3315 
   DMA_ds_BDA_o_Hi(C_DBUS_WIDTH/2-1 downto 0)
3316 
      <= DMA_ds_BDA_i(C_DBUS_WIDTH/2-1 downto 0) when Reg_RdMuxer_Hi(CINT_ADDR_DMA_DS_BDAL)='1'
3317 
         else (Others=>'0');
3318 
 
3319 
   --  Length
3320 
   DMA_ds_Length_o_Hi(32-1 downto 0)
3321 
      <= DMA_ds_Length_i(32-1 downto 0) when Reg_RdMuxer_Hi(CINT_ADDR_DMA_DS_LENG)='1'
3322 
         else (Others=>'0');
3323 
 
3324 
   --  Control word
3325 
   DMA_ds_Control_o_Hi(32-1 downto 0)
3326 
      <= DMA_ds_Control_i(32-1 downto 0) when Reg_RdMuxer_Hi(CINT_ADDR_DMA_DS_CTRL)='1'
3327 
         else (Others=>'0');
3328 
 
3329 
   --  Status (Read only)
3330 
   DMA_ds_Status_o_Hi(32-1 downto 0)
3331 
      <= DMA_ds_Status_i(32-1 downto 0) when Reg_RdMuxer_Hi(CINT_ADDR_DMA_DS_STA)='1'
3332 
         else (Others=>'0');
3333 
 
3334 
   --  Tranferred bytes (Read only)
3335 
   DMA_ds_Transf_Bytes_o_Hi(32-1 downto 0)
3336 
      <= DMA_ds_Transf_Bytes_i(32-1 downto 0) when Reg_RdMuxer_Hi(CINT_ADDR_DS_TRANSF_BC)='1'
3337 
         else (Others=>'0');
3338 
 
3339 
   --  Peripheral Address Start point
3340 
   DMA_ds_PA_o_Lo(C_DBUS_WIDTH-1 downto C_DBUS_WIDTH/2)
3341 
      <= DMA_ds_PA_i(C_DBUS_WIDTH-1 downto C_DBUS_WIDTH/2) when Reg_RdMuxer_Lo(CINT_ADDR_DMA_DS_PAH)='1'
3342 
         else (Others=>'0');
3343 
 
3344 
   DMA_ds_PA_o_Lo(C_DBUS_WIDTH/2-1 downto 0)
3345 
      <= DMA_ds_PA_i(C_DBUS_WIDTH/2-1 downto 0) when Reg_RdMuxer_Lo(CINT_ADDR_DMA_DS_PAL)='1'
3346 
         else (Others=>'0');
3347 
 
3348 
   --  Host Address Start point
3349 
   DMA_ds_HA_o_Lo(C_DBUS_WIDTH-1 downto C_DBUS_WIDTH/2)
3350 
      <= DMA_ds_HA_i(C_DBUS_WIDTH-1 downto C_DBUS_WIDTH/2) when Reg_RdMuxer_Lo(CINT_ADDR_DMA_DS_HAH)='1'
3351 
         else (Others=>'0');
3352 
 
3353 
   DMA_ds_HA_o_Lo(C_DBUS_WIDTH/2-1 downto 0)
3354 
      <= DMA_ds_HA_i(C_DBUS_WIDTH/2-1 downto 0) when Reg_RdMuxer_Lo(CINT_ADDR_DMA_DS_HAL)='1'
3355 
         else (Others=>'0');
3356 
 
3357 
   --  Next Descriptor Address
3358 
   DMA_ds_BDA_o_Lo(C_DBUS_WIDTH-1 downto C_DBUS_WIDTH/2)
3359 
      <= DMA_ds_BDA_i(C_DBUS_WIDTH-1 downto C_DBUS_WIDTH/2) when Reg_RdMuxer_Lo(CINT_ADDR_DMA_DS_BDAH)='1'
3360 
         else (Others=>'0');
3361 
 
3362 
   DMA_ds_BDA_o_Lo(C_DBUS_WIDTH/2-1 downto 0)
3363 
      <= DMA_ds_BDA_i(C_DBUS_WIDTH/2-1 downto 0) when Reg_RdMuxer_Lo(CINT_ADDR_DMA_DS_BDAL)='1'
3364 
         else (Others=>'0');
3365 
 
3366 
   --  Length
3367 
   DMA_ds_Length_o_Lo(32-1 downto 0)
3368 
      <= DMA_ds_Length_i(32-1 downto 0) when Reg_RdMuxer_Lo(CINT_ADDR_DMA_DS_LENG)='1'
3369 
         else (Others=>'0');
3370 
 
3371 
   --  Control word
3372 
   DMA_ds_Control_o_Lo(32-1 downto 0)
3373 
      <= DMA_ds_Control_i(32-1 downto 0) when Reg_RdMuxer_Lo(CINT_ADDR_DMA_DS_CTRL)='1'
3374 
         else (Others=>'0');
3375 
 
3376 
   --  Status (Read only)
3377 
   DMA_ds_Status_o_Lo(32-1 downto 0)
3378 
      <= DMA_ds_Status_i(32-1 downto 0) when Reg_RdMuxer_Lo(CINT_ADDR_DMA_DS_STA)='1'
3379 
         else (Others=>'0');
3380 
 
3381 
   --  Tranferred bytes (Read only)
3382 
   DMA_ds_Transf_Bytes_o_Lo(32-1 downto 0)
3383 
      <= DMA_ds_Transf_Bytes_i(32-1 downto 0) when Reg_RdMuxer_Lo(CINT_ADDR_DS_TRANSF_BC)='1'
3384 
         else (Others=>'0');
3385 
 
3386 
 
3387 
   --------------------------------------------------------------------------
3388 
   -- CTL
3389 
   --------------------------------------------------------------------------
3390 
   ctl_td_o_Hi(32-1 downto 0)
3391 
      <= ctl_td_r(32-1 downto 0) when Reg_RdMuxer_Hi(CINT_ADDR_CTL_CLASS)='1'
3392 
         else (Others=>'0');
3393 
 
3394 
   ctl_td_o_Lo(32-1 downto 0)
3395 
      <= ctl_td_r(32-1 downto 0) when Reg_RdMuxer_Lo(CINT_ADDR_CTL_CLASS)='1'
3396 
         else (Others=>'0');
3397 
 
3398 
   --------------------------------------------------------------------------
3399 
   -- DLM
3400 
   --------------------------------------------------------------------------
3401 
   dlm_rd_o_Hi(32-1 downto 0)
3402 
      <= dlm_rd_r(32-1 downto 0) when Reg_RdMuxer_Hi(CINT_ADDR_DLM_CLASS)='1'
3403 
         else (Others=>'0');
3404 
 
3405 
   dlm_rd_o_Lo(32-1 downto 0)
3406 
      <= dlm_rd_r(32-1 downto 0) when Reg_RdMuxer_Lo(CINT_ADDR_DLM_CLASS)='1'
3407 
         else (Others=>'0');
3408 
 
3409 
   --------------------------------------------------------------------------
3410 
   -- SIMONE USER REGISTERs
3411 
   --------------------------------------------------------------------------
3412 
   reg01_rd_o_Hi(32-1 downto 0)
3413 
      <= reg01_rd_r(32-1 downto 0) when Reg_RdMuxer_Hi(CINT_ADDR_REG01)='1'
3414 
         else (Others=>'0');
3415 
 
3416 
   reg01_rd_o_Lo(32-1 downto 0)
3417 
      <= reg01_rd_r(32-1 downto 0) when Reg_RdMuxer_Lo(CINT_ADDR_REG01)='1'
3418 
         else (Others=>'0');
3419 
 
3420 
   reg02_rd_o_Hi(32-1 downto 0)
3421 
      <= reg02_rd_r(32-1 downto 0) when Reg_RdMuxer_Hi(CINT_ADDR_REG02)='1'
3422 
         else (Others=>'0');
3423 
 
3424 
   reg02_rd_o_Lo(32-1 downto 0)
3425 
      <= reg02_rd_r(32-1 downto 0) when Reg_RdMuxer_Lo(CINT_ADDR_REG02)='1'
3426 
         else (Others=>'0');
3427 
 
3428 
   reg03_rd_o_Hi(32-1 downto 0)
3429 
      <= reg03_rd_r(32-1 downto 0) when Reg_RdMuxer_Hi(CINT_ADDR_REG03)='1'
3430 
         else (Others=>'0');
3431 
 
3432 
   reg03_rd_o_Lo(32-1 downto 0)
3433 
      <= reg03_rd_r(32-1 downto 0) when Reg_RdMuxer_Lo(CINT_ADDR_REG03)='1'
3434 
         else (Others=>'0');
3435 
 
3436 
   reg04_rd_o_Hi(32-1 downto 0)
3437 
      <= reg04_rd_r(32-1 downto 0) when Reg_RdMuxer_Hi(CINT_ADDR_REG04)='1'
3438 
         else (Others=>'0');
3439 
 
3440 
   reg04_rd_o_Lo(32-1 downto 0)
3441 
      <= reg04_rd_r(32-1 downto 0) when Reg_RdMuxer_Lo(CINT_ADDR_REG04)='1'
3442 
         else (Others=>'0');
3443 
 
3444 
   reg05_rd_o_Hi(32-1 downto 0)
3445 
      <= reg05_rd_r(32-1 downto 0) when Reg_RdMuxer_Hi(CINT_ADDR_REG05)='1'
3446 
         else (Others=>'0');
3447 
 
3448 
   reg05_rd_o_Lo(32-1 downto 0)
3449 
      <= reg05_rd_r(32-1 downto 0) when Reg_RdMuxer_Lo(CINT_ADDR_REG05)='1'
3450 
         else (Others=>'0');
3451 
 
3452 
   reg06_rd_o_Hi(32-1 downto 0)
3453 
      <= reg06_rd_r(32-1 downto 0) when Reg_RdMuxer_Hi(CINT_ADDR_REG06)='1'
3454 
         else (Others=>'0');
3455 
 
3456 
   reg06_rd_o_Lo(32-1 downto 0)
3457 
      <= reg06_rd_r(32-1 downto 0) when Reg_RdMuxer_Lo(CINT_ADDR_REG06)='1'
3458 
         else (Others=>'0');
3459 
 
3460 
   reg07_rd_o_Hi(32-1 downto 0)
3461 
      <= reg07_rd_r(32-1 downto 0) when Reg_RdMuxer_Hi(CINT_ADDR_REG07)='1'
3462 
         else (Others=>'0');
3463 
 
3464 
   reg07_rd_o_Lo(32-1 downto 0)
3465 
      <= reg07_rd_r(32-1 downto 0) when Reg_RdMuxer_Lo(CINT_ADDR_REG07)='1'
3466 
         else (Others=>'0');
3467 
 
3468 
   reg08_rd_o_Hi(32-1 downto 0)
3469 
      <= reg08_rd_r(32-1 downto 0) when Reg_RdMuxer_Hi(CINT_ADDR_REG08)='1'
3470 
         else (Others=>'0');
3471 
 
3472 
   reg08_rd_o_Lo(32-1 downto 0)
3473 
      <= reg08_rd_r(32-1 downto 0) when Reg_RdMuxer_Lo(CINT_ADDR_REG08)='1'
3474 
         else (Others=>'0');
3475 
 
3476 
   reg09_rd_o_Hi(32-1 downto 0)
3477 
      <= reg09_rd_r(32-1 downto 0) when Reg_RdMuxer_Hi(CINT_ADDR_REG09)='1'
3478 
         else (Others=>'0');
3479 
 
3480 
   reg09_rd_o_Lo(32-1 downto 0)
3481 
      <= reg09_rd_r(32-1 downto 0) when Reg_RdMuxer_Lo(CINT_ADDR_REG09)='1'
3482 
         else (Others=>'0');
3483 
 
3484 
   reg10_rd_o_Hi(32-1 downto 0)
3485 
      <= reg10_rd_r(32-1 downto 0) when Reg_RdMuxer_Hi(CINT_ADDR_REG10)='1'
3486 
         else (Others=>'0');
3487 
 
3488 
   reg10_rd_o_Lo(32-1 downto 0)
3489 
      <= reg10_rd_r(32-1 downto 0) when Reg_RdMuxer_Lo(CINT_ADDR_REG10)='1'
3490 
         else (Others=>'0');
3491 
 
3492 
   reg11_rd_o_Hi(32-1 downto 0)
3493 
      <= reg10_rd_r(32-1 downto 0) when Reg_RdMuxer_Hi(CINT_ADDR_REG11)='1'
3494 
         else (Others=>'0');
3495 
 
3496 
   reg11_rd_o_Lo(32-1 downto 0)
3497 
      <= reg10_rd_r(32-1 downto 0) when Reg_RdMuxer_Lo(CINT_ADDR_REG11)='1'
3498 
         else (Others=>'0');
3499 
 
3500 
   reg12_rd_o_Hi(32-1 downto 0)
3501 
      <= reg10_rd_r(32-1 downto 0) when Reg_RdMuxer_Hi(CINT_ADDR_REG12)='1'
3502 
         else (Others=>'0');
3503 
 
3504 
   reg12_rd_o_Lo(32-1 downto 0)
3505 
      <= reg10_rd_r(32-1 downto 0) when Reg_RdMuxer_Lo(CINT_ADDR_REG12)='1'
3506 
         else (Others=>'0');
3507 
 
3508 
   reg13_rd_o_Hi(32-1 downto 0)
3509 
      <= reg10_rd_r(32-1 downto 0) when Reg_RdMuxer_Hi(CINT_ADDR_REG13)='1'
3510 
         else (Others=>'0');
3511 
 
3512 
   reg13_rd_o_Lo(32-1 downto 0)
3513 
      <= reg10_rd_r(32-1 downto 0) when Reg_RdMuxer_Lo(CINT_ADDR_REG13)='1'
3514 
         else (Others=>'0');
3515 
 
3516 
   reg14_rd_o_Hi(32-1 downto 0)
3517 
      <= reg10_rd_r(32-1 downto 0) when Reg_RdMuxer_Hi(CINT_ADDR_REG14)='1'
3518 
         else (Others=>'0');
3519 
 
3520 
   reg14_rd_o_Lo(32-1 downto 0)
3521 
      <= reg10_rd_r(32-1 downto 0) when Reg_RdMuxer_Lo(CINT_ADDR_REG14)='1'
3522 
         else (Others=>'0');
3523 
 
3524 
   --------------------------------------------------------------------------
3525 
   -- System Interrupt Status
3526 
   --------------------------------------------------------------------------
3527 
   Sys_Int_Status_o_Hi(32-1 downto 0)
3528 
      <= (Sys_Int_Status_i(32-1 downto 0) and Sys_Int_Enable_i(32-1 downto 0)) when Reg_RdMuxer_Hi(CINT_ADDR_IRQ_STAT)='1'
3529 
         else (Others=>'0');
3530 
 
3531 
   Sys_Int_Enable_o_Hi(32-1 downto 0)
3532 
      <= Sys_Int_Enable_i(32-1 downto 0) when Reg_RdMuxer_Hi(CINT_ADDR_IRQ_EN)='1'
3533 
         else (Others=>'0');
3534 
 
3535 
   Sys_Int_Status_o_Lo(32-1 downto 0)
3536 
      <= (Sys_Int_Status_i(32-1 downto 0) and Sys_Int_Enable_i(32-1 downto 0)) when Reg_RdMuxer_Lo(CINT_ADDR_IRQ_STAT)='1'
3537 
         else (Others=>'0');
3538 
 
3539 
   Sys_Int_Enable_o_Lo(32-1 downto 0)
3540 
      <= Sys_Int_Enable_i(32-1 downto 0) when Reg_RdMuxer_Lo(CINT_ADDR_IRQ_EN)='1'
3541 
         else (Others=>'0');
3542 
 
3543 
 
3544 
        --debug_in_1i <= Sys_Int_Status_i(32-1 downto 0);
3545 
   --debug_in_2i <= Sys_Int_Enable_i(32-1 downto 0);
3546 
   --debug_in_3i <= "0000000000000000000000000000000" & DAQ_irq;
3547 
 
3548 
          debug_in_1i <= "0000000000000000000000000000000" & DMA_ds_Done;
3549 
          debug_in_2i <= "0000000000000000000000000000000" & DMA_us_Done;
3550 
     debug_in_3i <= "0000000000000000" & Sys_IRQ_i(C_NUM_OF_INTERRUPTS-1 downto 0);
3551 
          debug_in_4i <=  Sys_Int_Enable_i(32-1 downto 0);
3552 
 
3553 
 
3554 
   -- ----------------------------------------------------------------------------------
3555 
   -- ----------------------------------------------------------------------------------
3556 
   Gen_IG_Read:  if IMP_INT_GENERATOR generate
3557 
 
3558 
   --------------------------------------------------------------------------
3559 
   -- Interrupt Generator Latency
3560 
   --------------------------------------------------------------------------
3561 
   IG_Latency_o_Hi(32-1 downto 0)
3562 
      <= IG_Latency_i(32-1 downto 0) when Reg_RdMuxer_Hi(CINT_ADDR_IG_LATENCY)='1'
3563 
         else (Others=>'0');
3564 
 
3565 
   IG_Latency_o_Lo(32-1 downto 0)
3566 
      <= IG_Latency_i(32-1 downto 0) when Reg_RdMuxer_Lo(CINT_ADDR_IG_LATENCY)='1'
3567 
         else (Others=>'0');
3568 
   --------------------------------------------------------------------------
3569 
   -- Interrupt Generator Statistics
3570 
   --------------------------------------------------------------------------
3571 
   IG_Num_Assert_o_Hi(32-1 downto 0)
3572 
      <= IG_Num_Assert_i(32-1 downto 0) when Reg_RdMuxer_Hi(CINT_ADDR_IG_NUM_ASSERT)='1'
3573 
         else (Others=>'0');
3574 
 
3575 
   IG_Num_Deassert_o_Hi(32-1 downto 0)
3576 
      <= IG_Num_Deassert_i(32-1 downto 0) when Reg_RdMuxer_Hi(CINT_ADDR_IG_NUM_DEASSERT)='1'
3577 
         else (Others=>'0');
3578 
 
3579 
   IG_Num_Assert_o_Lo(32-1 downto 0)
3580 
      <= IG_Num_Assert_i(32-1 downto 0) when Reg_RdMuxer_Lo(CINT_ADDR_IG_NUM_ASSERT)='1'
3581 
         else (Others=>'0');
3582 
 
3583 
   IG_Num_Deassert_o_Lo(32-1 downto 0)
3584 
      <= IG_Num_Deassert_i(32-1 downto 0) when Reg_RdMuxer_Lo(CINT_ADDR_IG_NUM_DEASSERT)='1'
3585 
         else (Others=>'0');
3586 
 
3587 
   end generate;
3588 
 
3589 
 
3590 
   NotGen_IG_Read:  if not IMP_INT_GENERATOR generate
3591 
 
3592 
   IG_Latency_o_Hi(32-1 downto 0)      <= (Others=>'0');
3593 
   IG_Latency_o_Lo(32-1 downto 0)      <= (Others=>'0');
3594 
   IG_Num_Assert_o_Hi(32-1 downto 0)   <= (Others=>'0');
3595 
   IG_Num_Deassert_o_Hi(32-1 downto 0) <= (Others=>'0');
3596 
   IG_Num_Assert_o_Lo(32-1 downto 0)   <= (Others=>'0');
3597 
   IG_Num_Deassert_o_Lo(32-1 downto 0) <= (Others=>'0');
3598 
 
3599 
   end generate;
3600 
 
3601 
 
3602 
   --------------------------------------------------------------------------
3603 
   --  System Error
3604 
   --------------------------------------------------------------------------
3605 
   Synch_Sys_Error_i:
3606 
   process ( trn_clk, trn_lnk_up_n)
3607 
   begin
3608 
     if trn_lnk_up_n = '1' then
3609 
        Sys_Error_i                            <= (OTHERS => '0');
3610 
        eb_FIFO_OverWritten                    <= '0';
3611 
     elsif trn_clk'event and trn_clk = '1' then
3612 
        Sys_Error_i(CINT_BIT_TX_TOUT_IN_SER)   <= Tx_TimeOut;
3613 
        Sys_Error_i(CINT_BIT_EB_TOUT_IN_SER)   <= Tx_eb_TimeOut;
3614 
        Sys_Error_i(CINT_BIT_EB_OVERWRITTEN)   <= eb_FIFO_OverWritten;
3615 
        --  !!!!!!!!!!!!!! capture eb_FIFO overflow, temp cleared by MRd_Channel_Rst_i
3616 
        eb_FIFO_OverWritten      <= (not MRd_Channel_Rst_i) and (eb_FIFO_ow or eb_FIFO_OverWritten);
3617 
     end if;
3618 
   end process;
3619 
 
3620 
 
3621 
   --------------------------------------------------------------------------
3622 
   --  General Status and Control
3623 
   --------------------------------------------------------------------------
3624 
   Synch_General_Status_i:
3625 
   process ( trn_clk, trn_lnk_up_n)
3626 
   begin
3627 
     if trn_lnk_up_n = '1' then
3628 
       General_Status_i  <= (OTHERS => '0');
3629 
     elsif trn_clk'event and trn_clk = '1' then
3630 
       General_Status_i(32-1 downto 32-16)
3631 
                       <= cfg_dcommand;
3632 
       General_Status_i(CINT_BIT_LWIDTH_IN_GSR_TOP downto CINT_BIT_LWIDTH_IN_GSR_BOT)
3633 
                       <= pcie_link_width;
3634 
       General_Status_i(CINT_BIT_ICAP_BUSY_IN_GSR)
3635 
                       <= icap_Busy;
3636 
       General_Status_i(CINT_BIT_DG_AVAIL_IN_GSR)
3637 
                       <= DG_is_Available;
3638 
       General_Status_i(CINT_BIT_LINK_ACT_IN_GSR+1 downto CINT_BIT_LINK_ACT_IN_GSR)
3639 
                       <= protocol_link_act;
3640 
 
3641 
--       General_Status_i(8) <= CTL_read_counter(6-1);   ---- DEBUG !!!
3642 
     end if;
3643 
   end process;
3644 
 
3645 
 
3646 
 
3647 
   Sys_Error_o_Hi(32-1 downto 0)
3648 
      <= Sys_Error_i(32-1 downto 0) when Reg_RdMuxer_Hi(CINT_ADDR_ERROR)='1'
3649 
         else (Others=>'0');
3650 
 
3651 
   General_Status_o_Hi(32-1 downto 0)
3652 
      <= General_Status_i(32-1 downto 0) when Reg_RdMuxer_Hi(CINT_ADDR_STATUS)='1'
3653 
         else (Others=>'0');
3654 
 
3655 
   General_Control_o_Hi(32-1 downto 0)
3656 
      <= General_Control_i(32-1 downto 0) when Reg_RdMuxer_Hi(CINT_ADDR_CONTROL)='1'
3657 
         else (Others=>'0');
3658 
 
3659 
   Sys_Error_o_Lo(32-1 downto 0)
3660 
      <= Sys_Error_i(32-1 downto 0) when Reg_RdMuxer_Lo(CINT_ADDR_ERROR)='1'
3661 
         else (Others=>'0');
3662 
 
3663 
   General_Status_o_Lo(32-1 downto 0)
3664 
      <= General_Status_i(32-1 downto 0) when Reg_RdMuxer_Lo(CINT_ADDR_STATUS)='1'
3665 
         else (Others=>'0');
3666 
 
3667 
   General_Control_o_Lo(32-1 downto 0)
3668 
      <= General_Control_i(32-1 downto 0) when Reg_RdMuxer_Lo(CINT_ADDR_CONTROL)='1'
3669 
         else (Others=>'0');
3670 
 
3671 
 
3672 
   --------------------------------------------------------------------------
3673 
   -- ICAP
3674 
   --------------------------------------------------------------------------
3675 
   icap_O_o_Hi(32-1 downto 0)
3676 
      <= icap_O(32-1 downto 0) when Reg_RdMuxer_Hi(CINT_ADDR_ICAP)='1'
3677 
         else (Others=>'0');
3678 
 
3679 
   icap_O_o_Lo(32-1 downto 0)
3680 
      <= icap_O(32-1 downto 0) when Reg_RdMuxer_Lo(CINT_ADDR_ICAP)='1'
3681 
         else (Others=>'0');
3682 
 
3683 
   --------------------------------------------------------------------------
3684 
   -- FIFO Statuses (read only)
3685 
   --------------------------------------------------------------------------
3686 
   eb_FIFO_Status_o_Hi(32-1 downto 0)
3687 
      <= eb_FIFO_Status_r1(32-1 downto 0) when Reg_RdMuxer_Hi(CINT_ADDR_EB_STACON)='1'
3688 
         else (Others=>'0');
3689 
 
3690 
   eb_FIFO_Status_o_Lo(32-1 downto 0)
3691 
      <= eb_FIFO_Status_r1(32-1 downto 0) when Reg_RdMuxer_Lo(CINT_ADDR_EB_STACON)='1'
3692 
         else (Others=>'0');
3693 
 
3694 
   H2B_FIFO_Status_o_Hi(32-1 downto 0)
3695 
      <= H2B_FIFO_Status_r1(32-1 downto 0) when Reg_RdMuxer_Hi(CINT_ADDR_H2B_STACON)='1'
3696 
         else (Others=>'0');
3697 
 
3698 
   H2B_FIFO_Status_o_Lo(32-1 downto 0)
3699 
      <= H2B_FIFO_Status_r1(32-1 downto 0) when Reg_RdMuxer_Lo(CINT_ADDR_H2B_STACON)='1'
3700 
         else (Others=>'0');
3701 
 
3702 
   B2H_FIFO_Status_o_Hi(32-1 downto 0)
3703 
      <= B2H_FIFO_Status_r1(32-1 downto 0) when Reg_RdMuxer_Hi(CINT_ADDR_B2H_STACON)='1'
3704 
         else (Others=>'0');
3705 
 
3706 
   B2H_FIFO_Status_o_Lo(32-1 downto 0)
3707 
      <= B2H_FIFO_Status_r1(32-1 downto 0) when Reg_RdMuxer_Lo(CINT_ADDR_B2H_STACON)='1'
3708 
         else (Others=>'0');
3709 
 
3710 
        --S debug_in_4i <=  B2H_FIFO_Status_r1(32-1 downto 0);
3711 
 
3712 
   --------------------------------------------------------------------------
3713 
   -- Optical Link Status
3714 
   --------------------------------------------------------------------------
3715 
   Opto_Link_Status_o_Hi(32-1 downto 0)
3716 
      <= Opto_Link_Status_i(32-1 downto 0) when Reg_RdMuxer_Hi(CINT_ADDR_PROTOCOL_STACON)='1'
3717 
         else (Others=>'0');
3718 
 
3719 
   Opto_link_Status_o_Lo(32-1 downto 0)
3720 
      <= Opto_Link_Status_i(32-1 downto 0) when Reg_RdMuxer_Lo(CINT_ADDR_PROTOCOL_STACON)='1'
3721 
         else (Others=>'0');
3722 
 
3723 
   --------------------------------------------------------------------------
3724 
   -- Class CTL status
3725 
   --------------------------------------------------------------------------
3726 
   class_CTL_Status_o_Hi(32-1 downto 0)
3727 
      <= class_CTL_Status_i(32-1 downto 0) when Reg_RdMuxer_Hi(CINT_ADDR_TC_STATUS)='1'
3728 
         else (Others=>'0');
3729 
 
3730 
   class_CTL_Status_o_Lo(32-1 downto 0)
3731 
      <= class_CTL_Status_i(32-1 downto 0) when Reg_RdMuxer_Lo(CINT_ADDR_TC_STATUS)='1'
3732 
         else (Others=>'0');
3733 
 
3734 
   --------------------------------------------------------------------------
3735 
   -- Data generator Status
3736 
   --------------------------------------------------------------------------
3737 
   DG_Status_o_Hi(32-1 downto 0)
3738 
      <= DG_Status_i(32-1 downto 0) when Reg_RdMuxer_Hi(CINT_ADDR_DG_CTRL)='1'
3739 
         else (Others=>'0');
3740 
 
3741 
   DG_Status_o_Lo(32-1 downto 0)
3742 
      <= DG_Status_i(32-1 downto 0) when Reg_RdMuxer_Lo(CINT_ADDR_DG_CTRL)='1'
3743 
         else (Others=>'0');
3744 
 
3745 
   --------------------------------------------------------------------------
3746 
   -- Hardware version
3747 
   --------------------------------------------------------------------------
3748 
   HW_Version_o_Hi(32-1 downto 0)
3749 
      <= C_DESIGN_ID(32-1 downto 0) when Reg_RdMuxer_Hi(CINT_ADDR_VERSION)='1'
3750 
         else (Others=>'0');
3751 
 
3752 
   HW_Version_o_Lo(32-1 downto 0)
3753 
      <= C_DESIGN_ID(32-1 downto 0) when Reg_RdMuxer_Lo(CINT_ADDR_VERSION)='1'
3754 
         else (Others=>'0');
3755 
 
3756 
-----------------------------------------------------
3757 
-- Sequential : Regs_RdQout_i
3758 
--
3759 
   Synch_Regs_RdQout:
3760 
   process ( trn_clk, trn_lnk_up_n)
3761 
   begin
3762 
      if trn_lnk_up_n = '1' then
3763 
         Regs_RdQout_i <= (OTHERS =>'0');
3764 
 
3765 
      elsif trn_clk'event and trn_clk = '1' then
3766 
 
3767 
         Regs_RdQout_i(64-1 downto 32)        <=
3768 
                                  HW_Version_o_Hi     (32-1 downto 0)
3769 
 
3770 
                              or  Sys_Error_o_Hi      (32-1 downto 0)
3771 
                              or  General_Status_o_Hi (32-1 downto 0)
3772 
                              or  General_Control_o_Hi(32-1 downto 0)
3773 
 
3774 
                              or  Sys_Int_Status_o_Hi (32-1 downto 0)
3775 
                              or  Sys_Int_Enable_o_Hi (32-1 downto 0)
3776 
 
3777 
--                              or  DMA_us_PA_o_Hi      (C_DBUS_WIDTH-1 downto 32)
3778 
                              or  DMA_us_PA_o_Hi      (32-1   downto          0)
3779 
                              or  DMA_us_HA_o_Hi      (C_DBUS_WIDTH-1 downto 32)
3780 
                              or  DMA_us_HA_o_Hi      (32-1   downto          0)
3781 
                              or  DMA_us_BDA_o_Hi     (C_DBUS_WIDTH-1 downto 32)
3782 
                              or  DMA_us_BDA_o_Hi     (32-1   downto          0)
3783 
                              or  DMA_us_Length_o_Hi  (32-1 downto 0)
3784 
                              or  DMA_us_Control_o_Hi (32-1 downto 0)
3785 
                              or  DMA_us_Status_o_Hi  (32-1 downto 0)
3786 
                              or  DMA_us_Transf_Bytes_o_Hi  (32-1 downto 0)
3787 
 
3788 
--                              or  DMA_ds_PA_o_Hi      (C_DBUS_WIDTH-1 downto 32)
3789 
                              or  DMA_ds_PA_o_Hi      (32-1   downto          0)
3790 
                              or  DMA_ds_HA_o_Hi      (C_DBUS_WIDTH-1 downto 32)
3791 
                              or  DMA_ds_HA_o_Hi      (32-1   downto          0)
3792 
                              or  DMA_ds_BDA_o_Hi     (C_DBUS_WIDTH-1 downto 32)
3793 
                              or  DMA_ds_BDA_o_Hi     (32-1   downto          0)
3794 
                              or  DMA_ds_Length_o_Hi  (32-1 downto 0)
3795 
                              or  DMA_ds_Control_o_Hi (32-1 downto 0)
3796 
                              or  DMA_ds_Status_o_Hi  (32-1 downto 0)
3797 
                              or  DMA_ds_Transf_Bytes_o_Hi  (32-1 downto 0)
3798 
 
3799 
                              or  IG_Latency_o_Hi     (32-1 downto 0)
3800 
                              or  IG_Num_Assert_o_Hi  (32-1 downto 0)
3801 
                              or  IG_Num_Deassert_o_Hi(32-1 downto 0)
3802 
 
3803 
                              or  DG_Status_o_Hi      (32-1 downto 0)
3804 
                              or  class_CTL_Status_o_Hi  (32-1 downto 0)
3805 
 
3806 
--                              or  icap_O_o_Hi         (32-1 downto 0)
3807 
                              or  Opto_Link_Status_o_Hi (32-1 downto 0)
3808 
                              or  eb_FIFO_Status_o_Hi (32-1 downto 0)
3809 
                              or  H2B_FIFO_Status_o_Hi (32-1 downto 0)
3810 
                              or  B2H_FIFO_Status_o_Hi (32-1 downto 0)
3811 
                                                                                or  dlm_rd_o_Hi
3812 
                                                                                or  ctl_td_o_Hi
3813 
                                                                                or  reg01_rd_o_Hi
3814 
                              or  reg02_rd_o_Hi
3815 
                                                                                or  reg03_rd_o_Hi
3816 
                                                                                or  reg04_rd_o_Hi
3817 
                                                                                or  reg05_rd_o_Hi
3818 
                                                                                or  reg06_rd_o_Hi
3819 
                                                                                or  reg07_rd_o_Hi
3820 
                                                                                or  reg08_rd_o_Hi
3821 
                                                                                or  reg09_rd_o_Hi
3822 
                                                                                or  reg10_rd_o_Hi
3823 
                                                                                or  reg11_rd_o_Hi
3824 
                                                                                or  reg12_rd_o_Hi
3825 
                                                                                or  reg13_rd_o_Hi
3826 
                                                                                or  reg14_rd_o_Hi
3827 
                                                                                ;
3828 
 
3829 
 
3830 
         Regs_RdQout_i(32-1 downto 0)        <=
3831 
                                  HW_Version_o_Lo     (32-1 downto 0)
3832 
 
3833 
                              or  Sys_Error_o_Lo      (32-1 downto 0)
3834 
                              or  General_Status_o_Lo (32-1 downto 0)
3835 
                              or  General_Control_o_Lo(32-1 downto 0)
3836 
 
3837 
                              or  Sys_Int_Status_o_Lo (32-1 downto 0)
3838 
                              or  Sys_Int_Enable_o_Lo (32-1 downto 0)
3839 
 
3840 
--                              or  DMA_us_PA_o_Lo      (C_DBUS_WIDTH-1 downto 32)
3841 
                              or  DMA_us_PA_o_Lo      (32-1   downto          0)
3842 
                              or  DMA_us_HA_o_Lo      (C_DBUS_WIDTH-1 downto 32)
3843 
                              or  DMA_us_HA_o_Lo      (32-1   downto          0)
3844 
                              or  DMA_us_BDA_o_Lo     (C_DBUS_WIDTH-1 downto 32)
3845 
                              or  DMA_us_BDA_o_Lo     (32-1   downto          0)
3846 
                              or  DMA_us_Length_o_Lo  (32-1 downto 0)
3847 
                              or  DMA_us_Control_o_Lo (32-1 downto 0)
3848 
                              or  DMA_us_Status_o_Lo  (32-1 downto 0)
3849 
                              or  DMA_us_Transf_Bytes_o_Lo  (32-1 downto 0)
3850 
 
3851 
--                              or  DMA_ds_PA_o_Lo      (C_DBUS_WIDTH-1 downto 32)
3852 
                              or  DMA_ds_PA_o_Lo      (32-1   downto          0)
3853 
                              or  DMA_ds_HA_o_Lo      (C_DBUS_WIDTH-1 downto 32)
3854 
                              or  DMA_ds_HA_o_Lo      (32-1   downto          0)
3855 
                              or  DMA_ds_BDA_o_Lo     (C_DBUS_WIDTH-1 downto 32)
3856 
                              or  DMA_ds_BDA_o_Lo     (32-1   downto          0)
3857 
                              or  DMA_ds_Length_o_Lo  (32-1 downto 0)
3858 
                              or  DMA_ds_Control_o_Lo (32-1 downto 0)
3859 
                              or  DMA_ds_Status_o_Lo  (32-1 downto 0)
3860 
                              or  DMA_ds_Transf_Bytes_o_Lo  (32-1 downto 0)
3861 
 
3862 
                              or  IG_Latency_o_Lo     (32-1 downto 0)
3863 
                              or  IG_Num_Assert_o_Lo  (32-1 downto 0)
3864 
                              or  IG_Num_Deassert_o_Lo(32-1 downto 0)
3865 
 
3866 
                              or  DG_Status_o_Lo      (32-1 downto 0)
3867 
                              or  class_CTL_Status_o_Lo  (32-1 downto 0)
3868 
 
3869 
--                              or  icap_O_o_Lo(32-1 downto 0)
3870 
                              or  Opto_Link_Status_o_Lo (32-1 downto 0)
3871 
                              or  eb_FIFO_Status_o_Lo (32-1 downto 0)
3872 
                              or  H2B_FIFO_Status_o_Lo (32-1 downto 0)
3873 
                              or  B2H_FIFO_Status_o_Lo (32-1 downto 0)
3874 
                                                                                or  dlm_rd_o_Lo
3875 
                                                                                or  ctl_td_o_Lo
3876 
                                                                                or  reg01_rd_o_Lo
3877 
                              or  reg02_rd_o_Lo
3878 
                                                                                or  reg03_rd_o_Lo
3879 
                                                                                or  reg04_rd_o_Lo
3880 
                              or  reg05_rd_o_Lo
3881 
                                                                                or  reg06_rd_o_Lo
3882 
                                                                                or  reg07_rd_o_Lo
3883 
                              or  reg08_rd_o_Lo
3884 
                                                                                or  reg09_rd_o_Lo
3885 
                                                                                or  reg10_rd_o_Lo
3886 
                                                                                or  reg11_rd_o_Lo
3887 
                                                                                or  reg12_rd_o_Lo
3888 
                                                                                or  reg13_rd_o_Lo
3889 
                                                                                or  reg14_rd_o_Lo
3890 
                              ;
3891 
 
3892 
      end if;
3893 
   end process;
3894 
 
3895 
 
3896 
-- -----------------------------------------------------------------------------
3897 
-- -- Implementation codes
3898 
-- -----------------------------------------------------------------------------
3899 
--  Gen_ICAP_width_8:
3900 
--  if C_ICAP_WIDTH=8 generate
3901 
--
3902 
--     ICAP_VIRTEX4_pcie :
3903 
--     ICAP_VIRTEX4
3904 
--       generic map (
3905 
--                    ICAP_WIDTH => "X8"    -- "X8" or "X32"
3906 
--                   )
3907 
--          port map (
3908 
--                    BUSY  => icap_BUSY ,   -- Busy output
3909 
--                    O     => icap_O    ,   -- 8-bit data output
3910 
--                    CE    => icap_CE   ,   -- Clock enable input
3911 
--                    CLK   => icap_CLK  ,   -- Clock input
3912 
--                    I     => icap_I    ,   -- 8-bit data input
3913 
--                    WRITE => icap_WRITE    -- Write input
3914 
--                   );
3915 
--
3916 
--  end generate;
3917 
--
3918 
--  Gen_ICAP_width_32:
3919 
--  if C_ICAP_WIDTH=32 generate
3920 
--
3921 
--     ICAP_VIRTEX4_pcie :
3922 
--     ICAP_VIRTEX4
3923 
--       generic map (
3924 
--                    ICAP_WIDTH => "X32"    -- "X8" or "X32"
3925 
--                   )
3926 
--          port map (
3927 
--                    BUSY  => icap_BUSY ,   -- Busy output
3928 
--                    O     => icap_O    ,   -- 32-bit data output
3929 
--                    CE    => icap_CE   ,   -- Clock enable input
3930 
--                    CLK   => icap_CLK  ,   -- Clock input
3931 
--                    I     => icap_I    ,   -- 32-bit data input
3932 
--                    WRITE => icap_WRITE    -- Write input
3933 
--                   );
3934 
--
3935 
--  end generate;
3936 
--
3937 
 
3938 
end Behavioral;

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