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[/] [pcie_sg_dma/] [branches/] [Virtex6/] [ML605_ISE12.3/] [class_daq.vhd] - Blame information for rev 11

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----------------------------------------------------------------------------------
-- Company:   ziti
-- Engineer:  wgao
-- 
-- Create Date:    17:01:32 19 Jun 2009
-- Design Name: 
-- Module Name:    class_daq - Behavioral 
-- Project Name: 
-- Target Devices: 
-- Tool versions: 
-- Description: 
--
-- Dependencies: 
--
-- Revision: 
-- Revision 0.01 - File Created
-- Additional Comments: 
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
 
library work;
use work.abb64Package.all;
 
---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
 
entity class_daq is
--    Generic (
--             C_PRO_DAQ_WIDTH  :  integer  :=  16 ;
--             C_PRO_DLM_WIDTH  :  integer  :=   4 ;
--             C_PRO_CTL_WIDTH  :  integer  :=  16
--            );
    Port (
 
           -- DAQ Tx
           data2send_start          : OUT   std_logic;
           data2send_end            : OUT   std_logic;
           data2send                : OUT   std_logic_vector(64-1 downto 0);
           crc_error_send           : OUT   std_logic;
           data2send_stop           : IN    std_logic;
 
           -- DAQ Rx
           data_rec_start           : IN    std_logic;
           data_rec_end             : IN    std_logic;
           data_rec                 : IN    std_logic_vector(64-1 downto 0);
           crc_error_rec            : IN    std_logic;
           data_rec_stop            : OUT   std_logic;
 
           -- Common signals
           link_tx_clk              : IN    std_logic;
           link_rx_clk              : IN    std_logic;
 
           -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
 
           -- Fabric side: DAQ Rx
           daq_rv                   : IN    std_logic;
           daq_rsof                 : IN    std_logic;
           daq_reof                 : IN    std_logic;
           daq_rd                   : IN    std_logic_vector(C_DBUS_WIDTH-1 downto 0);
           daq_rstop                : OUT   std_logic;
 
           -- Fabric side: DAQ Tx
           daq_tv                   : OUT   std_logic;
           daq_tsof                 : OUT   std_logic;
           daq_teof                 : OUT   std_logic;
           daq_td                   : OUT   std_logic_vector(C_DBUS_WIDTH-1 downto 0);
           daq_tstop                : IN    std_logic;
 
           -- Interrupter trigger
           DAQ_irq                  : OUT   std_logic;
 
           -- Fabric side: Common signals
           trn_clk                  : IN    std_logic;
           protocol_rst             : IN    std_logic
 
          );
end entity class_daq;
 
 
architecture Behavioral of class_daq is
 
  -- Standard synchronous FIFO
  component sfifo_1024x72
    port (
          wr_en     : IN  std_logic;
          din       : IN  std_logic_VECTOR(72-1 downto 0);
          prog_full : OUT std_logic;
          full      : OUT std_logic;
 
          rd_en     : IN  std_logic;
          dout      : OUT std_logic_VECTOR(72-1 downto 0);
          empty     : OUT std_logic;
          prog_empty: OUT std_logic;
 
          clk       : IN  std_logic;
          rst       : IN  std_logic
          );
  end component;
 
  -- Standard asynchronous FIFO
  component v6_afifo_1024x72
    port (
          wr_clk    : IN  std_logic;
          wr_en     : IN  std_logic;
          din       : IN  std_logic_VECTOR(72-1 downto 0);
          prog_full : OUT std_logic;
          full      : OUT std_logic;
 
          rd_clk    : IN  std_logic;
          rd_en     : IN  std_logic;
          dout      : OUT std_logic_VECTOR(72-1 downto 0);
          empty     : OUT std_logic;
          prog_empty: OUT std_logic;
 
          rst       : IN  std_logic
          );
  end component;
 
  -- Standard synchronous FIFO
  component sfifo_256x18
    port (
          wr_en     : IN  std_logic;
          din       : IN  std_logic_VECTOR(18-1 downto 0);
          prog_full : OUT std_logic;
          full      : OUT std_logic;
 
          rd_en     : IN  std_logic;
          dout      : OUT std_logic_VECTOR(18-1 downto 0);
          empty     : OUT std_logic;
          prog_empty: OUT std_logic;
 
          clk       : IN  std_logic;
          rst       : IN  std_logic
          );
  end component;
 
  -- Interrupter trigger
  signal  DAQ_irq_i             : std_logic;
 
  -- Fabric side: DAQ Tx
  signal  daq_tv_i              : std_logic;
  signal  daq_tsof_i            : std_logic;
  signal  daq_tsof_vector       : std_logic_vector(C_DBUS_WIDTH/16-1 downto 0);
  signal  daq_teof_i            : std_logic;
  signal  daq_teof_vector       : std_logic_vector(C_DBUS_WIDTH/16-1 downto 0);
  signal  daq_td_i              : std_logic_vector(C_DBUS_WIDTH-1 downto 0);
  signal  daq_rstop_i           : std_logic;
 
  signal  daq_up_is_writing     : std_logic;
  signal  daq_up_is_writing_r1  : std_logic;
  signal  Tout_Cnt_daq_up_wr    : std_logic_vector(8-1 downto 0);
 
  -- protocol side: DAQ Send
  signal  data2send_start_i     : std_logic;
  signal  data2send_end_i       : std_logic;
  signal  data2send_i           : std_logic_vector(64-1 downto 0);
  signal  crc_error_send_i      : std_logic;
  signal  data_rec_start_r1     : std_logic;
  signal  data_rec_end_r1       : std_logic;
  signal  data_rec_end_r2       : std_logic;
  signal  data_rec_r1           : std_logic_vector(64-1 downto 0);
  signal  data_rec_stop_i       : std_logic;
  signal  data_rec_stop_r1      : std_logic;
  signal  data_rec_stop_r2      : std_logic;
  signal  data_rec_stop_r3      : std_logic;
  signal  data_rec_stop_r4      : std_logic;
 
  signal  daq_rd_padded         : std_logic_vector(72-1 downto 0);
  signal  daq_rd_r1             : std_logic_vector(C_DBUS_WIDTH-1 downto 0);
 
  -- DAQ packet number counting up
  signal  pkt_number_DAQ_down   : std_logic_vector(8-1 downto 0);
 
  signal  daq_down_buf_rden     : std_logic;
  signal  daq_down_buf_eop      : std_logic;
  signal  daq_down_buf_sop      : std_logic;
  signal  daq_down_buf_eop_r1   : std_logic;
  signal  daq_down_split_rden   : std_logic;
  signal  daq_down_buf_read_gap : std_logic;
  signal  daq_down_buf_stop_read: std_logic;
  signal  daq_down_buf_dout     : std_logic_vector(72-1 downto 0);
  signal  daq_down_buf_empty    : std_logic;
  signal  daq_down_buf_rd_valid : std_logic;
  signal  noPkt_in_daq_down_buf : std_logic;
 
  signal  daq_up_buf_we         : std_logic;
  signal  daq_up_buf_din        : std_logic_vector(72-1 downto 0);
  signal  daq_up_buf_afull      : std_logic;
  signal  daq_up_buf_afull_r1   : std_logic;
  signal  daq_up_buf_re         : std_logic;
  signal  daq_up_buf_rd_valid   : std_logic;
  signal  daq_up_buf_dout       : std_logic_vector(72-1 downto 0);
  signal  daq_up_buf_pempty     : std_logic;
  signal  daq_up_buf_empty      : std_logic;
  signal  daq_up_eop            : std_logic;
  signal  daq_up_eop_r1         : std_logic;
 
 
begin
 
  -- Fabric side: DAQ Tx
  daq_tv             <=  daq_tv_i;
  daq_tsof           <=  daq_tsof_i and daq_tv_i;
  daq_teof           <=  daq_teof_i and daq_tv_i;
  daq_td             <=  daq_td_i  when daq_tv_i='1' else (OTHERS=>'0');
 
  daq_rstop          <=  daq_rstop_i        ;
 
  DAQ_irq            <=  DAQ_irq_i          ;
  DAQ_irq_i          <=  '0';             -- ?
 
  -- protocol side: DAQ Send
  data2send_start    <=  data2send_start_i  ;
  data2send_end      <=  data2send_end_i    ;
  data2send          <=  data2send_i        ;
  crc_error_send     <=  crc_error_send_i   ;
 
 
  data_rec_stop      <=  data_rec_stop_i    ;
  data_rec_stop_i    <=  daq_up_buf_afull_r1   ;
 
 
  daq_up_eop         <=  daq_up_buf_dout(16) ;
 
  -- 
  DAQ_upstream_Read_Gap:
  process (trn_clk)
  begin
    if trn_clk'event and trn_clk = '1' then
      daq_up_eop_r1    <=  daq_up_eop;
    end if;
  end process;
 
  Syn_delay_daq_up_buf_afull:
  process (link_rx_clk)
  begin
    if link_rx_clk'event and link_rx_clk = '1' then
      daq_up_buf_afull_r1    <=  daq_up_buf_afull;
      data_rec_stop_r1       <=  data_rec_stop_i;
      data_rec_stop_r2       <=  data_rec_stop_r1;
      data_rec_stop_r3       <=  data_rec_stop_r2;
      data_rec_stop_r4       <=  data_rec_stop_r3;
    end if;
  end process;
 
  -- DAQ direction: upstream
  --     protocol side
  -- 
  Transfer_DAQ_upstream_protocol:
  process (link_rx_clk, protocol_rst )
  begin
    if protocol_rst = '1' then
      daq_up_is_writing     <= '0';
      Tout_Cnt_daq_up_wr    <= (OTHERS=>'0');
 
    elsif link_rx_clk'event and link_rx_clk = '1' then
 
      if daq_up_is_writing='0' then
        if data_rec_start='1' and data_rec_start_r1='0' then
           daq_up_is_writing  <= '1';
           Tout_Cnt_daq_up_wr <= (OTHERS=>'0');
        else
           daq_up_is_writing  <= '0';
           Tout_Cnt_daq_up_wr <= (OTHERS=>'0');
        end if;
      else
        if data_rec_end_r1='1' and data_rec_end_r2='0' then
           daq_up_is_writing  <= '0';
           Tout_Cnt_daq_up_wr <= (OTHERS=>'0');
        elsif Tout_Cnt_daq_up_wr(6)='1' then
           daq_up_is_writing  <= '0';
           Tout_Cnt_daq_up_wr <= Tout_Cnt_daq_up_wr;
        else
           daq_up_is_writing  <= '1';
           Tout_Cnt_daq_up_wr <= Tout_Cnt_daq_up_wr + '1';
        end if;
      end if;
 
    end if;
  end process;
 
 
--  Transfer_DAQ_upstream_protocol:
--  process (link_rx_clk, protocol_rst )
--  begin
--    if protocol_rst = '1' then
--      daq_up_is_writing     <= '0';
--      daq_up_is_writing_r1  <= '0';
--
--    elsif link_rx_clk'event and link_rx_clk = '1' then
--      if data_rec_start='1' and data_rec_end='1' then
--         daq_up_is_writing     <= '0';
--         daq_up_is_writing_r1  <= not data_rec_stop_i  or not data_rec_stop_r1 
--                               or not data_rec_stop_r2 or not data_rec_stop_r3
--                               or not data_rec_stop_r4
--                               ;
--      elsif data_rec_start='1' then
--         daq_up_is_writing     <= not data_rec_stop_i  or not data_rec_stop_r1 
--                               or not data_rec_stop_r2 or not data_rec_stop_r3
--                               or not data_rec_stop_r4
--                               ;
--         daq_up_is_writing_r1  <= daq_up_is_writing;
--      elsif data_rec_end='1' then
--         daq_up_is_writing     <= '0';
--         daq_up_is_writing_r1  <= daq_up_is_writing;
--      else
--         daq_up_is_writing     <= daq_up_is_writing;
--         daq_up_is_writing_r1  <= daq_up_is_writing;
--      end if;
--
--    end if;
--  end process;
 
  -- direction: upstream
  Transfer_DAQ_upstream_link:
  process (link_rx_clk, protocol_rst )
  begin
    if protocol_rst = '1' then
      data_rec_start_r1    <= '0';
      data_rec_end_r1      <= '0';
      data_rec_end_r2      <= '0';
      data_rec_r1          <= (OTHERS=>'0');
      daq_up_buf_we        <= '0';
      daq_up_buf_din       <= (OTHERS=>'0');
 
    elsif link_rx_clk'event and link_rx_clk = '1' then
      data_rec_start_r1    <= data_rec_start;
      data_rec_end_r1      <= data_rec_end;
      data_rec_end_r2      <= data_rec_end_r1;
      data_rec_r1          <= data_rec;
      daq_up_buf_we        <= daq_up_is_writing;  --(daq_up_is_writing or daq_up_is_writing_r1);
      daq_up_buf_din       <= "000000" & data_rec_start_r1 & data_rec_end_r1 & data_rec_r1;
 
    end if;
  end process;
 
 
  -- ------------------------------------------------------------------------------
  --   DAQ buffer to the host
  -- ------------------------------------------------------------------------------
  daq_buf_upstream:
  v6_afifo_1024x72
  port map (
            wr_clk     => link_rx_clk        ,  -- IN  std_logic;
            wr_en      => daq_up_buf_we      ,  -- IN  std_logic;
            din        => daq_up_buf_din     ,  -- IN  std_logic_VECTOR(17 downto 0);
            prog_full  => daq_up_buf_afull   ,  -- OUT std_logic;
            full       => open               ,  -- OUT std_logic;
 
            rd_clk     => trn_clk            ,  -- IN  std_logic;
            rd_en      => daq_up_buf_re      ,  -- IN  std_logic;
            dout       => daq_up_buf_dout    ,  -- OUT std_logic_VECTOR(17 downto 0);
            prog_empty => daq_up_buf_pempty  ,  -- OUT std_logic;
            empty      => daq_up_buf_empty   ,  -- OUT std_logic;
 
            rst        => protocol_rst          -- IN  std_logic
           );
 
  -- upstream: merging ...
  Transfer_DAQ_upstream_merge:
  process (trn_clk, protocol_rst )
  begin
    if protocol_rst = '1' then
      daq_up_buf_re        <= '0';
      daq_up_buf_rd_valid  <= '0';
      daq_tv_i             <= '0';
      daq_tsof_i           <= '0';
      daq_teof_i           <= '0';
      daq_td_i             <= (OTHERS=>'0');
 
    elsif trn_clk'event and trn_clk = '1' then
      daq_up_buf_re        <= not daq_tstop;
      daq_up_buf_rd_valid  <= daq_up_buf_re and not daq_up_buf_empty;
      daq_tv_i             <= daq_up_buf_rd_valid;
      daq_tsof_i           <= daq_up_buf_dout(65);
      daq_teof_i           <= daq_up_buf_dout(64);
      daq_td_i             <= daq_up_buf_dout(64-1 downto 0);
 
    end if;
  end process;
 
 
  -- ------------------------------------------------------------------------------
  --   DAQ buffer from the host
  -- ------------------------------------------------------------------------------
  daq_buf_downstream:
  v6_afifo_1024x72
  port map (
            wr_clk     => trn_clk            ,  -- IN  std_logic;
            wr_en      => daq_rv             ,  -- IN  std_logic;
            din        => daq_rd_padded      ,  -- IN  std_logic_VECTOR(71 downto 0);
            prog_full  => daq_rstop_i        ,  -- OUT std_logic;
            full       => open               ,  -- OUT std_logic;
 
            rd_clk     => link_tx_clk        ,  -- IN  std_logic;
            rd_en      => daq_down_buf_rden  ,  -- IN  std_logic;
            dout       => daq_down_buf_dout  ,  -- OUT std_logic_VECTOR(71 downto 0);
            prog_empty => open               ,  -- OUT std_logic;
            empty      => daq_down_buf_empty ,  -- OUT std_logic;
 
            rst        => protocol_rst          -- IN  std_logic
           );
 
  daq_down_buf_sop       <= daq_down_buf_dout(65);
  daq_down_buf_eop       <= daq_down_buf_dout(64);
  daq_down_buf_read_gap  <= daq_down_buf_eop and not daq_down_buf_eop_r1;
  daq_down_buf_rden      <= daq_down_split_rden and not daq_down_buf_read_gap;
  daq_rd_padded          <= "000000" & daq_rsof & daq_reof & daq_rd;
 
  -- ------------------------------------------------
  Syn_Delay_daq_down_buf_eop:
  process (link_tx_clk)
  begin
    if link_tx_clk'event and link_tx_clk = '1' then
        daq_down_buf_eop_r1      <= daq_down_buf_eop;
    end if;
  end process;
 
 
  ---------------------------------------------------
  -- Downstream DAQ buffer read and packets number
  --  bit[71] : mask[3]
  --  bit[70] : mask[2]
  --  bit[69] : mask[1]
  --  bit[68] : mask[0]
  --  bit[67] : (reserved)
  --  bit[66] : crc_error
  --  bit[65] : sof
  --  bit[64] : eof
  -- 
  Syn_rden_DAQ_downstream_buf:
  process (link_tx_clk, protocol_rst )
  begin
    if protocol_rst = '1' then
        pkt_number_DAQ_down      <= (OTHERS=>'0');
        daq_down_split_rden      <= '0';
        daq_down_buf_rd_valid    <= '0';
        noPkt_in_daq_down_buf    <= '1';
        daq_down_buf_stop_read   <= '0';
 
    elsif link_tx_clk'event and link_tx_clk = '1' then
 
        if daq_down_buf_read_gap='1' and data2send_stop='1' then
           daq_down_buf_stop_read   <= '1';
        elsif daq_down_buf_stop_read='0' and data2send_stop='1'  then
           daq_down_buf_stop_read   <= '0';
        else
           daq_down_buf_stop_read   <= data2send_stop;
        end if;
 
        daq_down_split_rden      <=  not noPkt_in_daq_down_buf
                                 --  maximal one read every four cycles
                                 and not daq_down_buf_read_gap
                                 and not daq_down_buf_stop_read
                                 ;
 
        daq_down_buf_rd_valid    <= daq_down_buf_rden and not daq_down_buf_empty;
 
        if (daq_rv='1' and daq_rd_padded(64)='1')
           and (daq_down_buf_rd_valid='1' and daq_down_buf_eop='1')
           then
           pkt_number_DAQ_down   <= pkt_number_DAQ_down;
        elsif daq_rv='1' and daq_rd_padded(64)='1' then
           pkt_number_DAQ_down   <= pkt_number_DAQ_down + '1';
        elsif daq_down_buf_rd_valid='1' and daq_down_buf_eop='1' then
           pkt_number_DAQ_down   <= pkt_number_DAQ_down - '1';
        else
           pkt_number_DAQ_down   <= pkt_number_DAQ_down;
        end if;
 
        if pkt_number_DAQ_down=C_ALL_ZEROS(8-1 downto 0) then
           noPkt_in_daq_down_buf <= '1';
        else
           noPkt_in_daq_down_buf <= '0';
        end if;
 
    end if;
  end process;
 
  -- ----------------------------------------------
  -- 
  -- 
  Syn_data2send_link:
  process (link_tx_clk, protocol_rst )
  begin
    if protocol_rst = '1' then
       data2send_start_i  <= '0';
       data2send_end_i    <= '0';
       data2send_i        <= (OTHERS=>'0');
       crc_error_send_i   <=  '0';
    elsif link_tx_clk'event and link_tx_clk = '1' then
       if daq_down_buf_rd_valid='1' then
          data2send_start_i  <= daq_down_buf_sop;
          data2send_end_i    <= daq_down_buf_eop;
          data2send_i        <= daq_down_buf_dout(64-1 downto 0);
       else
          data2send_start_i  <= '0';
          data2send_end_i    <= '0';
          data2send_i        <= (OTHERS=>'0');
       end if;
    end if;
  end process;
 
 
end architecture Behavioral;

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Subversion Repositories pcie_sg_dma

[/] [pcie_sg_dma/] [branches/] [Virtex6/] [ML605_ISE12.3/] [class_daq.vhd] - Blame information for rev 11

Line No.	Rev	Author	Line
1	11	barabba	`----------------------------------------------------------------------------------`
2			`-- Company: ziti`
3			`-- Engineer: wgao`
4			`--`
5			`-- Create Date: 17:01:32 19 Jun 2009`
6			`-- Design Name:`
7			`-- Module Name: class_daq - Behavioral`
8			`-- Project Name:`
9			`-- Target Devices:`
10			`-- Tool versions:`
11			`-- Description:`
12			`--`
13			`-- Dependencies:`
14			`--`
15			`-- Revision:`
16			`-- Revision 0.01 - File Created`
17			`-- Additional Comments:`
18			`--`
19			`----------------------------------------------------------------------------------`
20			`library IEEE;`
21			`use IEEE.STD_LOGIC_1164.ALL;`
22			`use IEEE.STD_LOGIC_ARITH.ALL;`
23			`use IEEE.STD_LOGIC_UNSIGNED.ALL;`
24
25			`library work;`
26			`use work.abb64Package.all;`
27
28			`---- Uncomment the following library declaration if instantiating`
29			`---- any Xilinx primitives in this code.`
30			`--library UNISIM;`
31			`--use UNISIM.VComponents.all;`
32
33			`entity class_daq is`
34			`-- Generic (`
35			`-- C_PRO_DAQ_WIDTH : integer := 16 ;`
36			`-- C_PRO_DLM_WIDTH : integer := 4 ;`
37			`-- C_PRO_CTL_WIDTH : integer := 16`
38			`-- );`
39			`Port (`
40
41			`-- DAQ Tx`
42			`data2send_start : OUT std_logic;`
43			`data2send_end : OUT std_logic;`
44			`data2send : OUT std_logic_vector(64-1 downto 0);`
45			`crc_error_send : OUT std_logic;`
46			`data2send_stop : IN std_logic;`
47
48			`-- DAQ Rx`
49			`data_rec_start : IN std_logic;`
50			`data_rec_end : IN std_logic;`
51			`data_rec : IN std_logic_vector(64-1 downto 0);`
52			`crc_error_rec : IN std_logic;`
53			`data_rec_stop : OUT std_logic;`
54
55			`-- Common signals`
56			`link_tx_clk : IN std_logic;`
57			`link_rx_clk : IN std_logic;`
58
59			`-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --`
60
61			`-- Fabric side: DAQ Rx`
62			`daq_rv : IN std_logic;`
63			`daq_rsof : IN std_logic;`
64			`daq_reof : IN std_logic;`
65			`daq_rd : IN std_logic_vector(C_DBUS_WIDTH-1 downto 0);`
66			`daq_rstop : OUT std_logic;`
67
68			`-- Fabric side: DAQ Tx`
69			`daq_tv : OUT std_logic;`
70			`daq_tsof : OUT std_logic;`
71			`daq_teof : OUT std_logic;`
72			`daq_td : OUT std_logic_vector(C_DBUS_WIDTH-1 downto 0);`
73			`daq_tstop : IN std_logic;`
74
75			`-- Interrupter trigger`
76			`DAQ_irq : OUT std_logic;`
77
78			`-- Fabric side: Common signals`
79			`trn_clk : IN std_logic;`
80			`protocol_rst : IN std_logic`
81
82			`);`
83			`end entity class_daq;`
84
85
86			`architecture Behavioral of class_daq is`
87
88			`-- Standard synchronous FIFO`
89			`component sfifo_1024x72`
90			`port (`
91			`wr_en : IN std_logic;`
92			`din : IN std_logic_VECTOR(72-1 downto 0);`
93			`prog_full : OUT std_logic;`
94			`full : OUT std_logic;`
95
96			`rd_en : IN std_logic;`
97			`dout : OUT std_logic_VECTOR(72-1 downto 0);`
98			`empty : OUT std_logic;`
99			`prog_empty: OUT std_logic;`
100
101			`clk : IN std_logic;`
102			`rst : IN std_logic`
103			`);`
104			`end component;`
105
106			`-- Standard asynchronous FIFO`
107			`component v6_afifo_1024x72`
108			`port (`
109			`wr_clk : IN std_logic;`
110			`wr_en : IN std_logic;`
111			`din : IN std_logic_VECTOR(72-1 downto 0);`
112			`prog_full : OUT std_logic;`
113			`full : OUT std_logic;`
114
115			`rd_clk : IN std_logic;`
116			`rd_en : IN std_logic;`
117			`dout : OUT std_logic_VECTOR(72-1 downto 0);`
118			`empty : OUT std_logic;`
119			`prog_empty: OUT std_logic;`
120
121			`rst : IN std_logic`
122			`);`
123			`end component;`
124
125			`-- Standard synchronous FIFO`
126			`component sfifo_256x18`
127			`port (`
128			`wr_en : IN std_logic;`
129			`din : IN std_logic_VECTOR(18-1 downto 0);`
130			`prog_full : OUT std_logic;`
131			`full : OUT std_logic;`
132
133			`rd_en : IN std_logic;`
134			`dout : OUT std_logic_VECTOR(18-1 downto 0);`
135			`empty : OUT std_logic;`
136			`prog_empty: OUT std_logic;`
137
138			`clk : IN std_logic;`
139			`rst : IN std_logic`
140			`);`
141			`end component;`
142
143			`-- Interrupter trigger`
144			`signal DAQ_irq_i : std_logic;`
145
146			`-- Fabric side: DAQ Tx`
147			`signal daq_tv_i : std_logic;`
148			`signal daq_tsof_i : std_logic;`
149			`signal daq_tsof_vector : std_logic_vector(C_DBUS_WIDTH/16-1 downto 0);`
150			`signal daq_teof_i : std_logic;`
151			`signal daq_teof_vector : std_logic_vector(C_DBUS_WIDTH/16-1 downto 0);`
152			`signal daq_td_i : std_logic_vector(C_DBUS_WIDTH-1 downto 0);`
153			`signal daq_rstop_i : std_logic;`
154
155			`signal daq_up_is_writing : std_logic;`
156			`signal daq_up_is_writing_r1 : std_logic;`
157			`signal Tout_Cnt_daq_up_wr : std_logic_vector(8-1 downto 0);`
158
159			`-- protocol side: DAQ Send`
160			`signal data2send_start_i : std_logic;`
161			`signal data2send_end_i : std_logic;`
162			`signal data2send_i : std_logic_vector(64-1 downto 0);`
163			`signal crc_error_send_i : std_logic;`
164			`signal data_rec_start_r1 : std_logic;`
165			`signal data_rec_end_r1 : std_logic;`
166			`signal data_rec_end_r2 : std_logic;`
167			`signal data_rec_r1 : std_logic_vector(64-1 downto 0);`
168			`signal data_rec_stop_i : std_logic;`
169			`signal data_rec_stop_r1 : std_logic;`
170			`signal data_rec_stop_r2 : std_logic;`
171			`signal data_rec_stop_r3 : std_logic;`
172			`signal data_rec_stop_r4 : std_logic;`
173
174			`signal daq_rd_padded : std_logic_vector(72-1 downto 0);`
175			`signal daq_rd_r1 : std_logic_vector(C_DBUS_WIDTH-1 downto 0);`
176
177			`-- DAQ packet number counting up`
178			`signal pkt_number_DAQ_down : std_logic_vector(8-1 downto 0);`
179
180			`signal daq_down_buf_rden : std_logic;`
181			`signal daq_down_buf_eop : std_logic;`
182			`signal daq_down_buf_sop : std_logic;`
183			`signal daq_down_buf_eop_r1 : std_logic;`
184			`signal daq_down_split_rden : std_logic;`
185			`signal daq_down_buf_read_gap : std_logic;`
186			`signal daq_down_buf_stop_read: std_logic;`
187			`signal daq_down_buf_dout : std_logic_vector(72-1 downto 0);`
188			`signal daq_down_buf_empty : std_logic;`
189			`signal daq_down_buf_rd_valid : std_logic;`
190			`signal noPkt_in_daq_down_buf : std_logic;`
191
192			`signal daq_up_buf_we : std_logic;`
193			`signal daq_up_buf_din : std_logic_vector(72-1 downto 0);`
194			`signal daq_up_buf_afull : std_logic;`
195			`signal daq_up_buf_afull_r1 : std_logic;`
196			`signal daq_up_buf_re : std_logic;`
197			`signal daq_up_buf_rd_valid : std_logic;`
198			`signal daq_up_buf_dout : std_logic_vector(72-1 downto 0);`
199			`signal daq_up_buf_pempty : std_logic;`
200			`signal daq_up_buf_empty : std_logic;`
201			`signal daq_up_eop : std_logic;`
202			`signal daq_up_eop_r1 : std_logic;`
203
204
205			`begin`
206
207			`-- Fabric side: DAQ Tx`
208			`daq_tv <= daq_tv_i;`
209			`daq_tsof <= daq_tsof_i and daq_tv_i;`
210			`daq_teof <= daq_teof_i and daq_tv_i;`
211			`daq_td <= daq_td_i when daq_tv_i='1' else (OTHERS=>'0');`
212
213			`daq_rstop <= daq_rstop_i ;`
214
215			`DAQ_irq <= DAQ_irq_i ;`
216			`DAQ_irq_i <= '0'; -- ?`
217
218			`-- protocol side: DAQ Send`
219			`data2send_start <= data2send_start_i ;`
220			`data2send_end <= data2send_end_i ;`
221			`data2send <= data2send_i ;`
222			`crc_error_send <= crc_error_send_i ;`
223
224
225			`data_rec_stop <= data_rec_stop_i ;`
226			`data_rec_stop_i <= daq_up_buf_afull_r1 ;`
227
228
229			`daq_up_eop <= daq_up_buf_dout(16) ;`
230
231			`--`
232			`DAQ_upstream_Read_Gap:`
233			`process (trn_clk)`
234			`begin`
235			`if trn_clk'event and trn_clk = '1' then`
236			`daq_up_eop_r1 <= daq_up_eop;`
237			`end if;`
238			`end process;`
239
240			`Syn_delay_daq_up_buf_afull:`
241			`process (link_rx_clk)`
242			`begin`
243			`if link_rx_clk'event and link_rx_clk = '1' then`
244			`daq_up_buf_afull_r1 <= daq_up_buf_afull;`
245			`data_rec_stop_r1 <= data_rec_stop_i;`
246			`data_rec_stop_r2 <= data_rec_stop_r1;`
247			`data_rec_stop_r3 <= data_rec_stop_r2;`
248			`data_rec_stop_r4 <= data_rec_stop_r3;`
249			`end if;`
250			`end process;`
251
252			`-- DAQ direction: upstream`
253			`-- protocol side`
254			`--`
255			`Transfer_DAQ_upstream_protocol:`
256			`process (link_rx_clk, protocol_rst )`
257			`begin`
258			`if protocol_rst = '1' then`
259			`daq_up_is_writing <= '0';`
260			`Tout_Cnt_daq_up_wr <= (OTHERS=>'0');`
261
262			`elsif link_rx_clk'event and link_rx_clk = '1' then`
263
264			`if daq_up_is_writing='0' then`
265			`if data_rec_start='1' and data_rec_start_r1='0' then`
266			`daq_up_is_writing <= '1';`
267			`Tout_Cnt_daq_up_wr <= (OTHERS=>'0');`
268			`else`
269			`daq_up_is_writing <= '0';`
270			`Tout_Cnt_daq_up_wr <= (OTHERS=>'0');`
271			`end if;`
272			`else`
273			`if data_rec_end_r1='1' and data_rec_end_r2='0' then`
274			`daq_up_is_writing <= '0';`
275			`Tout_Cnt_daq_up_wr <= (OTHERS=>'0');`
276			`elsif Tout_Cnt_daq_up_wr(6)='1' then`
277			`daq_up_is_writing <= '0';`
278			`Tout_Cnt_daq_up_wr <= Tout_Cnt_daq_up_wr;`
279			`else`
280			`daq_up_is_writing <= '1';`
281			`Tout_Cnt_daq_up_wr <= Tout_Cnt_daq_up_wr + '1';`
282			`end if;`
283			`end if;`
284
285			`end if;`
286			`end process;`
287
288
289			`-- Transfer_DAQ_upstream_protocol:`
290			`-- process (link_rx_clk, protocol_rst )`
291			`-- begin`
292			`-- if protocol_rst = '1' then`
293			`-- daq_up_is_writing <= '0';`
294			`-- daq_up_is_writing_r1 <= '0';`
295			`--`
296			`-- elsif link_rx_clk'event and link_rx_clk = '1' then`
297			`-- if data_rec_start='1' and data_rec_end='1' then`
298			`-- daq_up_is_writing <= '0';`
299			`-- daq_up_is_writing_r1 <= not data_rec_stop_i or not data_rec_stop_r1`
300			`-- or not data_rec_stop_r2 or not data_rec_stop_r3`
301			`-- or not data_rec_stop_r4`
302			`-- ;`
303			`-- elsif data_rec_start='1' then`
304			`-- daq_up_is_writing <= not data_rec_stop_i or not data_rec_stop_r1`
305			`-- or not data_rec_stop_r2 or not data_rec_stop_r3`
306			`-- or not data_rec_stop_r4`
307			`-- ;`
308			`-- daq_up_is_writing_r1 <= daq_up_is_writing;`
309			`-- elsif data_rec_end='1' then`
310			`-- daq_up_is_writing <= '0';`
311			`-- daq_up_is_writing_r1 <= daq_up_is_writing;`
312			`-- else`
313			`-- daq_up_is_writing <= daq_up_is_writing;`
314			`-- daq_up_is_writing_r1 <= daq_up_is_writing;`
315			`-- end if;`
316			`--`
317			`-- end if;`
318			`-- end process;`
319
320			`-- direction: upstream`
321			`Transfer_DAQ_upstream_link:`
322			`process (link_rx_clk, protocol_rst )`
323			`begin`
324			`if protocol_rst = '1' then`
325			`data_rec_start_r1 <= '0';`
326			`data_rec_end_r1 <= '0';`
327			`data_rec_end_r2 <= '0';`
328			`data_rec_r1 <= (OTHERS=>'0');`
329			`daq_up_buf_we <= '0';`
330			`daq_up_buf_din <= (OTHERS=>'0');`
331
332			`elsif link_rx_clk'event and link_rx_clk = '1' then`
333			`data_rec_start_r1 <= data_rec_start;`
334			`data_rec_end_r1 <= data_rec_end;`
335			`data_rec_end_r2 <= data_rec_end_r1;`
336			`data_rec_r1 <= data_rec;`
337			`daq_up_buf_we <= daq_up_is_writing; --(daq_up_is_writing or daq_up_is_writing_r1);`
338			`daq_up_buf_din <= "000000" & data_rec_start_r1 & data_rec_end_r1 & data_rec_r1;`
339
340			`end if;`
341			`end process;`
342
343
344			`-- ------------------------------------------------------------------------------`
345			`-- DAQ buffer to the host`
346			`-- ------------------------------------------------------------------------------`
347			`daq_buf_upstream:`
348			`v6_afifo_1024x72`
349			`port map (`
350			`wr_clk => link_rx_clk , -- IN std_logic;`
351			`wr_en => daq_up_buf_we , -- IN std_logic;`
352			`din => daq_up_buf_din , -- IN std_logic_VECTOR(17 downto 0);`
353			`prog_full => daq_up_buf_afull , -- OUT std_logic;`
354			`full => open , -- OUT std_logic;`
355
356			`rd_clk => trn_clk , -- IN std_logic;`
357			`rd_en => daq_up_buf_re , -- IN std_logic;`
358			`dout => daq_up_buf_dout , -- OUT std_logic_VECTOR(17 downto 0);`
359			`prog_empty => daq_up_buf_pempty , -- OUT std_logic;`
360			`empty => daq_up_buf_empty , -- OUT std_logic;`
361
362			`rst => protocol_rst -- IN std_logic`
363			`);`
364
365			`-- upstream: merging ...`
366			`Transfer_DAQ_upstream_merge:`
367			`process (trn_clk, protocol_rst )`
368			`begin`
369			`if protocol_rst = '1' then`
370			`daq_up_buf_re <= '0';`
371			`daq_up_buf_rd_valid <= '0';`
372			`daq_tv_i <= '0';`
373			`daq_tsof_i <= '0';`
374			`daq_teof_i <= '0';`
375			`daq_td_i <= (OTHERS=>'0');`
376
377			`elsif trn_clk'event and trn_clk = '1' then`
378			`daq_up_buf_re <= not daq_tstop;`
379			`daq_up_buf_rd_valid <= daq_up_buf_re and not daq_up_buf_empty;`
380			`daq_tv_i <= daq_up_buf_rd_valid;`
381			`daq_tsof_i <= daq_up_buf_dout(65);`
382			`daq_teof_i <= daq_up_buf_dout(64);`
383			`daq_td_i <= daq_up_buf_dout(64-1 downto 0);`
384
385			`end if;`
386			`end process;`
387
388
389			`-- ------------------------------------------------------------------------------`
390			`-- DAQ buffer from the host`
391			`-- ------------------------------------------------------------------------------`
392			`daq_buf_downstream:`
393			`v6_afifo_1024x72`
394			`port map (`
395			`wr_clk => trn_clk , -- IN std_logic;`
396			`wr_en => daq_rv , -- IN std_logic;`
397			`din => daq_rd_padded , -- IN std_logic_VECTOR(71 downto 0);`
398			`prog_full => daq_rstop_i , -- OUT std_logic;`
399			`full => open , -- OUT std_logic;`
400
401			`rd_clk => link_tx_clk , -- IN std_logic;`
402			`rd_en => daq_down_buf_rden , -- IN std_logic;`
403			`dout => daq_down_buf_dout , -- OUT std_logic_VECTOR(71 downto 0);`
404			`prog_empty => open , -- OUT std_logic;`
405			`empty => daq_down_buf_empty , -- OUT std_logic;`
406
407			`rst => protocol_rst -- IN std_logic`
408			`);`
409
410			`daq_down_buf_sop <= daq_down_buf_dout(65);`
411			`daq_down_buf_eop <= daq_down_buf_dout(64);`
412			`daq_down_buf_read_gap <= daq_down_buf_eop and not daq_down_buf_eop_r1;`
413			`daq_down_buf_rden <= daq_down_split_rden and not daq_down_buf_read_gap;`
414			`daq_rd_padded <= "000000" & daq_rsof & daq_reof & daq_rd;`
415
416			`-- ------------------------------------------------`
417			`Syn_Delay_daq_down_buf_eop:`
418			`process (link_tx_clk)`
419			`begin`
420			`if link_tx_clk'event and link_tx_clk = '1' then`
421			`daq_down_buf_eop_r1 <= daq_down_buf_eop;`
422			`end if;`
423			`end process;`
424
425
426			`---------------------------------------------------`
427			`-- Downstream DAQ buffer read and packets number`
428			`-- bit[71] : mask[3]`
429			`-- bit[70] : mask[2]`
430			`-- bit[69] : mask[1]`
431			`-- bit[68] : mask[0]`
432			`-- bit[67] : (reserved)`
433			`-- bit[66] : crc_error`
434			`-- bit[65] : sof`
435			`-- bit[64] : eof`
436			`--`
437			`Syn_rden_DAQ_downstream_buf:`
438			`process (link_tx_clk, protocol_rst )`
439			`begin`
440			`if protocol_rst = '1' then`
441			`pkt_number_DAQ_down <= (OTHERS=>'0');`
442			`daq_down_split_rden <= '0';`
443			`daq_down_buf_rd_valid <= '0';`
444			`noPkt_in_daq_down_buf <= '1';`
445			`daq_down_buf_stop_read <= '0';`
446
447			`elsif link_tx_clk'event and link_tx_clk = '1' then`
448
449			`if daq_down_buf_read_gap='1' and data2send_stop='1' then`
450			`daq_down_buf_stop_read <= '1';`
451			`elsif daq_down_buf_stop_read='0' and data2send_stop='1' then`
452			`daq_down_buf_stop_read <= '0';`
453			`else`
454			`daq_down_buf_stop_read <= data2send_stop;`
455			`end if;`
456
457			`daq_down_split_rden <= not noPkt_in_daq_down_buf`
458			`-- maximal one read every four cycles`
459			`and not daq_down_buf_read_gap`
460			`and not daq_down_buf_stop_read`
461			`;`
462
463			`daq_down_buf_rd_valid <= daq_down_buf_rden and not daq_down_buf_empty;`
464
465			`if (daq_rv='1' and daq_rd_padded(64)='1')`
466			`and (daq_down_buf_rd_valid='1' and daq_down_buf_eop='1')`
467			`then`
468			`pkt_number_DAQ_down <= pkt_number_DAQ_down;`
469			`elsif daq_rv='1' and daq_rd_padded(64)='1' then`
470			`pkt_number_DAQ_down <= pkt_number_DAQ_down + '1';`
471			`elsif daq_down_buf_rd_valid='1' and daq_down_buf_eop='1' then`
472			`pkt_number_DAQ_down <= pkt_number_DAQ_down - '1';`
473			`else`
474			`pkt_number_DAQ_down <= pkt_number_DAQ_down;`
475			`end if;`
476
477			`if pkt_number_DAQ_down=C_ALL_ZEROS(8-1 downto 0) then`
478			`noPkt_in_daq_down_buf <= '1';`
479			`else`
480			`noPkt_in_daq_down_buf <= '0';`
481			`end if;`
482
483			`end if;`
484			`end process;`
485
486			`-- ----------------------------------------------`
487			`--`
488			`--`
489			`Syn_data2send_link:`
490			`process (link_tx_clk, protocol_rst )`
491			`begin`
492			`if protocol_rst = '1' then`
493			`data2send_start_i <= '0';`
494			`data2send_end_i <= '0';`
495			`data2send_i <= (OTHERS=>'0');`
496			`crc_error_send_i <= '0';`
497			`elsif link_tx_clk'event and link_tx_clk = '1' then`
498			`if daq_down_buf_rd_valid='1' then`
499			`data2send_start_i <= daq_down_buf_sop;`
500			`data2send_end_i <= daq_down_buf_eop;`
501			`data2send_i <= daq_down_buf_dout(64-1 downto 0);`
502			`else`
503			`data2send_start_i <= '0';`
504			`data2send_end_i <= '0';`
505			`data2send_i <= (OTHERS=>'0');`
506			`end if;`
507			`end if;`
508			`end process;`
509
510
511			`end architecture Behavioral;`