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Subversion Repositories pcie_sg_dma

[/] [pcie_sg_dma/] [branches/] [Virtex6/] [ML605_ISE12.3/] [ipcore_dir_ISE12.1/] [coregen.cgc] - Blame information for rev 11

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   xilinx.com
   project
   coregen
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Subversion Repositories pcie_sg_dma

[/] [pcie_sg_dma/] [branches/] [Virtex6/] [ML605_ISE12.3/] [ipcore_dir_ISE12.1/] [coregen.cgc] - Blame information for rev 11

Line No.	Rev	Author	Line
1	11	barabba
2
3			`xilinx.com`
4			`project`
5			`coregen`
6			`1.0`
7
8
9			`v6_afifo_1024x72`
10
11
12
13
14			`false`
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22			`false`
23			`false`
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25			`false`
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27			`1`
28			`Active_High`
29			`10`
30			`false`
31			`10`
32			`1024`
33			`0`
34			`true`
35			`true`
36			`Active_High`
37			`Active_High`
38			`false`
39			`false`
40			`false`
41			`Single_Programmable_Full_Threshold_Constant`
42			`false`
43			`10`
44			`Asynchronous_Reset`
45			`Standard_FIFO`
46			`768`
47			`true`
48			`false`
49			`false`
50			`1`
51			`Active_High`
52			`false`
53			`3`
54			`72`
55			`1`
56			`false`
57
58
59
60
61			`coregen`
62			`./`
63			`./tmp/`
64			`./tmp/_cg`
65
66
67			`xc6vlx240t`
68			`virtex6`
69			`ff1156`
70			`-1`
71
72
73			`BusFormatAngleBracketNotRipped`
74			`VHDL`
75			`true`
76			`Foundation_ISE`
77			`false`
78			`false`
79			`false`
80			`Ngc`
81			`false`
82
83
84			`Behavioral`
85			`VHDL_and_Verilog`
86			`false`
87
88
89
90
91
92			`v6_afifo_256x36`
93
94
95
96
97			`false`
98			`false`
99			`319`
100			`9`
101			`36`
102			`512`
103			`false`
104			`Single_Programmable_Empty_Threshold_Constant`
105			`false`
106			`false`
107			`Independent_Clocks_Block_RAM`
108			`false`
109			`false`
110			`1`
111			`Active_High`
112			`9`
113			`false`
114			`9`
115			`512`
116			`0`
117			`true`
118			`true`
119			`Active_High`
120			`Active_High`
121			`false`
122			`false`
123			`false`
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125			`false`
126			`9`
127			`Asynchronous_Reset`
128			`Standard_FIFO`
129			`320`
130			`true`
131			`false`
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133			`1`
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135			`false`
136			`8`
137			`36`
138			`1`
139			`false`
140
141
142
143
144			`coregen`
145			`./`
146			`./tmp/`
147			`./tmp/_cg`
148
149
150			`xc6vlx240t`
151			`virtex6`
152			`ff1156`
153			`-1`
154
155
156			`BusFormatAngleBracketNotRipped`
157			`VHDL`
158			`true`
159			`Foundation_ISE`
160			`false`
161			`false`
162			`false`
163			`Ngc`
164			`false`
165
166
167			`Behavioral`
168			`VHDL_and_Verilog`
169			`false`
170
171
172
173
174
175			`v6_afifo_256x36c_fwft`
176
177
178
179
180			`false`
181			`false`
182			`319`
183			`9`
184			`36`
185			`512`
186			`false`
187			`Single_Programmable_Empty_Threshold_Constant`
188			`false`
189			`false`
190			`Independent_Clocks_Block_RAM`
191			`false`
192			`false`
193			`1`
194			`Active_High`
195			`9`
196			`false`
197			`9`
198			`512`
199			`0`
200			`true`
201			`true`
202			`Active_High`
203			`Active_High`
204			`false`
205			`true`
206			`false`
207			`Single_Programmable_Full_Threshold_Constant`
208			`false`
209			`9`
210			`Asynchronous_Reset`
211			`First_Word_Fall_Through`
212			`320`
213			`true`
214			`false`
215			`false`
216			`1`
217			`Active_High`
218			`false`
219			`8`
220			`36`
221			`1`
222			`false`
223
224
225
226
227			`coregen`
228			`./`
229			`./tmp/`
230			`./tmp/_cg`
231
232
233			`xc6vlx240t`
234			`virtex6`
235			`ff1156`
236			`-1`
237
238
239			`BusFormatAngleBracketNotRipped`
240			`VHDL`
241			`true`
242			`Foundation_ISE`
243			`false`
244			`false`
245			`false`
246			`Ngc`
247			`false`
248
249
250			`Behavioral`
251			`VHDL_and_Verilog`
252			`false`
253
254
255
256
257
258			`v6_afifo_8x8`
259
260
261
262
263			`false`
264			`false`
265			`12`
266			`3`
267			`8`
268			`16`
269			`false`
270			`No_Programmable_Empty_Threshold`
271			`false`
272			`false`
273			`Independent_Clocks_Distributed_RAM`
274			`false`
275			`false`
276			`1`
277			`Active_High`
278			`4`
279			`false`
280			`4`
281			`16`
282			`0`
283			`true`
284			`true`
285			`Active_High`
286			`Active_High`
287			`false`
288			`false`
289			`false`
290			`No_Programmable_Full_Threshold`
291			`false`
292			`4`
293			`Asynchronous_Reset`
294			`Standard_FIFO`
295			`13`
296			`true`
297			`false`
298			`false`
299			`1`
300			`Active_High`
301			`false`
302			`2`
303			`8`
304			`1`
305			`false`
306
307
308
309
310			`coregen`
311			`./`
312			`./tmp/`
313			`./tmp/_cg`
314
315
316			`xc6vlx240t`
317			`virtex6`
318			`ff1156`
319			`-1`
320
321
322			`BusFormatAngleBracketNotRipped`
323			`VHDL`
324			`true`
325			`Foundation_ISE`
326			`false`
327			`false`
328			`false`
329			`Ngc`
330			`false`
331
332
333			`Behavioral`
334			`VHDL_and_Verilog`
335			`false`
336
337
338
339
340
341			`v6_bram4096x64`
342
343
344
345
346			`50`
347			`true`
348			`4096`
349			`false`
350			`WRITE_FIRST`
351			`WRITE_FIRST`
352			`64`
353			`64`
354			`false`
355			`false`
356			`8kx2`
357			`True_Dual_Port_RAM`
358			`false`
359			`8`
360			`false`
361			`0`
362			`false`
363			`0`
364			`false`
365			`false`
366			`true`
367			`Always_Enabled`
368			`Always_Enabled`
369			`100`
370			`false`
371			`false`
372			`false`
373			`false`
374			`50`
375			`Minimum_Area`
376			`false`
377			`100`
378			`false`
379			`100`
380			`64`
381			`64`
382			`SYNC`
383			`false`
384			`100`
385			`0`
386			`0`
387			`false`
388			`false`
389			`no_coe_file_loaded`
390			`Single_Bit_Error_Injection`
391			`ALL`
392			`CE`
393			`CE`
394
395
396
397
398			`coregen`
399			`./`
400			`./tmp/`
401			`./tmp/_cg`
402
403
404			`xc6vlx240t`
405			`virtex6`
406			`ff1156`
407			`-1`
408
409
410			`BusFormatAngleBracketNotRipped`
411			`VHDL`
412			`true`
413			`Foundation_ISE`
414			`false`
415			`false`
416			`false`
417			`Ngc`
418			`false`
419
420
421			`Behavioral`
422			`VHDL_and_Verilog`
423			`false`
424
425
426
427
428
429			`v6_bram4096x64_fast`
430
431
432
433
434			`50`
435			`false`
436			`4096`
437			`false`
438			`WRITE_FIRST`
439			`WRITE_FIRST`
440			`64`
441			`64`
442			`false`
443			`false`
444			`8kx2`
445			`True_Dual_Port_RAM`
446			`false`
447			`8`
448			`false`
449			`0`
450			`false`
451			`0`
452			`false`
453			`false`
454			`true`
455			`Always_Enabled`
456			`Always_Enabled`
457			`100`
458			`false`
459			`false`
460			`false`
461			`false`
462			`50`
463			`Minimum_Area`
464			`false`
465			`100`
466			`false`
467			`100`
468			`64`
469			`64`
470			`SYNC`
471			`false`
472			`100`
473			`0`
474			`0`
475			`false`
476			`false`
477			`no_coe_file_loaded`
478			`Single_Bit_Error_Injection`
479			`ALL`
480			`CE`
481			`CE`
482
483
484
485
486			`coregen`
487			`./`
488			`./tmp/`
489			`./tmp/_cg`
490
491
492			`xc6vlx240t`
493			`virtex6`
494			`ff1156`
495			`-1`
496
497
498			`BusFormatAngleBracketNotRipped`
499			`VHDL`
500			`true`
501			`Foundation_ISE`
502			`false`
503			`false`
504			`false`
505			`Ngc`
506			`false`
507
508
509			`Behavioral`
510			`VHDL_and_Verilog`
511			`false`
512
513
514
515
516
517			`v6_eb_fifo_counted`
518
519
520
521
522			`false`
523			`false`
524			`12286`
525			`4097`
526			`72`
527			`16384`
528			`false`
529			`Single_Programmable_Empty_Threshold_Constant`
530			`false`
531			`false`
532			`Independent_Clocks_Block_RAM`
533			`false`
534			`false`
535			`1`
536			`Active_High`
537			`14`
538			`false`
539			`14`
540			`16384`
541			`0`
542			`true`
543			`true`
544			`Active_High`
545			`Active_High`
546			`false`
547			`true`
548			`false`
549			`Single_Programmable_Full_Threshold_Constant`
550			`false`
551			`14`
552			`Asynchronous_Reset`
553			`Standard_FIFO`
554			`12287`
555			`true`
556			`false`
557			`false`
558			`1`
559			`Active_High`
560			`false`
561			`4096`
562			`72`
563			`1`
564			`false`
565
566
567
568
569			`coregen`
570			`./`
571			`./tmp/`
572			`./tmp/_cg`
573
574
575			`xc6vlx240t`
576			`virtex6`
577			`ff1156`
578			`-1`
579
580
581			`BusFormatAngleBracketNotRipped`
582			`VHDL`
583			`true`
584			`Foundation_ISE`
585			`false`
586			`false`
587			`false`
588			`Ngc`
589			`false`
590
591
592			`Behavioral`
593			`VHDL_and_Verilog`
594			`false`
595
596
597
598
599
600			`v6_eb_fifo_counted_new`
601
602
603
604
605			`false`
606			`true`
607			`28670`
608			`4097`
609			`72`
610			`32768`
611			`true`
612			`Single_Programmable_Empty_Threshold_Constant`
613			`false`
614			`false`
615			`Independent_Clocks_Block_RAM`
616			`false`
617			`false`
618			`1`
619			`Active_High`
620			`15`
621			`false`
622			`15`
623			`32768`
624			`0`
625			`true`
626			`true`
627			`Active_High`
628			`Active_High`
629			`false`
630			`true`
631			`false`
632			`Single_Programmable_Full_Threshold_Constant`
633			`false`
634			`15`
635			`Asynchronous_Reset`
636			`Standard_FIFO`
637			`28671`
638			`true`
639			`false`
640			`false`
641			`1`
642			`Active_High`
643			`false`
644			`4096`
645			`72`
646			`1`
647			`false`
648
649
650
651
652			`coregen`
653			`./`
654			`./tmp/`
655			`./tmp/_cg`
656
657
658			`xc6vlx240t`
659			`virtex6`
660			`ff1156`
661			`-1`
662
663
664			`BusFormatAngleBracketNotRipped`
665			`VHDL`
666			`true`
667			`Foundation_ISE`
668			`false`
669			`false`
670			`false`
671			`Ngc`
672			`false`
673
674
675			`Behavioral`
676			`VHDL_and_Verilog`
677			`false`
678
679
680
681
682
683			`v6_mBuf_128x72`
684
685
686
687
688			`false`
689			`false`
690			`127`
691			`3`
692			`72`
693			`512`
694			`false`
695			`No_Programmable_Empty_Threshold`
696			`false`
697			`false`
698			`Common_Clock_Builtin_FIFO`
699			`false`
700			`false`
701			`0`
702			`Active_High`
703			`9`
704			`false`
705			`9`
706			`512`
707			`0`
708			`true`
709			`true`
710			`Active_High`
711			`Active_High`
712			`false`
713			`false`
714			`false`
715			`Single_Programmable_Full_Threshold_Constant`
716			`false`
717			`9`
718			`Asynchronous_Reset`
719			`Standard_FIFO`
720			`128`
721			`false`
722			`false`
723			`false`
724			`1`
725			`Active_High`
726			`false`
727			`2`
728			`72`
729			`1`
730			`false`
731
732
733
734
735			`coregen`
736			`./`
737			`./tmp/`
738			`./tmp/_cg`
739
740
741			`xc6vlx240t`
742			`virtex6`
743			`ff1156`
744			`-1`
745
746
747			`BusFormatAngleBracketNotRipped`
748			`VHDL`
749			`true`
750			`Foundation_ISE`
751			`false`
752			`false`
753			`false`
754			`Ngc`
755			`false`
756
757
758			`Behavioral`
759			`VHDL_and_Verilog`
760			`false`
761
762
763
764
765
766			`v6_pcie_v1_6`
767
768
769
770
771			`High`
772			`false`
773			`false`
774			`false`
775			`Kilobytes`
776			`Add`
777			`false`
778			`Memory`
779			`Simple_communication_controllers`
780			`1`
781			`0`
782			`0`
783			`true`
784			`false`
785			`00`
786			`Disabled`
787			`0`
788			`false`
789			`false`
790			`2`
791			`false`
792			`false`
793			`false`
794			`false`
795			`false`
796			`false`
797			`false`
798			`64`
799			`false`
800			`6014`
801			`10EE`
802			`No_limit`
803			`1`
804			`false`
805			`X0Y0`
806			`PCI_Express_Endpoint_device`
807			`false`
808			`0026`
809			`true`
810			`N/A`
811			`true`
812			`100_MHz`
813			`05`
814			`0`
815			`ML_605`
816			`3F`
817			`2`
818			`false`
819			`0`
820			`true`
821			`false`
822			`0`
823			`4'h1`
824			`false`
825			`true`
826			`0`
827			`false`
828			`1`
829			`512_bytes`
830			`true`
831			`0`
832			`125_default`
833			`false`
834			`N/A`
835			`0`
836			`false`
837			`false`
838			`Absolute`
839			`false`
840			`true`
841			`0`
842			`Kilobytes`
843			`false`
844			`false`
845			`false`
846			`false`
847			`false`
848			`false`
849			`false`
850			`Kilobytes`
851			`0`
852			`0`
853			`false`
854			`false`
855			`false`
856			`Kilobytes`
857			`false`
858			`true`
859			`false`
860			`4`
861			`false`
862			`false`
863			`Range_B`
864			`true`
865			`Kilobytes`
866			`ABB3`
867			`N/A`
868			`true`
869			`false`
870			`X4`
871			`Megabytes`
872			`0`
873			`0`
874			`false`
875			`Memory`
876			`0`
877			`true`
878			`false`
879			`BAR_0`
880			`Kilobytes`
881			`false`
882			`false`
883			`false`
884			`false`
885			`0`
886			`2.5_GT/s`
887			`false`
888			`false`
889			`true`
890			`false`
891			`None`
892			`None`
893			`3FF`
894			`false`
895			`No_function_number_bits_used`
896			`00`
897			`2`
898			`false`
899			`false`
900			`0`
901			`false`
902			`0`
903			`INTA`
904			`64_byte`
905			`0`
906			`false`
907			`false`
908			`Memory`
909			`06`
910			`false`
911			`false`
912			`1_vector`
913			`BAR_0`
914			`0`
915			`0084`
916			`0`
917			`false`
918			`0000`
919			`false`
920			`00`
921			`00000000`
922			`true`
923			`true`
924			`No_limit`
925			`Disabled`
926			`false`
927			`Generic_XT_compatible_serial_controller`
928			`0`
929			`2`
930			`false`
931
932
933
934
935			`coregen`
936			`./`
937			`./tmp/`
938			`./tmp/_cg`
939
940
941			`xc6vlx240t`
942			`virtex6`
943			`ff1156`
944			`-1`
945
946
947			`BusFormatAngleBracketNotRipped`
948			`VHDL`
949			`true`
950			`Other`
951			`false`
952			`false`
953			`false`
954			`Ngc`
955			`false`
956
957
958			`Behavioral`
959			`VHDL`
960			`false`
961
962
963
964
965
966			`v6_pkt_counter_1024`
967
968
969
970
971			`false`
972			`false`
973			`1015`
974			`3`
975			`1`
976			`1024`
977			`false`
978			`Single_Programmable_Empty_Threshold_Constant`
979			`false`
980			`false`
981			`Independent_Clocks_Distributed_RAM`
982			`false`
983			`false`
984			`1`
985			`Active_High`
986			`10`
987			`false`
988			`10`
989			`1024`
990			`0`
991			`true`
992			`true`
993			`Active_High`
994			`Active_High`
995			`false`
996			`false`
997			`false`
998			`Single_Programmable_Full_Threshold_Constant`
999			`false`
1000			`10`
1001			`Asynchronous_Reset`
1002			`Standard_FIFO`
1003			`1016`
1004			`true`
1005			`false`
1006			`false`
1007			`1`
1008			`Active_High`
1009			`false`
1010			`2`
1011			`1`
1012			`1`
1013			`false`
1014
1015
1016
1017
1018			`coregen`
1019			`./`
1020			`./tmp/`
1021			`./tmp/_cg`
1022
1023
1024			`xc6vlx240t`
1025			`virtex6`
1026			`ff1156`
1027			`-1`
1028
1029
1030			`BusFormatAngleBracketNotRipped`
1031			`VHDL`
1032			`true`
1033			`Foundation_ISE`
1034			`false`
1035			`false`
1036			`false`
1037			`Ngc`
1038			`false`
1039
1040
1041			`Behavioral`
1042			`VHDL_and_Verilog`
1043			`false`
1044
1045
1046
1047
1048
1049			`v6_prime_fifo_plain`
1050
1051
1052
1053
1054			`false`
1055			`false`
1056			`495`
1057			`6`
1058			`72`
1059			`512`
1060			`false`
1061			`No_Programmable_Empty_Threshold`
1062			`false`
1063			`false`
1064			`Independent_Clocks_Builtin_FIFO`
1065			`false`
1066			`false`
1067			`0`
1068			`Active_High`
1069			`9`
1070			`false`
1071			`9`
1072			`512`
1073			`0`
1074			`true`
1075			`true`
1076			`Active_High`
1077			`Active_High`
1078			`false`
1079			`false`
1080			`false`
1081			`Single_Programmable_Full_Threshold_Constant`
1082			`false`
1083			`9`
1084			`Asynchronous_Reset`
1085			`Standard_FIFO`
1086			`496`
1087			`false`
1088			`false`
1089			`false`
1090			`125`
1091			`Active_High`
1092			`false`
1093			`5`
1094			`72`
1095			`125`
1096			`false`
1097
1098
1099
1100
1101			`coregen`
1102			`./`
1103			`./tmp/`
1104			`./tmp/_cg`
1105
1106
1107			`xc6vlx240t`
1108			`virtex6`
1109			`ff1156`
1110			`-1`
1111
1112
1113			`BusFormatAngleBracketNotRipped`
1114			`VHDL`
1115			`true`
1116			`Foundation_ISE`
1117			`false`
1118			`false`
1119			`false`
1120			`Ngc`
1121			`false`
1122
1123
1124			`Behavioral`
1125			`VHDL_and_Verilog`
1126			`false`
1127
1128
1129
1130
1131
1132			`v6_sfifo_15x128`
1133
1134
1135
1136
1137			`false`
1138			`false`
1139			`11`
1140			`3`
1141			`128`
1142			`16`
1143			`false`
1144			`Single_Programmable_Empty_Threshold_Constant`
1145			`false`
1146			`false`
1147			`Common_Clock_Shift_Register`
1148			`false`
1149			`false`
1150			`1`
1151			`Active_High`
1152			`4`
1153			`false`
1154			`4`
1155			`16`
1156			`0`
1157			`true`
1158			`true`
1159			`Active_High`
1160			`Active_High`
1161			`false`
1162			`false`
1163			`false`
1164			`Single_Programmable_Full_Threshold_Constant`
1165			`false`
1166			`4`
1167			`Asynchronous_Reset`
1168			`Standard_FIFO`
1169			`12`
1170			`true`
1171			`false`
1172			`false`
1173			`1`
1174			`Active_High`
1175			`false`
1176			`2`
1177			`128`
1178			`1`
1179			`false`
1180
1181
1182
1183
1184			`coregen`
1185			`./`
1186			`./tmp/`
1187			`./tmp/_cg`
1188
1189
1190			`xc6vlx240t`
1191			`virtex6`
1192			`ff1156`
1193			`-1`
1194
1195
1196			`BusFormatAngleBracketNotRipped`
1197			`VHDL`
1198			`true`
1199			`Foundation_ISE`
1200			`false`
1201			`false`
1202			`false`
1203			`Ngc`
1204			`false`
1205
1206
1207			`Behavioral`
1208			`VHDL_and_Verilog`
1209			`false`
1210
1211
1212
1213
1214
1215
1216
1217
1218
1219			`coregen`
1220			`./`
1221			`./tmp/`
1222			`./tmp/_cg`
1223
1224
1225			`xc6vlx240t`
1226			`virtex6`
1227			`ff1156`
1228			`-1`
1229
1230
1231			`BusFormatAngleBracketNotRipped`
1232			`VHDL`
1233			`true`
1234			`Foundation_ISE`
1235			`false`
1236			`false`
1237			`false`
1238			`Ngc`
1239			`false`
1240
1241
1242			`Behavioral`
1243			`VHDL_and_Verilog`
1244			`false`
1245
1246
1247
1248