Subversion Repositories pcie_sg_dma

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SET designentry = VHDL

SET BusFormat = BusFormatAngleBracketNotRipped

SET devicefamily = virtex6

SET device = xc6vlx240t

SET package = ff1156

SET speedgrade = -1

SET FlowVendor = Foundation_ISE

SET VerilogSim = True

SET VHDLSim = True

SELECT Fifo_Generator family Xilinx,_Inc. 5.3

CSET almost_empty_flag=false

CSET almost_full_flag=false

CSET component_name=v6_eb_fifo_counted

CSET data_count=false

CSET data_count_width=14

CSET disable_timing_violations=false

CSET dout_reset_value=0

CSET empty_threshold_assert_value=4096

CSET empty_threshold_negate_value=4097

CSET enable_ecc=false

CSET enable_int_clk=false

CSET enable_reset_synchronization=true

CSET fifo_implementation=Independent_Clocks_Block_RAM

CSET full_flags_reset_value=1

CSET full_threshold_assert_value=12287

CSET full_threshold_negate_value=12286

CSET inject_dbit_error=false

CSET inject_sbit_error=false

CSET input_data_width=72

CSET input_depth=16384

CSET output_data_width=72

CSET output_depth=16384

CSET overflow_flag=false

CSET overflow_sense=Active_High

CSET performance_options=Standard_FIFO

CSET programmable_empty_type=Single_Programmable_Empty_Threshold_Constant

CSET programmable_full_type=Single_Programmable_Full_Threshold_Constant

CSET read_clock_frequency=1

CSET read_data_count=true

CSET read_data_count_width=14

CSET reset_pin=true

CSET reset_type=Asynchronous_Reset

CSET underflow_flag=false

CSET underflow_sense=Active_High

CSET use_dout_reset=true

CSET use_embedded_registers=false

CSET use_extra_logic=false

CSET valid_flag=false

CSET valid_sense=Active_High

CSET write_acknowledge_flag=false

CSET write_acknowledge_sense=Active_High

CSET write_clock_frequency=1

CSET write_data_count=false

CSET write_data_count_width=14