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//-----------------------------------------------------------------------------
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//
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// (c) Copyright 2009 Xilinx, Inc. All rights reserved.
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//
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// This file contains confidential and proprietary information of Xilinx, Inc.
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// and is protected under U.S. and international copyright and other
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// intellectual property laws.
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//
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// DISCLAIMER
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//
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// This disclaimer is not a license and does not grant any rights to the
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// materials distributed herewith. Except as otherwise provided in a valid
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// license issued to you by Xilinx, and to the maximum extent permitted by
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// applicable law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND WITH ALL
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// FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES AND CONDITIONS, EXPRESS,
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// IMPLIED, OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF
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// MERCHANTABILITY, NON-INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE;
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// and (2) Xilinx shall not be liable (whether in contract or tort, including
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// negligence, or under any other theory of liability) for any loss or damage
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// of any kind or nature related to, arising under or in connection with these
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// materials, including for any direct, or any indirect, special, incidental,
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// or consequential loss or damage (including loss of data, profits, goodwill,
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// or any type of loss or damage suffered as a result of any action brought by
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// a third party) even if such damage or loss was reasonably foreseeable or
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// Xilinx had been advised of the possibility of the same.
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//
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// CRITICAL APPLICATIONS
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//
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// Xilinx products are not designed or intended to be fail-safe, or for use in
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// any application requiring fail-safe performance, such as life-support or
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// safety devices or systems, Class III medical devices, nuclear facilities,
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// applications related to the deployment of airbags, or any other
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// applications that could lead to death, personal injury, or severe property
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// or environmental damage (individually and collectively, "Critical
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// Applications"). Customer assumes the sole risk and liability of any use of
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// Xilinx products in Critical Applications, subject only to applicable laws
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// and regulations governing limitations on product liability.
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//
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// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART OF THIS FILE
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// AT ALL TIMES.
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//
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//-----------------------------------------------------------------------------
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// Project : Virtex-6 Integrated Block for PCI Express
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// File : pcie_reset_delay_v6.v
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//--
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//-- Description: sys_reset_n delay (20ms) for Virtex6 PCIe Block
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//--
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//--
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//--
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//--------------------------------------------------------------------------------
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`timescale 1ns/1ns
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module pcie_reset_delay_v6 # (
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parameter PL_FAST_TRAIN = "FALSE",
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parameter REF_CLK_FREQ = 0 // 0 - 100 MHz, 1 - 125 MHz, 2 - 250 MHz
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)
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(
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input wire ref_clk,
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input wire sys_reset_n,
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output delayed_sys_reset_n
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);
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parameter TCQ = 1;
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localparam TBIT = (PL_FAST_TRAIN == "FALSE") ? ((REF_CLK_FREQ == 1) ? 20: (REF_CLK_FREQ == 0) ? 20 : 21) : 2;
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reg [7:0] reg_count_7_0;
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reg [7:0] reg_count_15_8;
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reg [7:0] reg_count_23_16;
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wire [23:0] concat_count;
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assign concat_count = {reg_count_23_16, reg_count_15_8, reg_count_7_0};
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always @(posedge ref_clk or negedge sys_reset_n) begin
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if (!sys_reset_n) begin
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reg_count_7_0 <= #TCQ 8'h0;
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reg_count_15_8 <= #TCQ 8'h0;
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reg_count_23_16 <= #TCQ 8'h0;
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end else begin
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if (delayed_sys_reset_n != 1'b1) begin
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reg_count_7_0 <= #TCQ reg_count_7_0 + 1'b1;
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reg_count_15_8 <= #TCQ (reg_count_7_0 == 8'hff)? reg_count_15_8 + 1'b1 : reg_count_15_8 ;
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reg_count_23_16 <= #TCQ ((reg_count_15_8 == 8'hff) & (reg_count_7_0 == 8'hff)) ? reg_count_23_16 + 1'b1 : reg_count_23_16;
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end
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end
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end
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assign delayed_sys_reset_n = concat_count[TBIT];
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endmodule
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