Subversion Repositories pcie_sg_dma

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//-----------------------------------------------------------------------------

// Project    : Virtex-6 Integrated Block for PCI Express

// File       : pcie_upconfig_fix_3451_v6.v

//--

//-- Description: Virtex6 Workaround for Root Port Upconfigurability Bug

//--

//--

//--------------------------------------------------------------------------------

`timescale 1ns/1ns

module pcie_upconfig_fix_3451_v6 # (

  parameter                                     UPSTREAM_FACING = "TRUE",

  parameter                                     PL_FAST_TRAIN = "FALSE",

  parameter                                     LINK_CAP_MAX_LINK_WIDTH = 6'h08

)

(

  input                                         pipe_clk,

  input                                         pl_phy_lnkup_n,

  input  [5:0]                                  pl_ltssm_state,

  input                                         pl_sel_lnk_rate,

  input  [1:0]                                  pl_directed_link_change,

  input  [3:0]                                  cfg_link_status_negotiated_width,

  output                                        filter_pipe

);

  parameter TCQ = 1;

  reg                                           reg_filter_pipe;

  reg  [5:0]                                    reg_prev_pl_ltssm_state;

  wire [5:0]                                    prev_pl_ltssm_state;

  reg  [15:0]                                   reg_tsx_counter;

  wire [15:0]                                   tsx_counter;

  wire [5:0]                                    cap_link_width;

  // Corrupting all Tsx on all lanes as soon as we do R.RC->R.RI transition to allow time for

  // the core to see the TS1s on all the lanes being configured at the same time

  // R.RI has a 2ms timeout.Corrupting tsxs for ~1/4 of that time

  // 225 pipe_clk cycles-sim_fast_train

  // 60000 pipe_clk cycles-without sim_fast_train

  // Not taking any action  when PLDIRECTEDLINKCHANGE is set

  always @ (posedge pipe_clk) begin

    if (pl_phy_lnkup_n) begin

      reg_tsx_counter <= #TCQ 16'h0;

      reg_filter_pipe <= #TCQ 1'b0;

    end else if ((pl_ltssm_state == 6'h20) &&

                 (prev_pl_ltssm_state == 6'h1d) &&

                 (cfg_link_status_negotiated_width != cap_link_width) &&

                 (pl_directed_link_change[1:0] == 2'b00)) begin

      reg_tsx_counter <= #TCQ 16'h0;

      reg_filter_pipe <= #TCQ 1'b1;

    end else if (filter_pipe == 1'b1) begin

      if (tsx_counter < ((PL_FAST_TRAIN == "TRUE") ? 16'd225: pl_sel_lnk_rate ? 16'd30000 : 16'd60000)) begin

        reg_tsx_counter <= #TCQ tsx_counter + 1'b1;

        reg_filter_pipe <= #TCQ 1'b1;

      end else begin

        reg_tsx_counter <= #TCQ 16'h0;

        reg_filter_pipe <= #TCQ 1'b0;

      end

    end

  end

  assign filter_pipe = (UPSTREAM_FACING == "TRUE") ? 1'b0 : reg_filter_pipe;

  assign tsx_counter = reg_tsx_counter;

  always @(posedge pipe_clk) begin

    if (pl_phy_lnkup_n)

      reg_prev_pl_ltssm_state <= #TCQ 6'h0;

    else

      reg_prev_pl_ltssm_state <= #TCQ pl_ltssm_state;

  end

  assign prev_pl_ltssm_state = reg_prev_pl_ltssm_state;

  assign cap_link_width = LINK_CAP_MAX_LINK_WIDTH;

endmodule