Subversion Repositories pcie_sg_dma

//-----------------------------------------------------------------------------

//

// (c) Copyright 2009 Xilinx, Inc. All rights reserved.

//

// This file contains confidential and proprietary information of Xilinx, Inc.

// and is protected under U.S. and international copyright and other

// intellectual property laws.

//

// DISCLAIMER

//

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//

//-----------------------------------------------------------------------------

// Project    : Virtex-6 Integrated Block for PCI Express

// File       : v6_pcie_v1_3.v

//--

//-- Description: Virtex6 solution wrapper : Endpoint for PCI Express

//--

//--

//--

//--------------------------------------------------------------------------------

`timescale 1ns/1ns

module v6_pcie_v1_3 # (

  parameter        ALLOW_X8_GEN2 = "FALSE",

  parameter        BAR0 = 32'hFFFF0000,

  parameter        BAR1 = 32'hFFF00000,

  parameter        BAR2 = 32'hFFFFF000,

  parameter        BAR3 = 32'h00000000,

  parameter        BAR4 = 32'h00000000,

  parameter        BAR5 = 32'h00000000,

  parameter        CARDBUS_CIS_POINTER = 32'h00000000,

  parameter        CLASS_CODE = 24'h050000,

  parameter        CMD_INTX_IMPLEMENTED = "TRUE",

  parameter        CPL_TIMEOUT_DISABLE_SUPPORTED = "FALSE",

  parameter        CPL_TIMEOUT_RANGES_SUPPORTED = 4'h2,

  parameter        DEV_CAP_ENDPOINT_L0S_LATENCY = 7,

  parameter        DEV_CAP_ENDPOINT_L1_LATENCY = 7,

  parameter        DEV_CAP_EXT_TAG_SUPPORTED = "FALSE",

  parameter        DEV_CAP_MAX_PAYLOAD_SUPPORTED = 2,

  parameter        DEV_CAP_PHANTOM_FUNCTIONS_SUPPORT = 0,

  parameter        DEVICE_ID = 16'h6014,        //--S 16'h0153,

  parameter        DISABLE_LANE_REVERSAL = "TRUE",

  parameter        DISABLE_SCRAMBLING = "FALSE",

  parameter        DSN_BASE_PTR = 12'h100,

  parameter        DSN_CAP_NEXTPTR = 12'h000,

  parameter        DSN_CAP_ON = "TRUE",

  parameter        ENABLE_MSG_ROUTE = 11'h00000000000,

  parameter        ENABLE_RX_TD_ECRC_TRIM = "TRUE",

  parameter        EXPANSION_ROM = 32'h00000000,

  parameter        EXT_CFG_CAP_PTR = 6'h3F,

  parameter        EXT_CFG_XP_CAP_PTR = 10'h3FF,

  parameter        HEADER_TYPE = 8'h00,

  parameter        INTERRUPT_PIN = 8'h1,

  parameter        LINK_CAP_DLL_LINK_ACTIVE_REPORTING_CAP = "FALSE",

  parameter        LINK_CAP_LINK_BANDWIDTH_NOTIFICATION_CAP = "FALSE",

  parameter        LINK_CAP_MAX_LINK_SPEED = 4'h1,

  parameter        LINK_CAP_MAX_LINK_WIDTH = 6'h04,

  parameter        LINK_CAP_SURPRISE_DOWN_ERROR_CAPABLE = "FALSE",

  parameter        LINK_CTRL2_DEEMPHASIS = "FALSE",

  parameter        LINK_CTRL2_HW_AUTONOMOUS_SPEED_DISABLE = "FALSE",

  parameter        LINK_CTRL2_TARGET_LINK_SPEED = 4'h0,

  parameter        LINK_STATUS_SLOT_CLOCK_CONFIG = "FALSE",

  parameter        LL_ACK_TIMEOUT = 15'h0000,

  parameter        LL_ACK_TIMEOUT_EN = "FALSE",

  parameter        LL_ACK_TIMEOUT_FUNC = 0,

  parameter        LL_REPLAY_TIMEOUT = 15'h0000,

  parameter        LL_REPLAY_TIMEOUT_EN = "FALSE",

  parameter        LL_REPLAY_TIMEOUT_FUNC = 0,

  parameter        LTSSM_MAX_LINK_WIDTH = LINK_CAP_MAX_LINK_WIDTH,

  parameter        MSI_CAP_MULTIMSGCAP = 0,

  parameter        MSI_CAP_MULTIMSG_EXTENSION = 0,

  parameter        MSI_CAP_ON = "TRUE",

  parameter        MSI_CAP_PER_VECTOR_MASKING_CAPABLE = "FALSE",

  parameter        MSI_CAP_64_BIT_ADDR_CAPABLE = "TRUE",

  parameter        MSIX_CAP_ON = "FALSE",

  parameter        MSIX_CAP_PBA_BIR = 0,

  parameter        MSIX_CAP_PBA_OFFSET = 29'h0,

  parameter        MSIX_CAP_TABLE_BIR = 0,

  parameter        MSIX_CAP_TABLE_OFFSET = 29'h0,

  parameter        MSIX_CAP_TABLE_SIZE = 11'h000,

  parameter        PCIE_CAP_DEVICE_PORT_TYPE = 4'b0000,

  parameter        PCIE_CAP_INT_MSG_NUM = 5'h1,

  parameter        PCIE_CAP_NEXTPTR = 8'h00,

  parameter        PCIE_DRP_ENABLE = "FALSE",

  parameter        PIPE_PIPELINE_STAGES = 0,                // 0 - 0 stages, 1 - 1 stage, 2 - 2 stages

  parameter        PM_CAP_DSI = "FALSE",

  parameter        PM_CAP_D1SUPPORT = "FALSE",

  parameter        PM_CAP_D2SUPPORT = "FALSE",

  parameter        PM_CAP_NEXTPTR = 8'h48,

  parameter        PM_CAP_PMESUPPORT = 5'h0F,

  parameter        PM_CSR_NOSOFTRST = "TRUE",

  parameter        PM_DATA_SCALE0 = 2'h0,

  parameter        PM_DATA_SCALE1 = 2'h0,

  parameter        PM_DATA_SCALE2 = 2'h0,

  parameter        PM_DATA_SCALE3 = 2'h0,

  parameter        PM_DATA_SCALE4 = 2'h0,

  parameter        PM_DATA_SCALE5 = 2'h0,

  parameter        PM_DATA_SCALE6 = 2'h0,

  parameter        PM_DATA_SCALE7 = 2'h0,

  parameter        PM_DATA0 = 8'h00,

  parameter        PM_DATA1 = 8'h00,

  parameter        PM_DATA2 = 8'h00,

  parameter        PM_DATA3 = 8'h00,

  parameter        PM_DATA4 = 8'h00,

  parameter        PM_DATA5 = 8'h00,

  parameter        PM_DATA6 = 8'h00,

  parameter        PM_DATA7 = 8'h00,

  parameter        REF_CLK_FREQ = 0,                        // 0 - 100 MHz, 1 - 125 MHz, 2 - 250 MHz

  parameter        REVISION_ID = 8'h06,

  parameter        SUBSYSTEM_ID = 16'hABB3,

  parameter        SUBSYSTEM_VENDOR_ID = 16'h0084,

  parameter        TL_RX_RAM_RADDR_LATENCY = 0,

  parameter        TL_RX_RAM_RDATA_LATENCY = 2,

  parameter        TL_RX_RAM_WRITE_LATENCY = 0,

  parameter        TL_TX_RAM_RADDR_LATENCY = 0,

  parameter        TL_TX_RAM_RDATA_LATENCY = 2,

  parameter        TL_TX_RAM_WRITE_LATENCY = 0,

  parameter        UPCONFIG_CAPABLE = "TRUE",

  parameter        USER_CLK_FREQ = 2,

  parameter        VC_BASE_PTR = 12'h0,

  parameter        VC_CAP_NEXTPTR = 12'h000,

  parameter        VC_CAP_ON = "FALSE",

  parameter        VC_CAP_REJECT_SNOOP_TRANSACTIONS = "FALSE",

  parameter        VC0_CPL_INFINITE = "TRUE",

  parameter        VC0_RX_RAM_LIMIT = 13'h7FF,

  parameter        VC0_TOTAL_CREDITS_CD = 308,

  parameter        VC0_TOTAL_CREDITS_CH = 36,

  parameter        VC0_TOTAL_CREDITS_NPH = 12,

  parameter        VC0_TOTAL_CREDITS_PD = 308,

  parameter        VC0_TOTAL_CREDITS_PH = 32,

  parameter        VC0_TX_LASTPACKET = 29,

  parameter        VENDOR_ID = 16'h10EE,                        //--S 16'h10DC,

  parameter        VSEC_BASE_PTR = 12'h0,

  parameter        VSEC_CAP_NEXTPTR = 12'h000,

  parameter        VSEC_CAP_ON = "FALSE",

  parameter        AER_BASE_PTR = 12'h128,

  parameter        AER_CAP_ECRC_CHECK_CAPABLE = "FALSE",

  parameter        AER_CAP_ECRC_GEN_CAPABLE = "FALSE",

  parameter        AER_CAP_ID = 16'h0001,

  parameter        AER_CAP_INT_MSG_NUM_MSI = 5'h0a,

  parameter        AER_CAP_INT_MSG_NUM_MSIX = 5'h15,

  parameter        AER_CAP_NEXTPTR = 12'h160,

  parameter        AER_CAP_ON = "FALSE",

  parameter        AER_CAP_PERMIT_ROOTERR_UPDATE = "TRUE",

  parameter        AER_CAP_VERSION = 4'h1,

  parameter        CAPABILITIES_PTR = 8'h40,

  parameter        CRM_MODULE_RSTS = 7'h00,

  parameter        DEV_CAP_ENABLE_SLOT_PWR_LIMIT_SCALE = "TRUE",

  parameter        DEV_CAP_ENABLE_SLOT_PWR_LIMIT_VALUE = "TRUE",

  parameter        DEV_CAP_FUNCTION_LEVEL_RESET_CAPABLE = "FALSE",

  parameter        DEV_CAP_ROLE_BASED_ERROR = "TRUE",

  parameter        DEV_CAP_RSVD_14_12 = 0,

  parameter        DEV_CAP_RSVD_17_16 = 0,

  parameter        DEV_CAP_RSVD_31_29 = 0,

  parameter        DEV_CONTROL_AUX_POWER_SUPPORTED = "FALSE",

  parameter        DISABLE_ASPM_L1_TIMER = "FALSE",

  parameter        DISABLE_BAR_FILTERING = "FALSE",

  parameter        DISABLE_ID_CHECK = "FALSE",

  parameter        DISABLE_RX_TC_FILTER = "FALSE",

  parameter        DNSTREAM_LINK_NUM = 8'h00,

  parameter        DSN_CAP_ID = 16'h0003,

  parameter        DSN_CAP_VERSION = 4'h1,

  parameter        ENTER_RVRY_EI_L0 = "TRUE",

  parameter        INFER_EI = 5'h0c,

  parameter        IS_SWITCH = "FALSE",

  parameter        LAST_CONFIG_DWORD = 10'h3FF,

  parameter        LINK_CAP_ASPM_SUPPORT = 1,

  parameter        LINK_CAP_CLOCK_POWER_MANAGEMENT = "FALSE",

  parameter        LINK_CAP_L0S_EXIT_LATENCY_COMCLK_GEN1 = 7,

  parameter        LINK_CAP_L0S_EXIT_LATENCY_COMCLK_GEN2 = 7,

  parameter        LINK_CAP_L0S_EXIT_LATENCY_GEN1 = 7,

  parameter        LINK_CAP_L0S_EXIT_LATENCY_GEN2 = 7,

  parameter        LINK_CAP_L1_EXIT_LATENCY_COMCLK_GEN1 = 7,

  parameter        LINK_CAP_L1_EXIT_LATENCY_COMCLK_GEN2 = 7,

  parameter        LINK_CAP_L1_EXIT_LATENCY_GEN1 = 7,

  parameter        LINK_CAP_L1_EXIT_LATENCY_GEN2 = 7,

  parameter        LINK_CAP_RSVD_23_22 = 0,

  parameter        LINK_CONTROL_RCB = 0,

  parameter        MSI_BASE_PTR = 8'h48,

  parameter        MSI_CAP_ID = 8'h05,

  parameter        MSI_CAP_NEXTPTR = 8'h60,

  parameter        MSIX_BASE_PTR = 8'h9c,

  parameter        MSIX_CAP_ID = 8'h11,

  parameter        MSIX_CAP_NEXTPTR = 8'h00,

  parameter        N_FTS_COMCLK_GEN1 = 255,

  parameter        N_FTS_COMCLK_GEN2 = 254,

  parameter        N_FTS_GEN1 = 255,

  parameter        N_FTS_GEN2 = 255,

  parameter        PCIE_BASE_PTR = 8'h60,

  parameter        PCIE_CAP_CAPABILITY_ID = 8'h10,

  parameter        PCIE_CAP_CAPABILITY_VERSION = 4'h2,

  parameter        PCIE_CAP_ON = "TRUE",

  parameter        PCIE_CAP_RSVD_15_14 = 0,

  parameter        PCIE_CAP_SLOT_IMPLEMENTED = "FALSE",

  parameter        PCIE_REVISION = 2,

  parameter        PGL0_LANE = 0,

  parameter        PGL1_LANE = 1,

  parameter        PGL2_LANE = 2,

  parameter        PGL3_LANE = 3,

  parameter        PGL4_LANE = 4,

  parameter        PGL5_LANE = 5,

  parameter        PGL6_LANE = 6,

  parameter        PGL7_LANE = 7,

  parameter        PL_AUTO_CONFIG = 0,

  parameter        PL_FAST_TRAIN = "FALSE",

  parameter        PM_BASE_PTR = 8'h40,

  parameter        PM_CAP_AUXCURRENT = 0,

  parameter        PM_CAP_ID = 8'h01,

  parameter        PM_CAP_ON = "TRUE",

  parameter        PM_CAP_PME_CLOCK = "FALSE",

  parameter        PM_CAP_RSVD_04 = 0,

  parameter        PM_CAP_VERSION = 3,

  parameter        PM_CSR_BPCCEN = "FALSE",

  parameter        PM_CSR_B2B3 = "FALSE",

  parameter        RECRC_CHK = 0,

  parameter        RECRC_CHK_TRIM = "FALSE",

  parameter        ROOT_CAP_CRS_SW_VISIBILITY = "FALSE",

  parameter        SELECT_DLL_IF = "FALSE",

  parameter        SLOT_CAP_ATT_BUTTON_PRESENT = "FALSE",

  parameter        SLOT_CAP_ATT_INDICATOR_PRESENT = "FALSE",

  parameter        SLOT_CAP_ELEC_INTERLOCK_PRESENT = "FALSE",

  parameter        SLOT_CAP_HOTPLUG_CAPABLE = "FALSE",

  parameter        SLOT_CAP_HOTPLUG_SURPRISE = "FALSE",

  parameter        SLOT_CAP_MRL_SENSOR_PRESENT = "FALSE",

  parameter        SLOT_CAP_NO_CMD_COMPLETED_SUPPORT = "FALSE",

  parameter        SLOT_CAP_PHYSICAL_SLOT_NUM = 13'h0000,

  parameter        SLOT_CAP_POWER_CONTROLLER_PRESENT = "FALSE",

  parameter        SLOT_CAP_POWER_INDICATOR_PRESENT = "FALSE",

  parameter        SLOT_CAP_SLOT_POWER_LIMIT_SCALE = 0,

  parameter        SLOT_CAP_SLOT_POWER_LIMIT_VALUE = 8'h00,

  parameter        SPARE_BIT0 = 0,

  parameter        SPARE_BIT1 = 0,

  parameter        SPARE_BIT2 = 0,

  parameter        SPARE_BIT3 = 0,

  parameter        SPARE_BIT4 = 0,

  parameter        SPARE_BIT5 = 0,

  parameter        SPARE_BIT6 = 0,

  parameter        SPARE_BIT7 = 0,

  parameter        SPARE_BIT8 = 0,

  parameter        SPARE_BYTE0 = 8'h00,

  parameter        SPARE_BYTE1 = 8'h00,

  parameter        SPARE_BYTE2 = 8'h00,

  parameter        SPARE_BYTE3 = 8'h00,

  parameter        SPARE_WORD0 = 32'h00000000,

  parameter        SPARE_WORD1 = 32'h00000000,

  parameter        SPARE_WORD2 = 32'h00000000,

  parameter        SPARE_WORD3 = 32'h00000000,

  parameter        TL_RBYPASS = "FALSE",

  parameter        TL_TFC_DISABLE = "FALSE",

  parameter        TL_TX_CHECKS_DISABLE = "FALSE",

  parameter        EXIT_LOOPBACK_ON_EI  = "TRUE",

  parameter        UPSTREAM_FACING = "TRUE",

  parameter        UR_INV_REQ = "TRUE",

  parameter        VC_CAP_ID = 16'h0002,

  parameter        VC_CAP_VERSION = 4'h1,

  parameter        VSEC_CAP_HDR_ID = 16'h1234,

  parameter        VSEC_CAP_HDR_LENGTH = 12'h018,

  parameter        VSEC_CAP_HDR_REVISION = 4'h1,

  parameter        VSEC_CAP_ID = 16'h000b,

  parameter        VSEC_CAP_IS_LINK_VISIBLE = "TRUE",

  parameter        VSEC_CAP_VERSION = 4'h1

)

(

  //-------------------------------------------------------

  // 1. PCI Express (pci_exp) Interface

  //-------------------------------------------------------

  // Tx

  output  [(LINK_CAP_MAX_LINK_WIDTH - 1):0]     pci_exp_txp,

  output  [(LINK_CAP_MAX_LINK_WIDTH - 1):0]     pci_exp_txn,

  // Rx

  input   [(LINK_CAP_MAX_LINK_WIDTH - 1):0]     pci_exp_rxp,

  input   [(LINK_CAP_MAX_LINK_WIDTH - 1):0]     pci_exp_rxn,

  //-------------------------------------------------------

  // 2. Transaction (TRN) Interface

  //-------------------------------------------------------

  // Common

  output                                        trn_clk,

  output                                        trn_reset_n,

  output                                        trn_lnk_up_n,

  // Tx

  output  [5:0]                                 trn_tbuf_av,

  output                                        trn_tcfg_req_n,

  output                                        trn_terr_drop_n,

  output                                        trn_tdst_rdy_n,

  input  [63:0]                                 trn_td,

  input                                         trn_trem_n,

  input                                         trn_tsof_n,

  input                                         trn_teof_n,

  input                                         trn_tsrc_rdy_n,

  input                                         trn_tsrc_dsc_n,

  input                                         trn_terrfwd_n,

  input                                         trn_tcfg_gnt_n,

  input                                         trn_tstr_n,

  // Rx

  output  [63:0]                                trn_rd,

  output                                        trn_rrem_n,

  output                                        trn_rsof_n,

  output                                        trn_reof_n,

  output                                        trn_rsrc_rdy_n,

  output                                        trn_rsrc_dsc_n,

  output                                        trn_rerrfwd_n,

  output  [6:0]                                 trn_rbar_hit_n,

  input                                         trn_rdst_rdy_n,

  input                                         trn_rnp_ok_n,

  // Flow Control

  output [11:0]                                 trn_fc_cpld,

  output  [7:0]                                 trn_fc_cplh,

  output [11:0]                                 trn_fc_npd,

  output  [7:0]                                 trn_fc_nph,

  output [11:0]                                 trn_fc_pd,

  output  [7:0]                                 trn_fc_ph,

  input   [2:0]                                 trn_fc_sel,

  //-------------------------------------------------------

  // 3. Configuration (CFG) Interface

  //-------------------------------------------------------

  output [31:0]                                 cfg_do,

  output                                        cfg_rd_wr_done_n,

  input  [31:0]                                 cfg_di,

  input   [3:0]                                 cfg_byte_en_n,

  input   [9:0]                                 cfg_dwaddr,

  input                                         cfg_wr_en_n,

  input                                         cfg_rd_en_n,

  input                                         cfg_err_cor_n,

  input                                         cfg_err_ur_n,

  input                                         cfg_err_ecrc_n,

  input                                         cfg_err_cpl_timeout_n,

  input                                         cfg_err_cpl_abort_n,

  input                                         cfg_err_cpl_unexpect_n,

  input                                         cfg_err_posted_n,

  input                                         cfg_err_locked_n,

  input  [47:0]                                 cfg_err_tlp_cpl_header,

  output                                        cfg_err_cpl_rdy_n,

  input                                         cfg_interrupt_n,

  output                                        cfg_interrupt_rdy_n,

  input                                         cfg_interrupt_assert_n,

  input  [7:0]                                  cfg_interrupt_di,

  output [7:0]                                  cfg_interrupt_do,

  output [2:0]                                  cfg_interrupt_mmenable,

  output                                        cfg_interrupt_msienable,

  output                                        cfg_interrupt_msixenable,

  output                                        cfg_interrupt_msixfm,

  input                                         cfg_turnoff_ok_n,

  output                                        cfg_to_turnoff_n,

  input                                         cfg_trn_pending_n,

  input                                         cfg_pm_wake_n,

  output  [7:0]                                 cfg_bus_number,

  output  [4:0]                                 cfg_device_number,

  output  [2:0]                                 cfg_function_number,

  output [15:0]                                 cfg_status,

  output [15:0]                                 cfg_command,

  output [15:0]                                 cfg_dstatus,

  output [15:0]                                 cfg_dcommand,

  output [15:0]                                 cfg_lstatus,

  output [15:0]                                 cfg_lcommand,

  output [15:0]                                 cfg_dcommand2,

  output  [2:0]                                 cfg_pcie_link_state_n,

  input  [63:0]                                 cfg_dsn,

  output                                        cfg_pmcsr_pme_en,

  output                                        cfg_pmcsr_pme_status,

  output  [1:0]                                 cfg_pmcsr_powerstate,

  output                                        lnk_clk_en,

  //-------------------------------------------------------

  // 4. Physical Layer Control and Status (PL) Interface

  //-------------------------------------------------------

  output [2:0]                                  pl_initial_link_width,

  output [1:0]                                  pl_lane_reversal_mode,

  output                                        pl_link_gen2_capable,

  output                                        pl_link_partner_gen2_supported,

  output                                        pl_link_upcfg_capable,

  output [5:0]                                  pl_ltssm_state,

  output                                        pl_received_hot_rst,

  output                                        pl_sel_link_rate,

  output [1:0]                                  pl_sel_link_width,

  input                                         pl_directed_link_auton,

  input  [1:0]                                  pl_directed_link_change,

  input                                         pl_directed_link_speed,

  input  [1:0]                                  pl_directed_link_width,

  input                                         pl_upstream_prefer_deemph,

  //-------------------------------------------------------

  // 5. System  (SYS) Interface

  //-------------------------------------------------------

  input                                         sys_clk,

  input                                         sys_reset_n

);

  wire                                          rx_func_level_reset_n;

  wire                                          cfg_msg_received;

  wire                                          cfg_msg_received_pme_to;

  wire                                          cfg_cmd_bme;

  wire                                          cfg_cmd_intdis;

  wire                                          cfg_cmd_io_en;

  wire                                          cfg_cmd_mem_en;

  wire                                          cfg_cmd_serr_en;

  wire                                          cfg_dev_control_aux_power_en ;

  wire                                          cfg_dev_control_corr_err_reporting_en ;

  wire                                          cfg_dev_control_enable_relaxed_order ;

  wire                                          cfg_dev_control_ext_tag_en ;

  wire                                          cfg_dev_control_fatal_err_reporting_en ;

  wire [2:0]                                    cfg_dev_control_maxpayload ;

  wire [2:0]                                    cfg_dev_control_max_read_req ;

  wire                                          cfg_dev_control_non_fatal_reporting_en ;

  wire                                          cfg_dev_control_nosnoop_en ;

  wire                                          cfg_dev_control_phantom_en ;

  wire                                          cfg_dev_control_ur_err_reporting_en ;

  wire                                          cfg_dev_control2_cpltimeout_dis ;

  wire [3:0]                                    cfg_dev_control2_cpltimeout_val ;

  wire                                          cfg_dev_status_corr_err_detected ;

  wire                                          cfg_dev_status_fatal_err_detected ;

  wire                                          cfg_dev_status_nonfatal_err_detected ;

  wire                                          cfg_dev_status_ur_detected ;

  wire                                          cfg_link_control_auto_bandwidth_int_en ;

  wire                                          cfg_link_control_bandwidth_int_en ;

  wire                                          cfg_link_control_hw_auto_width_dis ;

  wire                                          cfg_link_control_clock_pm_en ;

  wire                                          cfg_link_control_extended_sync ;

  wire                                          cfg_link_control_common_clock ;

  wire                                          cfg_link_control_retrain_link ;

  wire                                          cfg_link_control_linkdisable ;

  wire                                          cfg_link_control_rcb ;

  wire [1:0]                                    cfg_link_control_aspm_control ;

  wire                                          cfg_link_status_autobandwidth_status ;

  wire                                          cfg_link_status_bandwidth_status ;

  wire                                          cfg_link_status_dll_active ;

  wire                                          cfg_link_status_link_training ;

  wire [3:0]                                    cfg_link_status_negotiated_link_width ;

  wire [1:0]                                    cfg_link_status_current_speed ;

  wire [15:0]                                   cfg_msg_data;

  wire                                          sys_reset_n_d;

  wire                                          phy_rdy_n;

  wire                                          trn_lnk_up_n_int;

  wire                                          trn_lnk_up_n_int1;

  wire                                          trn_reset_n_int;

  wire                                          trn_reset_n_int1;

  reg  [7:0]                                    cfg_bus_number_d;

  reg  [4:0]                                    cfg_device_number_d;

  reg  [2:0]                                    cfg_function_number_d;

  // assigns to outputs

  assign                                        cfg_to_turnoff_n = ~cfg_msg_received_pme_to;

  assign                                        cfg_status = {16'b0};

  assign                                        cfg_command = {5'b0,

                                                               cfg_cmd_intdis,

                                                               1'b0,

                                                               cfg_cmd_serr_en,

                                                               5'b0,

                                                               cfg_cmd_bme,

                                                               cfg_cmd_mem_en,

                                                               cfg_cmd_io_en};

  assign                                        cfg_dstatus = {10'h0,

                                                               ~cfg_trn_pending_n,

                                                               1'b0,

                                                               cfg_dev_status_ur_detected,

                                                               cfg_dev_status_fatal_err_detected,

                                                               cfg_dev_status_nonfatal_err_detected,

                                                               cfg_dev_status_corr_err_detected};

  assign                                        cfg_dcommand = {1'b0,

                                                               cfg_dev_control_max_read_req,

                                                               cfg_dev_control_nosnoop_en,

                                                               cfg_dev_control_aux_power_en,

                                                               cfg_dev_control_phantom_en,

                                                               cfg_dev_control_ext_tag_en,

                                                               cfg_dev_control_maxpayload,

                                                               cfg_dev_control_enable_relaxed_order,

                                                               cfg_dev_control_ur_err_reporting_en,

                                                               cfg_dev_control_fatal_err_reporting_en,

                                                               cfg_dev_control_non_fatal_reporting_en,

                                                               cfg_dev_control_corr_err_reporting_en };

  assign                                        cfg_lstatus = {cfg_link_status_autobandwidth_status,

                                                               cfg_link_status_bandwidth_status,

                                                               cfg_link_status_dll_active,

                                                               (LINK_STATUS_SLOT_CLOCK_CONFIG == "TRUE") ? 1'b1 : 1'b0,

                                                               cfg_link_status_link_training,

                                                               1'b0,

                                                               {2'b00, cfg_link_status_negotiated_link_width},

                                                               {2'b00, cfg_link_status_current_speed} };

  assign                                        cfg_lcommand = {cfg_link_control_auto_bandwidth_int_en,

                                                                cfg_link_control_bandwidth_int_en,

                                                                cfg_link_control_hw_auto_width_dis,

                                                                cfg_link_control_clock_pm_en,

                                                                cfg_link_control_extended_sync,

                                                                cfg_link_control_common_clock,

                                                                cfg_link_control_retrain_link,

                                                                cfg_link_control_linkdisable,

                                                                cfg_link_control_rcb,

                                                                1'b0,

                                                                cfg_link_control_aspm_control};

  assign                                        cfg_bus_number = cfg_bus_number_d;

  assign                                        cfg_device_number = cfg_device_number_d;

  assign                                        cfg_function_number =  cfg_function_number_d;

  assign                                        cfg_dcommand2 = {11'b0,

                                                                 cfg_dev_control2_cpltimeout_dis,

                                                                 cfg_dev_control2_cpltimeout_val};

  // Capture Bus/Device/Function number

  always @(posedge trn_clk) begin

    if      (trn_lnk_up_n)      cfg_bus_number_d <= 8'b0;

    else if (~cfg_msg_received) cfg_bus_number_d <= cfg_msg_data[15:8];

  end

  always @(posedge trn_clk) begin

      if      (trn_lnk_up_n)      cfg_device_number_d <= 5'b0;

      else if (~cfg_msg_received) cfg_device_number_d <= cfg_msg_data[7:3];

  end

  always @(posedge trn_clk) begin

      if      (trn_lnk_up_n)      cfg_function_number_d <= 3'b0;

      else if (~cfg_msg_received) cfg_function_number_d <= cfg_msg_data[2:0];

  end

  // Generate trn_lnk_up_n

FDCP #(

  .INIT(1'b1)

) trn_lnk_up_n_i (

  .Q (trn_lnk_up_n),

  .D (trn_lnk_up_n_int1),

  .C (trn_clk),

  .CLR (1'b0),

  .PRE (1'b0)

);

FDCP #(

  .INIT(1'b1)

) trn_lnk_up_n_int_i (

  .Q (trn_lnk_up_n_int1),

  .D (trn_lnk_up_n_int),

  .C (trn_clk),

  .CLR (1'b0),

  .PRE (1'b0)

);

  // Generate trn_reset_n

FDCP #(

  .INIT(1'b0)

) trn_reset_n_i (

  .Q (trn_reset_n),

  .D (trn_reset_n_int1 & ~phy_rdy_n),

  .C (trn_clk),

  .CLR (~sys_reset_n_d),

  .PRE (1'b0)