Subversion Repositories pcie_sg_dma

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--     solely for design, simulation, implementation and creation of          --

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-- You must compile the wrapper file v6_sfifo_15x128.vhd when simulating

-- the core, v6_sfifo_15x128. When compiling the wrapper file, be sure to

-- reference the XilinxCoreLib VHDL simulation library. For detailed

-- instructions, please refer to the "CORE Generator Help".

-- The synthesis directives "translate_off/translate_on" specified

-- below are supported by Xilinx, Mentor Graphics and Synplicity

-- synthesis tools. Ensure they are correct for your synthesis tool(s).

LIBRARY ieee;

USE ieee.std_logic_1164.ALL;

-- synthesis translate_off

Library XilinxCoreLib;

-- synthesis translate_on

ENTITY v6_sfifo_15x128 IS

        port (

        clk: IN std_logic;

        rst: IN std_logic;

        din: IN std_logic_VECTOR(127 downto 0);

        wr_en: IN std_logic;

        rd_en: IN std_logic;

        dout: OUT std_logic_VECTOR(127 downto 0);

        full: OUT std_logic;

        empty: OUT std_logic;

        prog_full: OUT std_logic;

        prog_empty: OUT std_logic);

END v6_sfifo_15x128;

ARCHITECTURE v6_sfifo_15x128_a OF v6_sfifo_15x128 IS

-- synthesis translate_off

component wrapped_v6_sfifo_15x128

        port (

        clk: IN std_logic;

        rst: IN std_logic;

        din: IN std_logic_VECTOR(127 downto 0);

        wr_en: IN std_logic;

        rd_en: IN std_logic;

        dout: OUT std_logic_VECTOR(127 downto 0);

        full: OUT std_logic;

        empty: OUT std_logic;

        prog_full: OUT std_logic;

        prog_empty: OUT std_logic);

end component;

-- Configuration specification 

        for all : wrapped_v6_sfifo_15x128 use entity XilinxCoreLib.fifo_generator_v5_3(behavioral)

                generic map(

                        c_has_int_clk => 0,

                        c_wr_response_latency => 1,

                        c_rd_freq => 1,

                        c_has_srst => 0,

                        c_enable_rst_sync => 1,

                        c_has_rd_data_count => 0,

                        c_din_width => 128,

                        c_has_wr_data_count => 0,

                        c_full_flags_rst_val => 1,

                        c_implementation_type => 1,

                        c_family => "virtex6",

                        c_use_embedded_reg => 0,

                        c_has_wr_rst => 0,

                        c_wr_freq => 1,

                        c_use_dout_rst => 1,

                        c_underflow_low => 0,

                        c_has_meminit_file => 0,

                        c_has_overflow => 0,

                        c_preload_latency => 1,

                        c_dout_width => 128,

                        c_msgon_val => 1,

                        c_rd_depth => 16,

                        c_default_value => "BlankString",

                        c_mif_file_name => "BlankString",

                        c_error_injection_type => 0,

                        c_has_underflow => 0,

                        c_has_rd_rst => 0,

                        c_has_almost_full => 0,

                        c_has_rst => 1,

                        c_data_count_width => 4,

                        c_has_wr_ack => 0,

                        c_use_ecc => 0,

                        c_wr_ack_low => 0,

                        c_common_clock => 1,

                        c_rd_pntr_width => 4,

                        c_use_fwft_data_count => 0,

                        c_has_almost_empty => 0,

                        c_rd_data_count_width => 4,

                        c_enable_rlocs => 0,

                        c_wr_pntr_width => 4,

                        c_overflow_low => 0,

                        c_prog_empty_type => 1,

                        c_optimization_mode => 0,

                        c_wr_data_count_width => 4,

                        c_preload_regs => 0,

                        c_dout_rst_val => "0",

                        c_has_data_count => 0,

                        c_prog_full_thresh_negate_val => 11,

                        c_wr_depth => 16,

                        c_prog_empty_thresh_negate_val => 3,

                        c_prog_empty_thresh_assert_val => 2,

                        c_has_valid => 0,

                        c_init_wr_pntr_val => 0,

                        c_prog_full_thresh_assert_val => 12,

                        c_use_fifo16_flags => 0,

                        c_has_backup => 0,

                        c_valid_low => 0,

                        c_prim_fifo_type => "512x72",

                        c_count_type => 0,

                        c_prog_full_type => 1,

                        c_memory_type => 3);

-- synthesis translate_on

BEGIN

-- synthesis translate_off

U0 : wrapped_v6_sfifo_15x128

                port map (

                        clk => clk,

                        rst => rst,

                        din => din,

                        wr_en => wr_en,

                        rd_en => rd_en,

                        dout => dout,

                        full => full,

                        empty => empty,

                        prog_full => prog_full,

                        prog_empty => prog_empty);

-- synthesis translate_on

END v6_sfifo_15x128_a;