Subversion Repositories pcie_sg_dma

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-- The following code must appear in the VHDL architecture header:

------------- Begin Cut here for COMPONENT Declaration ------ COMP_TAG

component v6_sfifo_15x128

        port (

        clk: IN std_logic;

        rst: IN std_logic;

        din: IN std_logic_VECTOR(127 downto 0);

        wr_en: IN std_logic;

        rd_en: IN std_logic;

        dout: OUT std_logic_VECTOR(127 downto 0);

        full: OUT std_logic;

        empty: OUT std_logic;

        prog_full: OUT std_logic;

        prog_empty: OUT std_logic);

end component;

-- Synplicity black box declaration

attribute syn_black_box : boolean;

attribute syn_black_box of v6_sfifo_15x128: component is true;

-- COMP_TAG_END ------ End COMPONENT Declaration ------------

-- The following code must appear in the VHDL architecture

-- body. Substitute your own instance name and net names.

------------- Begin Cut here for INSTANTIATION Template ----- INST_TAG

your_instance_name : v6_sfifo_15x128

                port map (

                        clk => clk,

                        rst => rst,

                        din => din,

                        wr_en => wr_en,

                        rd_en => rd_en,

                        dout => dout,

                        full => full,

                        empty => empty,

                        prog_full => prog_full,

                        prog_empty => prog_empty);

-- INST_TAG_END ------ End INSTANTIATION Template ------------

-- You must compile the wrapper file v6_sfifo_15x128.vhd when simulating

-- the core, v6_sfifo_15x128. When compiling the wrapper file, be sure to

-- reference the XilinxCoreLib VHDL simulation library. For detailed

-- instructions, please refer to the "CORE Generator Help".