OpenCores
URL https://opencores.org/ocsvn/pcie_sg_dma/pcie_sg_dma/trunk

Subversion Repositories pcie_sg_dma

[/] [pcie_sg_dma/] [branches/] [Virtex6/] [ML605_ISE12.3/] [ipcore_dir_ISE12.3/] [coregen.cgc] - Blame information for rev 11

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Line No. Rev Author Line
1 11 barabba
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1064 
            1
1065 
            false
1066 
            false
1067 
            false
1068 
            false
1069 
            1
1070 
            1022
1071 
            false
1072 
            Active_High
1073 
            14
1074 
            false
1075 
            false
1076 
            Full
1077 
            Common_Clock_Block_RAM
1078 
            1023
1079 
            false
1080 
            14
1081 
            4
1082 
            32
1083 
            1024
1084 
            false
1085 
            FIFO
1086 
            16384
1087 
            1023
1088 
            false
1089 
            0
1090 
            true
1091 
            true
1092 
            Active_High
1093 
            Active_High
1094 
            false
1095 
            Empty
1096 
            1022
1097 
            false
1098 
            false
1099 
            false
1100 
            false
1101 
            false
1102 
            true
1103 
            false
1104 
            1022
1105 
            Full
1106 
            false
1107 
            Data_FIFO
1108 
            Common_Clock_Block_RAM
1109 
            false
1110 
            Full
1111 
            false
1112 
            Common_Clock_Block_RAM
1113 
            1023
1114 
            FIFO
1115 
            1
1116 
            false
1117 
            false
1118 
            Single_Programmable_Full_Threshold_Constant
1119 
            false
1120 
            Empty
1121 
            14
1122 
            Common_Clock
1123 
            Asynchronous_Reset
1124 
            false
1125 
            Empty
1126 
            false
1127 
            1022
1128 
            FIFO
1129 
            false
1130 
            Data_FIFO
1131 
            false
1132 
            Full
1133 
            1
1134 
            Common_Clock_Block_RAM
1135 
            Standard_FIFO
1136 
            false
1137 
            false
1138 
            Data_FIFO
1139 
            true
1140 
            16
1141 
            false
1142 
            12287
1143 
            false
1144 
            Full
1145 
            FIFO
1146 
            false
1147 
            4
1148 
            false
1149 
            Common_Clock_Block_RAM
1150 
            false
1151 
            false
1152 
            false
1153 
            1
1154 
            Active_High
1155 
            false
1156 
            Empty
1157 
            false
1158 
            AXI4_Stream
1159 
            4096
1160 
            72
1161 
            1
1162 
            Empty
1163 
            true
1164 
            8
1165 
            Active_High
1166 
            Data_FIFO
1167 
            false
1168
1169
1170
1171
1172 
               coregen
1173 
               ./
1174 
               ./tmp/
1175 
               ./tmp/_cg
1176
1177
1178 
               xc6vlx240t
1179 
               virtex6
1180 
               ff1156
1181 
               -1
1182
1183
1184 
               BusFormatAngleBracketNotRipped
1185 
               VHDL
1186 
               true
1187 
               Foundation_ISE
1188 
               false
1189 
               false
1190 
               false
1191 
               Ngc
1192 
               false
1193
1194
1195 
               Behavioral
1196 
               VHDL_and_Verilog
1197 
               false
1198
1199
1200
1201
1202
1203 
         v6_eb_fifo_counted_new
1204
1205
1206
1207
1208 
            false
1209 
            false
1210 
            1024
1211 
            Native
1212 
            Full
1213 
            false
1214 
            1023
1215 
            Data_FIFO
1216 
            false
1217 
            Active_High
1218 
            Common_Clock_Block_RAM
1219 
            false
1220 
            false
1221 
            false
1222 
            true
1223 
            false
1224 
            false
1225 
            16
1226 
            Slave_Interface_Clock_Enable
1227 
            false
1228 
            false
1229 
            false
1230 
            28670
1231 
            false
1232 
            1
1233 
            1022
1234 
            false
1235 
            Empty
1236 
            4
1237 
            1
1238 
            4
1239 
            FIFO
1240 
            64
1241 
            false
1242 
            4097
1243 
            1023
1244 
            72
1245 
            64
1246 
            1024
1247 
            false
1248 
            Data_FIFO
1249 
            32768
1250 
            false
1251 
            4
1252 
            true
1253 
            1023
1254 
            false
1255 
            Single_Programmable_Empty_Threshold_Constant
1256 
            16
1257 
            false
1258 
            FIFO
1259 
            false
1260 
            false
1261 
            false
1262 
            1022
1263 
            false
1264 
            Independent_Clocks_Block_RAM
1265 
            false
1266 
            1
1267 
            false
1268 
            false
1269 
            false
1270 
            false
1271 
            1
1272 
            1022
1273 
            false
1274 
            Active_High
1275 
            15
1276 
            false
1277 
            false
1278 
            Full
1279 
            Common_Clock_Block_RAM
1280 
            1023
1281 
            false
1282 
            15
1283 
            4
1284 
            32
1285 
            1024
1286 
            false
1287 
            FIFO
1288 
            32768
1289 
            1023
1290 
            false
1291 
            0
1292 
            true
1293 
            true
1294 
            Active_High
1295 
            Active_High
1296 
            false
1297 
            Empty
1298 
            1022
1299 
            false
1300 
            false
1301 
            false
1302 
            false
1303 
            false
1304 
            true
1305 
            false
1306 
            1022
1307 
            Full
1308 
            false
1309 
            Data_FIFO
1310 
            Common_Clock_Block_RAM
1311 
            false
1312 
            Full
1313 
            false
1314 
            Common_Clock_Block_RAM
1315 
            1023
1316 
            FIFO
1317 
            1
1318 
            false
1319 
            false
1320 
            Single_Programmable_Full_Threshold_Constant
1321 
            false
1322 
            Empty
1323 
            15
1324 
            Common_Clock
1325 
            Asynchronous_Reset
1326 
            false
1327 
            Empty
1328 
            false
1329 
            1022
1330 
            FIFO
1331 
            false
1332 
            Data_FIFO
1333 
            false
1334 
            Full
1335 
            1
1336 
            Common_Clock_Block_RAM
1337 
            Standard_FIFO
1338 
            false
1339 
            false
1340 
            Data_FIFO
1341 
            true
1342 
            16
1343 
            false
1344 
            28671
1345 
            false
1346 
            Full
1347 
            FIFO
1348 
            false
1349 
            4
1350 
            false
1351 
            Common_Clock_Block_RAM
1352 
            false
1353 
            false
1354 
            false
1355 
            1
1356 
            Active_High
1357 
            false
1358 
            Empty
1359 
            false
1360 
            AXI4_Stream
1361 
            4096
1362 
            72
1363 
            1
1364 
            Empty
1365 
            true
1366 
            8
1367 
            Active_High
1368 
            Data_FIFO
1369 
            false
1370
1371
1372
1373
1374 
               coregen
1375 
               ./
1376 
               ./tmp/
1377 
               ./tmp/_cg
1378
1379
1380 
               xc6vlx240t
1381 
               virtex6
1382 
               ff1156
1383 
               -1
1384
1385
1386 
               BusFormatAngleBracketNotRipped
1387 
               VHDL
1388 
               true
1389 
               Foundation_ISE
1390 
               false
1391 
               false
1392 
               false
1393 
               Ngc
1394 
               false
1395
1396
1397 
               Behavioral
1398 
               VHDL_and_Verilog
1399 
               false
1400
1401
1402
1403
1404
1405 
         v6_eb_fifo_counted_resized
1406
1407
1408
1409
1410 
            false
1411 
            false
1412 
            1024
1413 
            Native
1414 
            Full
1415 
            false
1416 
            1023
1417 
            Data_FIFO
1418 
            false
1419 
            Active_High
1420 
            Common_Clock_Block_RAM
1421 
            false
1422 
            false
1423 
            false
1424 
            true
1425 
            false
1426 
            false
1427 
            16
1428 
            Slave_Interface_Clock_Enable
1429 
            false
1430 
            false
1431 
            false
1432 
            28670
1433 
            false
1434 
            1
1435 
            1022
1436 
            false
1437 
            Empty
1438 
            4
1439 
            1
1440 
            4
1441 
            FIFO
1442 
            64
1443 
            false
1444 
            4097
1445 
            1023
1446 
            64
1447 
            64
1448 
            1024
1449 
            false
1450 
            Data_FIFO
1451 
            32768
1452 
            false
1453 
            4
1454 
            true
1455 
            1023
1456 
            false
1457 
            Single_Programmable_Empty_Threshold_Constant
1458 
            16
1459 
            false
1460 
            FIFO
1461 
            false
1462 
            false
1463 
            false
1464 
            1022
1465 
            false
1466 
            Independent_Clocks_Block_RAM
1467 
            false
1468 
            1
1469 
            false
1470 
            false
1471 
            false
1472 
            false
1473 
            1
1474 
            1022
1475 
            false
1476 
            Active_High
1477 
            15
1478 
            false
1479 
            false
1480 
            Full
1481 
            Common_Clock_Block_RAM
1482 
            1023
1483 
            false
1484 
            15
1485 
            4
1486 
            32
1487 
            1024
1488 
            false
1489 
            FIFO
1490 
            32768
1491 
            1023
1492 
            false
1493 
            0
1494 
            true
1495 
            true
1496 
            Active_High
1497 
            Active_High
1498 
            false
1499 
            Empty
1500 
            1022
1501 
            false
1502 
            false
1503 
            false
1504 
            false
1505 
            false
1506 
            true
1507 
            false
1508 
            1022
1509 
            Full
1510 
            false
1511 
            Data_FIFO
1512 
            Common_Clock_Block_RAM
1513 
            false
1514 
            Full
1515 
            false
1516 
            Common_Clock_Block_RAM
1517 
            1023
1518 
            FIFO
1519 
            1
1520 
            false
1521 
            false
1522 
            Single_Programmable_Full_Threshold_Constant
1523 
            false
1524 
            Empty
1525 
            15
1526 
            Common_Clock
1527 
            Asynchronous_Reset
1528 
            false
1529 
            Empty
1530 
            false
1531 
            1022
1532 
            FIFO
1533 
            false
1534 
            Data_FIFO
1535 
            false
1536 
            Full
1537 
            1
1538 
            Common_Clock_Block_RAM
1539 
            Standard_FIFO
1540 
            false
1541 
            false
1542 
            Data_FIFO
1543 
            true
1544 
            16
1545 
            false
1546 
            28671
1547 
            false
1548 
            Full
1549 
            FIFO
1550 
            false
1551 
            4
1552 
            false
1553 
            Common_Clock_Block_RAM
1554 
            false
1555 
            false
1556 
            false
1557 
            1
1558 
            Active_High
1559 
            false
1560 
            Empty
1561 
            false
1562 
            AXI4_Stream
1563 
            4096
1564 
            64
1565 
            1
1566 
            Empty
1567 
            true
1568 
            8
1569 
            Active_High
1570 
            Data_FIFO
1571 
            false
1572
1573
1574
1575
1576 
               coregen
1577 
               ./
1578 
               ./tmp/
1579 
               ./tmp/_cg
1580
1581
1582 
               xc6vlx240t
1583 
               virtex6
1584 
               ff1156
1585 
               -1
1586
1587
1588 
               BusFormatAngleBracketNotRipped
1589 
               VHDL
1590 
               true
1591 
               Foundation_ISE
1592 
               false
1593 
               false
1594 
               false
1595 
               Ngc
1596 
               false
1597
1598
1599 
               Structural
1600 
               VHDL
1601 
               false
1602
1603
1604
1605
1606
1607 
         v6_mBuf_128x72
1608
1609
1610
1611
1612 
            false
1613 
            false
1614 
            1024
1615 
            Native
1616 
            Full
1617 
            false
1618 
            1023
1619 
            Data_FIFO
1620 
            false
1621 
            Active_High
1622 
            Common_Clock_Block_RAM
1623 
            false
1624 
            false
1625 
            false
1626 
            false
1627 
            false
1628 
            false
1629 
            16
1630 
            Slave_Interface_Clock_Enable
1631 
            false
1632 
            false
1633 
            false
1634 
            127
1635 
            false
1636 
            1
1637 
            1022
1638 
            false
1639 
            Empty
1640 
            4
1641 
            1
1642 
            4
1643 
            FIFO
1644 
            64
1645 
            false
1646 
            3
1647 
            1023
1648 
            72
1649 
            64
1650 
            1024
1651 
            false
1652 
            Data_FIFO
1653 
            512
1654 
            false
1655 
            4
1656 
            false
1657 
            1023
1658 
            false
1659 
            No_Programmable_Empty_Threshold
1660 
            16
1661 
            false
1662 
            FIFO
1663 
            false
1664 
            false
1665 
            false
1666 
            1022
1667 
            false
1668 
            Common_Clock_Builtin_FIFO
1669 
            false
1670 
            1
1671 
            false
1672 
            false
1673 
            false
1674 
            false
1675 
            0
1676 
            1022
1677 
            false
1678 
            Active_High
1679 
            9
1680 
            false
1681 
            false
1682 
            Full
1683 
            Common_Clock_Block_RAM
1684 
            1023
1685 
            false
1686 
            9
1687 
            4
1688 
            32
1689 
            1024
1690 
            false
1691 
            FIFO
1692 
            512
1693 
            1023
1694 
            false
1695 
            0
1696 
            true
1697 
            true
1698 
            Active_High
1699 
            Active_High
1700 
            false
1701 
            Empty
1702 
            1022
1703 
            false
1704 
            false
1705 
            false
1706 
            false
1707 
            false
1708 
            false
1709 
            false
1710 
            1022
1711 
            Full
1712 
            false
1713 
            Data_FIFO
1714 
            Common_Clock_Block_RAM
1715 
            false
1716 
            Full
1717 
            false
1718 
            Common_Clock_Block_RAM
1719 
            1023
1720 
            FIFO
1721 
            1
1722 
            false
1723 
            false
1724 
            Single_Programmable_Full_Threshold_Constant
1725 
            false
1726 
            Empty
1727 
            9
1728 
            Common_Clock
1729 
            Asynchronous_Reset
1730 
            false
1731 
            Empty
1732 
            false
1733 
            1022
1734 
            FIFO
1735 
            false
1736 
            Data_FIFO
1737 
            false
1738 
            Full
1739 
            1
1740 
            Common_Clock_Block_RAM
1741 
            Standard_FIFO
1742 
            false
1743 
            false
1744 
            Data_FIFO
1745 
            false
1746 
            16
1747 
            false
1748 
            128
1749 
            false
1750 
            Full
1751 
            FIFO
1752 
            false
1753 
            4
1754 
            false
1755 
            Common_Clock_Block_RAM
1756 
            false
1757 
            false
1758 
            false
1759 
            1
1760 
            Active_High
1761 
            false
1762 
            Empty
1763 
            false
1764 
            AXI4_Stream
1765 
            2
1766 
            72
1767 
            1
1768 
            Empty
1769 
            true
1770 
            8
1771 
            Active_High
1772 
            Data_FIFO
1773 
            false
1774
1775
1776
1777
1778 
               coregen
1779 
               ./
1780 
               ./tmp/
1781 
               ./tmp/_cg
1782
1783
1784 
               xc6vlx240t
1785 
               virtex6
1786 
               ff1156
1787 
               -1
1788
1789
1790 
               BusFormatAngleBracketNotRipped
1791 
               VHDL
1792 
               true
1793 
               Foundation_ISE
1794 
               false
1795 
               false
1796 
               false
1797 
               Ngc
1798 
               false
1799
1800
1801 
               Behavioral
1802 
               VHDL_and_Verilog
1803 
               false
1804
1805
1806
1807
1808
1809 
         v6_pcie_v1_6
1810
1811
1812
1813
1814 
            High
1815 
            false
1816 
            false
1817 
            false
1818 
            Kilobytes
1819 
            Add
1820 
            false
1821 
            Memory
1822 
            Simple_communication_controllers
1823 
            1
1824 
            0
1825 
            0
1826 
            true
1827 
            false
1828 
            00
1829 
            Disabled
1830 
            0
1831 
            false
1832 
            false
1833 
            2
1834 
            false
1835 
            false
1836 
            false
1837 
            false
1838 
            false
1839 
            false
1840 
            false
1841 
            64
1842 
            false
1843 
            6014
1844 
            10EE
1845 
            No_limit
1846 
            1
1847 
            false
1848 
            X0Y0
1849 
            PCI_Express_Endpoint_device
1850 
            false
1851 
            0026
1852 
            true
1853 
            N/A
1854 
            true
1855 
            100_MHz
1856 
            05
1857 
            0
1858 
            ML_605
1859 
            3F
1860 
            2
1861 
            false
1862 
            0
1863 
            true
1864 
            false
1865 
            0
1866 
            4'h1
1867 
            false
1868 
            true
1869 
            0
1870 
            false
1871 
            1
1872 
            512_bytes
1873 
            true
1874 
            0
1875 
            125_default
1876 
            false
1877 
            N/A
1878 
            0
1879 
            false
1880 
            false
1881 
            Absolute
1882 
            false
1883 
            true
1884 
            0
1885 
            Kilobytes
1886 
            false
1887 
            false
1888 
            false
1889 
            false
1890 
            false
1891 
            false
1892 
            false
1893 
            Kilobytes
1894 
            0
1895 
            0
1896 
            false
1897 
            false
1898 
            false
1899 
            Kilobytes
1900 
            false
1901 
            true
1902 
            false
1903 
            4
1904 
            false
1905 
            false
1906 
            Range_B
1907 
            true
1908 
            Kilobytes
1909 
            ABB3
1910 
            N/A
1911 
            true
1912 
            false
1913 
            X4
1914 
            Megabytes
1915 
            0
1916 
            0
1917 
            false
1918 
            Memory
1919 
            0
1920 
            true
1921 
            false
1922 
            BAR_0
1923 
            Kilobytes
1924 
            false
1925 
            false
1926 
            false
1927 
            false
1928 
            0
1929 
            2.5_GT/s
1930 
            false
1931 
            false
1932 
            true
1933 
            false
1934 
            None
1935 
            None
1936 
            3FF
1937 
            false
1938 
            No_function_number_bits_used
1939 
            00
1940 
            2
1941 
            false
1942 
            false
1943 
            0
1944 
            false
1945 
            0
1946 
            INTA
1947 
            64_byte
1948 
            0
1949 
            false
1950 
            false
1951 
            Memory
1952 
            06
1953 
            false
1954 
            false
1955 
            1_vector
1956 
            BAR_0
1957 
            0
1958 
            0084
1959 
            0
1960 
            false
1961 
            0000
1962 
            false
1963 
            00
1964 
            00000000
1965 
            true
1966 
            true
1967 
            No_limit
1968 
            Disabled
1969 
            false
1970 
            Generic_XT_compatible_serial_controller
1971 
            0
1972 
            2
1973 
            false
1974
1975
1976
1977
1978 
               coregen
1979 
               ./
1980 
               ./tmp/
1981 
               ./tmp/_cg
1982
1983
1984 
               xc6vlx240t
1985 
               virtex6
1986 
               ff1156
1987 
               -1
1988
1989
1990 
               BusFormatAngleBracketNotRipped
1991 
               VHDL
1992 
               true
1993 
               Other
1994 
               false
1995 
               false
1996 
               false
1997 
               Ngc
1998 
               false
1999
2000
2001 
               Behavioral
2002 
               VHDL
2003 
               false
2004
2005
2006
2007
2008
2009 
         v6_pcie_v1_6_x1
2010
2011
2012
2013
2014 
            High
2015 
            false
2016 
            false
2017 
            false
2018 
            Kilobytes
2019 
            Add
2020 
            false
2021 
            Memory
2022 
            Simple_communication_controllers
2023 
            1
2024 
            0
2025 
            0
2026 
            true
2027 
            false
2028 
            00
2029 
            Disabled
2030 
            0
2031 
            false
2032 
            false
2033 
            2
2034 
            false
2035 
            false
2036 
            false
2037 
            false
2038 
            false
2039 
            false
2040 
            false
2041 
            64
2042 
            false
2043 
            6014
2044 
            10EE
2045 
            No_limit
2046 
            1
2047 
            false
2048 
            X0Y0
2049 
            PCI_Express_Endpoint_device
2050 
            false
2051 
            0026
2052 
            true
2053 
            N/A
2054 
            true
2055 
            100_MHz
2056 
            05
2057 
            0
2058 
            ML_605
2059 
            3F
2060 
            2
2061 
            false
2062 
            0
2063 
            true
2064 
            false
2065 
            0
2066 
            4'h2
2067 
            false
2068 
            true
2069 
            0
2070 
            false
2071 
            1
2072 
            512_bytes
2073 
            true
2074 
            0
2075 
            125
2076 
            false
2077 
            N/A
2078 
            0
2079 
            false
2080 
            false
2081 
            Absolute
2082 
            false
2083 
            true
2084 
            0
2085 
            Kilobytes
2086 
            false
2087 
            false
2088 
            false
2089 
            false
2090 
            false
2091 
            false
2092 
            false
2093 
            Kilobytes
2094 
            0
2095 
            0
2096 
            false
2097 
            false
2098 
            false
2099 
            Kilobytes
2100 
            false
2101 
            true
2102 
            false
2103 
            4
2104 
            false
2105 
            false
2106 
            Range_B
2107 
            true
2108 
            Kilobytes
2109 
            ABB3
2110 
            N/A
2111 
            true
2112 
            false
2113 
            X1
2114 
            Megabytes
2115 
            0
2116 
            0
2117 
            false
2118 
            Memory
2119 
            0
2120 
            true
2121 
            false
2122 
            BAR_0
2123 
            Kilobytes
2124 
            false
2125 
            false
2126 
            false
2127 
            false
2128 
            0
2129 
            5.0_GT/s
2130 
            false
2131 
            false
2132 
            true
2133 
            false
2134 
            None
2135 
            None
2136 
            3FF
2137 
            false
2138 
            No_function_number_bits_used
2139 
            00
2140 
            2
2141 
            false
2142 
            false
2143 
            0
2144 
            false
2145 
            0
2146 
            INTA
2147 
            64_byte
2148 
            0
2149 
            false
2150 
            false
2151 
            Memory
2152 
            06
2153 
            false
2154 
            false
2155 
            1_vector
2156 
            BAR_0
2157 
            0
2158 
            0084
2159 
            0
2160 
            false
2161 
            0000
2162 
            false
2163 
            00
2164 
            00000000
2165 
            true
2166 
            true
2167 
            No_limit
2168 
            Disabled
2169 
            false
2170 
            Generic_XT_compatible_serial_controller
2171 
            0
2172 
            2
2173 
            false
2174
2175
2176
2177
2178 
               coregen
2179 
               ./
2180 
               ./tmp/
2181 
               ./tmp/_cg
2182
2183
2184 
               xc6vlx240t
2185 
               virtex6
2186 
               ff1156
2187 
               -1
2188
2189
2190 
               BusFormatAngleBracketNotRipped
2191 
               VHDL
2192 
               true
2193 
               Other
2194 
               false
2195 
               false
2196 
               false
2197 
               Ngc
2198 
               false
2199
2200
2201 
               Behavioral
2202 
               VHDL
2203 
               false
2204
2205
2206
2207
2208
2209 
         v6_pcie_v1_6_x8_Test
2210
2211
2212
2213
2214 
            High
2215 
            false
2216 
            false
2217 
            false
2218 
            Kilobytes
2219 
            Add
2220 
            false
2221 
            Memory
2222 
            Simple_communication_controllers
2223 
            1
2224 
            0
2225 
            0
2226 
            true
2227 
            false
2228 
            00
2229 
            Disabled
2230 
            0
2231 
            false
2232 
            false
2233 
            2
2234 
            false
2235 
            false
2236 
            false
2237 
            false
2238 
            false
2239 
            false
2240 
            false
2241 
            64
2242 
            false
2243 
            6014
2244 
            10EE
2245 
            No_limit
2246 
            1
2247 
            false
2248 
            X0Y0
2249 
            PCI_Express_Endpoint_device
2250 
            false
2251 
            0026
2252 
            true
2253 
            N/A
2254 
            true
2255 
            100_MHz
2256 
            05
2257 
            0
2258 
            ML_605
2259 
            3F
2260 
            2
2261 
            false
2262 
            0
2263 
            true
2264 
            false
2265 
            0
2266 
            4'h1
2267 
            false
2268 
            true
2269 
            0
2270 
            false
2271 
            1
2272 
            512_bytes
2273 
            true
2274 
            0
2275 
            250_default
2276 
            false
2277 
            N/A
2278 
            0
2279 
            false
2280 
            false
2281 
            Absolute
2282 
            false
2283 
            true
2284 
            0
2285 
            Kilobytes
2286 
            false
2287 
            false
2288 
            false
2289 
            false
2290 
            false
2291 
            false
2292 
            false
2293 
            Kilobytes
2294 
            0
2295 
            0
2296 
            false
2297 
            false
2298 
            false
2299 
            Kilobytes
2300 
            false
2301 
            true
2302 
            false
2303 
            4
2304 
            false
2305 
            false
2306 
            Range_B
2307 
            true
2308 
            Kilobytes
2309 
            ABB3
2310 
            N/A
2311 
            false
2312 
            false
2313 
            X8
2314 
            Megabytes
2315 
            0
2316 
            0
2317 
            false
2318 
            Memory
2319 
            0
2320 
            true
2321 
            false
2322 
            BAR_0
2323 
            Kilobytes
2324 
            false
2325 
            false
2326 
            false
2327 
            false
2328 
            0
2329 
            2.5_GT/s
2330 
            false
2331 
            false
2332 
            true
2333 
            false
2334 
            None
2335 
            None
2336 
            3FF
2337 
            false
2338 
            No_function_number_bits_used
2339 
            00
2340 
            2
2341 
            false
2342 
            false
2343 
            0
2344 
            false
2345 
            0
2346 
            INTA
2347 
            64_byte
2348 
            0
2349 
            false
2350 
            false
2351 
            N/A
2352 
            06
2353 
            false
2354 
            false
2355 
            1_vector
2356 
            BAR_0
2357 
            0
2358 
            0084
2359 
            0
2360 
            false
2361 
            0000
2362 
            false
2363 
            00
2364 
            00000000
2365 
            true
2366 
            true
2367 
            No_limit
2368 
            Disabled
2369 
            false
2370 
            Generic_XT_compatible_serial_controller
2371 
            0
2372 
            2
2373 
            false
2374
2375
2376
2377
2378 
               coregen
2379 
               ./
2380 
               ./tmp/
2381 
               ./tmp/_cg
2382
2383
2384 
               xc6vlx240t
2385 
               virtex6
2386 
               ff1156
2387 
               -1
2388
2389
2390 
               BusFormatAngleBracketNotRipped
2391 
               VHDL
2392 
               true
2393 
               Other
2394 
               false
2395 
               false
2396 
               false
2397 
               Ngc
2398 
               false
2399
2400
2401 
               Behavioral
2402 
               VHDL
2403 
               false
2404
2405
2406
2407
2408 
                  customization_generator
2409
2410
2411 
                  ip_xco_generator
2412
2413 
                     ./v6_pcie_v1_6_x8_Test.xco
2414 
                     xco
2415 
                     Thu Mar 22 11:50:52 GMT 2012
2416 
                     0xA1157B5C
2417
2418
2419
2420 
                  implementation_netlist_generator
2421
2422 
                     ./v6_pcie_v1_6_x8_Test/doc/v6_pcie_ds715.pdf
2423 
                     ignore
2424 
                     pdf
2425 
                     Thu Mar 22 11:51:02 GMT 2012
2426 
                     0xF4EE6874
2427
2428
2429 
                     ./v6_pcie_v1_6_x8_Test/doc/v6_pcie_ug517.pdf
2430 
                     ignore
2431 
                     pdf
2432 
                     Thu Mar 22 11:51:02 GMT 2012
2433 
                     0x984EF007
2434
2435
2436 
                     ./v6_pcie_v1_6_x8_Test/example_design/EP_MEM.vhd
2437 
                     ignore
2438 
                     vhdl
2439 
                     Thu Mar 22 11:51:08 GMT 2012
2440 
                     0xA1D76CC7
2441
2442
2443 
                     ./v6_pcie_v1_6_x8_Test/example_design/PIO.vhd
2444 
                     ignore
2445 
                     vhdl
2446 
                     Thu Mar 22 11:51:08 GMT 2012
2447 
                     0x0BB183C7
2448
2449
2450 
                     ./v6_pcie_v1_6_x8_Test/example_design/PIO_EP.vhd
2451 
                     ignore
2452 
                     vhdl
2453 
                     Thu Mar 22 11:51:08 GMT 2012
2454 
                     0xF000AE99
2455
2456
2457 
                     ./v6_pcie_v1_6_x8_Test/example_design/PIO_EP_MEM_ACCESS.vhd
2458 
                     ignore
2459 
                     vhdl
2460 
                     Thu Mar 22 11:51:08 GMT 2012
2461 
                     0x5B487E72
2462
2463
2464 
                     ./v6_pcie_v1_6_x8_Test/example_design/PIO_RX_ENGINE.vhd
2465 
                     ignore
2466 
                     vhdl
2467 
                     Thu Mar 22 11:51:08 GMT 2012
2468 
                     0x557C9B6D
2469
2470
2471 
                     ./v6_pcie_v1_6_x8_Test/example_design/PIO_TO_CTRL.vhd
2472 
                     ignore
2473 
                     vhdl
2474 
                     Thu Mar 22 11:51:08 GMT 2012
2475 
                     0x7EAAA9F6
2476
2477
2478 
                     ./v6_pcie_v1_6_x8_Test/example_design/PIO_TX_ENGINE.vhd
2479 
                     ignore
2480 
                     vhdl
2481 
                     Thu Mar 22 11:51:08 GMT 2012
2482 
                     0x6E91E6D6
2483
2484
2485 
                     ./v6_pcie_v1_6_x8_Test/example_design/pci_exp_8_lane_64b_ep.v
2486 
                     ignore
2487 
                     verilog
2488 
                     Thu Mar 22 11:51:02 GMT 2012
2489 
                     0x84EAEFBF
2490
2491
2492 
                     ./v6_pcie_v1_6_x8_Test/example_design/pcie_app_v6.vhd
2493 
                     ignore
2494 
                     vhdl
2495 
                     Thu Mar 22 11:51:08 GMT 2012
2496 
                     0x35A09E64
2497
2498
2499 
                     ./v6_pcie_v1_6_x8_Test/example_design/xilinx_pcie_2_0_ep_v6.vhd
2500 
                     ignore
2501 
                     vhdl
2502 
                     Thu Mar 22 11:51:09 GMT 2012
2503 
                     0xCA87424A
2504
2505
2506 
                     ./v6_pcie_v1_6_x8_Test/example_design/xilinx_pcie_2_0_ep_v6_08_lane_gen1_xc6vlx240t-ff1156-1_ML605.ucf
2507 
                     ucf
2508 
                     Thu Mar 22 11:51:03 GMT 2012
2509 
                     0xCE6F32A5
2510
2511
2512 
                     ./v6_pcie_v1_6_x8_Test/implement/implement.bat
2513 
                     ignore
2514 
                     unknown
2515 
                     Thu Mar 22 11:51:02 GMT 2012
2516 
                     0x8B846784
2517
2518
2519 
                     ./v6_pcie_v1_6_x8_Test/implement/implement.sh
2520 
                     ignore
2521 
                     unknown
2522 
                     Thu Mar 22 11:51:02 GMT 2012
2523 
                     0x9E029F87
2524
2525
2526 
                     ./v6_pcie_v1_6_x8_Test/implement/xilinx_pcie_2_0_ep_v6.cmd
2527 
                     ignore
2528 
                     unknown
2529 
                     Thu Mar 22 11:51:02 GMT 2012
2530 
                     0x851E5BDE
2531
2532
2533 
                     ./v6_pcie_v1_6_x8_Test/implement/xilinx_pcie_2_0_ep_v6.prj
2534 
                     ignore
2535 
                     unknown
2536 
                     Thu Mar 22 11:51:09 GMT 2012
2537 
                     0xD05F5535
2538
2539
2540 
                     ./v6_pcie_v1_6_x8_Test/implement/xilinx_pcie_2_0_ep_v6.xcf
2541 
                     ignore
2542 
                     unknown
2543 
                     Thu Mar 22 11:51:02 GMT 2012
2544 
                     0x7B0051D4
2545
2546
2547 
                     ./v6_pcie_v1_6_x8_Test/simulation/dsport/pci_exp_usrapp_cfg.vhd
2548 
                     ignore
2549 
                     vhdl
2550 
                     Thu Mar 22 11:51:08 GMT 2012
2551 
                     0xC6431C8B
2552
2553
2554 
                     ./v6_pcie_v1_6_x8_Test/simulation/dsport/pci_exp_usrapp_pl.vhd
2555 
                     ignore
2556 
                     vhdl
2557 
                     Thu Mar 22 11:51:08 GMT 2012
2558 
                     0xAA0A7C2D
2559
2560
2561 
                     ./v6_pcie_v1_6_x8_Test/simulation/dsport/pci_exp_usrapp_rx.vhd
2562 
                     ignore
2563 
                     vhdl
2564 
                     Thu Mar 22 11:51:08 GMT 2012
2565 
                     0xF58BB5BF
2566
2567
2568 
                     ./v6_pcie_v1_6_x8_Test/simulation/dsport/pci_exp_usrapp_tx.vhd
2569 
                     ignore
2570 
                     vhdl
2571 
                     Thu Mar 22 11:51:08 GMT 2012
2572 
                     0x00163DE3
2573
2574
2575 
                     ./v6_pcie_v1_6_x8_Test/simulation/dsport/pcie_2_0_rport_v6.vhd
2576 
                     ignore
2577 
                     vhdl
2578 
                     Thu Mar 22 11:51:07 GMT 2012
2579 
                     0xC56B2339
2580
2581
2582 
                     ./v6_pcie_v1_6_x8_Test/simulation/dsport/pcie_2_0_v6_rp.vhd
2583 
                     ignore
2584 
                     vhdl
2585 
                     Thu Mar 22 11:51:06 GMT 2012
2586 
                     0xA6A0E729
2587
2588
2589 
                     ./v6_pcie_v1_6_x8_Test/simulation/dsport/test_interface.vhd
2590 
                     ignore
2591 
                     vhdl
2592 
                     Thu Mar 22 11:51:08 GMT 2012
2593 
                     0x6E91CB07
2594
2595
2596 
                     ./v6_pcie_v1_6_x8_Test/simulation/dsport/xilinx_pcie_2_0_rport_v6.vhd
2597 
                     ignore
2598 
                     vhdl
2599 
                     Thu Mar 22 11:51:09 GMT 2012
2600 
                     0xB301A6D8
2601
2602
2603 
                     ./v6_pcie_v1_6_x8_Test/simulation/functional/board.f
2604 
                     ignore
2605 
                     unknown
2606 
                     Thu Mar 22 11:51:09 GMT 2012
2607 
                     0x024EA5B0
2608
2609
2610 
                     ./v6_pcie_v1_6_x8_Test/simulation/functional/board.vhd
2611 
                     ignore
2612 
                     vhdl
2613 
                     Thu Mar 22 11:51:08 GMT 2012
2614 
                     0xDD4CDB97
2615
2616
2617 
                     ./v6_pcie_v1_6_x8_Test/simulation/functional/isim_cmd.tcl
2618 
                     ignore
2619 
                     tcl
2620 
                     Thu Mar 22 11:51:03 GMT 2012
2621 
                     0x31029C51
2622
2623
2624 
                     ./v6_pcie_v1_6_x8_Test/simulation/functional/simulate_isim.bat
2625 
                     ignore
2626 
                     unknown
2627 
                     Thu Mar 22 11:51:02 GMT 2012
2628 
                     0x7EA19B23
2629
2630
2631 
                     ./v6_pcie_v1_6_x8_Test/simulation/functional/simulate_isim.sh
2632 
                     ignore
2633 
                     unknown
2634 
                     Thu Mar 22 11:51:02 GMT 2012
2635 
                     0x5A6F0B3A
2636
2637
2638 
                     ./v6_pcie_v1_6_x8_Test/simulation/functional/simulate_mti.do
2639 
                     ignore
2640 
                     unknown
2641 
                     Thu Mar 22 11:51:09 GMT 2012
2642 
                     0x35A83905
2643
2644
2645 
                     ./v6_pcie_v1_6_x8_Test/simulation/functional/simulate_ncsim.sh
2646 
                     ignore
2647 
                     unknown
2648 
                     Thu Mar 22 11:51:09 GMT 2012
2649 
                     0x7055C75B
2650
2651
2652 
                     ./v6_pcie_v1_6_x8_Test/simulation/functional/sys_clk_gen.vhd
2653 
                     ignore
2654 
                     vhdl
2655 
                     Thu Mar 22 11:51:08 GMT 2012
2656 
                     0x5B6B3399
2657
2658
2659 
                     ./v6_pcie_v1_6_x8_Test/simulation/functional/sys_clk_gen_ds.vhd
2660 
                     ignore
2661 
                     vhdl
2662 
                     Thu Mar 22 11:51:08 GMT 2012
2663 
                     0x8AE0FB1D
2664
2665
2666 
                     ./v6_pcie_v1_6_x8_Test/simulation/functional/wave.wcfg
2667 
                     ignore
2668 
                     unknown
2669 
                     Thu Mar 22 11:51:03 GMT 2012
2670 
                     0x2AD07F5B
2671
2672
2673 
                     ./v6_pcie_v1_6_x8_Test/simulation/tests/tests.vhd
2674 
                     ignore
2675 
                     vhdl
2676 
                     Thu Mar 22 11:51:08 GMT 2012
2677 
                     0x087885B5
2678
2679
2680 
                     ./v6_pcie_v1_6_x8_Test/source/gtx_drp_chanalign_fix_3752_v6.vhd
2681 
                     ignore
2682 
                     vhdl
2683 
                     Thu Mar 22 11:51:05 GMT 2012
2684 
                     0x7C3BA33E
2685
2686
2687 
                     ./v6_pcie_v1_6_x8_Test/source/gtx_rx_valid_filter_v6.vhd
2688 
                     vhdl
2689 
                     Thu Mar 22 11:51:05 GMT 2012
2690 
                     0x347665BB
2691
2692
2693 
                     ./v6_pcie_v1_6_x8_Test/source/gtx_tx_sync_rate_v6.vhd
2694 
                     vhdl
2695 
                     Thu Mar 22 11:51:05 GMT 2012
2696 
                     0x33654F81
2697
2698
2699 
                     ./v6_pcie_v1_6_x8_Test/source/gtx_wrapper_v6.vhd
2700 
                     vhdl
2701 
                     Thu Mar 22 11:51:05 GMT 2012
2702 
                     0x1CAC2731
2703
2704
2705 
                     ./v6_pcie_v1_6_x8_Test/source/pcie_2_0_v6.vhd
2706 
                     vhdl
2707 
                     Thu Mar 22 11:51:06 GMT 2012
2708 
                     0xBFDDB110
2709
2710
2711 
                     ./v6_pcie_v1_6_x8_Test/source/pcie_bram_top_v6.vhd
2712 
                     vhdl
2713 
                     Thu Mar 22 11:51:06 GMT 2012
2714 
                     0x421E4E85
2715
2716
2717 
                     ./v6_pcie_v1_6_x8_Test/source/pcie_bram_v6.vhd
2718 
                     vhdl
2719 
                     Thu Mar 22 11:51:05 GMT 2012
2720 
                     0x15441E81
2721
2722
2723 
                     ./v6_pcie_v1_6_x8_Test/source/pcie_brams_v6.vhd
2724 
                     vhdl
2725 
                     Thu Mar 22 11:51:05 GMT 2012
2726 
                     0x629C7221
2727
2728
2729 
                     ./v6_pcie_v1_6_x8_Test/source/pcie_clocking_v6.vhd
2730 
                     vhdl
2731 
                     Thu Mar 22 11:51:06 GMT 2012
2732 
                     0x35D300CC
2733
2734
2735 
                     ./v6_pcie_v1_6_x8_Test/source/pcie_gtx_v6.vhd
2736 
                     vhdl
2737 
                     Thu Mar 22 11:51:06 GMT 2012
2738 
                     0x0936E0F0
2739
2740
2741 
                     ./v6_pcie_v1_6_x8_Test/source/pcie_pipe_lane_v6.vhd
2742 
                     vhdl
2743 
                     Thu Mar 22 11:51:05 GMT 2012
2744 
                     0xB2D30D12
2745
2746
2747 
                     ./v6_pcie_v1_6_x8_Test/source/pcie_pipe_misc_v6.vhd
2748 
                     vhdl
2749 
                     Thu Mar 22 11:51:05 GMT 2012
2750 
                     0xB1660DC5
2751
2752
2753 
                     ./v6_pcie_v1_6_x8_Test/source/pcie_pipe_v6.vhd
2754 
                     vhdl
2755 
                     Thu Mar 22 11:51:06 GMT 2012
2756 
                     0x5163157C
2757
2758
2759 
                     ./v6_pcie_v1_6_x8_Test/source/pcie_reset_delay_v6.vhd
2760 
                     vhdl
2761 
                     Thu Mar 22 11:51:06 GMT 2012
2762 
                     0x5D5ECFF8
2763
2764
2765 
                     ./v6_pcie_v1_6_x8_Test/source/pcie_upconfig_fix_3451_v6.vhd
2766 
                     vhdl
2767 
                     Thu Mar 22 11:51:06 GMT 2012
2768 
                     0x8A83D211
2769
2770
2771 
                     ./v6_pcie_v1_6_x8_Test/source/v6_pcie_v1_6_x8_Test.vhd
2772 
                     vhdl
2773 
                     Thu Mar 22 11:51:07 GMT 2012
2774 
                     0xB2AF77C3
2775
2776
2777 
                     ./v6_pcie_v1_6_x8_Test/v6_pcie_readme.txt
2778 
                     ignore
2779 
                     txt
2780 
                     Thu Mar 22 11:51:02 GMT 2012
2781 
                     0xEF2CE7BC
2782
2783
2784 
                     ./v6_pcie_v1_6_x8_Test.vho
2785 
                     vho
2786 
                     Thu Mar 22 11:51:09 GMT 2012
2787 
                     0xF43461D2
2788
2789
2790 
                     ./v6_pcie_v1_6_x8_Test_xmdf.tcl
2791 
                     tcl
2792 
                     Thu Mar 22 11:51:02 GMT 2012
2793 
                     0x5EDCD2DB
2794
2795
2796
2797 
                  instantiation_template_generator
2798
2799 
                     ./v6_pcie_v1_6_x8_Test.vho
2800 
                     vho
2801 
                     Thu Mar 22 11:51:22 GMT 2012
2802 
                     0xF43461D2
2803
2804
2805
2806 
                  xco_generator
2807
2808 
                     ./v6_pcie_v1_6_x8_Test.xco
2809 
                     xco
2810 
                     Thu Mar 22 11:51:28 GMT 2012
2811 
                     0x4E61A4BB
2812
2813
2814
2815 
                  xmdf_generator
2816
2817
2818 
                  ise_generator
2819
2820 
                     ./_xmsgs/pn_parser.xmsgs
2821 
                     ignore
2822 
                     unknown
2823 
                     Thu Mar 22 11:52:04 GMT 2012
2824 
                     0x02C55629
2825
2826
2827 
                     ./v6_pcie_v1_6_x8_Test.gise
2828 
                     ignore
2829 
                     gise
2830 
                     Thu Mar 22 11:52:05 GMT 2012
2831 
                     0x83A35ACB
2832
2833
2834 
                     ./v6_pcie_v1_6_x8_Test.xise
2835 
                     ignore
2836 
                     xise
2837 
                     Thu Mar 22 11:52:05 GMT 2012
2838 
                     0x6F0D805D
2839
2840
2841
2842 
                  deliver_readme_generator
2843
2844
2845 
                  flist_generator
2846
2847 
                     ./v6_pcie_v1_6_x8_Test_flist.txt
2848 
                     ignore
2849 
                     txtFlist
2850 
                     txt
2851 
                     Thu Mar 22 11:52:09 GMT 2012
2852 
                     0x7FCCFA9D
2853
2854
2855
2856 
                  view_readme_generator
2857
2858
2859
2860
2861
2862 
         v6_pkt_counter_1024
2863
2864
2865
2866
2867 
            false
2868 
            false
2869 
            1024
2870 
            Native
2871 
            Full
2872 
            false
2873 
            1023
2874 
            Data_FIFO
2875 
            false
2876 
            Active_High
2877 
            Common_Clock_Block_RAM
2878 
            false
2879 
            false
2880 
            false
2881 
            false
2882 
            false
2883 
            false
2884 
            16
2885 
            Slave_Interface_Clock_Enable
2886 
            false
2887 
            false
2888 
            false
2889 
            1015
2890 
            false
2891 
            1
2892 
            1022
2893 
            false
2894 
            Empty
2895 
            4
2896 
            1
2897 
            4
2898 
            FIFO
2899 
            64
2900 
            false
2901 
            3
2902 
            1023
2903 
            1
2904 
            64
2905 
            1024
2906 
            false
2907 
            Data_FIFO
2908 
            1024
2909 
            false
2910 
            4
2911 
            false
2912 
            1023
2913 
            false
2914 
            Single_Programmable_Empty_Threshold_Constant
2915 
            16
2916 
            false
2917 
            FIFO
2918 
            false
2919 
            false
2920 
            false
2921 
            1022
2922 
            false
2923 
            Independent_Clocks_Distributed_RAM
2924 
            false
2925 
            1
2926 
            false
2927 
            false
2928 
            false
2929 
            false
2930 
            1
2931 
            1022
2932 
            false
2933 
            Active_High
2934 
            10
2935 
            false
2936 
            false
2937 
            Full
2938 
            Common_Clock_Block_RAM
2939 
            1023
2940 
            false
2941 
            10
2942 
            4
2943 
            32
2944 
            1024
2945 
            false
2946 
            FIFO
2947 
            1024
2948 
            1023
2949 
            false
2950 
            0
2951 
            true
2952 
            true
2953 
            Active_High
2954 
            Active_High
2955 
            false
2956 
            Empty
2957 
            1022
2958 
            false
2959 
            false
2960 
            false
2961 
            false
2962 
            false
2963 
            false
2964 
            false
2965 
            1022
2966 
            Full
2967 
            false
2968 
            Data_FIFO
2969 
            Common_Clock_Block_RAM
2970 
            false
2971 
            Full
2972 
            false
2973 
            Common_Clock_Block_RAM
2974 
            1023
2975 
            FIFO
2976 
            1
2977 
            false
2978 
            false
2979 
            Single_Programmable_Full_Threshold_Constant
2980 
            false
2981 
            Empty
2982 
            10
2983 
            Common_Clock
2984 
            Asynchronous_Reset
2985 
            false
2986 
            Empty
2987 
            false
2988 
            1022
2989 
            FIFO
2990 
            false
2991 
            Data_FIFO
2992 
            false
2993 
            Full
2994 
            1
2995 
            Common_Clock_Block_RAM
2996 
            Standard_FIFO
2997 
            false
2998 
            false
2999 
            Data_FIFO
3000 
            true
3001 
            16
3002 
            false
3003 
            1016
3004 
            false
3005 
            Full
3006 
            FIFO
3007 
            false
3008 
            4
3009 
            false
3010 
            Common_Clock_Block_RAM
3011 
            false
3012 
            false
3013 
            false
3014 
            1
3015 
            Active_High
3016 
            false
3017 
            Empty
3018 
            false
3019 
            AXI4_Stream
3020 
            2
3021 
            1
3022 
            1
3023 
            Empty
3024 
            true
3025 
            8
3026 
            Active_High
3027 
            Data_FIFO
3028 
            false
3029
3030
3031
3032
3033 
               coregen
3034 
               ./
3035 
               ./tmp/
3036 
               ./tmp/_cg
3037
3038
3039 
               xc6vlx240t
3040 
               virtex6
3041 
               ff1156
3042 
               -1
3043
3044
3045 
               BusFormatAngleBracketNotRipped
3046 
               VHDL
3047 
               true
3048 
               Foundation_ISE
3049 
               false
3050 
               false
3051 
               false
3052 
               Ngc
3053 
               false
3054
3055
3056 
               Behavioral
3057 
               VHDL_and_Verilog
3058 
               false
3059
3060
3061
3062
3063
3064 
         v6_prime_fifo_plain
3065
3066
3067
3068
3069 
            false
3070 
            false
3071 
            1024
3072 
            Native
3073 
            Full
3074 
            false
3075 
            1023
3076 
            Data_FIFO
3077 
            false
3078 
            Active_High
3079 
            Common_Clock_Block_RAM
3080 
            false
3081 
            false
3082 
            false
3083 
            false
3084 
            false
3085 
            false
3086 
            16
3087 
            Slave_Interface_Clock_Enable
3088 
            false
3089 
            false
3090 
            false
3091 
            495
3092 
            false
3093 
            1
3094 
            1022
3095 
            false
3096 
            Empty
3097 
            4
3098 
            1
3099 
            4
3100 
            FIFO
3101 
            64
3102 
            false
3103 
            6
3104 
            1023
3105 
            72
3106 
            64
3107 
            1024
3108 
            false
3109 
            Data_FIFO
3110 
            512
3111 
            false
3112 
            4
3113 
            false
3114 
            1023
3115 
            false
3116 
            No_Programmable_Empty_Threshold
3117 
            16
3118 
            false
3119 
            FIFO
3120 
            false
3121 
            false
3122 
            false
3123 
            1022
3124 
            false
3125 
            Independent_Clocks_Builtin_FIFO
3126 
            false
3127 
            1
3128 
            false
3129 
            false
3130 
            false
3131 
            false
3132 
            0
3133 
            1022
3134 
            false
3135 
            Active_High
3136 
            9
3137 
            false
3138 
            false
3139 
            Full
3140 
            Common_Clock_Block_RAM
3141 
            1023
3142 
            false
3143 
            9
3144 
            4
3145 
            32
3146 
            1024
3147 
            false
3148 
            FIFO
3149 
            512
3150 
            1023
3151 
            false
3152 
            0
3153 
            true
3154 
            true
3155 
            Active_High
3156 
            Active_High
3157 
            false
3158 
            Empty
3159 
            1022
3160 
            false
3161 
            false
3162 
            false
3163 
            false
3164 
            false
3165 
            false
3166 
            false
3167 
            1022
3168 
            Full
3169 
            false
3170 
            Data_FIFO
3171 
            Common_Clock_Block_RAM
3172 
            false
3173 
            Full
3174 
            false
3175 
            Common_Clock_Block_RAM
3176 
            1023
3177 
            FIFO
3178 
            1
3179 
            false
3180 
            false
3181 
            Single_Programmable_Full_Threshold_Constant
3182 
            false
3183 
            Empty
3184 
            9
3185 
            Common_Clock
3186 
            Asynchronous_Reset
3187 
            false
3188 
            Empty
3189 
            false
3190 
            1022
3191 
            FIFO
3192 
            false
3193 
            Data_FIFO
3194 
            false
3195 
            Full
3196 
            1
3197 
            Common_Clock_Block_RAM
3198 
            Standard_FIFO
3199 
            false
3200 
            false
3201 
            Data_FIFO
3202 
            false
3203 
            16
3204 
            false
3205 
            496
3206 
            false
3207 
            Full
3208 
            FIFO
3209 
            false
3210 
            4
3211 
            false
3212 
            Common_Clock_Block_RAM
3213 
            false
3214 
            false
3215 
            false
3216 
            125
3217 
            Active_High
3218 
            false
3219 
            Empty
3220 
            false
3221 
            AXI4_Stream
3222 
            5
3223 
            72
3224 
            125
3225 
            Empty
3226 
            true
3227 
            8
3228 
            Active_High
3229 
            Data_FIFO
3230 
            false
3231
3232
3233
3234
3235 
               coregen
3236 
               ./
3237 
               ./tmp/
3238 
               ./tmp/_cg
3239
3240
3241 
               xc6vlx240t
3242 
               virtex6
3243 
               ff1156
3244 
               -1
3245
3246
3247 
               BusFormatAngleBracketNotRipped
3248 
               VHDL
3249 
               true
3250 
               Foundation_ISE
3251 
               false
3252 
               false
3253 
               false
3254 
               Ngc
3255 
               false
3256
3257
3258 
               Behavioral
3259 
               VHDL_and_Verilog
3260 
               false
3261
3262
3263
3264
3265
3266 
         v6_sfifo_15x128
3267
3268
3269
3270
3271 
            false
3272 
            false
3273 
            1024
3274 
            Native
3275 
            Full
3276 
            false
3277 
            1023
3278 
            Data_FIFO
3279 
            false
3280 
            Active_High
3281 
            Common_Clock_Block_RAM
3282 
            false
3283 
            false
3284 
            false
3285 
            false
3286 
            false
3287 
            false
3288 
            16
3289 
            Slave_Interface_Clock_Enable
3290 
            false
3291 
            false
3292 
            false
3293 
            11
3294 
            false
3295 
            1
3296 
            1022
3297 
            false
3298 
            Empty
3299 
            4
3300 
            1
3301 
            4
3302 
            FIFO
3303 
            64
3304 
            false
3305 
            3
3306 
            1023
3307 
            128
3308 
            64
3309 
            1024
3310 
            false
3311 
            Data_FIFO
3312 
            16
3313 
            false
3314 
            4
3315 
            false
3316 
            1023
3317 
            false
3318 
            Single_Programmable_Empty_Threshold_Constant
3319 
            16
3320 
            false
3321 
            FIFO
3322 
            false
3323 
            false
3324 
            false
3325 
            1022
3326 
            false
3327 
            Common_Clock_Shift_Register
3328 
            false
3329 
            1
3330 
            false
3331 
            false
3332 
            false
3333 
            false
3334 
            1
3335 
            1022
3336 
            false
3337 
            Active_High
3338 
            4
3339 
            false
3340 
            false
3341 
            Full
3342 
            Common_Clock_Block_RAM
3343 
            1023
3344 
            false
3345 
            4
3346 
            4
3347 
            32
3348 
            1024
3349 
            false
3350 
            FIFO
3351 
            16
3352 
            1023
3353 
            false
3354 
            0
3355 
            true
3356 
            true
3357 
            Active_High
3358 
            Active_High
3359 
            false
3360 
            Empty
3361 
            1022
3362 
            false
3363 
            false
3364 
            false
3365 
            false
3366 
            false
3367 
            false
3368 
            false
3369 
            1022
3370 
            Full
3371 
            false
3372 
            Data_FIFO
3373 
            Common_Clock_Block_RAM
3374 
            false
3375 
            Full
3376 
            false
3377 
            Common_Clock_Block_RAM
3378 
            1023
3379 
            FIFO
3380 
            1
3381 
            false
3382 
            false
3383 
            Single_Programmable_Full_Threshold_Constant
3384 
            false
3385 
            Empty
3386 
            4
3387 
            Common_Clock
3388 
            Asynchronous_Reset
3389 
            false
3390 
            Empty
3391 
            false
3392 
            1022
3393 
            FIFO
3394 
            false
3395 
            Data_FIFO
3396 
            false
3397 
            Full
3398 
            1
3399 
            Common_Clock_Block_RAM
3400 
            Standard_FIFO
3401 
            false
3402 
            false
3403 
            Data_FIFO
3404 
            true
3405 
            16
3406 
            false
3407 
            12
3408 
            false
3409 
            Full
3410 
            FIFO
3411 
            false
3412 
            4
3413 
            false
3414 
            Common_Clock_Block_RAM
3415 
            false
3416 
            false
3417 
            false
3418 
            1
3419 
            Active_High
3420 
            false
3421 
            Empty
3422 
            false
3423 
            AXI4_Stream
3424 
            2
3425 
            128
3426 
            1
3427 
            Empty
3428 
            true
3429 
            8
3430 
            Active_High
3431 
            Data_FIFO
3432 
            false
3433
3434
3435
3436
3437 
               coregen
3438 
               ./
3439 
               ./tmp/
3440 
               ./tmp/_cg
3441
3442
3443 
               xc6vlx240t
3444 
               virtex6
3445 
               ff1156
3446 
               -1
3447
3448
3449 
               BusFormatAngleBracketNotRipped
3450 
               VHDL
3451 
               true
3452 
               Foundation_ISE
3453 
               false
3454 
               false
3455 
               false
3456 
               Ngc
3457 
               false
3458
3459
3460 
               Behavioral
3461 
               VHDL_and_Verilog
3462 
               false
3463
3464
3465
3466
3467
3468 
         v6_pcie_v1_6_x8
3469
3470
3471
3472
3473 
            High
3474 
            false
3475 
            false
3476 
            false
3477 
            Kilobytes
3478 
            Add
3479 
            false
3480 
            Memory
3481 
            Simple_communication_controllers
3482 
            1
3483 
            0
3484 
            0
3485 
            true
3486 
            false
3487 
            00
3488 
            Disabled
3489 
            0
3490 
            false
3491 
            false
3492 
            2
3493 
            false
3494 
            false
3495 
            false
3496 
            false
3497 
            false
3498 
            false
3499 
            false
3500 
            64
3501 
            false
3502 
            6014
3503 
            10EE
3504 
            No_limit
3505 
            1
3506 
            false
3507 
            X0Y0
3508 
            PCI_Express_Endpoint_device
3509 
            false
3510 
            0026
3511 
            true
3512 
            N/A
3513 
            true
3514 
            100_MHz
3515 
            05
3516 
            0
3517 
            ML_605
3518 
            3F
3519 
            2
3520 
            false
3521 
            0
3522 
            true
3523 
            false
3524 
            0
3525 
            4'h1
3526 
            false
3527 
            true
3528 
            0
3529 
            false
3530 
            1
3531 
            512_bytes
3532 
            true
3533 
            0
3534 
            250_default
3535 
            false
3536 
            N/A
3537 
            0
3538 
            false
3539 
            false
3540 
            Absolute
3541 
            false
3542 
            true
3543 
            0
3544 
            Kilobytes
3545 
            false
3546 
            false
3547 
            false
3548 
            false
3549 
            false
3550 
            false
3551 
            false
3552 
            Kilobytes
3553 
            0
3554 
            0
3555 
            false
3556 
            false
3557 
            false
3558 
            Kilobytes
3559 
            false
3560 
            true
3561 
            false
3562 
            4
3563 
            false
3564 
            false
3565 
            Range_B
3566 
            true
3567 
            Kilobytes
3568 
            ABB3
3569 
            N/A
3570 
            true
3571 
            false
3572 
            X8
3573 
            Megabytes
3574 
            0
3575 
            0
3576 
            false
3577 
            Memory
3578 
            0
3579 
            true
3580 
            false
3581 
            BAR_0
3582 
            Kilobytes
3583 
            false
3584 
            false
3585 
            false
3586 
            false
3587 
            0
3588 
            2.5_GT/s
3589 
            false
3590 
            false
3591 
            true
3592 
            false
3593 
            None
3594 
            None
3595 
            3FF
3596 
            false
3597 
            No_function_number_bits_used
3598 
            00
3599 
            2
3600 
            false
3601 
            false
3602 
            0
3603 
            false
3604 
            0
3605 
            INTA
3606 
            64_byte
3607 
            0
3608 
            false
3609 
            false
3610 
            Memory
3611 
            06
3612 
            false
3613 
            false
3614 
            1_vector
3615 
            BAR_0
3616 
            0
3617 
            0084
3618 
            0
3619 
            false
3620 
            0000
3621 
            false
3622 
            00
3623 
            00000000
3624 
            true
3625 
            true
3626 
            No_limit
3627 
            Disabled
3628 
            false
3629 
            Generic_XT_compatible_serial_controller
3630 
            0
3631 
            2
3632 
            false
3633
3634
3635
3636
3637 
               coregen
3638 
               ./
3639 
               ./tmp/
3640 
               ./tmp/_cg
3641
3642
3643 
               xc6vlx240t
3644 
               virtex6
3645 
               ff1156
3646 
               -1
3647
3648
3649 
               BusFormatAngleBracketNotRipped
3650 
               VHDL
3651 
               true
3652 
               Other
3653 
               false
3654 
               false
3655 
               false
3656 
               Ngc
3657 
               false
3658
3659
3660 
               Behavioral
3661 
               VHDL
3662 
               false
3663
3664
3665
3666
3667
3668
3669
3670
3671
3672 
         coregen
3673 
         ./
3674 
         ./tmp/
3675 
         ./tmp/_cg
3676
3677
3678 
         xc6vlx240t
3679 
         virtex6
3680 
         ff1156
3681 
         -1
3682
3683
3684 
         BusFormatAngleBracketNotRipped
3685 
         VHDL
3686 
         true
3687 
         Other
3688 
         false
3689 
         false
3690 
         false
3691 
         Ngc
3692 
         false
3693
3694
3695 
         Behavioral
3696 
         VHDL
3697 
         false
3698
3699
3700
3701

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