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barabba |
/*******************************************************************************
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* This file is owned and controlled by Xilinx and must be used *
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* solely for design, simulation, implementation and creation of *
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* design files limited to Xilinx devices or technologies. Use *
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* with non-Xilinx devices or technologies is expressly prohibited *
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* and immediately terminates your license. *
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* *
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* XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" *
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* SOLELY FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR *
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* XILINX DEVICES. BY PROVIDING THIS DESIGN, CODE, OR INFORMATION *
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* AS ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, APPLICATION *
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* OR STANDARD, XILINX IS MAKING NO REPRESENTATION THAT THIS *
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* IMPLEMENTATION IS FREE FROM ANY CLAIMS OF INFRINGEMENT, *
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* AND YOU ARE RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE *
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* FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY DISCLAIMS ANY *
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* WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE *
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* IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR *
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* REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF *
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* INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS *
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* FOR A PARTICULAR PURPOSE. *
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* *
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* Xilinx products are not intended for use in life support *
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* appliances, devices, or systems. Use in such applications are *
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* expressly prohibited. *
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* *
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* (c) Copyright 1995-2009 Xilinx, Inc. *
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* All rights reserved. *
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*******************************************************************************/
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// The synthesis directives "translate_off/translate_on" specified below are
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// supported by Xilinx, Mentor Graphics and Synplicity synthesis
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// tools. Ensure they are correct for your synthesis tool(s).
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// You must compile the wrapper file v6_prime_fifo_plain.v when simulating
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// the core, v6_prime_fifo_plain. When compiling the wrapper file, be sure to
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// reference the XilinxCoreLib Verilog simulation library. For detailed
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// instructions, please refer to the "CORE Generator Help".
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`timescale 1ns/1ps
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module v6_prime_fifo_plain(
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rst,
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wr_clk,
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rd_clk,
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din,
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wr_en,
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rd_en,
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dout,
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full,
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empty,
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prog_full);
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input rst;
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input wr_clk;
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input rd_clk;
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input [71 : 0] din;
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input wr_en;
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input rd_en;
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output [71 : 0] dout;
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output full;
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output empty;
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output prog_full;
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// synthesis translate_off
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FIFO_GENERATOR_V7_2 #(
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.C_ADD_NGC_CONSTRAINT(0),
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.C_APPLICATION_TYPE_AXIS(0),
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.C_APPLICATION_TYPE_RACH(0),
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.C_APPLICATION_TYPE_RDCH(0),
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.C_APPLICATION_TYPE_WACH(0),
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.C_APPLICATION_TYPE_WDCH(0),
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.C_APPLICATION_TYPE_WRCH(0),
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.C_AXIS_TDATA_WIDTH(64),
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.C_AXIS_TDEST_WIDTH(4),
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.C_AXIS_TID_WIDTH(8),
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.C_AXIS_TKEEP_WIDTH(4),
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.C_AXIS_TSTRB_WIDTH(4),
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.C_AXIS_TUSER_WIDTH(4),
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.C_AXIS_TYPE(0),
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.C_AXI_ADDR_WIDTH(32),
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.C_AXI_ARUSER_WIDTH(1),
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.C_AXI_AWUSER_WIDTH(1),
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.C_AXI_BUSER_WIDTH(1),
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.C_AXI_DATA_WIDTH(64),
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.C_AXI_ID_WIDTH(4),
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.C_AXI_RUSER_WIDTH(1),
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.C_AXI_TYPE(0),
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.C_AXI_WUSER_WIDTH(1),
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.C_COMMON_CLOCK(0),
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.C_COUNT_TYPE(0),
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.C_DATA_COUNT_WIDTH(9),
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.C_DEFAULT_VALUE("BlankString"),
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.C_DIN_WIDTH(72),
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.C_DIN_WIDTH_AXIS(1),
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.C_DIN_WIDTH_RACH(32),
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.C_DIN_WIDTH_RDCH(64),
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.C_DIN_WIDTH_WACH(32),
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.C_DIN_WIDTH_WDCH(64),
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.C_DIN_WIDTH_WRCH(2),
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.C_DOUT_RST_VAL("0"),
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.C_DOUT_WIDTH(72),
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.C_ENABLE_RLOCS(0),
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.C_ENABLE_RST_SYNC(1),
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.C_ERROR_INJECTION_TYPE(0),
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.C_ERROR_INJECTION_TYPE_AXIS(0),
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.C_ERROR_INJECTION_TYPE_RACH(0),
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.C_ERROR_INJECTION_TYPE_RDCH(0),
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.C_ERROR_INJECTION_TYPE_WACH(0),
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.C_ERROR_INJECTION_TYPE_WDCH(0),
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.C_ERROR_INJECTION_TYPE_WRCH(0),
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.C_FAMILY("virtex6"),
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.C_FULL_FLAGS_RST_VAL(0),
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.C_HAS_ALMOST_EMPTY(0),
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.C_HAS_ALMOST_FULL(0),
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.C_HAS_AXIS_TDATA(0),
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.C_HAS_AXIS_TDEST(0),
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.C_HAS_AXIS_TID(0),
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.C_HAS_AXIS_TKEEP(0),
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.C_HAS_AXIS_TLAST(0),
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.C_HAS_AXIS_TREADY(1),
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.C_HAS_AXIS_TSTRB(0),
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.C_HAS_AXIS_TUSER(0),
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.C_HAS_AXI_ARUSER(0),
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.C_HAS_AXI_AWUSER(0),
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.C_HAS_AXI_BUSER(0),
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.C_HAS_AXI_RD_CHANNEL(0),
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.C_HAS_AXI_RUSER(0),
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.C_HAS_AXI_WR_CHANNEL(0),
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.C_HAS_AXI_WUSER(0),
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.C_HAS_BACKUP(0),
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.C_HAS_DATA_COUNT(0),
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.C_HAS_DATA_COUNTS_AXIS(0),
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.C_HAS_DATA_COUNTS_RACH(0),
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.C_HAS_DATA_COUNTS_RDCH(0),
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.C_HAS_DATA_COUNTS_WACH(0),
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.C_HAS_DATA_COUNTS_WDCH(0),
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.C_HAS_DATA_COUNTS_WRCH(0),
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.C_HAS_INT_CLK(0),
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.C_HAS_MASTER_CE(0),
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| 141 |
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.C_HAS_MEMINIT_FILE(0),
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| 142 |
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.C_HAS_OVERFLOW(0),
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| 143 |
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.C_HAS_PROG_FLAGS_AXIS(0),
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| 144 |
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.C_HAS_PROG_FLAGS_RACH(0),
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| 145 |
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.C_HAS_PROG_FLAGS_RDCH(0),
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| 146 |
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.C_HAS_PROG_FLAGS_WACH(0),
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.C_HAS_PROG_FLAGS_WDCH(0),
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| 148 |
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.C_HAS_PROG_FLAGS_WRCH(0),
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.C_HAS_RD_DATA_COUNT(0),
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.C_HAS_RD_RST(0),
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.C_HAS_RST(1),
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.C_HAS_SLAVE_CE(0),
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.C_HAS_SRST(0),
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.C_HAS_UNDERFLOW(0),
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.C_HAS_VALID(0),
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| 156 |
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.C_HAS_WR_ACK(0),
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| 157 |
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.C_HAS_WR_DATA_COUNT(0),
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| 158 |
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.C_HAS_WR_RST(0),
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| 159 |
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.C_IMPLEMENTATION_TYPE(5),
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| 160 |
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.C_IMPLEMENTATION_TYPE_AXIS(1),
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| 161 |
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.C_IMPLEMENTATION_TYPE_RACH(1),
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| 162 |
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.C_IMPLEMENTATION_TYPE_RDCH(1),
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| 163 |
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.C_IMPLEMENTATION_TYPE_WACH(1),
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| 164 |
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.C_IMPLEMENTATION_TYPE_WDCH(1),
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| 165 |
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.C_IMPLEMENTATION_TYPE_WRCH(1),
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| 166 |
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.C_INIT_WR_PNTR_VAL(0),
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.C_INTERFACE_TYPE(0),
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| 168 |
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.C_MEMORY_TYPE(4),
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.C_MIF_FILE_NAME("BlankString"),
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.C_MSGON_VAL(1),
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.C_OPTIMIZATION_MODE(0),
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| 172 |
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.C_OVERFLOW_LOW(0),
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.C_PRELOAD_LATENCY(1),
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| 174 |
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.C_PRELOAD_REGS(0),
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| 175 |
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.C_PRIM_FIFO_TYPE("512x72"),
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| 176 |
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.C_PROG_EMPTY_THRESH_ASSERT_VAL(5),
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| 177 |
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.C_PROG_EMPTY_THRESH_ASSERT_VAL_AXIS(1022),
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| 178 |
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.C_PROG_EMPTY_THRESH_ASSERT_VAL_RACH(1022),
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| 179 |
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.C_PROG_EMPTY_THRESH_ASSERT_VAL_RDCH(1022),
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| 180 |
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.C_PROG_EMPTY_THRESH_ASSERT_VAL_WACH(1022),
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| 181 |
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.C_PROG_EMPTY_THRESH_ASSERT_VAL_WDCH(1022),
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| 182 |
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.C_PROG_EMPTY_THRESH_ASSERT_VAL_WRCH(1022),
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| 183 |
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.C_PROG_EMPTY_THRESH_NEGATE_VAL(6),
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| 184 |
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.C_PROG_EMPTY_TYPE(0),
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| 185 |
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.C_PROG_EMPTY_TYPE_AXIS(5),
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| 186 |
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.C_PROG_EMPTY_TYPE_RACH(5),
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| 187 |
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.C_PROG_EMPTY_TYPE_RDCH(5),
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| 188 |
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.C_PROG_EMPTY_TYPE_WACH(5),
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| 189 |
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.C_PROG_EMPTY_TYPE_WDCH(5),
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| 190 |
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.C_PROG_EMPTY_TYPE_WRCH(5),
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| 191 |
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.C_PROG_FULL_THRESH_ASSERT_VAL(496),
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| 192 |
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.C_PROG_FULL_THRESH_ASSERT_VAL_AXIS(1023),
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| 193 |
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.C_PROG_FULL_THRESH_ASSERT_VAL_RACH(1023),
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| 194 |
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.C_PROG_FULL_THRESH_ASSERT_VAL_RDCH(1023),
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| 195 |
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.C_PROG_FULL_THRESH_ASSERT_VAL_WACH(1023),
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| 196 |
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.C_PROG_FULL_THRESH_ASSERT_VAL_WDCH(1023),
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| 197 |
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.C_PROG_FULL_THRESH_ASSERT_VAL_WRCH(1023),
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| 198 |
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.C_PROG_FULL_THRESH_NEGATE_VAL(495),
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| 199 |
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.C_PROG_FULL_TYPE(1),
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| 200 |
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.C_PROG_FULL_TYPE_AXIS(5),
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| 201 |
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.C_PROG_FULL_TYPE_RACH(5),
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| 202 |
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.C_PROG_FULL_TYPE_RDCH(5),
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| 203 |
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.C_PROG_FULL_TYPE_WACH(5),
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| 204 |
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.C_PROG_FULL_TYPE_WDCH(5),
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| 205 |
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.C_PROG_FULL_TYPE_WRCH(5),
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| 206 |
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.C_RACH_TYPE(0),
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| 207 |
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.C_RDCH_TYPE(0),
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| 208 |
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.C_RD_DATA_COUNT_WIDTH(9),
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| 209 |
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.C_RD_DEPTH(512),
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| 210 |
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.C_RD_FREQ(125),
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| 211 |
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.C_RD_PNTR_WIDTH(9),
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| 212 |
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.C_REG_SLICE_MODE_AXIS(0),
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| 213 |
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.C_REG_SLICE_MODE_RACH(0),
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| 214 |
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.C_REG_SLICE_MODE_RDCH(0),
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| 215 |
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.C_REG_SLICE_MODE_WACH(0),
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| 216 |
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.C_REG_SLICE_MODE_WDCH(0),
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| 217 |
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.C_REG_SLICE_MODE_WRCH(0),
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| 218 |
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.C_UNDERFLOW_LOW(0),
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| 219 |
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.C_USE_COMMON_OVERFLOW(0),
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| 220 |
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.C_USE_COMMON_UNDERFLOW(0),
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| 221 |
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.C_USE_DEFAULT_SETTINGS(0),
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| 222 |
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.C_USE_DOUT_RST(0),
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| 223 |
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.C_USE_ECC(0),
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| 224 |
|
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.C_USE_ECC_AXIS(0),
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| 225 |
|
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.C_USE_ECC_RACH(0),
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| 226 |
|
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.C_USE_ECC_RDCH(0),
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| 227 |
|
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.C_USE_ECC_WACH(0),
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| 228 |
|
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.C_USE_ECC_WDCH(0),
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| 229 |
|
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.C_USE_ECC_WRCH(0),
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| 230 |
|
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.C_USE_EMBEDDED_REG(0),
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| 231 |
|
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.C_USE_FIFO16_FLAGS(0),
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| 232 |
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.C_USE_FWFT_DATA_COUNT(0),
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| 233 |
|
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.C_VALID_LOW(0),
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| 234 |
|
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.C_WACH_TYPE(0),
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| 235 |
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.C_WDCH_TYPE(0),
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| 236 |
|
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.C_WRCH_TYPE(0),
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| 237 |
|
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.C_WR_ACK_LOW(0),
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| 238 |
|
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.C_WR_DATA_COUNT_WIDTH(9),
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| 239 |
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.C_WR_DEPTH(512),
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| 240 |
|
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.C_WR_DEPTH_AXIS(1024),
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| 241 |
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.C_WR_DEPTH_RACH(16),
|
| 242 |
|
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.C_WR_DEPTH_RDCH(1024),
|
| 243 |
|
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.C_WR_DEPTH_WACH(16),
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| 244 |
|
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.C_WR_DEPTH_WDCH(1024),
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| 245 |
|
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.C_WR_DEPTH_WRCH(16),
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| 246 |
|
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.C_WR_FREQ(125),
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| 247 |
|
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.C_WR_PNTR_WIDTH(9),
|
| 248 |
|
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.C_WR_PNTR_WIDTH_AXIS(10),
|
| 249 |
|
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.C_WR_PNTR_WIDTH_RACH(4),
|
| 250 |
|
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.C_WR_PNTR_WIDTH_RDCH(10),
|
| 251 |
|
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.C_WR_PNTR_WIDTH_WACH(4),
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| 252 |
|
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.C_WR_PNTR_WIDTH_WDCH(10),
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| 253 |
|
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.C_WR_PNTR_WIDTH_WRCH(4),
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| 254 |
|
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.C_WR_RESPONSE_LATENCY(1))
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| 255 |
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inst (
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| 256 |
|
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.RST(rst),
|
| 257 |
|
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.WR_CLK(wr_clk),
|
| 258 |
|
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.RD_CLK(rd_clk),
|
| 259 |
|
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.DIN(din),
|
| 260 |
|
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.WR_EN(wr_en),
|
| 261 |
|
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.RD_EN(rd_en),
|
| 262 |
|
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.DOUT(dout),
|
| 263 |
|
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.FULL(full),
|
| 264 |
|
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.EMPTY(empty),
|
| 265 |
|
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.PROG_FULL(prog_full),
|
| 266 |
|
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.BACKUP(),
|
| 267 |
|
|
.BACKUP_MARKER(),
|
| 268 |
|
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.CLK(),
|
| 269 |
|
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.SRST(),
|
| 270 |
|
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.WR_RST(),
|
| 271 |
|
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.RD_RST(),
|
| 272 |
|
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.PROG_EMPTY_THRESH(),
|
| 273 |
|
|
.PROG_EMPTY_THRESH_ASSERT(),
|
| 274 |
|
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.PROG_EMPTY_THRESH_NEGATE(),
|
| 275 |
|
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.PROG_FULL_THRESH(),
|
| 276 |
|
|
.PROG_FULL_THRESH_ASSERT(),
|
| 277 |
|
|
.PROG_FULL_THRESH_NEGATE(),
|
| 278 |
|
|
.INT_CLK(),
|
| 279 |
|
|
.INJECTDBITERR(),
|
| 280 |
|
|
.INJECTSBITERR(),
|
| 281 |
|
|
.ALMOST_FULL(),
|
| 282 |
|
|
.WR_ACK(),
|
| 283 |
|
|
.OVERFLOW(),
|
| 284 |
|
|
.ALMOST_EMPTY(),
|
| 285 |
|
|
.VALID(),
|
| 286 |
|
|
.UNDERFLOW(),
|
| 287 |
|
|
.DATA_COUNT(),
|
| 288 |
|
|
.RD_DATA_COUNT(),
|
| 289 |
|
|
.WR_DATA_COUNT(),
|
| 290 |
|
|
.PROG_EMPTY(),
|
| 291 |
|
|
.SBITERR(),
|
| 292 |
|
|
.DBITERR(),
|
| 293 |
|
|
.M_ACLK(),
|
| 294 |
|
|
.S_ACLK(),
|
| 295 |
|
|
.S_ARESETN(),
|
| 296 |
|
|
.M_ACLK_EN(),
|
| 297 |
|
|
.S_ACLK_EN(),
|
| 298 |
|
|
.S_AXI_AWID(),
|
| 299 |
|
|
.S_AXI_AWADDR(),
|
| 300 |
|
|
.S_AXI_AWLEN(),
|
| 301 |
|
|
.S_AXI_AWSIZE(),
|
| 302 |
|
|
.S_AXI_AWBURST(),
|
| 303 |
|
|
.S_AXI_AWLOCK(),
|
| 304 |
|
|
.S_AXI_AWCACHE(),
|
| 305 |
|
|
.S_AXI_AWPROT(),
|
| 306 |
|
|
.S_AXI_AWQOS(),
|
| 307 |
|
|
.S_AXI_AWREGION(),
|
| 308 |
|
|
.S_AXI_AWUSER(),
|
| 309 |
|
|
.S_AXI_AWVALID(),
|
| 310 |
|
|
.S_AXI_AWREADY(),
|
| 311 |
|
|
.S_AXI_WID(),
|
| 312 |
|
|
.S_AXI_WDATA(),
|
| 313 |
|
|
.S_AXI_WSTRB(),
|
| 314 |
|
|
.S_AXI_WLAST(),
|
| 315 |
|
|
.S_AXI_WUSER(),
|
| 316 |
|
|
.S_AXI_WVALID(),
|
| 317 |
|
|
.S_AXI_WREADY(),
|
| 318 |
|
|
.S_AXI_BID(),
|
| 319 |
|
|
.S_AXI_BRESP(),
|
| 320 |
|
|
.S_AXI_BUSER(),
|
| 321 |
|
|
.S_AXI_BVALID(),
|
| 322 |
|
|
.S_AXI_BREADY(),
|
| 323 |
|
|
.M_AXI_AWID(),
|
| 324 |
|
|
.M_AXI_AWADDR(),
|
| 325 |
|
|
.M_AXI_AWLEN(),
|
| 326 |
|
|
.M_AXI_AWSIZE(),
|
| 327 |
|
|
.M_AXI_AWBURST(),
|
| 328 |
|
|
.M_AXI_AWLOCK(),
|
| 329 |
|
|
.M_AXI_AWCACHE(),
|
| 330 |
|
|
.M_AXI_AWPROT(),
|
| 331 |
|
|
.M_AXI_AWQOS(),
|
| 332 |
|
|
.M_AXI_AWREGION(),
|
| 333 |
|
|
.M_AXI_AWUSER(),
|
| 334 |
|
|
.M_AXI_AWVALID(),
|
| 335 |
|
|
.M_AXI_AWREADY(),
|
| 336 |
|
|
.M_AXI_WID(),
|
| 337 |
|
|
.M_AXI_WDATA(),
|
| 338 |
|
|
.M_AXI_WSTRB(),
|
| 339 |
|
|
.M_AXI_WLAST(),
|
| 340 |
|
|
.M_AXI_WUSER(),
|
| 341 |
|
|
.M_AXI_WVALID(),
|
| 342 |
|
|
.M_AXI_WREADY(),
|
| 343 |
|
|
.M_AXI_BID(),
|
| 344 |
|
|
.M_AXI_BRESP(),
|
| 345 |
|
|
.M_AXI_BUSER(),
|
| 346 |
|
|
.M_AXI_BVALID(),
|
| 347 |
|
|
.M_AXI_BREADY(),
|
| 348 |
|
|
.S_AXI_ARID(),
|
| 349 |
|
|
.S_AXI_ARADDR(),
|
| 350 |
|
|
.S_AXI_ARLEN(),
|
| 351 |
|
|
.S_AXI_ARSIZE(),
|
| 352 |
|
|
.S_AXI_ARBURST(),
|
| 353 |
|
|
.S_AXI_ARLOCK(),
|
| 354 |
|
|
.S_AXI_ARCACHE(),
|
| 355 |
|
|
.S_AXI_ARPROT(),
|
| 356 |
|
|
.S_AXI_ARQOS(),
|
| 357 |
|
|
.S_AXI_ARREGION(),
|
| 358 |
|
|
.S_AXI_ARUSER(),
|
| 359 |
|
|
.S_AXI_ARVALID(),
|
| 360 |
|
|
.S_AXI_ARREADY(),
|
| 361 |
|
|
.S_AXI_RID(),
|
| 362 |
|
|
.S_AXI_RDATA(),
|
| 363 |
|
|
.S_AXI_RRESP(),
|
| 364 |
|
|
.S_AXI_RLAST(),
|
| 365 |
|
|
.S_AXI_RUSER(),
|
| 366 |
|
|
.S_AXI_RVALID(),
|
| 367 |
|
|
.S_AXI_RREADY(),
|
| 368 |
|
|
.M_AXI_ARID(),
|
| 369 |
|
|
.M_AXI_ARADDR(),
|
| 370 |
|
|
.M_AXI_ARLEN(),
|
| 371 |
|
|
.M_AXI_ARSIZE(),
|
| 372 |
|
|
.M_AXI_ARBURST(),
|
| 373 |
|
|
.M_AXI_ARLOCK(),
|
| 374 |
|
|
.M_AXI_ARCACHE(),
|
| 375 |
|
|
.M_AXI_ARPROT(),
|
| 376 |
|
|
.M_AXI_ARQOS(),
|
| 377 |
|
|
.M_AXI_ARREGION(),
|
| 378 |
|
|
.M_AXI_ARUSER(),
|
| 379 |
|
|
.M_AXI_ARVALID(),
|
| 380 |
|
|
.M_AXI_ARREADY(),
|
| 381 |
|
|
.M_AXI_RID(),
|
| 382 |
|
|
.M_AXI_RDATA(),
|
| 383 |
|
|
.M_AXI_RRESP(),
|
| 384 |
|
|
.M_AXI_RLAST(),
|
| 385 |
|
|
.M_AXI_RUSER(),
|
| 386 |
|
|
.M_AXI_RVALID(),
|
| 387 |
|
|
.M_AXI_RREADY(),
|
| 388 |
|
|
.S_AXIS_TVALID(),
|
| 389 |
|
|
.S_AXIS_TREADY(),
|
| 390 |
|
|
.S_AXIS_TDATA(),
|
| 391 |
|
|
.S_AXIS_TSTRB(),
|
| 392 |
|
|
.S_AXIS_TKEEP(),
|
| 393 |
|
|
.S_AXIS_TLAST(),
|
| 394 |
|
|
.S_AXIS_TID(),
|
| 395 |
|
|
.S_AXIS_TDEST(),
|
| 396 |
|
|
.S_AXIS_TUSER(),
|
| 397 |
|
|
.M_AXIS_TVALID(),
|
| 398 |
|
|
.M_AXIS_TREADY(),
|
| 399 |
|
|
.M_AXIS_TDATA(),
|
| 400 |
|
|
.M_AXIS_TSTRB(),
|
| 401 |
|
|
.M_AXIS_TKEEP(),
|
| 402 |
|
|
.M_AXIS_TLAST(),
|
| 403 |
|
|
.M_AXIS_TID(),
|
| 404 |
|
|
.M_AXIS_TDEST(),
|
| 405 |
|
|
.M_AXIS_TUSER(),
|
| 406 |
|
|
.AXI_AW_INJECTSBITERR(),
|
| 407 |
|
|
.AXI_AW_INJECTDBITERR(),
|
| 408 |
|
|
.AXI_AW_PROG_FULL_THRESH(),
|
| 409 |
|
|
.AXI_AW_PROG_EMPTY_THRESH(),
|
| 410 |
|
|
.AXI_AW_DATA_COUNT(),
|
| 411 |
|
|
.AXI_AW_WR_DATA_COUNT(),
|
| 412 |
|
|
.AXI_AW_RD_DATA_COUNT(),
|
| 413 |
|
|
.AXI_AW_SBITERR(),
|
| 414 |
|
|
.AXI_AW_DBITERR(),
|
| 415 |
|
|
.AXI_AW_OVERFLOW(),
|
| 416 |
|
|
.AXI_AW_UNDERFLOW(),
|
| 417 |
|
|
.AXI_W_INJECTSBITERR(),
|
| 418 |
|
|
.AXI_W_INJECTDBITERR(),
|
| 419 |
|
|
.AXI_W_PROG_FULL_THRESH(),
|
| 420 |
|
|
.AXI_W_PROG_EMPTY_THRESH(),
|
| 421 |
|
|
.AXI_W_DATA_COUNT(),
|
| 422 |
|
|
.AXI_W_WR_DATA_COUNT(),
|
| 423 |
|
|
.AXI_W_RD_DATA_COUNT(),
|
| 424 |
|
|
.AXI_W_SBITERR(),
|
| 425 |
|
|
.AXI_W_DBITERR(),
|
| 426 |
|
|
.AXI_W_OVERFLOW(),
|
| 427 |
|
|
.AXI_W_UNDERFLOW(),
|
| 428 |
|
|
.AXI_B_INJECTSBITERR(),
|
| 429 |
|
|
.AXI_B_INJECTDBITERR(),
|
| 430 |
|
|
.AXI_B_PROG_FULL_THRESH(),
|
| 431 |
|
|
.AXI_B_PROG_EMPTY_THRESH(),
|
| 432 |
|
|
.AXI_B_DATA_COUNT(),
|
| 433 |
|
|
.AXI_B_WR_DATA_COUNT(),
|
| 434 |
|
|
.AXI_B_RD_DATA_COUNT(),
|
| 435 |
|
|
.AXI_B_SBITERR(),
|
| 436 |
|
|
.AXI_B_DBITERR(),
|
| 437 |
|
|
.AXI_B_OVERFLOW(),
|
| 438 |
|
|
.AXI_B_UNDERFLOW(),
|
| 439 |
|
|
.AXI_AR_INJECTSBITERR(),
|
| 440 |
|
|
.AXI_AR_INJECTDBITERR(),
|
| 441 |
|
|
.AXI_AR_PROG_FULL_THRESH(),
|
| 442 |
|
|
.AXI_AR_PROG_EMPTY_THRESH(),
|
| 443 |
|
|
.AXI_AR_DATA_COUNT(),
|
| 444 |
|
|
.AXI_AR_WR_DATA_COUNT(),
|
| 445 |
|
|
.AXI_AR_RD_DATA_COUNT(),
|
| 446 |
|
|
.AXI_AR_SBITERR(),
|
| 447 |
|
|
.AXI_AR_DBITERR(),
|
| 448 |
|
|
.AXI_AR_OVERFLOW(),
|
| 449 |
|
|
.AXI_AR_UNDERFLOW(),
|
| 450 |
|
|
.AXI_R_INJECTSBITERR(),
|
| 451 |
|
|
.AXI_R_INJECTDBITERR(),
|
| 452 |
|
|
.AXI_R_PROG_FULL_THRESH(),
|
| 453 |
|
|
.AXI_R_PROG_EMPTY_THRESH(),
|
| 454 |
|
|
.AXI_R_DATA_COUNT(),
|
| 455 |
|
|
.AXI_R_WR_DATA_COUNT(),
|
| 456 |
|
|
.AXI_R_RD_DATA_COUNT(),
|
| 457 |
|
|
.AXI_R_SBITERR(),
|
| 458 |
|
|
.AXI_R_DBITERR(),
|
| 459 |
|
|
.AXI_R_OVERFLOW(),
|
| 460 |
|
|
.AXI_R_UNDERFLOW(),
|
| 461 |
|
|
.AXIS_INJECTSBITERR(),
|
| 462 |
|
|
.AXIS_INJECTDBITERR(),
|
| 463 |
|
|
.AXIS_PROG_FULL_THRESH(),
|
| 464 |
|
|
.AXIS_PROG_EMPTY_THRESH(),
|
| 465 |
|
|
.AXIS_DATA_COUNT(),
|
| 466 |
|
|
.AXIS_WR_DATA_COUNT(),
|
| 467 |
|
|
.AXIS_RD_DATA_COUNT(),
|
| 468 |
|
|
.AXIS_SBITERR(),
|
| 469 |
|
|
.AXIS_DBITERR(),
|
| 470 |
|
|
.AXIS_OVERFLOW(),
|
| 471 |
|
|
.AXIS_UNDERFLOW());
|
| 472 |
|
|
|
| 473 |
|
|
|
| 474 |
|
|
// synthesis translate_on
|
| 475 |
|
|
|
| 476 |
|
|
// XST black box declaration
|
| 477 |
|
|
// box_type "black_box"
|
| 478 |
|
|
// synthesis attribute box_type of v6_prime_fifo_plain is "black_box"
|
| 479 |
|
|
|
| 480 |
|
|
endmodule
|
| 481 |
|
|
|
