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Subversion Repositories pcie_sg_dma

[/] [pcie_sg_dma/] [branches/] [Virtex6/] [ML605_ISE12.3/] [ipcore_dir_ISE13.3/] [coregen.cgc] - Blame information for rev 11

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   xilinx.com
   project
   coregen
   1.0
   
      
         v6_afifo_1024x72
         Fifo Generator
         The FIFO Generator is a parameterizable first-in/first-out memory queue generator. Use it to generate resource and performance optimized FIFOs with common or independent read/write clock domains, and optional fixed or programmable full and empty flags and handshaking signals.  Choose from a selection of memory resource types for implementation.  Optional Hamming code based error detection and correction as well as error injection capability for system test help to insure data integrity.  FIFO width and depth are parameterizable, and for native interface FIFOs, asymmetric read and write port widths are also supported.
         
         
            v6_afifo_1024x72
            Independent_Clocks_Block_RAM
            Native
            Standard_FIFO
            72
            1024
            72
            1024
            false
            false
            true
            true
            Asynchronous_Reset
            1
            true
            0
            false
            false
            false
            Active_High
            false
            Active_High
            false
            Active_High
            false
            Active_High
            false
            false
            false
            false
            10
            false
            10
            false
            10
            false
            1
            1
            Single_Programmable_Full_Threshold_Constant
            768
            767
            Single_Programmable_Empty_Threshold_Constant
            3
            4
            AXI4_Stream
            Common_Clock
            false
            Slave_Interface_Clock_Enable
            false
            false
            4
            32
            64
            false
            1
            false
            1
            false
            1
            false
            1
            false
            1
            false
            64
            false
            8
            false
            4
            false
            4
            true
            false
            false
            4
            false
            4
            FIFO
            Common_Clock_Block_RAM
            Data_FIFO
            false
            false
            false
            16
            false
            false
            Full
            1023
            Empty
            1022
            FIFO
            Common_Clock_Block_RAM
            Data_FIFO
            false
            false
            false
            1024
            false
            false
            Full
            1023
            Empty
            1022
            FIFO
            Common_Clock_Block_RAM
            Data_FIFO
            false
            false
            false
            16
            false
            false
            Full
            1023
            Empty
            1022
            FIFO
            Common_Clock_Block_RAM
            Data_FIFO
            false
            false
            false
            16
            false
            false
            Full
            1023
            Empty
            1022
            FIFO
            Common_Clock_Block_RAM
            Data_FIFO
            false
            false
            false
            1024
            false
            false
            Full
            1023
            Empty
            1022
            FIFO
            Common_Clock_Block_RAM
            Data_FIFO
            false
            false
            false
            1024
            false
            false
            Full
            1023
            Empty
            1022
            Fully_Registered
            Fully_Registered
            Fully_Registered
            Fully_Registered
            Fully_Registered
            Fully_Registered
            false
            Active_High
            false
            Active_High
            false
            false
            false
            false
            false
            0
            10
            72
            0
            72
            virtex6
            1
            0
            0
            0
            0
            0
            0
            1
            0
            0
            0
            0
            0
            2
            1
            0
            1
            0
            1kx36
            3
            4
            1
            768
            767
            1
            10
            1024
            1
            10
            0
            1
            0
            0
            0
            0
            0
            10
            1024
            1
            10
            1
            1
            0
            0
            0
            0
            0
            0
            0
            0
            0
            0
            4
            32
            64
            0
            0
            0
            0
            0
            1
            1
            1
            1
            1
            0
            0
            0
            0
            1
            0
            0
            0
            64
            8
            4
            4
            4
            4
            0
            0
            0
            0
            0
            0
            1
            1
            1
            1
            1
            1
            0
            0
            0
            0
            0
            0
            0
            0
            0
            0
            0
            0
            0
            0
            0
            0
            0
            0
            32
            64
            2
            32
            64
            1
            16
            1024
            16
            16
            1024
            1024
            4
            10
            4
            4
            10
            10
            0
            0
            0
            0
            0
            0
            0
            0
            0
            0
            0
            0
            5
            5
            5
            5
            5
            5
            1023
            1023
            1023
            1023
            1023
            1023
            5
            5
            5
            5
            5
            5
            1022
            1022
            1022
            1022
            1022
            1022
            0
            0
            0
            0
            0
            0
         
         
            
               
                  coregen
                  ./
                  ./tmp/
                  ./tmp/_cg/
               
               
                  xc6vlx240t
                  virtex6
                  ff1156
                  -1
               
               
                  BusFormatAngleBracketNotRipped
                  VHDL
                  true
                  Foundation_ISE
                  false
                  false
                  false
                  Ngc
                  false
               
               
                  Behavioral
                  VHDL_and_Verilog
                  false
               
               
                  2011-03-14T07:12:32.000Z
               
            
            
               
                  ip_upgrade_generator
                  
                     ./v6_afifo_1024x72_upgrade.txt
                     txt
                     Mon Mar 12 16:22:03 GMT 2012
                     0x79EF5B79
                     generationid_1450439901
                  
               
               
                  view_upgrade_report_generator
               
               
                  model_parameter_resolution_generator
               
               
                  ip_xco_generator
                  
                     ./v6_afifo_1024x72.xco
                     xco
                     Mon Mar 12 16:22:21 GMT 2012
                     0xAAE9CC22
                     generationid_1450439901
                  
               
               
                  associated_files_generator
                  
                     ./fifo_generator_ug175.pdf
                     pdf
                     Tue Oct 04 23:21:33 GMT 2011
                     0x42070F84
                     generationid_1450439901
                  
                  
                     ./fifo_generator_v8_3_readme.txt
                     txt
                     Tue Oct 04 23:21:33 GMT 2011
                     0xCD35AB83
                     generationid_1450439901
                  
               
               
                  ejava_generator
                  
                     ./v6_afifo_1024x72_ste/example_design/v6_afifo_1024x72_top.ucf
                     ignore
                     ucf
                     Mon Mar 12 16:22:31 GMT 2012
                     0xB0FB4AAF
                     generationid_1450439901
                  
                  
                     ./v6_afifo_1024x72_ste/example_design/v6_afifo_1024x72_top.vhd
                     ignore
                     vhdl
                     Mon Mar 12 16:22:32 GMT 2012
                     0x02CCED3C
                     generationid_1450439901
                  
                  
                     ./v6_afifo_1024x72_ste/example_design/v6_afifo_1024x72_top.xdc
                     ignore
                     xdc
                     Mon Mar 12 16:22:32 GMT 2012
                     0xA1CB2F49
                     generationid_1450439901
                  
                  
                     ./v6_afifo_1024x72_ste/implement/implement.bat
                     ignore
                     unknown
                     Mon Mar 12 16:22:32 GMT 2012
                     0x07C12B28
                     generationid_1450439901
                  
                  
                     ./v6_afifo_1024x72_ste/implement/implement.sh
                     ignore
                     unknown
                     Mon Mar 12 16:22:32 GMT 2012
                     0x50E0432C
                     generationid_1450439901
                  
                  
                     ./v6_afifo_1024x72_ste/implement/planAhead_rdn.bat
                     ignore
                     unknown
                     Mon Mar 12 16:22:32 GMT 2012
                     0x7F2BE4C8
                     generationid_1450439901
                  
                  
                     ./v6_afifo_1024x72_ste/implement/planAhead_rdn.sh
                     ignore
                     unknown
                     Mon Mar 12 16:22:32 GMT 2012
                     0x2B802AE7
                     generationid_1450439901
                  
                  
                     ./v6_afifo_1024x72_ste/implement/planAhead_rdn.tcl
                     ignore
                     tcl
                     Mon Mar 12 16:22:32 GMT 2012
                     0x9ECFBD67
                     generationid_1450439901
                  
                  
                     ./v6_afifo_1024x72_ste/implement/xst.prj
                     ignore
                     unknown
                     Mon Mar 12 16:22:32 GMT 2012
                     0x8DD474AC
                     generationid_1450439901
                  
                  
                     ./v6_afifo_1024x72_ste/implement/xst.scr
                     ignore
                     unknown
                     Mon Mar 12 16:22:32 GMT 2012
                     0x000016DD
                     generationid_1450439901
                  
               
               
                  ngc_netlist_generator
                  
                     ./v6_afifo_1024x72.ngc
                     ngc
                     Mon Mar 12 16:25:02 GMT 2012
                     0xEA4CDFFB
                     generationid_1450439901
                  
               
               
                  obfuscate_netlist_generator
               
               
                  padded_implementation_netlist_generator
               
               
                  instantiation_template_generator
                  
                     ./v6_afifo_1024x72.veo
                     veo
                     Mon Mar 12 16:25:08 GMT 2012
                     0x8A272A6F
                     generationid_1450439901
                  
                  
                     ./v6_afifo_1024x72.vho
                     vho
                     Mon Mar 12 16:25:08 GMT 2012
                     0x035310A7
                     generationid_1450439901
                  
               
               
                  structural_simulation_model_generator
                  
                     ./v6_afifo_1024x72.v
                     verilog
                     Mon Mar 12 16:25:09 GMT 2012
                     0x2843AA73
                     generationid_1450439901
                  
                  
                     ./v6_afifo_1024x72.vhd
                     vhdl
                     Mon Mar 12 16:25:09 GMT 2012
                     0x87CA0CEE
                     generationid_1450439901
                  
               
               
                  asy_generator
                  
                     ./v6_afifo_1024x72.asy
                     asy
                     Mon Mar 12 16:25:16 GMT 2012
                     0x49DA6BBB
                     generationid_1450439901
                  
               
               
                  xmdf_generator
                  
                     ./v6_afifo_1024x72_xmdf.tcl
                     tclXmdf
                     tcl
                     Mon Mar 12 16:25:17 GMT 2012
                     0x9BB94AA2
                     generationid_1450439901
                  
               
               
                  ise_generator
                  
                     ./_xmsgs/pn_parser.xmsgs
                     ignore
                     unknown
                     Mon Mar 12 16:26:01 GMT 2012
                     0xB4FDCDAB
                     generationid_1450439901
                  
                  
                     ./v6_afifo_1024x72.gise
                     ignore
                     gise
                     Mon Mar 12 16:26:02 GMT 2012
                     0xC523EE5D
                     generationid_1450439901
                  
                  
                     ./v6_afifo_1024x72.xise
                     ignore
                     xise
                     Mon Mar 12 16:26:02 GMT 2012
                     0x678A73D9
                     generationid_1450439901
                  
               
               
                  deliver_readme_generator
               
               
                  flist_generator
                  
                     ./v6_afifo_1024x72_flist.txt
                     ignore
                     txtFlist
                     txt
                     Mon Mar 12 16:26:02 GMT 2012
                     0xB2E3F603
                     generationid_1450439901
                  
               
            
         
      
      
         v6_afifo_256x36
         Fifo Generator
         The FIFO Generator is a parameterizable first-in/first-out memory queue generator. Use it to generate resource and performance optimized FIFOs with common or independent read/write clock domains, and optional fixed or programmable full and empty flags and handshaking signals.  Choose from a selection of memory resource types for implementation.  Optional Hamming code based error detection and correction as well as error injection capability for system test help to insure data integrity.  FIFO width and depth are parameterizable, and for native interface FIFOs, asymmetric read and write port widths are also supported.
         
         
            v6_afifo_256x36
            Independent_Clocks_Block_RAM
            Native
            Standard_FIFO
            36
            512
            36
            512
            false
            false
            true
            true
            Asynchronous_Reset
            1
            true
            0
            false
            false
            false
            Active_High
            false
            Active_High
            false
            Active_High
            false
            Active_High
            false
            false
            false
            false
            9
            false
            9
            false
            9
            false
            1
            1
            Single_Programmable_Full_Threshold_Constant
            320
            319
            Single_Programmable_Empty_Threshold_Constant
            8
            9
            AXI4_Stream
            Common_Clock
            false
            Slave_Interface_Clock_Enable
            false
            false
            4
            32
            64
            false
            1
            false
            1
            false
            1
            false
            1
            false
            1
            false
            64
            false
            8
            false
            4
            false
            4
            true
            false
            false
            4
            false
            4
            FIFO
            Common_Clock_Block_RAM
            Data_FIFO
            false
            false
            false
            16
            false
            false
            Full
            1023
            Empty
            1022
            FIFO
            Common_Clock_Block_RAM
            Data_FIFO
            false
            false
            false
            1024
            false
            false
            Full
            1023
            Empty
            1022
            FIFO
            Common_Clock_Block_RAM
            Data_FIFO
            false
            false
            false
            16
            false
            false
            Full
            1023
            Empty
            1022
            FIFO
            Common_Clock_Block_RAM
            Data_FIFO
            false
            false
            false
            16
            false
            false
            Full
            1023
            Empty
            1022
            FIFO
            Common_Clock_Block_RAM
            Data_FIFO
            false
            false
            false
            1024
            false
            false
            Full
            1023
            Empty
            1022
            FIFO
            Common_Clock_Block_RAM
            Data_FIFO
            false
            false
            false
            1024
            false
            false
            Full
            1023
            Empty
            1022
            Fully_Registered
            Fully_Registered
            Fully_Registered
            Fully_Registered
            Fully_Registered
            Fully_Registered
            false
            Active_High
            false
            Active_High
            false
            false
            false
            false
            false
            0
            9
            36
            0
            36
            virtex6
            1
            0
            0
            0
            0
            0
            0
            1
            0
            0
            0
            0
            0
            2
            1
            0
            1
            0
            512x36
            8
            9
            1
            320
            319
            1
            9
            512
            1
            9
            0
            1
            0
            0
            0
            0
            0
            9
            512
            1
            9
            1
            1
            0
            0
            0
            0
            0
            0
            0
            0
            0
            0
            4
            32
            64
            0
            0
            0
            0
            0
            1
            1
            1
            1
            1
            0
            0
            0
            0
            1
            0
            0
            0
            64
            8
            4
            4
            4
            4
            0
            0
            0
            0
            0
            0
            1
            1
            1
            1
            1
            1
            0
            0
            0
            0
            0
            0
            0
            0
            0
            0
            0
            0
            0
            0
            0
            0
            0
            0
            32
            64
            2
            32
            64
            1
            16
            1024
            16
            16
            1024
            1024
            4
            10
            4
            4
            10
            10
            0
            0
            0
            0
            0
            0
            0
            0
            0
            0
            0
            0
            5
            5
            5
            5
            5
            5
            1023
            1023
            1023
            1023
            1023
            1023
            5
            5
            5
            5
            5
            5
            1022
            1022
            1022
            1022
            1022
            1022
            0
            0
            0
            0
            0
            0
         
         
            
               
                  coregen
                  ./
                  ./tmp/
                  ./tmp/_cg/
               
               
                  xc6vlx240t
                  virtex6
                  ff1156
                  -1
               
               
                  BusFormatAngleBracketNotRipped
                  VHDL
                  true
                  Foundation_ISE
                  false
                  false
                  false
                  Ngc
                  false
               
               
                  Behavioral
                  VHDL_and_Verilog
                  false
               
               
                  2011-03-14T07:12:32.000Z
               
            
            
               
                  ip_upgrade_generator
                  
                     ./v6_afifo_256x36_upgrade.txt
                     txt
                     Mon Mar 12 16:32:32 GMT 2012
                     0x48CB9E2A
                     generationid_191393288
                  
               
               
                  view_upgrade_report_generator
               
               
                  model_parameter_resolution_generator
               
               
                  ip_xco_generator
                  
                     ./v6_afifo_256x36.xco
                     xco
                     Mon Mar 12 16:32:43 GMT 2012
                     0x6F372281
                     generationid_191393288
                  
               
               
                  associated_files_generator
                  
                     ./fifo_generator_ug175.pdf
                     pdf
                     Tue Oct 04 23:21:33 GMT 2011
                     0x42070F84
                     generationid_191393288
                  
                  
                     ./fifo_generator_v8_3_readme.txt
                     txt
                     Tue Oct 04 23:21:33 GMT 2011
                     0xCD35AB83
                     generationid_191393288
                  
               
               
                  ejava_generator
                  
                     ./v6_afifo_256x36_ste/example_design/v6_afifo_256x36_top.ucf
                     ignore
                     ucf
                     Mon Mar 12 16:32:48 GMT 2012
                     0xB0FB4AAF
                     generationid_191393288
                  
                  
                     ./v6_afifo_256x36_ste/example_design/v6_afifo_256x36_top.vhd
                     ignore
                     vhdl
                     Mon Mar 12 16:32:48 GMT 2012
                     0xFF5FDC4B
                     generationid_191393288
                  
                  
                     ./v6_afifo_256x36_ste/example_design/v6_afifo_256x36_top.xdc
                     ignore
                     xdc
                     Mon Mar 12 16:32:48 GMT 2012
                     0xA1CB2F49
                     generationid_191393288
                  
                  
                     ./v6_afifo_256x36_ste/implement/implement.bat
                     ignore
                     unknown
                     Mon Mar 12 16:32:48 GMT 2012
                     0xD74DD09A
                     generationid_191393288
                  
                  
                     ./v6_afifo_256x36_ste/implement/implement.sh
                     ignore
                     unknown
                     Mon Mar 12 16:32:48 GMT 2012
                     0x7B98DABF
                     generationid_191393288
                  
                  
                     ./v6_afifo_256x36_ste/implement/planAhead_rdn.bat
                     ignore
                     unknown
                     Mon Mar 12 16:32:48 GMT 2012
                     0xA496078D
                     generationid_191393288
                  
                  
                     ./v6_afifo_256x36_ste/implement/planAhead_rdn.sh
                     ignore
                     unknown
                     Mon Mar 12 16:32:48 GMT 2012
                     0x6AFC3016
                     generationid_191393288
                  
                  
                     ./v6_afifo_256x36_ste/implement/planAhead_rdn.tcl
                     ignore
                     tcl
                     Mon Mar 12 16:32:48 GMT 2012
                     0xCC2F62F9
                     generationid_191393288
                  
                  
                     ./v6_afifo_256x36_ste/implement/xst.prj
                     ignore
                     unknown
                     Mon Mar 12 16:32:48 GMT 2012
                     0x52D06ED1
                     generationid_191393288
                  
                  
                     ./v6_afifo_256x36_ste/implement/xst.scr
                     ignore
                     unknown
                     Mon Mar 12 16:32:48 GMT 2012
                     0xDCF3959F
                     generationid_191393288
                  
               
               
                  ngc_netlist_generator
                  
                     ./v6_afifo_256x36.ngc
                     ngc
                     Mon Mar 12 16:34:23 GMT 2012
                     0x562CDDD4
                     generationid_191393288
                  
               
               
                  obfuscate_netlist_generator
               
               
                  padded_implementation_netlist_generator
               
               
                  instantiation_template_generator
                  
                     ./v6_afifo_256x36.veo
                     veo
                     Mon Mar 12 16:34:26 GMT 2012
                     0x503A67AE
                     generationid_191393288
                  
                  
                     ./v6_afifo_256x36.vho
                     vho
                     Mon Mar 12 16:34:26 GMT 2012
                     0xB9A340C4
                     generationid_191393288
                  
               
               
                  structural_simulation_model_generator
                  
                     ./v6_afifo_256x36.v
                     verilog
                     Mon Mar 12 16:34:26 GMT 2012
                     0xFD693200
                     generationid_191393288
                  
                  
                     ./v6_afifo_256x36.vhd
                     vhdl
                     Mon Mar 12 16:34:26 GMT 2012
                     0x40B3D650
                     generationid_191393288
                  
               
               
                  asy_generator
                  
                     ./v6_afifo_256x36.asy
                     asy
                     Mon Mar 12 16:34:31 GMT 2012
                     0xF028BBDB
                     generationid_191393288
                  
               
               
                  xmdf_generator
                  
                     ./v6_afifo_256x36_xmdf.tcl
                     tclXmdf
                     tcl
                     Mon Mar 12 16:34:31 GMT 2012
                     0x735E26A6
                     generationid_191393288
                  
               
               
                  ise_generator
                  
                     ./_xmsgs/pn_parser.xmsgs
                     ignore
                     unknown
                     Mon Mar 12 16:34:47 GMT 2012
                     0x5F0866EC
                     generationid_191393288
                  
                  
                     ./v6_afifo_256x36.gise
                     ignore
                     gise
                     Mon Mar 12 16:34:47 GMT 2012
                     0x21137287
                     generationid_191393288
                  
                  
                     ./v6_afifo_256x36.xise
                     ignore
                     xise
                     Mon Mar 12 16:34:47 GMT 2012
                     0x5F0AFC16
                     generationid_191393288
                  
               
               
                  deliver_readme_generator
               
               
                  flist_generator
                  
                     ./v6_afifo_256x36_flist.txt
                     ignore
                     txtFlist
                     txt
                     Mon Mar 12 16:34:47 GMT 2012
                     0xA5748A27
                     generationid_191393288
                  
               
            
         
      
      
         v6_afifo_256x36c_fwft
         Fifo Generator
         The FIFO Generator is a parameterizable first-in/first-out memory queue generator. Use it to generate resource and performance optimized FIFOs with common or independent read/write clock domains, and optional fixed or programmable full and empty flags and handshaking signals.  Choose from a selection of memory resource types for implementation.  Optional Hamming code based error detection and correction as well as error injection capability for system test help to insure data integrity.  FIFO width and depth are parameterizable, and for native interface FIFOs, asymmetric read and write port widths are also supported.
         
         
            v6_afifo_256x36c_fwft
            Independent_Clocks_Block_RAM
            Native
            First_Word_Fall_Through
            36
            512
            36
            512
            false
            false
            true
            true
            Asynchronous_Reset
            1
            true
            0
            false
            false
            false
            Active_High
            false
            Active_High
            false
            Active_High
            false
            Active_High
            false
            false
            false
            false
            9
            false
            9
            true
            9
            false
            1
            1
            Single_Programmable_Full_Threshold_Constant
            320
            319
            Single_Programmable_Empty_Threshold_Constant
            8
            9
            AXI4_Stream
            Common_Clock
            false
            Slave_Interface_Clock_Enable
            false
            false
            4
            32
            64
            false
            1
            false
            1
            false
            1
            false
            1
            false
            1
            false
            64
            false
            8
            false
            4
            false
            4
            true
            false
            false
            4
            false
            4
            FIFO
            Common_Clock_Block_RAM
            Data_FIFO
            false
            false
            false
            16
            false
            false
            Full
            1023
            Empty
            1022
            FIFO
            Common_Clock_Block_RAM
            Data_FIFO
            false
            false
            false
            1024
            false
            false
            Full
            1023
            Empty
            1022
            FIFO
            Common_Clock_Block_RAM
            Data_FIFO
            false
            false
            false
            16
            false
            false
            Full
            1023
            Empty
            1022
            FIFO
            Common_Clock_Block_RAM
            Data_FIFO
            false
            false
            false
            16
            false
            false
            Full
            1023
            Empty
            1022
            FIFO
            Common_Clock_Block_RAM
            Data_FIFO
            false
            false
            false
            1024
            false
            false
            Full
            1023
            Empty
            1022
            FIFO
            Common_Clock_Block_RAM
            Data_FIFO
            false
            false
            false
            1024
            false
            false
            Full
            1023
            Empty
            1022
            Fully_Registered
            Fully_Registered
            Fully_Registered
            Fully_Registered
            Fully_Registered
            Fully_Registered
            false
            Active_High
            false
            Active_High
            false
            false
            false
            false
            false
            0
            9
            36
            0
            36
            virtex6
            1
            0
            0
            0
            0
            0
            1
            1
            0
            0
            0
            0
            0
            2
            1
            0
            0
            1
            512x36
            8
            9
            1
            320
            319
            1
            9
            512
            1
            9
            0
            1
            0
            0
            0
            0
            0
            9
            512
            1
            9
            1
            1
            0
            0
            0
            0
            0
            0
            0
            0
            0
            0
            4
            32
            64
            0
            0
            0
            0
            0
            1
            1
            1
            1
            1
            0
            0
            0
            0
            1
            0
            0
            0
            64
            8
            4
            4
            4
            4
            0
            0
            0
            0
            0
            0
            1
            1
            1
            1
            1
            1
            0
            0
            0
            0
            0
            0
            0
            0
            0
            0
            0
            0
            0
            0
            0
            0
            0
            0
            32
            64
            2
            32
            64
            1
            16
            1024
            16
            16
            1024
            1024
            4
            10
            4
            4
            10
            10
            0
            0
            0
            0
            0
            0
            0
            0
            0
            0
            0
            0
            5
            5
            5
            5
            5
            5
            1023
            1023
            1023
            1023
            1023
            1023
            5
            5
            5
            5
            5
            5
            1022
            1022
            1022
            1022
            1022
            1022
            0
            0
            0
            0
            0
            0
         
         
            
               
                  coregen
                  ./
                  ./tmp/
                  ./tmp/_cg/
               
               
                  xc6vlx240t
                  virtex6
                  ff1156
                  -1
               
               
                  BusFormatAngleBracketNotRipped
                  VHDL
                  true
                  Foundation_ISE
                  false
                  false
                  false
                  Ngc
                  false
               
               
                  Behavioral
                  VHDL_and_Verilog
                  false
               
               
                  2011-03-14T07:12:32.000Z
               
            
            
               
                  ip_upgrade_generator
                  
                     ./v6_afifo_256x36c_fwft_upgrade.txt
                     txt
                     Mon Mar 12 16:35:18 GMT 2012
                     0x233E35D8
                     generationid_868397911
                  
               
               
                  view_upgrade_report_generator
               
               
                  model_parameter_resolution_generator
               
               
                  ip_xco_generator
                  
                     ./v6_afifo_256x36c_fwft.xco
                     xco
                     Mon Mar 12 16:35:26 GMT 2012
                     0x58BC9B43
                     generationid_868397911
                  
               
               
                  associated_files_generator
                  
                     ./fifo_generator_ug175.pdf
                     pdf
                     Tue Oct 04 23:21:33 GMT 2011
                     0x42070F84
                     generationid_868397911
                  
                  
                     ./fifo_generator_v8_3_readme.txt
                     txt
                     Tue Oct 04 23:21:33 GMT 2011
                     0xCD35AB83
                     generationid_868397911
                  
               
               
                  ejava_generator
                  
                     ./v6_afifo_256x36c_fwft_ste/example_design/v6_afifo_256x36c_fwft_top.ucf
                     ignore
                     ucf
                     Mon Mar 12 16:35:27 GMT 2012
                     0xB0FB4AAF
                     generationid_868397911
                  
                  
                     ./v6_afifo_256x36c_fwft_ste/example_design/v6_afifo_256x36c_fwft_top.vhd
                     ignore
                     vhdl
                     Mon Mar 12 16:35:27 GMT 2012
                     0x3929C5D1
                     generationid_868397911
                  
                  
                     ./v6_afifo_256x36c_fwft_ste/example_design/v6_afifo_256x36c_fwft_top.xdc
                     ignore
                     xdc
                     Mon Mar 12 16:35:27 GMT 2012
                     0xA1CB2F49
                     generationid_868397911
                  
                  
                     ./v6_afifo_256x36c_fwft_ste/implement/implement.bat
                     ignore
                     unknown
                     Mon Mar 12 16:35:27 GMT 2012
                     0x2231F750
                     generationid_868397911
                  
                  
                     ./v6_afifo_256x36c_fwft_ste/implement/implement.sh
                     ignore
                     unknown
                     Mon Mar 12 16:35:27 GMT 2012
                     0x1F7C9EED
                     generationid_868397911
                  
                  
                     ./v6_afifo_256x36c_fwft_ste/implement/planAhead_rdn.bat
                     ignore
                     unknown
                     Mon Mar 12 16:35:27 GMT 2012
                     0xA2ADD42D
                     generationid_868397911
                  
                  
                     ./v6_afifo_256x36c_fwft_ste/implement/planAhead_rdn.sh
                     ignore
                     unknown
                     Mon Mar 12 16:35:27 GMT 2012
                     0x7AC68DF6
                     generationid_868397911
                  
                  
                     ./v6_afifo_256x36c_fwft_ste/implement/planAhead_rdn.tcl
                     ignore
                     tcl
                     Mon Mar 12 16:35:27 GMT 2012
                     0x423335B0
                     generationid_868397911
                  
                  
                     ./v6_afifo_256x36c_fwft_ste/implement/xst.prj
                     ignore
                     unknown
                     Mon Mar 12 16:35:27 GMT 2012
                     0x57CC4E14
                     generationid_868397911
                  
                  
                     ./v6_afifo_256x36c_fwft_ste/implement/xst.scr
                     ignore
                     unknown
                     Mon Mar 12 16:35:27 GMT 2012
                     0xFA3827C9
                     generationid_868397911
                  
               
               
                  ngc_netlist_generator
                  
                     ./v6_afifo_256x36c_fwft.ngc
                     ngc
                     Mon Mar 12 16:36:53 GMT 2012
                     0xAC28261D
                     generationid_868397911
                  
               
               
                  obfuscate_netlist_generator
               
               
                  padded_implementation_netlist_generator
               
               
                  instantiation_template_generator
                  
                     ./v6_afifo_256x36c_fwft.veo
                     veo
                     Mon Mar 12 16:36:55 GMT 2012
                     0x40F2612B
                     generationid_868397911
                  
                  
                     ./v6_afifo_256x36c_fwft.vho
                     vho
                     Mon Mar 12 16:36:55 GMT 2012
                     0xA334A8DC
                     generationid_868397911
                  
               
               
                  structural_simulation_model_generator
                  
                     ./v6_afifo_256x36c_fwft.v
                     verilog
                     Mon Mar 12 16:36:55 GMT 2012
                     0xB3348EFD
                     generationid_868397911
                  
                  
                     ./v6_afifo_256x36c_fwft.vhd
                     vhdl
                     Mon Mar 12 16:36:55 GMT 2012
                     0xF0365E76
                     generationid_868397911
                  
               
               
                  asy_generator
                  
                     ./v6_afifo_256x36c_fwft.asy
                     asy
                     Mon Mar 12 16:37:00 GMT 2012
                     0x7CCD393F
                     generationid_868397911
                  
               
               
                  xmdf_generator
                  
                     ./v6_afifo_256x36c_fwft_xmdf.tcl
                     tclXmdf
                     tcl
                     Mon Mar 12 16:37:00 GMT 2012
                     0x3223D43C
                     generationid_868397911
                  
               
               
                  ise_generator
                  
                     ./_xmsgs/pn_parser.xmsgs
                     ignore
                     unknown
                     Mon Mar 12 16:37:05 GMT 2012
                     0x8F132F2F
                     generationid_868397911
                  
                  
                     ./v6_afifo_256x36c_fwft.gise
                     ignore
                     gise
                     Mon Mar 12 16:37:06 GMT 2012
                     0x5A618648
                     generationid_868397911
                  
                  
                     ./v6_afifo_256x36c_fwft.xise
                     ignore
                     xise
                     Mon Mar 12 16:37:06 GMT 2012
                     0xCF4348E9
                     generationid_868397911
                  
               
               
                  deliver_readme_generator
               
               
                  flist_generator
                  
                     ./v6_afifo_256x36c_fwft_flist.txt
                     ignore
                     txtFlist
                     txt
                     Mon Mar 12 16:37:06 GMT 2012
                     0xCA35C0E4
                     generationid_868397911
                  
               
            
         
      
      
         v6_afifo_8x8
         Fifo Generator
         The FIFO Generator is a parameterizable first-in/first-out memory queue generator. Use it to generate resource and performance optimized FIFOs with common or independent read/write clock domains, and optional fixed or programmable full and empty flags and handshaking signals.  Choose from a selection of memory resource types for implementation.  Optional Hamming code based error detection and correction as well as error injection capability for system test help to insure data integrity.  FIFO width and depth are parameterizable, and for native interface FIFOs, asymmetric read and write port widths are also supported.
         
         
            v6_afifo_8x8
            Independent_Clocks_Distributed_RAM
            Native
            Standard_FIFO
            8
            16
            8
            16
            false
            false
            true
            true
            Asynchronous_Reset
            1
            true
            0
            false
            false
            false
            Active_High
            false
            Active_High
            false
            Active_High
            false
            Active_High
            false
            false
            false
            false
            4
            false
            4
            false
            4
            false
            1
            1
            No_Programmable_Full_Threshold
            13
            12
            No_Programmable_Empty_Threshold
            2
            3
            AXI4_Stream
            Common_Clock
            false
            Slave_Interface_Clock_Enable
            false
            false
            4
            32
            64
            false
            1
            false
            1
            false
            1
            false
            1
            false
            1
            false
            64
            false
            8
            false
            4
            false
            4
            true
            false
            false
            4
            false
            4
            FIFO
            Common_Clock_Block_RAM
            Data_FIFO
            false
            false
            false
            16
            false
            false
            Full
            1023
            Empty
            1022
            FIFO
            Common_Clock_Block_RAM
            Data_FIFO
            false
            false
            false
            1024
            false
            false
            Full
            1023
            Empty
            1022
            FIFO
            Common_Clock_Block_RAM
            Data_FIFO
            false
            false
            false
            16
            false
            false
            Full
            1023
            Empty
            1022
            FIFO
            Common_Clock_Block_RAM
            Data_FIFO
            false
            false
            false
            16
            false
            false
            Full
            1023
            Empty
            1022
            FIFO
            Common_Clock_Block_RAM
            Data_FIFO
            false
            false
            false
            1024
            false
            false
            Full
            1023
            Empty
            1022
            FIFO
            Common_Clock_Block_RAM
            Data_FIFO
            false
            false
            false
            1024
            false
            false
            Full
            1023
            Empty
            1022
            Fully_Registered
            Fully_Registered
            Fully_Registered
            Fully_Registered
            Fully_Registered
            Fully_Registered
            false
            Active_High
            false
            Active_High
            false
            false
            false
            false
            false
            0
            4
            8
            0
            8
            virtex6
            1
            0
            0
            0
            0
            0
            0
            1
            0
            0
            0
            0
            0
            2
            2
            0
            1
            0
            512x36
            2
            3
            0
            13
            12
            0
            4
            16
            1
            4
            0
            1
            0
            0
            0
            0
            0
            4
            16
            1
            4
            1
            1
            0
            0
            0
            0
            0
            0
            0
            0
            0
            0
            4
            32
            64
            0
            0
            0
            0
            0
            1
            1
            1
            1
            1
            0
            0
            0
            0
            1
            0
            0
            0
            64
            8
            4
            4
            4
            4
            0
            0
            0
            0
            0
            0
            1
            1
            1
            1
            1
            1
            0
            0
            0
            0
            0
            0
            0
            0
            0
            0
            0
            0
            0
            0
            0
            0
            0
            0
            32
            64
            2
            32
            64
            1
            16
            1024
            16
            16
            1024
            1024
            4
            10
            4
            4
            10
            10
            0
            0
            0
            0
            0
            0
            0
            0
            0
            0
            0
            0
            5
            5
            5
            5
            5
            5
            1023
            1023
            1023
            1023
            1023
            1023
            5
            5
            5
            5
            5
            5
            1022
            1022
            1022
            1022
            1022
            1022
            0
            0
            0
            0
            0
            0
         
         
            
               
                  coregen
                  ./
                  ./tmp/
                  ./tmp/_cg/
               
               
                  xc6vlx240t
                  virtex6
                  ff1156
                  -1
               
               
                  BusFormatAngleBracketNotRipped
                  VHDL
                  true
                  Foundation_ISE
                  false
                  false
                  false
                  Ngc
                  false
               
               
                  Behavioral
                  VHDL_and_Verilog
                  false
               
               
                  2011-03-14T07:12:32.000Z
               
            
            
               
                  ip_upgrade_generator
                  
                     ./v6_afifo_8x8_upgrade.txt
                     txt
                     Mon Mar 12 16:37:13 GMT 2012
                     0xAE5F43DC
                     generationid_2776375893
                  
               
               
                  view_upgrade_report_generator
               
               
                  model_parameter_resolution_generator
               
               
                  ip_xco_generator
                  
                     ./v6_afifo_8x8.xco
                     xco
                     Mon Mar 12 16:37:21 GMT 2012
                     0xEF2922A0
                     generationid_2776375893
                  
               
               
                  associated_files_generator
                  
                     ./fifo_generator_ug175.pdf
                     pdf
                     Tue Oct 04 23:21:33 GMT 2011
                     0x42070F84
                     generationid_2776375893
                  
                  
                     ./fifo_generator_v8_3_readme.txt
                     txt
                     Tue Oct 04 23:21:33 GMT 2011
                     0xCD35AB83
                     generationid_2776375893
                  
               
               
                  ejava_generator
                  
                     ./v6_afifo_8x8_ste/example_design/v6_afifo_8x8_top.ucf
                     ignore
                     ucf
                     Mon Mar 12 16:37:22 GMT 2012
                     0xB0FB4AAF
                     generationid_2776375893
                  
                  
                     ./v6_afifo_8x8_ste/example_design/v6_afifo_8x8_top.vhd
                     ignore
                     vhdl
                     Mon Mar 12 16:37:22 GMT 2012
                     0x6923F236
                     generationid_2776375893
                  
                  
                     ./v6_afifo_8x8_ste/example_design/v6_afifo_8x8_top.xdc
                     ignore
                     xdc
                     Mon Mar 12 16:37:22 GMT 2012
                     0xA1CB2F49
                     generationid_2776375893
                  
                  
                     ./v6_afifo_8x8_ste/implement/implement.bat
                     ignore
                     unknown
                     Mon Mar 12 16:37:22 GMT 2012
                     0x414797B1
                     generationid_2776375893
                  
                  
                     ./v6_afifo_8x8_ste/implement/implement.sh
                     ignore
                     unknown
                     Mon Mar 12 16:37:22 GMT 2012
                     0x78A5E10C
                     generationid_2776375893
                  
                  
                     ./v6_afifo_8x8_ste/implement/planAhead_rdn.bat
                     ignore
                     unknown
                     Mon Mar 12 16:37:22 GMT 2012
                     0xEA6E7A23
                     generationid_2776375893
                  
                  
                     ./v6_afifo_8x8_ste/implement/planAhead_rdn.sh
                     ignore
                     unknown
                     Mon Mar 12 16:37:22 GMT 2012
                     0x0B401B6B
                     generationid_2776375893
                  
                  
                     ./v6_afifo_8x8_ste/implement/planAhead_rdn.tcl
                     ignore
                     tcl
                     Mon Mar 12 16:37:22 GMT 2012
                     0x38B322A2
                     generationid_2776375893
                  
                  
                     ./v6_afifo_8x8_ste/implement/xst.prj
                     ignore
                     unknown
                     Mon Mar 12 16:37:22 GMT 2012
                     0x17B3BE6C
                     generationid_2776375893
                  
                  
                     ./v6_afifo_8x8_ste/implement/xst.scr
                     ignore
                     unknown
                     Mon Mar 12 16:37:22 GMT 2012
                     0x4573F144
                     generationid_2776375893
                  
               
               
                  ngc_netlist_generator
                  
                     ./v6_afifo_8x8.ngc
                     ngc
                     Mon Mar 12 16:38:39 GMT 2012
                     0xB963E129
                     generationid_2776375893
                  
               
               
                  obfuscate_netlist_generator
               
               
                  padded_implementation_netlist_generator
               
               
                  instantiation_template_generator
                  
                     ./v6_afifo_8x8.veo
                     veo
                     Mon Mar 12 16:38:40 GMT 2012
                     0x8F7D80C1
                     generationid_2776375893
                  
                  
                     ./v6_afifo_8x8.vho
                     vho
                     Mon Mar 12 16:38:40 GMT 2012
                     0x227CE66D
                     generationid_2776375893
                  
               
               
                  structural_simulation_model_generator
                  
                     ./v6_afifo_8x8.v
                     verilog
                     Mon Mar 12 16:38:41 GMT 2012
                     0x608C2E64
                     generationid_2776375893
                  
                  
                     ./v6_afifo_8x8.vhd
                     vhdl
                     Mon Mar 12 16:38:41 GMT 2012
                     0xF1049D72
                     generationid_2776375893
                  
               
               
                  asy_generator
                  
                     ./v6_afifo_8x8.asy
                     asy
                     Mon Mar 12 16:38:45 GMT 2012
                     0x1D22D7F4
                     generationid_2776375893
                  
               
               
                  xmdf_generator
                  
                     ./v6_afifo_8x8_xmdf.tcl
                     tclXmdf
                     tcl
                     Mon Mar 12 16:38:45 GMT 2012
                     0x15B20DCF
                     generationid_2776375893
                  
               
               
                  ise_generator
                  
                     ./_xmsgs/pn_parser.xmsgs
                     ignore
                     unknown
                     Mon Mar 12 16:38:50 GMT 2012
                     0xA7BEA588
                     generationid_2776375893
                  
                  
                     ./v6_afifo_8x8.gise
                     ignore
                     gise
                     Mon Mar 12 16:38:50 GMT 2012
                     0x7B68AC78
                     generationid_2776375893
                  
                  
                     ./v6_afifo_8x8.xise
                     ignore
                     xise
                     Mon Mar 12 16:38:50 GMT 2012
                     0x59508203
                     generationid_2776375893
                  
               
               
                  deliver_readme_generator
               
               
                  flist_generator
                  
                     ./v6_afifo_8x8_flist.txt
                     ignore
                     txtFlist
                     txt
                     Mon Mar 12 16:38:51 GMT 2012
                     0x4C6DDE12
                     generationid_2776375893
                  
               
            
         
      
      
         v6_bram4096x64
         Block Memory Generator
         The Xilinx LogiCORE IP Block Memory Generator replaces the Dual Port Block Memory and Single Port Block Memory LogiCOREs, but is not a direct drop-in replacement.  It should be used in all new Xilinx designs. The core supports RAM and ROM functions over a wide range of widths and depths. Use this core to generate block memories with symmetric or asymmetric read and write port widths, as well as cores which can perform simultaneous write operations to separate locations, and simultaneous read operations from the same location. For more information on differences in interface and feature support between this core and the Dual Port Block Memory and Single Port Block Memory LogiCOREs, please consult the data sheet.
         
         
            v6_bram4096x64
            Native
            AXI4_Full
            Memory_Slave
            false
            4
            True_Dual_Port_RAM
            No_ECC
            false
            false
            false
            Single_Bit_Error_Injection
            true
            8
            Minimum_Area
            8kx2
            false
            64
            4096
            64
            WRITE_FIRST
            Always_Enabled
            64
            64
            WRITE_FIRST
            Always_Enabled
            false
            false
            false
            true
            false
            false
            false
            false
            0
            false
            no_coe_file_loaded
            false
            0
            false
            false
            CE
            0
            false
            false
            CE
            0
            SYNC
            false
            100
            50
            100
            50
            100
            100
            ALL
            false
            false
            virtex6
            virtex6
            C:/Temp/Xilinx PCI Express/pcie-v6-ml605_ISE13_User/ipcore_dir_update/tmp/_cg/
            0
            1
            0
            0
            4
            2
            8
            1
            1
            0
            no_coe_file_loaded
            0
            0
            SYNC
            0
            CE
            0
            0
            0
            0
            1
            8
            WRITE_FIRST
            64
            64
            4096
            4096
            12
            0
            CE
            0
            0
            0
            0
            1
            8
            WRITE_FIRST
            64
            64
            4096
            4096
            12
            0
            1
            0
            0
            0
            0
            0
            0
            0
            0
            ALL
            0
            0
            0
         
         
            
               
                  coregen
                  ./
                  ./tmp/
                  ./tmp/_cg/
               
               
                  xc6vlx240t
                  virtex6
                  ff1156
                  -1
               
               
                  BusFormatAngleBracketNotRipped
                  VHDL
                  true
                  Foundation_ISE
                  false
                  false
                  false
                  Ngc
                  false
               
               
                  Behavioral
                  VHDL_and_Verilog
                  false
               
               
                  2011-03-11T08:24:14.000Z
               
            
            
               
                  ip_upgrade_generator
                  
                     ./v6_bram4096x64_upgrade.txt
                     txt
                     Mon Mar 12 17:05:45 GMT 2012
                     0x4DD59F1C
                     generationid_2628640656
                  
               
               
                  view_upgrade_report_generator
               
               
                  model_parameter_resolution_generator
                  
                     ./summary.log
                     unknown
                     Mon Mar 12 17:05:51 GMT 2012
                     0x724D9538
                     generationid_2628640656
                  
               
               
                  ip_xco_generator
                  
                     ./v6_bram4096x64.xco
                     xco
                     Mon Mar 12 17:05:51 GMT 2012
                     0x71864271
                     generationid_2628640656
                  
               
               
                  associated_files_generator
                  
                     ./blk_mem_gen_ds512.pdf
                     pdf
                     Tue Oct 04 23:21:26 GMT 2011
                     0xA43B8952
                     generationid_2628640656
                  
                  
                     ./blk_mem_gen_v6_2_readme.txt
                     txt
                     Tue Oct 04 23:21:26 GMT 2011
                     0x399E1D72
                     generationid_2628640656
                  
               
               
                  ejava_generator
                  
                     ./v6_bram4096x64_ste/example_design/bmg_wrapper.vhd
                     ignore
                     vhdl
                     Mon Mar 12 17:05:53 GMT 2012
                     0xC1BCB7D7
                     generationid_2628640656
                  
                  
                     ./v6_bram4096x64_ste/example_design/v6_bram4096x64_top.ucf
                     ignore
                     ucf
                     Mon Mar 12 17:05:53 GMT 2012
                     0x8915DFA1
                     generationid_2628640656
                  
                  
                     ./v6_bram4096x64_ste/example_design/v6_bram4096x64_top.vhd
                     ignore
                     vhdl
                     Mon Mar 12 17:05:53 GMT 2012
                     0xBD41FE10
                     generationid_2628640656
                  
                  
                     ./v6_bram4096x64_ste/example_design/v6_bram4096x64_top.xdc
                     ignore
                     xdc
                     Mon Mar 12 17:05:52 GMT 2012
                     0x78E2D49A
                     generationid_2628640656
                  
                  
                     ./v6_bram4096x64_ste/implement/implement.bat
                     ignore
                     unknown
                     Mon Mar 12 17:05:53 GMT 2012
                     0xB4DA0A6E
                     generationid_2628640656
                  
                  
                     ./v6_bram4096x64_ste/implement/implement.sh
                     ignore
                     unknown
                     Mon Mar 12 17:05:53 GMT 2012
                     0x82AAF119
                     generationid_2628640656
                  
                  
                     ./v6_bram4096x64_ste/implement/planAhead_rdn.bat
                     ignore
                     unknown
                     Mon Mar 12 17:05:53 GMT 2012
                     0xB1B38E28
                     generationid_2628640656
                  
                  
                     ./v6_bram4096x64_ste/implement/planAhead_rdn.sh
                     ignore
                     unknown
                     Mon Mar 12 17:05:53 GMT 2012
                     0x0193BB32
                     generationid_2628640656
                  
                  
                     ./v6_bram4096x64_ste/implement/planAhead_rdn.tcl
                     ignore
                     tcl
                     Mon Mar 12 17:05:53 GMT 2012
                     0x6E89856B
                     generationid_2628640656
                  
                  
                     ./v6_bram4096x64_ste/implement/xst.prj
                     ignore
                     unknown
                     Mon Mar 12 17:05:53 GMT 2012
                     0xE787D002
                     generationid_2628640656
                  
                  
                     ./v6_bram4096x64_ste/implement/xst.scr
                     ignore
                     unknown
                     Mon Mar 12 17:05:53 GMT 2012
                     0xB3D7E20E
                     generationid_2628640656
                  
               
               
                  ngc_netlist_generator
                  
                     ./v6_bram4096x64.ngc
                     ngc
                     Mon Mar 12 17:06:44 GMT 2012
                     0x55157413
                     generationid_2628640656
                  
               
               
                  obfuscate_netlist_generator
               
               
                  padded_implementation_netlist_generator
               
               
                  instantiation_template_generator
                  
                     ./v6_bram4096x64.veo
                     veo
                     Mon Mar 12 17:06:46 GMT 2012
                     0xA95F455A
                     generationid_2628640656
                  
                  
                     ./v6_bram4096x64.vho
                     vho
                     Mon Mar 12 17:06:46 GMT 2012
                     0xAA3E2BD4
                     generationid_2628640656
                  
               
               
                  structural_simulation_model_generator
                  
                     ./v6_bram4096x64.v
                     verilog
                     Mon Mar 12 17:06:46 GMT 2012
                     0x832FB6C7
                     generationid_2628640656
                  
                  
                     ./v6_bram4096x64.vhd
                     vhdl
                     Mon Mar 12 17:06:46 GMT 2012
                     0x5A594C75
                     generationid_2628640656
                  
               
               
                  asy_generator
                  
                     ./summary.log
                     unknown
                     Mon Mar 12 17:06:51 GMT 2012
                     0x724D9538
                     generationid_2628640656
                  
                  
                     ./v6_bram4096x64.asy
                     asy
                     Mon Mar 12 17:06:51 GMT 2012
                     0xF60CFE5D
                     generationid_2628640656
                  
               
               
                  xmdf_generator
                  
                     ./v6_bram4096x64_xmdf.tcl
                     tclXmdf
                     tcl
                     Mon Mar 12 17:06:51 GMT 2012
                     0x7B6B2503
                     generationid_2628640656
                  
               
               
                  ise_generator
                  
                     ./_xmsgs/pn_parser.xmsgs
                     ignore
                     unknown
                     Mon Mar 12 17:06:56 GMT 2012
                     0x2020DF34
                     generationid_2628640656
                  
                  
                     ./v6_bram4096x64.gise
                     ignore
                     gise
                     Mon Mar 12 17:06:56 GMT 2012
                     0x3438226F
                     generationid_2628640656
                  
                  
                     ./v6_bram4096x64.xise
                     ignore
                     xise
                     Mon Mar 12 17:06:56 GMT 2012
                     0x6233B914
                     generationid_2628640656
                  
               
               
                  deliver_readme_generator
               
               
                  flist_generator
                  
                     ./v6_bram4096x64_flist.txt
                     ignore
                     txtFlist
                     txt
                     Mon Mar 12 17:06:56 GMT 2012
                     0x78F62361
                     generationid_2628640656
                  
               
            
         
      
      
         v6_bram4096x64_fast
         Block Memory Generator
         The Xilinx LogiCORE IP Block Memory Generator replaces the Dual Port Block Memory and Single Port Block Memory LogiCOREs, but is not a direct drop-in replacement.  It should be used in all new Xilinx designs. The core supports RAM and ROM functions over a wide range of widths and depths. Use this core to generate block memories with symmetric or asymmetric read and write port widths, as well as cores which can perform simultaneous write operations to separate locations, and simultaneous read operations from the same location. For more information on differences in interface and feature support between this core and the Dual Port Block Memory and Single Port Block Memory LogiCOREs, please consult the data sheet.
         
         
            v6_bram4096x64_fast
            Native
            AXI4_Full
            Memory_Slave
            false
            4
            True_Dual_Port_RAM
            No_ECC
            false
            false
            false
            Single_Bit_Error_Injection
            true
            8
            Minimum_Area
            8kx2
            false
            64
            4096
            64
            WRITE_FIRST
            Always_Enabled
            64
            64
            WRITE_FIRST
            Always_Enabled
            false
            false
            false
            false
            false
            false
            false
            false
            0
            false
            no_coe_file_loaded
            false
            0
            false
            false
            CE
            0
            false
            false
            CE
            0
            SYNC
            false
            100
            50
            100
            50
            100
            100
            ALL
            false
            false
            virtex6
            virtex6
            C:/Temp/Xilinx PCI Express/pcie-v6-ml605_ISE13_User/ipcore_dir_update/tmp/_cg/
            0
            1
            0
            0
            4
            2
            8
            1
            1
            0
            no_coe_file_loaded
            0
            0
            SYNC
            0
            CE
            0
            0
            0
            0
            1
            8
            WRITE_FIRST
            64
            64
            4096
            4096
            12
            0
            CE
            0
            0
            0
            0
            1
            8
            WRITE_FIRST
            64
            64
            4096
            4096
            12
            0
            0
            0
            0
            0
            0
            0
            0
            0
            0
            ALL
            0
            0
            0
         
         
            
               
                  coregen
                  ./
                  ./tmp/
                  ./tmp/_cg/
               
               
                  xc6vlx240t
                  virtex6
                  ff1156
                  -1
               
               
                  BusFormatAngleBracketNotRipped
                  VHDL
                  true
                  Foundation_ISE
                  false
                  false
                  false
                  Ngc
                  false
               
               
                  Behavioral
                  VHDL_and_Verilog
                  false
               
               
                  2011-03-11T08:24:14.000Z
               
            
            
               
                  ip_upgrade_generator
                  
                     ./v6_bram4096x64_fast_upgrade.txt
                     txt
                     Mon Mar 12 17:07:10 GMT 2012
                     0xA0948C53
                     generationid_2692897682
                  
               
               
                  view_upgrade_report_generator
               
               
                  model_parameter_resolution_generator
                  
                     ./summary.log
                     unknown
                     Mon Mar 12 17:07:16 GMT 2012
                     0x724D9538
                     generationid_2692897682
                  
               
               
                  ip_xco_generator
                  
                     ./v6_bram4096x64_fast.xco
                     xco
                     Mon Mar 12 17:07:16 GMT 2012
                     0xDBA2297A
                     generationid_2692897682
                  
               
               
                  associated_files_generator
                  
                     ./blk_mem_gen_ds512.pdf
                     pdf
                     Tue Oct 04 23:21:26 GMT 2011
                     0xA43B8952
                     generationid_2692897682
                  
                  
                     ./blk_mem_gen_v6_2_readme.txt
                     txt
                     Tue Oct 04 23:21:26 GMT 2011
                     0x399E1D72
                     generationid_2692897682
                  
               
               
                  ejava_generator
                  
                     ./v6_bram4096x64_fast_ste/example_design/bmg_wrapper.vhd
                     ignore
                     vhdl
                     Mon Mar 12 17:07:17 GMT 2012
                     0xEF9A84BF
                     generationid_2692897682
                  
                  
                     ./v6_bram4096x64_fast_ste/example_design/v6_bram4096x64_fast_top.ucf
                     ignore
                     ucf
                     Mon Mar 12 17:07:17 GMT 2012
                     0x8915DFA1
                     generationid_2692897682
                  
                  
                     ./v6_bram4096x64_fast_ste/example_design/v6_bram4096x64_fast_top.vhd
                     ignore
                     vhdl
                     Mon Mar 12 17:07:17 GMT 2012
                     0xD140BB94
                     generationid_2692897682
                  
                  
                     ./v6_bram4096x64_fast_ste/example_design/v6_bram4096x64_fast_top.xdc
                     ignore
                     xdc
                     Mon Mar 12 17:07:17 GMT 2012
                     0x78E2D49A
                     generationid_2692897682
                  
                  
                     ./v6_bram4096x64_fast_ste/implement/implement.bat
                     ignore
                     unknown
                     Mon Mar 12 17:07:17 GMT 2012
                     0x06D6741B
                     generationid_2692897682
                  
                  
                     ./v6_bram4096x64_fast_ste/implement/implement.sh
                     ignore
                     unknown
                     Mon Mar 12 17:07:17 GMT 2012
                     0xB504602A
                     generationid_2692897682
                  
                  
                     ./v6_bram4096x64_fast_ste/implement/planAhead_rdn.bat
                     ignore
                     unknown
                     Mon Mar 12 17:07:17 GMT 2012
                     0xE84D1EFF
                     generationid_2692897682
                  
                  
                     ./v6_bram4096x64_fast_ste/implement/planAhead_rdn.sh
                     ignore
                     unknown
                     Mon Mar 12 17:07:17 GMT 2012
                     0xDFF223FD
                     generationid_2692897682
                  
                  
                     ./v6_bram4096x64_fast_ste/implement/planAhead_rdn.tcl
                     ignore
                     tcl
                     Mon Mar 12 17:07:17 GMT 2012
                     0x4BBBF52A
                     generationid_2692897682
                  
                  
                     ./v6_bram4096x64_fast_ste/implement/xst.prj
                     ignore
                     unknown
                     Mon Mar 12 17:07:17 GMT 2012
                     0xDAD9BD55
                     generationid_2692897682
                  
                  
                     ./v6_bram4096x64_fast_ste/implement/xst.scr
                     ignore
                     unknown
                     Mon Mar 12 17:07:17 GMT 2012
                     0xC6419EE5
                     generationid_2692897682
                  
               
               
                  ngc_netlist_generator
                  
                     ./v6_bram4096x64_fast.ngc
                     ngc
                     Mon Mar 12 17:08:08 GMT 2012
                     0x74B38A9F
                     generationid_2692897682
                  
               
               
                  obfuscate_netlist_generator
               
               
                  padded_implementation_netlist_generator
               
               
                  instantiation_template_generator
                  
                     ./v6_bram4096x64_fast.veo
                     veo
                     Mon Mar 12 17:08:09 GMT 2012
                     0x7EC8351F
                     generationid_2692897682
                  
                  
                     ./v6_bram4096x64_fast.vho
                     vho
                     Mon Mar 12 17:08:09 GMT 2012
                     0xDB665464
                     generationid_2692897682
                  
               
               
                  structural_simulation_model_generator
                  
                     ./v6_bram4096x64_fast.v
                     verilog
                     Mon Mar 12 17:08:10 GMT 2012
                     0x71A44806
                     generationid_2692897682
                  
                  
                     ./v6_bram4096x64_fast.vhd
                     vhdl
                     Mon Mar 12 17:08:10 GMT 2012
                     0xA7382809
                     generationid_2692897682
                  
               
               
                  asy_generator
                  
                     ./summary.log
                     unknown
                     Mon Mar 12 17:08:15 GMT 2012
                     0x724D9538
                     generationid_2692897682
                  
                  
                     ./v6_bram4096x64_fast.asy
                     asy
                     Mon Mar 12 17:08:15 GMT 2012
                     0x6F5D907A
                     generationid_2692897682
                  
               
               
                  xmdf_generator
                  
                     ./v6_bram4096x64_fast_xmdf.tcl
                     tclXmdf
                     tcl
                     Mon Mar 12 17:08:15 GMT 2012
                     0xCDCF7247
                     generationid_2692897682
                  
               
               
                  ise_generator
                  
                     ./_xmsgs/pn_parser.xmsgs
                     ignore
                     unknown
                     Mon Mar 12 17:08:20 GMT 2012
                     0xA4981814
                     generationid_2692897682
                  
                  
                     ./v6_bram4096x64_fast.gise
                     ignore
                     gise
                     Mon Mar 12 17:08:20 GMT 2012
                     0x6716109C
                     generationid_2692897682
                  
                  
                     ./v6_bram4096x64_fast.xise
                     ignore
                     xise
                     Mon Mar 12 17:08:20 GMT 2012
                     0x0ACE39A2
                     generationid_2692897682
                  
               
               
                  deliver_readme_generator
               
               
                  flist_generator
                  
                     ./v6_bram4096x64_fast_flist.txt
                     ignore
                     txtFlist
                     txt
                     Mon Mar 12 17:08:20 GMT 2012
                     0xBC0AE373
                     generationid_2692897682
                  
               
            
         
      
      
         v6_eb_fifo_counted
         Fifo Generator
         The FIFO Generator is a parameterizable first-in/first-out memory queue generator. Use it to generate resource and performance optimized FIFOs with common or independent read/write clock domains, and optional fixed or programmable full and empty flags and handshaking signals.  Choose from a selection of memory resource types for implementation.  Optional Hamming code based error detection and correction as well as error injection capability for system test help to insure data integrity.  FIFO width and depth are parameterizable, and for native interface FIFOs, asymmetric read and write port widths are also supported.
         
         
            v6_eb_fifo_counted
            Independent_Clocks_Block_RAM
            Native
            Standard_FIFO
            72
            16384
            72
            16384
            false
            false
            true
            true
            Asynchronous_Reset
            1
            true
            0
            false
            false
            false
            Active_High
            false
            Active_High
            false
            Active_High
            false
            Active_High
            false
            false
            false
            false
            14
            false
            14
            true
            14
            false
            1
            1
            Single_Programmable_Full_Threshold_Constant
            12287
            12286
            Single_Programmable_Empty_Threshold_Constant
            4096
            4097
            AXI4_Stream
            Common_Clock
            false
            Slave_Interface_Clock_Enable
            false
            false
            4
            32
            64
            false
            1
            false
            1
            false
            1
            false
            1
            false
            1
            false
            64
            false
            8
            false
            4
            false
            4
            true
            false
            false
            4
            false
            4
            FIFO
            Common_Clock_Block_RAM
            Data_FIFO
            false
            false
            false
            16
            false
            false
            Full
            1023
            Empty
            1022
            FIFO
            Common_Clock_Block_RAM
            Data_FIFO
            false
            false
            false
            1024
            false
            false
            Full
            1023
            Empty
            1022
            FIFO
            Common_Clock_Block_RAM
            Data_FIFO
            false
            false
            false
            16
            false
            false
            Full
            1023
            Empty
            1022
            FIFO
            Common_Clock_Block_RAM
            Data_FIFO
            false
            false
            false
            16
            false
            false
            Full
            1023
            Empty
            1022
            FIFO
            Common_Clock_Block_RAM
            Data_FIFO
            false
            false
            false
            1024
            false
            false
            Full
            1023
            Empty
            1022
            FIFO
            Common_Clock_Block_RAM
            Data_FIFO
            false
            false
            false
            1024
            false
            false
            Full
            1023
            Empty
            1022
            Fully_Registered
            Fully_Registered
            Fully_Registered
            Fully_Registered
            Fully_Registered
            Fully_Registered
            false
            Active_High
            false
            Active_High
            false
            false
            false
            false
            false
            0
            14
            72
            0
            72
            virtex6
            1
            0
            0
            0
            0
            0
            1
            1
            0
            0
            0
            0
            0
            2
            1
            0
            1
            0
            4kx9
            4096
            4097
            1
            12287
            12286
            1
            14
            16384
            1
            14
            0
            1
            0
            0
            0
            0
            0
            14
            16384
            1
            14
            1
            1
            0
            0
            0
            0
            0
            0
            0
            0
            0
            0
            4
            32
            64
            0
            0
            0
            0
            0
            1
            1
            1
            1
            1
            0
            0
            0
            0
            1
            0
            0
            0
            64
            8
            4
            4
            4
            4
            0
            0
            0
            0
            0
            0
            1
            1
            1
            1
            1
            1
            0
            0
            0
            0
            0
            0
            0
            0
            0
            0
            0
            0
            0
            0
            0
            0
            0
            0
            32
            64
            2
            32
            64
            1
            16
            1024
            16
            16
            1024
            1024
            4
            10
            4
            4
            10
            10
            0
            0
            0
            0
            0
            0
            0
            0
            0
            0
            0
            0
            5
            5
            5
            5
            5
            5
            1023
            1023
            1023
            1023
            1023
            1023
            5
            5
            5
            5
            5
            5
            1022
            1022
            1022
            1022
            1022
            1022
            0
            0
            0
            0
            0
            0
         
         
            
               
                  coregen
                  ./
                  ./tmp/
                  ./tmp/_cg/
               
               
                  xc6vlx240t
                  virtex6
                  ff1156
                  -1
               
               
                  BusFormatAngleBracketNotRipped
                  VHDL
                  true
                  Foundation_ISE
                  false
                  false
                  false
                  Ngc
                  false
               
               
                  Behavioral
                  VHDL_and_Verilog
                  false
               
               
                  2011-03-14T07:12:32.000Z
               
            
            
               
                  ip_upgrade_generator
                  
                     ./v6_eb_fifo_counted_upgrade.txt
                     txt
                     Mon Mar 12 16:39:08 GMT 2012
                     0xC5F526BA
                     generationid_63922064
                  
               
               
                  view_upgrade_report_generator
               
               
                  model_parameter_resolution_generator
               
               
                  ip_xco_generator
                  
                     ./v6_eb_fifo_counted.xco
                     xco
                     Mon Mar 12 16:39:17 GMT 2012
                     0xE0F99FC3
                     generationid_63922064
                  
               
               
                  associated_files_generator
                  
                     ./fifo_generator_ug175.pdf
                     pdf
                     Tue Oct 04 23:21:33 GMT 2011
                     0x42070F84
                     generationid_63922064
                  
                  
                     ./fifo_generator_v8_3_readme.txt
                     txt
                     Tue Oct 04 23:21:33 GMT 2011
                     0xCD35AB83
                     generationid_63922064
                  
               
               
                  ejava_generator
                  
                     ./v6_eb_fifo_counted_ste/example_design/v6_eb_fifo_counted_top.ucf
                     ignore
                     ucf
                     Mon Mar 12 16:39:17 GMT 2012
                     0xB0FB4AAF
                     generationid_63922064
                  
                  
                     ./v6_eb_fifo_counted_ste/example_design/v6_eb_fifo_counted_top.vhd
                     ignore
                     vhdl
                     Mon Mar 12 16:39:17 GMT 2012
                     0xDF46ED6C
                     generationid_63922064
                  
                  
                     ./v6_eb_fifo_counted_ste/example_design/v6_eb_fifo_counted_top.xdc
                     ignore
                     xdc
                     Mon Mar 12 16:39:17 GMT 2012
                     0xA1CB2F49
                     generationid_63922064
                  
                  
                     ./v6_eb_fifo_counted_ste/implement/implement.bat
                     ignore
                     unknown
                     Mon Mar 12 16:39:17 GMT 2012
                     0x38380825
                     generationid_63922064
                  
                  
                     ./v6_eb_fifo_counted_ste/implement/implement.sh
                     ignore
                     unknown
                     Mon Mar 12 16:39:17 GMT 2012
                     0x5811C8B1
                     generationid_63922064
                  
                  
                     ./v6_eb_fifo_counted_ste/implement/planAhead_rdn.bat
                     ignore
                     unknown
                     Mon Mar 12 16:39:17 GMT 2012
                     0x7F3E496D
                     generationid_63922064
                  
                  
                     ./v6_eb_fifo_counted_ste/implement/planAhead_rdn.sh
                     ignore
                     unknown
                     Mon Mar 12 16:39:17 GMT 2012
                     0xA3CB8AEB
                     generationid_63922064
                  
                  
                     ./v6_eb_fifo_counted_ste/implement/planAhead_rdn.tcl
                     ignore
                     tcl
                     Mon Mar 12 16:39:17 GMT 2012
                     0x70310FC0
                     generationid_63922064
                  
                  
                     ./v6_eb_fifo_counted_ste/implement/xst.prj
                     ignore
                     unknown
                     Mon Mar 12 16:39:17 GMT 2012
                     0xE760EB1B
                     generationid_63922064
                  
                  
                     ./v6_eb_fifo_counted_ste/implement/xst.scr
                     ignore
                     unknown
                     Mon Mar 12 16:39:17 GMT 2012
                     0xD1B44AA0
                     generationid_63922064
                  
               
               
                  ngc_netlist_generator
                  
                     ./v6_eb_fifo_counted.ngc
                     ngc
                     Mon Mar 12 16:41:30 GMT 2012
                     0x0187874D
                     generationid_63922064
                  
               
               
                  obfuscate_netlist_generator
               
               
                  padded_implementation_netlist_generator
               
               
                  instantiation_template_generator
                  
                     ./v6_eb_fifo_counted.veo
                     veo
                     Mon Mar 12 16:41:32 GMT 2012
                     0x8AF05284
                     generationid_63922064
                  
                  
                     ./v6_eb_fifo_counted.vho
                     vho
                     Mon Mar 12 16:41:32 GMT 2012
                     0x47EDC701
                     generationid_63922064
                  
               
               
                  structural_simulation_model_generator
                  
                     ./v6_eb_fifo_counted.v
                     verilog
                     Mon Mar 12 16:41:32 GMT 2012
                     0x79112F79
                     generationid_63922064
                  
                  
                     ./v6_eb_fifo_counted.vhd
                     vhdl
                     Mon Mar 12 16:41:32 GMT 2012
                     0xDEB4AFFE
                     generationid_63922064
                  
               
               
                  asy_generator
                  
                     ./v6_eb_fifo_counted.asy
                     asy
                     Mon Mar 12 16:41:37 GMT 2012
                     0x790A4035
                     generationid_63922064
                  
               
               
                  xmdf_generator
                  
                     ./v6_eb_fifo_counted_xmdf.tcl
                     tclXmdf
                     tcl
                     Mon Mar 12 16:41:37 GMT 2012
                     0x8854ADA0
                     generationid_63922064
                  
               
               
                  ise_generator
                  
                     ./_xmsgs/pn_parser.xmsgs
                     ignore
                     unknown
                     Mon Mar 12 16:41:42 GMT 2012
                     0x088D9D56
                     generationid_63922064
                  
                  
                     ./v6_eb_fifo_counted.gise
                     ignore
                     gise
                     Mon Mar 12 16:41:42 GMT 2012
                     0xF8585D26
                     generationid_63922064
                  
                  
                     ./v6_eb_fifo_counted.xise
                     ignore
                     xise
                     Mon Mar 12 16:41:42 GMT 2012
                     0xFDBA9FF8
                     generationid_63922064
                  
               
               
                  deliver_readme_generator
               
               
                  flist_generator
                  
                     ./v6_eb_fifo_counted_flist.txt
                     ignore
                     txtFlist
                     txt
                     Mon Mar 12 16:41:43 GMT 2012
                     0x7CF421F1
                     generationid_63922064
                  
               
            
         
      
      
         v6_eb_fifo_counted_new
         Fifo Generator
         The FIFO Generator is a parameterizable first-in/first-out memory queue generator. Use it to generate resource and performance optimized FIFOs with common or independent read/write clock domains, and optional fixed or programmable full and empty flags and handshaking signals.  Choose from a selection of memory resource types for implementation.  Optional Hamming code based error detection and correction as well as error injection capability for system test help to insure data integrity.  FIFO width and depth are parameterizable, and for native interface FIFOs, asymmetric read and write port widths are also supported.
         
         
            v6_eb_fifo_counted_new
            Independent_Clocks_Block_RAM
            Native
            Standard_FIFO
            72
            32768
            72
            32768
            false
            false
            true
            true
            Asynchronous_Reset
            1
            true
            0
            false
            false
            true
            Active_High
            false
            Active_High
            false
            Active_High
            false
            Active_High
            false
            false
            false
            false
            15
            true
            15
            true
            15
            false
            1
            1
            Single_Programmable_Full_Threshold_Constant
            28671
            28670
            Single_Programmable_Empty_Threshold_Constant
            4096
            4097
            AXI4_Stream
            Common_Clock
            false
            Slave_Interface_Clock_Enable
            false
            false
            4
            32
            64
            false
            1
            false
            1
            false
            1
            false
            1
            false
            1
            false
            64
            false
            8
            false
            4
            false
            4
            true
            false
            false
            4
            false
            4
            FIFO
            Common_Clock_Block_RAM
            Data_FIFO
            false
            false
            false
            16
            false
            false
            Full
            1023
            Empty
            1022
            FIFO
            Common_Clock_Block_RAM
            Data_FIFO
            false
            false
            false
            1024
            false
            false
            Full
            1023
            Empty
            1022
            FIFO
            Common_Clock_Block_RAM
            Data_FIFO
            false
            false
            false
            16
            false
            false
            Full
            1023
            Empty
            1022
            FIFO
            Common_Clock_Block_RAM
            Data_FIFO
            false
            false
            false
            16
            false
            false
            Full
            1023
            Empty
            1022
            FIFO
            Common_Clock_Block_RAM
            Data_FIFO
            false
            false
            false
            1024
            false
            false
            Full
            1023
            Empty
            1022
            FIFO
            Common_Clock_Block_RAM
            Data_FIFO
            false
            false
            false
            1024
            false
            false
            Full
            1023
            Empty
            1022
            Fully_Registered
            Fully_Registered
            Fully_Registered
            Fully_Registered
            Fully_Registered
            Fully_Registered
            false
            Active_High
            false
            Active_High
            false
            false
            false
            false
            false
            0
            15
            72
            0
            72
            virtex6
            1
            0
            0
            0
            0
            0
            1
            1
            0
            0
            1
            0
            1
            2
            1
            0
            1
            0
            4kx9
            4096
            4097
            1
            28671
            28670
            1
            15
            32768
            1
            15
            0
            1
            0
            0
            0
            0
            0
            15
            32768
            1
            15
            1
            1
            0
            0
            0
            0
            0
            0
            0
            0
            0
            0
            4
            32
            64
            0
            0
            0
            0
            0
            1
            1
            1
            1
            1
            0
            0
            0
            0
            1
            0
            0
            0
            64
            8
            4
            4
            4
            4
            0
            0
            0
            0
            0
            0
            1
            1
            1
            1
            1
            1
            0
            0
            0
            0
            0
            0
            0
            0
            0
            0
            0
            0
            0
            0
            0
            0
            0
            0
            32
            64
            2
            32
            64
            1
            16
            1024
            16
            16
            1024
            1024
            4
            10
            4
            4
            10
            10
            0
            0
            0
            0
            0
            0
            0
            0
            0
            0
            0
            0
            5
            5
            5
            5
            5
            5
            1023
            1023
            1023
            1023
            1023
            1023
            5
            5
            5
            5
            5
            5
            1022
            1022
            1022
            1022
            1022
            1022
            0
            0
            0
            0
            0
            0
         
         
            
               
                  coregen
                  ./
                  ./tmp/
                  ./tmp/_cg/
               
               
                  xc6vlx240t
                  virtex6
                  ff1156
                  -1
               
               
                  BusFormatAngleBracketNotRipped
                  VHDL
                  true
                  Foundation_ISE
                  false
                  false
                  false
                  Ngc
                  false
               
               
                  Behavioral
                  VHDL_and_Verilog
                  false
               
               
                  2011-03-14T07:12:32.000Z
               
            
            
               
                  ip_upgrade_generator
                  
                     ./v6_eb_fifo_counted_new_upgrade.txt
                     txt
                     Mon Mar 12 16:44:44 GMT 2012
                     0x993A7FB2
                     generationid_2584806448
                  
               
               
                  view_upgrade_report_generator
               
               
                  model_parameter_resolution_generator
               
               
                  ip_xco_generator
                  
                     ./v6_eb_fifo_counted_new.xco
                     xco
                     Mon Mar 12 16:44:53 GMT 2012
                     0xB2FB4195
                     generationid_2584806448
                  
               
               
                  associated_files_generator
                  
                     ./fifo_generator_ug175.pdf
                     pdf
                     Tue Oct 04 23:21:33 GMT 2011
                     0x42070F84
                     generationid_2584806448
                  
                  
                     ./fifo_generator_v8_3_readme.txt
                     txt
                     Tue Oct 04 23:21:33 GMT 2011
                     0xCD35AB83
                     generationid_2584806448
                  
               
               
                  ejava_generator
                  
                     ./v6_eb_fifo_counted_new_ste/example_design/v6_eb_fifo_counted_new_top.ucf
                     ignore
                     ucf
                     Mon Mar 12 16:44:54 GMT 2012
                     0xB0FB4AAF
                     generationid_2584806448
                  
                  
                     ./v6_eb_fifo_counted_new_ste/example_design/v6_eb_fifo_counted_new_top.vhd
                     ignore
                     vhdl
                     Mon Mar 12 16:44:54 GMT 2012
                     0xE2DCE317
                     generationid_2584806448
                  
                  
                     ./v6_eb_fifo_counted_new_ste/example_design/v6_eb_fifo_counted_new_top.xdc
                     ignore
                     xdc
                     Mon Mar 12 16:44:54 GMT 2012
                     0xA1CB2F49
                     generationid_2584806448
                  
                  
                     ./v6_eb_fifo_counted_new_ste/implement/implement.bat
                     ignore
                     unknown
                     Mon Mar 12 16:44:54 GMT 2012
                     0xF4B9D34D
                     generationid_2584806448
                  
                  
                     ./v6_eb_fifo_counted_new_ste/implement/implement.sh
                     ignore
                     unknown
                     Mon Mar 12 16:44:54 GMT 2012
                     0x7F14AB23
                     generationid_2584806448
                  
                  
                     ./v6_eb_fifo_counted_new_ste/implement/planAhead_rdn.bat
                     ignore
                     unknown
                     Mon Mar 12 16:44:54 GMT 2012
                     0xDF3C4CCE
                     generationid_2584806448
                  
                  
                     ./v6_eb_fifo_counted_new_ste/implement/planAhead_rdn.sh
                     ignore
                     unknown
                     Mon Mar 12 16:44:54 GMT 2012
                     0xFD5DC21F
                     generationid_2584806448
                  
                  
                     ./v6_eb_fifo_counted_new_ste/implement/planAhead_rdn.tcl
                     ignore
                     tcl
                     Mon Mar 12 16:44:54 GMT 2012
                     0x5F1B023C
                     generationid_2584806448
                  
                  
                     ./v6_eb_fifo_counted_new_ste/implement/xst.prj
                     ignore
                     unknown
                     Mon Mar 12 16:44:54 GMT 2012
                     0xFD6F4891
                     generationid_2584806448
                  
                  
                     ./v6_eb_fifo_counted_new_ste/implement/xst.scr
                     ignore
                     unknown
                     Mon Mar 12 16:44:54 GMT 2012
                     0xF9CA88FE
                     generationid_2584806448
                  
               
               
                  ngc_netlist_generator
                  
                     ./v6_eb_fifo_counted_new.ngc
                     ngc
                     Mon Mar 12 16:48:02 GMT 2012
                     0xDD507B20
                     generationid_2584806448
                  
               
               
                  obfuscate_netlist_generator
               
               
                  padded_implementation_netlist_generator
               
               
                  instantiation_template_generator
                  
                     ./v6_eb_fifo_counted_new.veo
                     veo
                     Mon Mar 12 16:48:04 GMT 2012
                     0x607DE2C4
                     generationid_2584806448
                  
                  
                     ./v6_eb_fifo_counted_new.vho
                     vho
                     Mon Mar 12 16:48:04 GMT 2012
                     0xF3FC0153
                     generationid_2584806448
                  
               
               
                  structural_simulation_model_generator
                  
                     ./v6_eb_fifo_counted_new.v
                     verilog
                     Mon Mar 12 16:48:04 GMT 2012
                     0xAF602DDF
                     generationid_2584806448
                  
                  
                     ./v6_eb_fifo_counted_new.vhd
                     vhdl
                     Mon Mar 12 16:48:04 GMT 2012
                     0x815F1D29
                     generationid_2584806448
                  
               
               
                  asy_generator
                  
                     ./v6_eb_fifo_counted_new.asy
                     asy
                     Mon Mar 12 16:48:09 GMT 2012
                     0x65CF4A97
                     generationid_2584806448
                  
               
               
                  xmdf_generator
                  
                     ./v6_eb_fifo_counted_new_xmdf.tcl
                     tclXmdf
                     tcl
                     Mon Mar 12 16:48:09 GMT 2012
                     0x069C28CC
                     generationid_2584806448
                  
               
               
                  ise_generator
                  
                     ./_xmsgs/pn_parser.xmsgs
                     ignore
                     unknown
                     Mon Mar 12 16:48:15 GMT 2012
                     0xC6487EBD
                     generationid_2584806448
                  
                  
                     ./v6_eb_fifo_counted_new.gise
                     ignore
                     gise
                     Mon Mar 12 16:48:15 GMT 2012
                     0xC4C61B7D
                     generationid_2584806448
                  
                  
                     ./v6_eb_fifo_counted_new.xise
                     ignore
                     xise
                     Mon Mar 12 16:48:15 GMT 2012
                     0xF617C9BC
                     generationid_2584806448
                  
               
               
                  deliver_readme_generator
               
               
                  flist_generator
                  
                     ./v6_eb_fifo_counted_new_flist.txt
                     ignore
                     txtFlist
                     txt
                     Mon Mar 12 16:48:15 GMT 2012
                     0xE88F2EC6
                     generationid_2584806448
                  
               
            
         
      
      
         v6_mBuf_128x72
         Fifo Generator
         The FIFO Generator is a parameterizable first-in/first-out memory queue generator. Use it to generate resource and performance optimized FIFOs with common or independent read/write clock domains, and optional fixed or programmable full and empty flags and handshaking signals.  Choose from a selection of memory resource types for implementation.  Optional Hamming code based error detection and correction as well as error injection capability for system test help to insure data integrity.  FIFO width and depth are parameterizable, and for native interface FIFOs, asymmetric read and write port widths are also supported.
         
         
            v6_mBuf_128x72
            Common_Clock_Builtin_FIFO
            Native
            Standard_FIFO
            72
            512
            72
            512
            false
            false
            true
            true
            Asynchronous_Reset
            0
            false
            0
            false
            false
            false
            Active_High
            false
            Active_High
            false
            Active_High
            false
            Active_High
            false
            false
            false
            false
            9
            false
            9
            false
            9
            false
            1
            1
            Single_Programmable_Full_Threshold_Constant
            128
            127
            No_Programmable_Empty_Threshold
            2
            3
            AXI4_Stream
            Common_Clock
            false
            Slave_Interface_Clock_Enable
            false
            false
            4
            32
            64
            false
            1
            false
            1
            false
            1
            false
            1
            false
            1
            false
            64
            false
            8
            false
            4
            false
            4
            true
            false
            false
            4
            false
            4
            FIFO
            Common_Clock_Block_RAM
            Data_FIFO
            false
            false
            false
            16
            false
            false
            Full
            1023
            Empty
            1022
            FIFO
            Common_Clock_Block_RAM
            Data_FIFO
            false
            false
            false
            1024
            false
            false
            Full
            1023
            Empty
            1022
            FIFO
            Common_Clock_Block_RAM
            Data_FIFO
            false
            false
            false
            16
            false
            false
            Full
            1023
            Empty
            1022
            FIFO
            Common_Clock_Block_RAM
            Data_FIFO
            false
            false
            false
            16
            false
            false
            Full
            1023
            Empty
            1022
            FIFO
            Common_Clock_Block_RAM
            Data_FIFO
            false
            false
            false
            1024
            false
            false
            Full
            1023
            Empty
            1022
            FIFO
            Common_Clock_Block_RAM
            Data_FIFO
            false
            false
            false
            1024
            false
            false
            Full
            1023
            Empty
            1022
            Fully_Registered
            Fully_Registered
            Fully_Registered
            Fully_Registered
            Fully_Registered
            Fully_Registered
            false
            Active_High
            false
            Active_High
            false
            false
            false
            false
            false
            1
            9
            72
            0
            72
            virtex6
            0
            0
            0
            0
            0
            0
            0
            1
            0
            0
            0
            0
            0
            5
            4
            0
            1
            0
            512x72
            2
            3
            0
            128
            127
            1
            9
            512
            1
            9
            0
            0
            0
            0
            0
            0
            0
            9
            512
            1
            9
            1
            1
            0
            0
            0
            0
            0
            0
            0
            0
            0
            0
            4
            32
            64
            0
            0
            0
            0
            0
            1
            1
            1
            1
            1
            0
            0
            0
            0
            1
            0
            0
            0
            64
            8
            4
            4
            4
            4
            0
            0
            0
            0
            0
            0
            1
            1
            1
            1
            1
            1
            0
            0
            0
            0
            0
            0
            0
            0
            0
            0
            0
            0
            0
            0
            0
            0
            0
            0
            32
            64
            2
            32
            64
            1
            16
            1024
            16
            16
            1024
            1024
            4
            10
            4
            4
            10
            10
            0
            0
            0
            0
            0
            0
            0
            0
            0
            0
            0
            0
            5
            5
            5
            5
            5
            5
            1023
            1023
            1023
            1023
            1023
            1023
            5
            5
            5
            5
            5
            5
            1022
            1022
            1022
            1022
            1022
            1022
            0
            0
            0
            0
            0
            0
         
         
            
               
                  coregen
                  ./
                  ./tmp/
                  ./tmp/_cg/
               
               
                  xc6vlx240t
                  virtex6
                  ff1156
                  -1
               
               
                  BusFormatAngleBracketNotRipped
                  VHDL
                  true
                  Foundation_ISE
                  false
                  false
                  false
                  Ngc
                  false
               
               
                  Behavioral
                  VHDL_and_Verilog
                  false
               
               
                  2011-03-14T07:12:32.000Z
               
            
            
               
                  ip_upgrade_generator
                  
                     ./v6_mBuf_128x72_upgrade.txt
                     txt
                     Mon Mar 12 16:48:31 GMT 2012
                     0xB5D175F0
                     generationid_3356943671
                  
               
               
                  view_upgrade_report_generator
               
               
                  model_parameter_resolution_generator
               
               
                  ip_xco_generator
                  
                     ./v6_mBuf_128x72.xco
                     xco
                     Mon Mar 12 16:48:39 GMT 2012
                     0xB0347C75
                     generationid_3356943671
                  
               
               
                  associated_files_generator
                  
                     ./fifo_generator_ug175.pdf
                     pdf
                     Tue Oct 04 23:21:33 GMT 2011
                     0x42070F84
                     generationid_3356943671
                  
                  
                     ./fifo_generator_v8_3_readme.txt
                     txt
                     Tue Oct 04 23:21:33 GMT 2011
                     0xCD35AB83
                     generationid_3356943671
                  
               
               
                  ejava_generator
                  
                     ./v6_mBuf_128x72_ste/example_design/v6_mBuf_128x72_top.ucf
                     ignore
                     ucf
                     Mon Mar 12 16:48:40 GMT 2012
                     0x3C560FD9
                     generationid_3356943671
                  
                  
                     ./v6_mBuf_128x72_ste/example_design/v6_mBuf_128x72_top.vhd
                     ignore
                     vhdl
                     Mon Mar 12 16:48:40 GMT 2012
                     0xFF9D18B9
                     generationid_3356943671
                  
                  
                     ./v6_mBuf_128x72_ste/example_design/v6_mBuf_128x72_top.xdc
                     ignore
                     xdc
                     Mon Mar 12 16:48:40 GMT 2012
                     0xFA2BDC02
                     generationid_3356943671
                  
                  
                     ./v6_mBuf_128x72_ste/implement/implement.bat
                     ignore
                     unknown
                     Mon Mar 12 16:48:40 GMT 2012
                     0xAD24CA02
                     generationid_3356943671
                  
                  
                     ./v6_mBuf_128x72_ste/implement/implement.sh
                     ignore
                     unknown
                     Mon Mar 12 16:48:40 GMT 2012
                     0xCF52E211
                     generationid_3356943671
                  
                  
                     ./v6_mBuf_128x72_ste/implement/planAhead_rdn.bat
                     ignore
                     unknown
                     Mon Mar 12 16:48:40 GMT 2012
                     0xFA541053
                     generationid_3356943671
                  
                  
                     ./v6_mBuf_128x72_ste/implement/planAhead_rdn.sh
                     ignore
                     unknown
                     Mon Mar 12 16:48:40 GMT 2012
                     0x4A742549
                     generationid_3356943671
                  
                  
                     ./v6_mBuf_128x72_ste/implement/planAhead_rdn.tcl
                     ignore
                     tcl
                     Mon Mar 12 16:48:40 GMT 2012
                     0xD4500344
                     generationid_3356943671
                  
                  
                     ./v6_mBuf_128x72_ste/implement/xst.prj
                     ignore
                     unknown
                     Mon Mar 12 16:48:40 GMT 2012
                     0x582D4653
                     generationid_3356943671
                  
                  
                     ./v6_mBuf_128x72_ste/implement/xst.scr
                     ignore
                     unknown
                     Mon Mar 12 16:48:40 GMT 2012
                     0x6C2CD70D
                     generationid_3356943671
                  
               
               
                  ngc_netlist_generator
                  
                     ./v6_mBuf_128x72.ngc
                     ngc
                     Mon Mar 12 16:49:57 GMT 2012
                     0x84B4AD3B
                     generationid_3356943671
                  
               
               
                  obfuscate_netlist_generator
               
               
                  padded_implementation_netlist_generator
               
               
                  instantiation_template_generator
                  
                     ./v6_mBuf_128x72.veo
                     veo
                     Mon Mar 12 16:49:58 GMT 2012
                     0x043677C2
                     generationid_3356943671
                  
                  
                     ./v6_mBuf_128x72.vho
                     vho
                     Mon Mar 12 16:49:58 GMT 2012
                     0xF028F8EE
                     generationid_3356943671
                  
               
               
                  structural_simulation_model_generator
                  
                     ./v6_mBuf_128x72.v
                     verilog
                     Mon Mar 12 16:49:59 GMT 2012
                     0x4994AC0F
                     generationid_3356943671
                  
                  
                     ./v6_mBuf_128x72.vhd
                     vhdl
                     Mon Mar 12 16:49:59 GMT 2012
                     0xEDE3B0DB
                     generationid_3356943671
                  
               
               
                  asy_generator
                  
                     ./v6_mBuf_128x72.asy
                     asy
                     Mon Mar 12 16:50:04 GMT 2012
                     0xE883F712
                     generationid_3356943671
                  
               
               
                  xmdf_generator
                  
                     ./v6_mBuf_128x72_xmdf.tcl
                     tclXmdf
                     tcl
                     Mon Mar 12 16:50:04 GMT 2012
                     0x06254290
                     generationid_3356943671
                  
               
               
                  ise_generator
                  
                     ./_xmsgs/pn_parser.xmsgs
                     ignore
                     unknown
                     Mon Mar 12 16:50:09 GMT 2012
                     0x0917E8BC
                     generationid_3356943671
                  
                  
                     ./v6_mBuf_128x72.gise
                     ignore
                     gise
                     Mon Mar 12 16:50:09 GMT 2012
                     0x0F3A6119
                     generationid_3356943671
                  
                  
                     ./v6_mBuf_128x72.xise
                     ignore
                     xise
                     Mon Mar 12 16:50:09 GMT 2012
                     0x80AE94F0
                     generationid_3356943671
                  
               
               
                  deliver_readme_generator
               
               
                  flist_generator
                  
                     ./v6_mBuf_128x72_flist.txt
                     ignore
                     txtFlist
                     txt
                     Mon Mar 12 16:50:09 GMT 2012
                     0x33AA0B9B
                     generationid_3356943671
                  
               
            
         
      
      
         v6_pcie_v1_6
         
         
            v6_pcie_v1_6
            High
            false
            false
            false
            Kilobytes
            Add
            false
            Memory
            Simple_communication_controllers
            1
            0
            0
            true
            false
            00
            Disabled
            0
            false
            false
            2
            false
            false
            false
            false
            false
            false
            false
            64
            false
            6014
            10EE
            No_limit
            1
            X0Y0
            false
            PCI_Express_Endpoint_device
            false
            N/A
            true
            0026
            true
            100_MHz
            05
            0
            ML_605
            3F
            2
            false
            0
            true
            false
            0
            4'h1
            false
            true
            0
            false
            1
            512_bytes
            true
            0
            125_default
            false
            N/A
            false
            0
            false
            Absolute
            false
            true
            0
            Kilobytes
            false
            false
            false
            false
            false
            false
            false
            Kilobytes
            0
            0
            false
            false
            false
            Kilobytes
            false
            true
            false
            4
            false
            false
            Range_B
            true
            Kilobytes
            ABB3
            N/A
            true
            X4
            false
            Megabytes
            false
            0
            0
            Memory
            0
            true
            false
            BAR_0
            Kilobytes
            false
            false
            false
            false
            0
            false
            2.5_GT/s
            false
            true
            false
            None
            None
            3FF
            false
            No_function_number_bits_used
            00
            2
            false
            false
            0
            false
            0
            INTA
            64_byte
            0
            false
            false
            Memory
            06
            false
            BAR_0
            1_vector
            false
            0
            0
            0084
            false
            0000
            00
            false
            00000000
            true
            true
            No_limit
            Disabled
            false
            Generic_XT_compatible_serial_controller
            0
            2
            false
         
         
            
               
                  coregen
                  ./
                  ./tmp/
                  ./tmp/_cg/
               
               
                  xc6vlx240t
                  virtex6
                  ff1156
                  -1
               
               
                  BusFormatAngleBracketNotRipped
                  VHDL
                  true
                  Other
                  false
                  false
                  false
                  Ngc
                  false
               
               
                  Behavioral
                  VHDL
                  false
               
            
         
      
      
         v6_pkt_counter_1024
         Fifo Generator
         The FIFO Generator is a parameterizable first-in/first-out memory queue generator. Use it to generate resource and performance optimized FIFOs with common or independent read/write clock domains, and optional fixed or programmable full and empty flags and handshaking signals.  Choose from a selection of memory resource types for implementation.  Optional Hamming code based error detection and correction as well as error injection capability for system test help to insure data integrity.  FIFO width and depth are parameterizable, and for native interface FIFOs, asymmetric read and write port widths are also supported.
         
         
            v6_pkt_counter_1024
            Independent_Clocks_Distributed_RAM
            Native
            Standard_FIFO
            1
            1024
            1
            1024
            false
            false
            true
            true
            Asynchronous_Reset
            1
            true
            0
            false
            false
            false
            Active_High
            false
            Active_High
            false
            Active_High
            false
            Active_High
            false
            false
            false
            false
            10
            false
            10
            false
            10
            false
            1
            1
            Single_Programmable_Full_Threshold_Constant
            1016
            1015
            Single_Programmable_Empty_Threshold_Constant
            2
            3
            AXI4_Stream
            Common_Clock
            false
            Slave_Interface_Clock_Enable
            false
            false
            4
            32
            64
            false
            1
            false
            1
            false
            1
            false
            1
            false
            1
            false
            64
            false
            8
            false
            4
            false
            4
            true
            false
            false
            4
            false
            4
            FIFO
            Common_Clock_Block_RAM
            Data_FIFO
            false
            false
            false
            16
            false
            false
            Full
            1023
            Empty
            1022
            FIFO
            Common_Clock_Block_RAM
            Data_FIFO
            false
            false
            false
            1024
            false
            false
            Full
            1023
            Empty
            1022
            FIFO
            Common_Clock_Block_RAM
            Data_FIFO
            false
            false
            false
            16
            false
            false
            Full
            1023
            Empty
            1022
            FIFO
            Common_Clock_Block_RAM
            Data_FIFO
            false
            false
            false
            16
            false
            false
            Full
            1023
            Empty
            1022
            FIFO
            Common_Clock_Block_RAM
            Data_FIFO
            false
            false
            false
            1024
            false
            false
            Full
            1023
            Empty
            1022
            FIFO
            Common_Clock_Block_RAM
            Data_FIFO
            false
            false
            false
            1024
            false
            false
            Full
            1023
            Empty
            1022
            Fully_Registered
            Fully_Registered
            Fully_Registered
            Fully_Registered
            Fully_Registered
            Fully_Registered
            false
            Active_High
            false
            Active_High
            false
            false
            false
            false
            false
            0
            10
            1
            0
            1
            virtex6
            1
            0
            0
            0
            0
            0
            0
            1
            0
            0
            0
            0
            0
            2
            2
            0
            1
            0
            1kx18
            2
            3
            1
            1016
            1015
            1
            10
            1024
            1
            10
            0
            1
            0
            0
            0
            0
            0
            10
            1024
            1
            10
            1
            1
            0
            0
            0
            0
            0
            0
            0
            0
            0
            0
            4
            32
            64
            0
            0
            0
            0
            0
            1
            1
            1
            1
            1
            0
            0
            0
            0
            1
            0
            0
            0
            64
            8
            4
            4
            4
            4
            0
            0
            0
            0
            0
            0
            1
            1
            1
            1
            1
            1
            0
            0
            0
            0
            0
            0
            0
            0
            0
            0
            0
            0
            0
            0
            0
            0
            0
            0
            32
            64
            2
            32
            64
            1
            16
            1024
            16
            16
            1024
            1024
            4
            10
            4
            4
            10
            10
            0
            0
            0
            0
            0
            0
            0
            0
            0
            0
            0
            0
            5
            5
            5
            5
            5
            5
            1023
            1023
            1023
            1023
            1023
            1023
            5
            5
            5
            5
            5
            5
            1022
            1022
            1022
            1022
            1022
            1022
            0
            0
            0
            0
            0
            0
         
         
            
               
                  coregen
                  ./
                  ./tmp/
                  ./tmp/_cg/
               
               
                  xc6vlx240t
                  virtex6
                  ff1156
                  -1
               
               
                  BusFormatAngleBracketNotRipped
                  VHDL
                  true
                  Foundation_ISE
                  false
                  false
                  false
                  Ngc
                  false
               
               
                  Behavioral
                  VHDL_and_Verilog
                  false
               
               
                  2011-03-14T07:12:32.000Z
               
            
            
               
                  ip_upgrade_generator
                  
                     ./v6_pkt_counter_1024_upgrade.txt
                     txt
                     Mon Mar 12 16:50:44 GMT 2012
                     0xCEBA5C02
                     generationid_3577855143
                  
               
               
                  view_upgrade_report_generator
               
               
                  model_parameter_resolution_generator
               
               
                  ip_xco_generator
                  
                     ./v6_pkt_counter_1024.xco
                     xco
                     Mon Mar 12 16:50:57 GMT 2012
                     0xD343DDFA
                     generationid_3577855143
                  
               
               
                  associated_files_generator
                  
                     ./fifo_generator_ug175.pdf
                     pdf
                     Tue Oct 04 23:21:33 GMT 2011
                     0x42070F84
                     generationid_3577855143
                  
                  
                     ./fifo_generator_v8_3_readme.txt
                     txt
                     Tue Oct 04 23:21:33 GMT 2011
                     0xCD35AB83
                     generationid_3577855143
                  
               
               
                  ejava_generator
                  
                     ./v6_pkt_counter_1024_ste/example_design/v6_pkt_counter_1024_top.ucf
                     ignore
                     ucf
                     Mon Mar 12 16:51:00 GMT 2012
                     0xB0FB4AAF
                     generationid_3577855143
                  
                  
                     ./v6_pkt_counter_1024_ste/example_design/v6_pkt_counter_1024_top.vhd
                     ignore
                     vhdl
                     Mon Mar 12 16:51:00 GMT 2012
                     0x0466E6AB
                     generationid_3577855143
                  
                  
                     ./v6_pkt_counter_1024_ste/example_design/v6_pkt_counter_1024_top.xdc
                     ignore
                     xdc
                     Mon Mar 12 16:51:00 GMT 2012
                     0xA1CB2F49
                     generationid_3577855143
                  
                  
                     ./v6_pkt_counter_1024_ste/implement/implement.bat
                     ignore
                     unknown
                     Mon Mar 12 16:51:00 GMT 2012
                     0x14412A2E
                     generationid_3577855143
                  
                  
                     ./v6_pkt_counter_1024_ste/implement/implement.sh
                     ignore
                     unknown
                     Mon Mar 12 16:51:00 GMT 2012
                     0x8CED1160
                     generationid_3577855143
                  
                  
                     ./v6_pkt_counter_1024_ste/implement/planAhead_rdn.bat
                     ignore
                     unknown
                     Mon Mar 12 16:51:00 GMT 2012
                     0x8284FFC5
                     generationid_3577855143
                  
                  
                     ./v6_pkt_counter_1024_ste/implement/planAhead_rdn.sh
                     ignore
                     unknown
                     Mon Mar 12 16:51:00 GMT 2012
                     0xB53BC2C7
                     generationid_3577855143
                  
                  
                     ./v6_pkt_counter_1024_ste/implement/planAhead_rdn.tcl
                     ignore
                     tcl
                     Mon Mar 12 16:51:00 GMT 2012
                     0x69ABAED8
                     generationid_3577855143
                  
                  
                     ./v6_pkt_counter_1024_ste/implement/xst.prj
                     ignore
                     unknown
                     Mon Mar 12 16:51:00 GMT 2012
                     0x1A85A882
                     generationid_3577855143
                  
                  
                     ./v6_pkt_counter_1024_ste/implement/xst.scr
                     ignore
                     unknown
                     Mon Mar 12 16:51:00 GMT 2012
                     0xD7FFF7CD
                     generationid_3577855143
                  
               
               
                  ngc_netlist_generator
                  
                     ./v6_pkt_counter_1024.ngc
                     ngc
                     Mon Mar 12 16:52:29 GMT 2012
                     0x6430DCB4
                     generationid_3577855143
                  
               
               
                  obfuscate_netlist_generator
               
               
                  padded_implementation_netlist_generator
               
               
                  instantiation_template_generator
                  
                     ./v6_pkt_counter_1024.veo
                     veo
                     Mon Mar 12 16:52:31 GMT 2012
                     0x8E9FA385
                     generationid_3577855143
                  
                  
                     ./v6_pkt_counter_1024.vho
                     vho
                     Mon Mar 12 16:52:31 GMT 2012
                     0x9D1E6AE6
                     generationid_3577855143
                  
               
               
                  structural_simulation_model_generator
                  
                     ./v6_pkt_counter_1024.v
                     verilog
                     Mon Mar 12 16:52:31 GMT 2012
                     0x10A708A6
                     generationid_3577855143
                  
                  
                     ./v6_pkt_counter_1024.vhd
                     vhdl
                     Mon Mar 12 16:52:31 GMT 2012
                     0xE9FE5808
                     generationid_3577855143
                  
               
               
                  asy_generator
                  
                     ./v6_pkt_counter_1024.asy
                     asy
                     Mon Mar 12 16:52:36 GMT 2012
                     0x50C00E62
                     generationid_3577855143
                  
               
               
                  xmdf_generator
                  
                     ./v6_pkt_counter_1024_xmdf.tcl
                     tclXmdf
                     tcl
                     Mon Mar 12 16:52:36 GMT 2012
                     0xAF4F21F0
                     generationid_3577855143
                  
               
               
                  ise_generator
                  
                     ./_xmsgs/pn_parser.xmsgs
                     ignore
                     unknown
                     Mon Mar 12 16:52:48 GMT 2012
                     0xB9E8AD1D
                     generationid_3577855143
                  
                  
                     ./v6_pkt_counter_1024.gise
                     ignore
                     gise
                     Mon Mar 12 16:52:48 GMT 2012
                     0x34445B5D
                     generationid_3577855143
                  
                  
                     ./v6_pkt_counter_1024.xise
                     ignore
                     xise
                     Mon Mar 12 16:52:48 GMT 2012
                     0xDD25FE32
                     generationid_3577855143
                  
               
               
                  deliver_readme_generator
               
               
                  flist_generator
                  
                     ./v6_pkt_counter_1024_flist.txt
                     ignore
                     txtFlist
                     txt
                     Mon Mar 12 16:52:48 GMT 2012
                     0x1B0B0873
                     generationid_3577855143
                  
               
            
         
      
      
         v6_prime_fifo_plain
         Fifo Generator
         The FIFO Generator is a parameterizable first-in/first-out memory queue generator. Use it to generate resource and performance optimized FIFOs with common or independent read/write clock domains, and optional fixed or programmable full and empty flags and handshaking signals.  Choose from a selection of memory resource types for implementation.  Optional Hamming code based error detection and correction as well as error injection capability for system test help to insure data integrity.  FIFO width and depth are parameterizable, and for native interface FIFOs, asymmetric read and write port widths are also supported.
         
         
            v6_prime_fifo_plain
            Independent_Clocks_Builtin_FIFO
            Native
            Standard_FIFO
            72
            512
            72
            512
            false
            false
            true
            true
            Asynchronous_Reset
            0
            false
            0
            false
            false
            false
            Active_High
            false
            Active_High
            false
            Active_High
            false
            Active_High
            false
            false
            false
            false
            9
            false
            9
            false
            9
            false
            125
            125
            Single_Programmable_Full_Threshold_Constant
            496
            495
            No_Programmable_Empty_Threshold
            5
            6
            AXI4_Stream
            Common_Clock
            false
            Slave_Interface_Clock_Enable
            false
            false
            4
            32
            64
            false
            1
            false
            1
            false
            1
            false
            1
            false
            1
            false
            64
            false
            8
            false
            4
            false
            4
            true
            false
            false
            4
            false
            4
            FIFO
            Common_Clock_Block_RAM
            Data_FIFO
            false
            false
            false
            16
            false
            false
            Full
            1023
            Empty
            1022
            FIFO
            Common_Clock_Block_RAM
            Data_FIFO
            false
            false
            false
            1024
            false
            false
            Full
            1023
            Empty
            1022
            FIFO
            Common_Clock_Block_RAM
            Data_FIFO
            false
            false
            false
            16
            false
            false
            Full
            1023
            Empty
            1022
            FIFO
            Common_Clock_Block_RAM
            Data_FIFO
            false
            false
            false
            16
            false
            false
            Full
            1023
            Empty
            1022
            FIFO
            Common_Clock_Block_RAM
            Data_FIFO
            false
            false
            false
            1024
            false
            false
            Full
            1023
            Empty
            1022
            FIFO
            Common_Clock_Block_RAM
            Data_FIFO
            false
            false
            false
            1024
            false
            false
            Full
            1023
            Empty
            1022
            Fully_Registered
            Fully_Registered
            Fully_Registered
            Fully_Registered
            Fully_Registered
            Fully_Registered
            false
            Active_High
            false
            Active_High
            false
            false
            false
            false
            false
            0
            9
            72
            0
            72
            virtex6
            0
            0
            0
            0
            0
            0
            0
            1
            0
            0
            0
            0
            0
            5
            4
            0
            1
            0
            512x72
            5
            6
            0
            496
            495
            1
            9
            512
            125
            9
            0
            0
            0
            0
            0
            0
            0
            9
            512
            125
            9
            1
            1
            0
            0
            0
            0
            0
            0
            0
            0
            0
            0
            4
            32
            64
            0
            0
            0
            0
            0
            1
            1
            1
            1
            1
            0
            0
            0
            0
            1
            0
            0
            0
            64
            8
            4
            4
            4
            4
            0
            0
            0
            0
            0
            0
            1
            1
            1
            1
            1
            1
            0
            0
            0
            0
            0
            0
            0
            0
            0
            0
            0
            0
            0
            0
            0
            0
            0
            0
            32
            64
            2
            32
            64
            1
            16
            1024
            16
            16
            1024
            1024
            4
            10
            4
            4
            10
            10
            0
            0
            0
            0
            0
            0
            0
            0
            0
            0
            0
            0
            5
            5
            5
            5
            5
            5
            1023
            1023
            1023
            1023
            1023
            1023
            5
            5
            5
            5
            5
            5
            1022
            1022
            1022
            1022
            1022
            1022
            0
            0
            0
            0
            0
            0
         
         
            
               
                  coregen
                  ./
                  ./tmp/
                  ./tmp/_cg/
               
               
                  xc6vlx240t
                  virtex6
                  ff1156
                  -1
               
               
                  BusFormatAngleBracketNotRipped
                  VHDL
                  true
                  Foundation_ISE
                  false
                  false
                  false
                  Ngc
                  false
               
               
                  Behavioral
                  VHDL_and_Verilog
                  false
               
               
                  2011-03-14T07:12:32.000Z
               
            
            
               
                  ip_upgrade_generator
                  
                     ./v6_prime_fifo_plain_upgrade.txt
                     txt
                     Mon Mar 12 16:59:36 GMT 2012
                     0x146A58A5
                     generationid_248767791
                  
               
               
                  view_upgrade_report_generator
               
               
                  model_parameter_resolution_generator
               
               
                  ip_xco_generator
                  
                     ./v6_prime_fifo_plain.xco
                     xco
                     Mon Mar 12 16:59:44 GMT 2012
                     0x81164B1A
                     generationid_248767791
                  
               
               
                  associated_files_generator
                  
                     ./fifo_generator_ug175.pdf
                     pdf
                     Tue Oct 04 23:21:33 GMT 2011
                     0x42070F84
                     generationid_248767791
                  
                  
                     ./fifo_generator_v8_3_readme.txt
                     txt
                     Tue Oct 04 23:21:33 GMT 2011
                     0xCD35AB83
                     generationid_248767791
                  
               
               
                  ejava_generator
                  
                     ./v6_prime_fifo_plain_ste/example_design/v6_prime_fifo_plain_top.ucf
                     ignore
                     ucf
                     Mon Mar 12 16:59:45 GMT 2012
                     0xB0FB4AAF
                     generationid_248767791
                  
                  
                     ./v6_prime_fifo_plain_ste/example_design/v6_prime_fifo_plain_top.vhd
                     ignore
                     vhdl
                     Mon Mar 12 16:59:46 GMT 2012
                     0xEAB2CE89
                     generationid_248767791
                  
                  
                     ./v6_prime_fifo_plain_ste/example_design/v6_prime_fifo_plain_top.xdc
                     ignore
                     xdc
                     Mon Mar 12 16:59:46 GMT 2012
                     0xA1CB2F49
                     generationid_248767791
                  
                  
                     ./v6_prime_fifo_plain_ste/implement/implement.bat
                     ignore
                     unknown
                     Mon Mar 12 16:59:46 GMT 2012
                     0xFDDF12A5
                     generationid_248767791
                  
                  
                     ./v6_prime_fifo_plain_ste/implement/implement.sh
                     ignore
                     unknown
                     Mon Mar 12 16:59:46 GMT 2012
                     0xD4CE24E6
                     generationid_248767791
                  
                  
                     ./v6_prime_fifo_plain_ste/implement/planAhead_rdn.bat
                     ignore
                     unknown
                     Mon Mar 12 16:59:46 GMT 2012
                     0x8BD0220A
                     generationid_248767791
                  
                  
                     ./v6_prime_fifo_plain_ste/implement/planAhead_rdn.sh
                     ignore
                     unknown
                     Mon Mar 12 16:59:46 GMT 2012
                     0xBC6F1F08
                     generationid_248767791
                  
                  
                     ./v6_prime_fifo_plain_ste/implement/planAhead_rdn.tcl
                     ignore
                     tcl
                     Mon Mar 12 16:59:46 GMT 2012
                     0xDE8437BA
                     generationid_248767791
                  
                  
                     ./v6_prime_fifo_plain_ste/implement/xst.prj
                     ignore
                     unknown
                     Mon Mar 12 16:59:46 GMT 2012
                     0x83AC6FF6
                     generationid_248767791
                  
                  
                     ./v6_prime_fifo_plain_ste/implement/xst.scr
                     ignore
                     unknown
                     Mon Mar 12 16:59:46 GMT 2012
                     0x8A8BDF9E
                     generationid_248767791
                  
               
               
                  ngc_netlist_generator
                  
                     ./v6_prime_fifo_plain.ngc
                     ngc
                     Mon Mar 12 17:01:01 GMT 2012
                     0xBF968E16
                     generationid_248767791
                  
               
               
                  obfuscate_netlist_generator
               
               
                  padded_implementation_netlist_generator
               
               
                  instantiation_template_generator
                  
                     ./v6_prime_fifo_plain.veo
                     veo
                     Mon Mar 12 17:01:02 GMT 2012
                     0x8405511F
                     generationid_248767791
                  
                  
                     ./v6_prime_fifo_plain.vho
                     vho
                     Mon Mar 12 17:01:02 GMT 2012
                     0x0D373C0C
                     generationid_248767791
                  
               
               
                  structural_simulation_model_generator
                  
                     ./v6_prime_fifo_plain.v
                     verilog
                     Mon Mar 12 17:01:03 GMT 2012
                     0x1B4FFEE1
                     generationid_248767791
                  
                  
                     ./v6_prime_fifo_plain.vhd
                     vhdl
                     Mon Mar 12 17:01:03 GMT 2012
                     0x930FA8BA
                     generationid_248767791
                  
               
               
                  asy_generator
                  
                     ./v6_prime_fifo_plain.asy
                     asy
                     Mon Mar 12 17:01:07 GMT 2012
                     0x74958B2C
                     generationid_248767791
                  
               
               
                  xmdf_generator
                  
                     ./v6_prime_fifo_plain_xmdf.tcl
                     tclXmdf
                     tcl
                     Mon Mar 12 17:01:07 GMT 2012
                     0x0F22D906
                     generationid_248767791
                  
               
               
                  ise_generator
                  
                     ./_xmsgs/pn_parser.xmsgs
                     ignore
                     unknown
                     Mon Mar 12 17:01:12 GMT 2012
                     0x9076B5D4
                     generationid_248767791
                  
                  
                     ./v6_prime_fifo_plain.gise
                     ignore
                     gise
                     Mon Mar 12 17:01:12 GMT 2012
                     0xD2E411D6
                     generationid_248767791
                  
                  
                     ./v6_prime_fifo_plain.xise
                     ignore
                     xise
                     Mon Mar 12 17:01:12 GMT 2012
                     0x94C3B6AC
                     generationid_248767791
                  
               
               
                  deliver_readme_generator
               
               
                  flist_generator
                  
                     ./v6_prime_fifo_plain_flist.txt
                     ignore
                     txtFlist
                     txt
                     Mon Mar 12 17:01:13 GMT 2012
                     0x70544297
                     generationid_248767791
                  
               
            
         
      
      
         v6_sfifo_15x128
         Fifo Generator
         The FIFO Generator is a parameterizable first-in/first-out memory queue generator. Use it to generate resource and performance optimized FIFOs with common or independent read/write clock domains, and optional fixed or programmable full and empty flags and handshaking signals.  Choose from a selection of memory resource types for implementation.  Optional Hamming code based error detection and correction as well as error injection capability for system test help to insure data integrity.  FIFO width and depth are parameterizable, and for native interface FIFOs, asymmetric read and write port widths are also supported.
         
         
            v6_sfifo_15x128
            Common_Clock_Shift_Register
            Native
            Standard_FIFO
            128
            16
            128
            16
            false
            false
            true
            true
            Asynchronous_Reset
            1
            true
            0
            false
            false
            false
            Active_High
            false
            Active_High
            false
            Active_High
            false
            Active_High
            false
            false
            false
            false
            4
            false
            4
            false
            4
            false
            1
            1
            Single_Programmable_Full_Threshold_Constant
            12
            11
            Single_Programmable_Empty_Threshold_Constant
            2
            3
            AXI4_Stream
            Common_Clock
            false
            Slave_Interface_Clock_Enable
            false
            false
            4
            32
            64
            false
            1
            false
            1
            false
            1
            false
            1
            false
            1
            false
            64
            false
            8
            false
            4
            false
            4
            true
            false
            false
            4
            false
            4
            FIFO
            Common_Clock_Block_RAM
            Data_FIFO
            false
            false
            false
            16
            false
            false
            Full
            1023
            Empty
            1022
            FIFO
            Common_Clock_Block_RAM
            Data_FIFO
            false
            false
            false
            1024
            false
            false
            Full
            1023
            Empty
            1022
            FIFO
            Common_Clock_Block_RAM
            Data_FIFO
            false
            false
            false
            16
            false
            false
            Full
            1023
            Empty
            1022
            FIFO
            Common_Clock_Block_RAM
            Data_FIFO
            false
            false
            false
            16
            false
            false
            Full
            1023
            Empty
            1022
            FIFO
            Common_Clock_Block_RAM
            Data_FIFO
            false
            false
            false
            1024
            false
            false
            Full
            1023
            Empty
            1022
            FIFO
            Common_Clock_Block_RAM
            Data_FIFO
            false
            false
            false
            1024
            false
            false
            Full
            1023
            Empty
            1022
            Fully_Registered
            Fully_Registered
            Fully_Registered
            Fully_Registered
            Fully_Registered
            Fully_Registered
            false
            Active_High
            false
            Active_High
            false
            false
            false
            false
            false
            1
            4
            128
            0
            128
            virtex6
            1
            0
            0
            0
            0
            0
            0
            1
            0
            0
            0
            0
            0
            1
            3
            0
            1
            0
            512x72
            2
            3
            1
            12
            11
            1
            4
            16
            1
            4
            0
            1
            0
            0
            0
            0
            0
            4
            16
            1
            4
            1
            1
            0
            0
            0
            0
            0
            0
            0
            0
            0
            0
            4
            32
            64
            0
            0
            0
            0
            0
            1
            1
            1
            1
            1
            0
            0
            0
            0
            1
            0
            0
            0
            64
            8
            4
            4
            4
            4
            0
            0
            0
            0
            0
            0
            1
            1
            1
            1
            1
            1
            0
            0
            0
            0
            0
            0
            0
            0
            0
            0
            0
            0
            0
            0
            0
            0
            0
            0
            32
            64
            2
            32
            64
            1
            16
            1024
            16
            16
            1024
            1024
            4
            10
            4
            4
            10
            10
            0
            0
            0
            0
            0
            0
            0
            0
            0
            0
            0
            0
            5
            5
            5
            5
            5
            5
            1023
            1023
            1023
            1023
            1023
            1023
            5
            5
            5
            5
            5
            5
            1022
            1022
            1022
            1022
            1022
            1022
            0
            0
            0
            0
            0
            0
         
         
            
               
                  coregen
                  ./
                  ./tmp/
                  ./tmp/_cg/
               
               
                  xc6vlx240t
                  virtex6
                  ff1156
                  -1
               
               
                  BusFormatAngleBracketNotRipped
                  VHDL
                  true
                  Foundation_ISE
                  false
                  false
                  false
                  Ngc
                  false
               
               
                  Behavioral
                  VHDL_and_Verilog
                  false
               
               
                  2011-03-14T07:12:32.000Z
               
            
            
               
                  ip_upgrade_generator
                  
                     ./v6_sfifo_15x128_upgrade.txt
                     txt
                     Mon Mar 12 17:02:10 GMT 2012
                     0xAF1C584D
                     generationid_49274805
                  
               
               
                  view_upgrade_report_generator
               
               
                  model_parameter_resolution_generator
               
               
                  ip_xco_generator
                  
                     ./v6_sfifo_15x128.xco
                     xco
                     Mon Mar 12 17:02:18 GMT 2012
                     0xAE34F934
                     generationid_49274805
                  
               
               
                  associated_files_generator
                  
                     ./fifo_generator_ug175.pdf
                     pdf
                     Tue Oct 04 23:21:33 GMT 2011
                     0x42070F84
                     generationid_49274805
                  
                  
                     ./fifo_generator_v8_3_readme.txt
                     txt
                     Tue Oct 04 23:21:33 GMT 2011
                     0xCD35AB83
                     generationid_49274805
                  
               
               
                  ejava_generator
                  
                     ./v6_sfifo_15x128_ste/example_design/v6_sfifo_15x128_top.ucf
                     ignore
                     ucf
                     Mon Mar 12 17:02:19 GMT 2012
                     0xFBABF62F
                     generationid_49274805
                  
                  
                     ./v6_sfifo_15x128_ste/example_design/v6_sfifo_15x128_top.vhd
                     ignore
                     vhdl
                     Mon Mar 12 17:02:19 GMT 2012
                     0x52561756
                     generationid_49274805
                  
                  
                     ./v6_sfifo_15x128_ste/example_design/v6_sfifo_15x128_top.xdc
                     ignore
                     xdc
                     Mon Mar 12 17:02:19 GMT 2012
                     0xFFD9113C
                     generationid_49274805
                  
                  
                     ./v6_sfifo_15x128_ste/implement/implement.bat
                     ignore
                     unknown
                     Mon Mar 12 17:02:19 GMT 2012
                     0x3431D03F
                     generationid_49274805
                  
                  
                     ./v6_sfifo_15x128_ste/implement/implement.sh
                     ignore
                     unknown
                     Mon Mar 12 17:02:19 GMT 2012
                     0x3987A847
                     generationid_49274805
                  
                  
                     ./v6_sfifo_15x128_ste/implement/planAhead_rdn.bat
                     ignore
                     unknown
                     Mon Mar 12 17:02:19 GMT 2012
                     0x6E622BE0
                     generationid_49274805
                  
                  
                     ./v6_sfifo_15x128_ste/implement/planAhead_rdn.sh
                     ignore
                     unknown
                     Mon Mar 12 17:02:19 GMT 2012
                     0xA0081C7B
                     generationid_49274805
                  
                  
                     ./v6_sfifo_15x128_ste/implement/planAhead_rdn.tcl
                     ignore
                     tcl
                     Mon Mar 12 17:02:19 GMT 2012
                     0xA24BB939
                     generationid_49274805
                  
                  
                     ./v6_sfifo_15x128_ste/implement/xst.prj
                     ignore
                     unknown
                     Mon Mar 12 17:02:19 GMT 2012
                     0x855607B9
                     generationid_49274805
                  
                  
                     ./v6_sfifo_15x128_ste/implement/xst.scr
                     ignore
                     unknown
                     Mon Mar 12 17:02:19 GMT 2012
                     0x5F99CEAB
                     generationid_49274805
                  
               
               
                  ngc_netlist_generator
                  
                     ./v6_sfifo_15x128.ngc
                     ngc
                     Mon Mar 12 17:03:37 GMT 2012
                     0xF0C88D06
                     generationid_49274805
                  
               
               
                  obfuscate_netlist_generator
               
               
                  padded_implementation_netlist_generator
               
               
                  instantiation_template_generator
                  
                     ./v6_sfifo_15x128.veo
                     veo
                     Mon Mar 12 17:03:38 GMT 2012
                     0x283521E5
                     generationid_49274805
                  
                  
                     ./v6_sfifo_15x128.vho
                     vho
                     Mon Mar 12 17:03:38 GMT 2012
                     0x7EDF3CB7
                     generationid_49274805
                  
               
               
                  structural_simulation_model_generator
                  
                     ./v6_sfifo_15x128.v
                     verilog
                     Mon Mar 12 17:03:39 GMT 2012
                     0x1330A8D0
                     generationid_49274805
                  
                  
                     ./v6_sfifo_15x128.vhd
                     vhdl
                     Mon Mar 12 17:03:39 GMT 2012
                     0x62EAB166
                     generationid_49274805
                  
               
               
                  asy_generator
                  
                     ./v6_sfifo_15x128.asy
                     asy
                     Mon Mar 12 17:03:44 GMT 2012
                     0xB2B86D59
                     generationid_49274805
                  
               
               
                  xmdf_generator
                  
                     ./v6_sfifo_15x128_xmdf.tcl
                     tclXmdf
                     tcl
                     Mon Mar 12 17:03:44 GMT 2012
                     0x1027E0AA
                     generationid_49274805
                  
               
               
                  ise_generator
                  
                     ./_xmsgs/pn_parser.xmsgs
                     ignore
                     unknown
                     Mon Mar 12 17:03:49 GMT 2012
                     0xB56CC30E
                     generationid_49274805
                  
                  
                     ./v6_sfifo_15x128.gise
                     ignore
                     gise
                     Mon Mar 12 17:03:49 GMT 2012
                     0x7891BF9D
                     generationid_49274805
                  
                  
                     ./v6_sfifo_15x128.xise
                     ignore
                     xise
                     Mon Mar 12 17:03:49 GMT 2012
                     0x6BBC114D
                     generationid_49274805
                  
               
               
                  deliver_readme_generator
               
               
                  flist_generator
                  
                     ./v6_sfifo_15x128_flist.txt
                     ignore
                     txtFlist
                     txt
                     Mon Mar 12 17:03:49 GMT 2012
                     0xE47CE109
                     generationid_49274805
                  
               
            
         
      
   
   
      
         
            coregen
            ./
            ./tmp/
            ./tmp/_cg/
         
         
            xc6vlx240t
            virtex6
            ff1156
            -1
         
         
            BusFormatAngleBracketNotRipped
            VHDL
            true
            Foundation_ISE
            false
            false
            false
            Ngc
            false
         
         
            Behavioral
            VHDL_and_Verilog
            false
         
      
   

 
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Subversion Repositories pcie_sg_dma

[/] [pcie_sg_dma/] [branches/] [Virtex6/] [ML605_ISE12.3/] [ipcore_dir_ISE13.3/] [coregen.cgc] - Blame information for rev 11

Line No.	Rev	Author	Line
1	11	barabba
2
3			`xilinx.com`
4			`project`
5			`coregen`
6			`1.0`
7
8
9			`v6_afifo_1024x72`
10			`Fifo Generator`
11			The FIFO Generator is a parameterizable first-in/first-out memory queue generator. Use it to generate resource and performance optimized FIFOs with common or independent read/write clock domains, and optional fixed or programmable full and empty flags and handshaking signals. Choose from a selection of memory resource types for implementation. Optional Hamming code based error detection and correction as well as error injection capability for system test help to insure data integrity. FIFO width and depth are parameterizable, and for native interface FIFOs, asymmetric read and write port widths are also supported.
12
13
14			`v6_afifo_1024x72`
15			`Independent_Clocks_Block_RAM`
16			`Native`
17			`Standard_FIFO`
18			`72`
19			`1024`
20			`72`
21			`1024`
22			`false`
23			`false`
24			`true`
25			`true`
26			`Asynchronous_Reset`
27			`1`
28			`true`
29			`0`
30			`false`
31			`false`
32			`false`
33			`Active_High`
34			`false`
35			`Active_High`
36			`false`
37			`Active_High`
38			`false`
39			`Active_High`
40			`false`