URL https://opencores.org/ocsvn/pcie_sg_dma/pcie_sg_dma/trunk

Subversion Repositories pcie_sg_dma

[/] [pcie_sg_dma/] [branches/] [Virtex6/] [ML605_ISE12.3/] [ipcore_dir_ISE13.3/] [coregen.cgp] - Blame information for rev 11

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SET designentry = VHDL
SET BusFormat = BusFormatAngleBracketNotRipped
SET devicefamily = virtex6
SET device = xc6vlx240t
SET package = ff1156
SET speedgrade = -1
SET FlowVendor = Foundation_ISE
SET VerilogSim = True
SET VHDLSim = True

Line No.	Rev	Author	Line
1	11	barabba	`SET designentry = VHDL`
2			`SET BusFormat = BusFormatAngleBracketNotRipped`
3			`SET devicefamily = virtex6`
4			`SET device = xc6vlx240t`
5			`SET package = ff1156`
6			`SET speedgrade = -1`
7			`SET FlowVendor = Foundation_ISE`
8			`SET VerilogSim = True`
9			`SET VHDLSim = True`

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Subversion Repositories pcie_sg_dma

[/] [pcie_sg_dma/] [branches/] [Virtex6/] [ML605_ISE12.3/] [ipcore_dir_ISE13.3/] [coregen.cgp] - Blame information for rev 11