Subversion Repositories pcie_sg_dma

                    Core Name: Xilinx LogiCORE FIFO Generator

                    Version: 7.2

                    Release Date: September 21, 2010

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This document contains the following sections:

1. Introduction

2. New Features

3. Supported Devices

4. Resolved Issues

5. Known Issues

6. Technical Support

7. Core Release History

8. Legal Disclaimer

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1. INTRODUCTION

For the most recent updates to the IP installation instructions for this core,

please go to:

   http://www.xilinx.com/products/ipcenter/FIFO_Generator.htm

For software requirements, please go to the "Software Requirements" link on that page.

This file contains release notes for the Xilinx LogiCORE IP FIFO Generator v7.2

solution. For the latest core updates, see the product page at:

   http://www.xilinx.com/products/ipcenter/FIFO_Generator.htm

2. NEW FEATURES

   - AXI4 (AXI4-Stream, AXI4 and AXI4-Lite) Support (Spartan-6 and Virtex-6 devices only)

   - ISE 12.3 software support

3. SUPPORTED DEVICES

   The following device families are supported by the core for this release.

   - Virtex-6 XC CXT/LXT/SXT/HXT

   - Virtex-6 XQ LXT/SXT

   - Virtex-6 -1L XC LXT/SXT

   - Spartan-6 XC LX/LXT

   - Spartan-6 XA

   - Spartan-6 XQ LX/LXT

   - Spartan-6 -1L XC LX

   - Virtex-5 XC LX/LXT/SXT/TXT/FXT

   - Virtex-5 XQ LX/ LXT/SXT/FXT

   - Virtex-4 XC LX/SX/FX

   - Virtex-4 XQ LX/SX/FX

   - Virtex-4 XQR LX/SX/FX

   - Spartan-3 XC

   - Spartan-3 XA

   - Spartan-3A XC 3A / 3A DSP / 3AN DSP

   - Spartan-3A XA 3A / 3A DSP

   - Spartan-3E XC

   - Spartan-3E XA

4. RESOLVED ISSUES

   - In the FIFO Generator GUI, navigation buttons at the bottom are not accessible unless the screen resolution

     is set to 1600x1200 or 1900x1200.

     - CR 568630

   - The FIFO Generator GUI does not generate the core if the depth is reduced after the data count option is selected.

     - CR 570314

5. KNOWN ISSUES

   The following are known issues for v7.2 of this core at time of release:

   - In the FIFO Generator GUI, after importing an XCO file (Independent clock, distributed memory configuration)

     into a Virtex-4 CORE Generator project, if the FIFO type is changed to "Independent Clocks, Built-in FIFO" in page 1,

     page 2 does not correctly offer the Read Clock Frequency and Write Clock Frequency options as it should.

     - CR 467240

     - AR 31379

   - The FIFO Generator GUI does not generate the core if the Family is Spartan-6, and FIFO Implementation Type is

     either Common or Independent Clock Block RAM, and the depth is 64K and the width is 36.

     - CR 570041

     - AR 37201

   The most recent information, including known issues, workarounds, and

   resolutions for this version is provided in the IP Release Notes User Guide

   located at

   www.xilinx.com/support/documentation/user_guides/xtp025.pdf

6. TECHNICAL SUPPORT

   To obtain technical support, create a WebCase at www.xilinx.com/support.

   Questions are routed to a team with expertise using this product.

   Xilinx provides technical support for use of this product when used

   according to the guidelines described in the core documentation, and

   cannot guarantee timing, functionality, or support of this product for

   designs that do not follow specified guidelines.

7. CORE RELEASE HISTORY

Date        By            Version      Description

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09/21/2010  Xilinx, Inc.  7.2          ISE 12.3 support; AXI4 Support

07/30/2010  Xilinx, Inc.  7.1          ISE 13.0.1 support

06/18/2010  Xilinx, Inc.  6.2          ISE 12.2 support

04/19/2010  Xilinx, Inc.  6.1          ISE 12.1 support

12/02/2009  Xilinx, Inc.  5.3 rev 1    ISE 11.4 support; Spartan-6 Low Power and Automotive Spartan-6 Device support

09/16/2009  Xilinx, Inc.  5.3          Update to add 11.3; Virtex-6 Low Power and Virtex-6 HXT Device support

06/24/2009  Xilinx, Inc.  5.2          Update to add 11.2 and Virtex-6 CXT device support

04/24/2009  Xilinx, Inc.  5.1          Update to add 11.1 and Virtex-6 and Spartan-6 device support

09/19/2008  Xilinx, Inc.  4.4          Update to add 10.1 SP3 and Virtex-5 TXT device support and miscellaneous bug fixes

03/24/2008  Xilinx, Inc.  4.3          Update to add 10.1 support and miscellaneous bug fixes

10/03/2007  Xilinx, Inc.  4.2          Support for FWFT for Block RAM and Distributed RAM Common Clock FIFOs

08/08/2007  Xilinx, Inc.  4.1          Update to add 9.2i support; Revised to v4.1; ECC support for block RAM FIFO

04/02/2007  Xilinx, Inc.  3.3          Update to add 9.1i support; Revised to v3.3; Spartan-3A and Spartan-3A DSP support; ECC support

09/21/2006  Xilinx, Inc.  3.2          Revised to v3.2; Spartan-3 and Virtex-4 automotive device support

07/13/2006  Xilinx, Inc.  3.1          Update to add 8.2i support; Revised to v3.1; Virtex-5 support

01/11/2006  Xilinx, Inc.  2.3          Update to add 8.1i support; Revised to v2.3

08/31/2005  Xilinx, Inc.  2.2          Update to add 7.1i SP4 support; Revised to v2.2

04/28/2005  Xilinx, Inc.  2.1          Update to add 7.1i SP1 support; Revised to v2.1

11/04/2004  Xilinx, Inc.  2.0          Update to add 6.3i support; Revised to v2.0

05/21/2004  Xilinx, Inc.  1.1          Revised to v1.1; Virtex-4 support

04/23/2004  Xilinx, Inc.  1.0          Update to add 6.2i support; First release

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8. Legal Disclaimer

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