Subversion Repositories pcie_sg_dma

Message file "usenglish/ip.msg" wasn't found.

0: (0,0)   : 8x4096        u:8

1: (8,0)         : 8x4096        u:8

2: (16,0)        : 8x4096        u:8

3: (24,0)        : 8x4096        u:8

4: (32,0)        : 8x4096        u:8

5: (40,0)        : 8x4096        u:8

6: (48,0)        : 8x4096        u:8

7: (56,0)        : 8x4096        u:8

0: (0,0)   : 8x4096        u:8

1: (8,0)         : 8x4096        u:8

2: (16,0)        : 8x4096        u:8

3: (24,0)        : 8x4096        u:8

4: (32,0)        : 8x4096        u:8

5: (40,0)        : 8x4096        u:8

6: (48,0)        : 8x4096        u:8

7: (56,0)        : 8x4096        u:8

"C:\Temp\Xilinx PCI Express\pcie-v6-ml605_ISE13_User\ipcore_dir_update\tmp\_cg\_dbg\blk_mem_gen_v6_2\blk_mem_gen_prim_width.vhd" Line 977: Range is empty (null range)

"C:\Temp\Xilinx PCI Express\pcie-v6-ml605_ISE13_User\ipcore_dir_update\tmp\_cg\_dbg\blk_mem_gen_v6_2\blk_mem_gen_prim_width.vhd" Line 977: Assignment ignored

"C:\Temp\Xilinx PCI Express\pcie-v6-ml605_ISE13_User\ipcore_dir_update\tmp\_cg\_dbg\blk_mem_gen_v6_2\blk_mem_gen_prim_width.vhd" Line 978: Range is empty (null range)

"C:\Temp\Xilinx PCI Express\pcie-v6-ml605_ISE13_User\ipcore_dir_update\tmp\_cg\_dbg\blk_mem_gen_v6_2\blk_mem_gen_prim_width.vhd" Line 978: Assignment ignored

"C:\Temp\Xilinx PCI Express\pcie-v6-ml605_ISE13_User\ipcore_dir_update\tmp\_cg\_dbg\blk_mem_gen_v6_2\blk_mem_gen_prim_width.vhd" Line 429: Net <dina_pad[8]> does not have a driver.

"C:\Temp\Xilinx PCI Express\pcie-v6-ml605_ISE13_User\ipcore_dir_update\tmp\_cg\_dbg\blk_mem_gen_v6_2\blk_mem_gen_prim_width.vhd" Line 433: Net <dinb_pad[8]> does not have a driver.

"C:\Temp\Xilinx PCI Express\pcie-v6-ml605_ISE13_User\ipcore_dir_update\tmp\_cg\_dbg\blk_mem_gen_v6_2\blk_mem_gen_mux.vhd" Line 428: Comparison between arrays of unequal length always returns FALSE.

"C:\Temp\Xilinx PCI Express\pcie-v6-ml605_ISE13_User\ipcore_dir_update\tmp\_cg\_dbg\blk_mem_gen_v6_2\blk_mem_gen_mux.vhd" Line 459: Comparison between arrays of unequal length always returns FALSE.

"C:\Temp\Xilinx PCI Express\pcie-v6-ml605_ISE13_User\ipcore_dir_update\tmp\_cg\_dbg\blk_mem_gen_v6_2\blk_mem_gen_mux.vhd" Line 470: Comparison between arrays of unequal length always returns FALSE.

"C:\Temp\Xilinx PCI Express\pcie-v6-ml605_ISE13_User\ipcore_dir_update\tmp\_cg\_dbg\blk_mem_gen_v6_2\blk_mem_gen_generic_cstr.vhd" Line 446: Net <sbiterr_array[15]> does not have a driver.

"C:\Temp\Xilinx PCI Express\pcie-v6-ml605_ISE13_User\ipcore_dir_update\tmp\_cg\_dbg\blk_mem_gen_v6_2\blk_mem_gen_generic_cstr.vhd" Line 447: Net <dbiterr_array[15]> does not have a driver.

"c:/temp/xilinx pci express/pcie-v6-ml605_ise13_user/ipcore_dir_update/tmp/_cg/_dbg/v6_bram4096x64_fast.vhd" line 162: Output port <rdaddrecc> of the instance <U0> is unconnected or connected to loadless signal.

"c:/temp/xilinx pci express/pcie-v6-ml605_ise13_user/ipcore_dir_update/tmp/_cg/_dbg/v6_bram4096x64_fast.vhd" line 162: Output port <s_axi_bid> of the instance <U0> is unconnected or connected to loadless signal.

"c:/temp/xilinx pci express/pcie-v6-ml605_ise13_user/ipcore_dir_update/tmp/_cg/_dbg/v6_bram4096x64_fast.vhd" line 162: Output port <s_axi_bresp> of the instance <U0> is unconnected or connected to loadless signal.

"c:/temp/xilinx pci express/pcie-v6-ml605_ise13_user/ipcore_dir_update/tmp/_cg/_dbg/v6_bram4096x64_fast.vhd" line 162: Output port <s_axi_rid> of the instance <U0> is unconnected or connected to loadless signal.

"c:/temp/xilinx pci express/pcie-v6-ml605_ise13_user/ipcore_dir_update/tmp/_cg/_dbg/v6_bram4096x64_fast.vhd" line 162: Output port <s_axi_rdata> of the instance <U0> is unconnected or connected to loadless signal.

"c:/temp/xilinx pci express/pcie-v6-ml605_ise13_user/ipcore_dir_update/tmp/_cg/_dbg/v6_bram4096x64_fast.vhd" line 162: Output port <s_axi_rresp> of the instance <U0> is unconnected or connected to loadless signal.

"c:/temp/xilinx pci express/pcie-v6-ml605_ise13_user/ipcore_dir_update/tmp/_cg/_dbg/v6_bram4096x64_fast.vhd" line 162: Output port <s_axi_rdaddrecc> of the instance <U0> is unconnected or connected to loadless signal.

"c:/temp/xilinx pci express/pcie-v6-ml605_ise13_user/ipcore_dir_update/tmp/_cg/_dbg/v6_bram4096x64_fast.vhd" line 162: Output port <sbiterr> of the instance <U0> is unconnected or connected to loadless signal.

"c:/temp/xilinx pci express/pcie-v6-ml605_ise13_user/ipcore_dir_update/tmp/_cg/_dbg/v6_bram4096x64_fast.vhd" line 162: Output port <dbiterr> of the instance <U0> is unconnected or connected to loadless signal.

"c:/temp/xilinx pci express/pcie-v6-ml605_ise13_user/ipcore_dir_update/tmp/_cg/_dbg/v6_bram4096x64_fast.vhd" line 162: Output port <s_axi_awready> of the instance <U0> is unconnected or connected to loadless signal.

"c:/temp/xilinx pci express/pcie-v6-ml605_ise13_user/ipcore_dir_update/tmp/_cg/_dbg/v6_bram4096x64_fast.vhd" line 162: Output port <s_axi_wready> of the instance <U0> is unconnected or connected to loadless signal.

"c:/temp/xilinx pci express/pcie-v6-ml605_ise13_user/ipcore_dir_update/tmp/_cg/_dbg/v6_bram4096x64_fast.vhd" line 162: Output port <s_axi_bvalid> of the instance <U0> is unconnected or connected to loadless signal.

"c:/temp/xilinx pci express/pcie-v6-ml605_ise13_user/ipcore_dir_update/tmp/_cg/_dbg/v6_bram4096x64_fast.vhd" line 162: Output port <s_axi_arready> of the instance <U0> is unconnected or connected to loadless signal.

"c:/temp/xilinx pci express/pcie-v6-ml605_ise13_user/ipcore_dir_update/tmp/_cg/_dbg/v6_bram4096x64_fast.vhd" line 162: Output port <s_axi_rlast> of the instance <U0> is unconnected or connected to loadless signal.

"c:/temp/xilinx pci express/pcie-v6-ml605_ise13_user/ipcore_dir_update/tmp/_cg/_dbg/v6_bram4096x64_fast.vhd" line 162: Output port <s_axi_rvalid> of the instance <U0> is unconnected or connected to loadless signal.

"c:/temp/xilinx pci express/pcie-v6-ml605_ise13_user/ipcore_dir_update/tmp/_cg/_dbg/v6_bram4096x64_fast.vhd" line 162: Output port <s_axi_sbiterr> of the instance <U0> is unconnected or connected to loadless signal.

"c:/temp/xilinx pci express/pcie-v6-ml605_ise13_user/ipcore_dir_update/tmp/_cg/_dbg/v6_bram4096x64_fast.vhd" line 162: Output port <s_axi_dbiterr> of the instance <U0> is unconnected or connected to loadless signal.

Input <S_AXI_AWID<3:0>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.

Input <S_AXI_AWADDR<31:0>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.

Input <S_AXI_AWLEN<7:0>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.

Input <S_AXI_AWSIZE<2:0>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.

Input <S_AXI_AWBURST<1:0>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.

Input <S_AXI_WDATA<63:0>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.

Input <S_AXI_WSTRB<7:0>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.

Input <S_AXI_ARID<3:0>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.

Input <S_AXI_ARADDR<31:0>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.

Input <S_AXI_ARLEN<7:0>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.

Input <S_AXI_ARSIZE<2:0>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.

Input <S_AXI_ARBURST<1:0>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.

Input <S_AClk> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.

Input <S_ARESETN> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.

Input <S_AXI_AWVALID> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.

Input <S_AXI_WLAST> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.

Input <S_AXI_WVALID> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.

Input <S_AXI_BREADY> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.

Input <S_AXI_ARVALID> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.

Input <S_AXI_RREADY> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.

Input <S_AXI_INJECTSBITERR> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.

Input <S_AXI_INJECTDBITERR> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.

Signal 'S_AXI_BID', unconnected in block 'blk_mem_gen_v6_2_xst', is tied to its initial value (0000).

Signal <S_AXI_BRESP> is used but never assigned. This sourceless signal will be automatically connected to value GND.

Signal 'S_AXI_RID', unconnected in block 'blk_mem_gen_v6_2_xst', is tied to its initial value (0000).

Signal <S_AXI_RDATA> is used but never assigned. This sourceless signal will be automatically connected to value GND.

Signal <S_AXI_RRESP> is used but never assigned. This sourceless signal will be automatically connected to value GND.

Signal <S_AXI_RDADDRECC> is used but never assigned. This sourceless signal will be automatically connected to value GND.

Signal <S_AXI_AWREADY> is used but never assigned. This sourceless signal will be automatically connected to value GND.

Signal <S_AXI_WREADY> is used but never assigned. This sourceless signal will be automatically connected to value GND.

Signal <S_AXI_BVALID> is used but never assigned. This sourceless signal will be automatically connected to value GND.

Signal <S_AXI_ARREADY> is used but never assigned. This sourceless signal will be automatically connected to value GND.

Signal <S_AXI_RLAST> is used but never assigned. This sourceless signal will be automatically connected to value GND.

Signal <S_AXI_RVALID> is used but never assigned. This sourceless signal will be automatically connected to value GND.

Signal <S_AXI_SBITERR> is used but never assigned. This sourceless signal will be automatically connected to value GND.

Signal <S_AXI_DBITERR> is used but never assigned. This sourceless signal will be automatically connected to value GND.

Input <RSTA> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.

Input <ENA> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.

Input <REGCEA> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.

Input <RSTB> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.

Input <ENB> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.

Input <REGCEB> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.

Input <INJECTDBITERR> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.

Input <INJECTSBITERR> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.

Signal <INJECTDBITERR_I> is used but never assigned. This sourceless signal will be automatically connected to value GND.

Signal <INJECTSBITERR_I> is used but never assigned. This sourceless signal will be automatically connected to value GND.

Input <INJECTSBITERR> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.

Input <INJECTDBITERR> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.

"c:/temp/xilinx pci express/pcie-v6-ml605_ise13_user/ipcore_dir_update/tmp/_cg/_dbg/blk_mem_gen_v6_2/blk_mem_gen_generic_cstr.vhd" line 1341: Output port <SBITERR> of the instance <ramloop[0].ram.r> is unconnected or connected to loadless signal.

"c:/temp/xilinx pci express/pcie-v6-ml605_ise13_user/ipcore_dir_update/tmp/_cg/_dbg/blk_mem_gen_v6_2/blk_mem_gen_generic_cstr.vhd" line 1341: Output port <DBITERR> of the instance <ramloop[0].ram.r> is unconnected or connected to loadless signal.

"c:/temp/xilinx pci express/pcie-v6-ml605_ise13_user/ipcore_dir_update/tmp/_cg/_dbg/blk_mem_gen_v6_2/blk_mem_gen_generic_cstr.vhd" line 1341: Output port <SBITERR> of the instance <ramloop[1].ram.r> is unconnected or connected to loadless signal.

"c:/temp/xilinx pci express/pcie-v6-ml605_ise13_user/ipcore_dir_update/tmp/_cg/_dbg/blk_mem_gen_v6_2/blk_mem_gen_generic_cstr.vhd" line 1341: Output port <DBITERR> of the instance <ramloop[1].ram.r> is unconnected or connected to loadless signal.

"c:/temp/xilinx pci express/pcie-v6-ml605_ise13_user/ipcore_dir_update/tmp/_cg/_dbg/blk_mem_gen_v6_2/blk_mem_gen_generic_cstr.vhd" line 1341: Output port <SBITERR> of the instance <ramloop[2].ram.r> is unconnected or connected to loadless signal.

"c:/temp/xilinx pci express/pcie-v6-ml605_ise13_user/ipcore_dir_update/tmp/_cg/_dbg/blk_mem_gen_v6_2/blk_mem_gen_generic_cstr.vhd" line 1341: Output port <DBITERR> of the instance <ramloop[2].ram.r> is unconnected or connected to loadless signal.

"c:/temp/xilinx pci express/pcie-v6-ml605_ise13_user/ipcore_dir_update/tmp/_cg/_dbg/blk_mem_gen_v6_2/blk_mem_gen_generic_cstr.vhd" line 1341: Output port <SBITERR> of the instance <ramloop[3].ram.r> is unconnected or connected to loadless signal.

"c:/temp/xilinx pci express/pcie-v6-ml605_ise13_user/ipcore_dir_update/tmp/_cg/_dbg/blk_mem_gen_v6_2/blk_mem_gen_generic_cstr.vhd" line 1341: Output port <DBITERR> of the instance <ramloop[3].ram.r> is unconnected or connected to loadless signal.

"c:/temp/xilinx pci express/pcie-v6-ml605_ise13_user/ipcore_dir_update/tmp/_cg/_dbg/blk_mem_gen_v6_2/blk_mem_gen_generic_cstr.vhd" line 1341: Output port <SBITERR> of the instance <ramloop[4].ram.r> is unconnected or connected to loadless signal.

"c:/temp/xilinx pci express/pcie-v6-ml605_ise13_user/ipcore_dir_update/tmp/_cg/_dbg/blk_mem_gen_v6_2/blk_mem_gen_generic_cstr.vhd" line 1341: Output port <DBITERR> of the instance <ramloop[4].ram.r> is unconnected or connected to loadless signal.

"c:/temp/xilinx pci express/pcie-v6-ml605_ise13_user/ipcore_dir_update/tmp/_cg/_dbg/blk_mem_gen_v6_2/blk_mem_gen_generic_cstr.vhd" line 1341: Output port <SBITERR> of the instance <ramloop[5].ram.r> is unconnected or connected to loadless signal.

"c:/temp/xilinx pci express/pcie-v6-ml605_ise13_user/ipcore_dir_update/tmp/_cg/_dbg/blk_mem_gen_v6_2/blk_mem_gen_generic_cstr.vhd" line 1341: Output port <DBITERR> of the instance <ramloop[5].ram.r> is unconnected or connected to loadless signal.

"c:/temp/xilinx pci express/pcie-v6-ml605_ise13_user/ipcore_dir_update/tmp/_cg/_dbg/blk_mem_gen_v6_2/blk_mem_gen_generic_cstr.vhd" line 1341: Output port <SBITERR> of the instance <ramloop[6].ram.r> is unconnected or connected to loadless signal.

"c:/temp/xilinx pci express/pcie-v6-ml605_ise13_user/ipcore_dir_update/tmp/_cg/_dbg/blk_mem_gen_v6_2/blk_mem_gen_generic_cstr.vhd" line 1341: Output port <DBITERR> of the instance <ramloop[6].ram.r> is unconnected or connected to loadless signal.

"c:/temp/xilinx pci express/pcie-v6-ml605_ise13_user/ipcore_dir_update/tmp/_cg/_dbg/blk_mem_gen_v6_2/blk_mem_gen_generic_cstr.vhd" line 1341: Output port <SBITERR> of the instance <ramloop[7].ram.r> is unconnected or connected to loadless signal.

"c:/temp/xilinx pci express/pcie-v6-ml605_ise13_user/ipcore_dir_update/tmp/_cg/_dbg/blk_mem_gen_v6_2/blk_mem_gen_generic_cstr.vhd" line 1341: Output port <DBITERR> of the instance <ramloop[7].ram.r> is unconnected or connected to loadless signal.

"c:/temp/xilinx pci express/pcie-v6-ml605_ise13_user/ipcore_dir_update/tmp/_cg/_dbg/blk_mem_gen_v6_2/blk_mem_gen_generic_cstr.vhd" line 1604: Output port <RDADDRECC> of the instance <has_mux_a.A> is unconnected or connected to loadless signal.

"c:/temp/xilinx pci express/pcie-v6-ml605_ise13_user/ipcore_dir_update/tmp/_cg/_dbg/blk_mem_gen_v6_2/blk_mem_gen_generic_cstr.vhd" line 1604: Output port <SBITERR> of the instance <has_mux_a.A> is unconnected or connected to loadless signal.

"c:/temp/xilinx pci express/pcie-v6-ml605_ise13_user/ipcore_dir_update/tmp/_cg/_dbg/blk_mem_gen_v6_2/blk_mem_gen_generic_cstr.vhd" line 1604: Output port <DBITERR> of the instance <has_mux_a.A> is unconnected or connected to loadless signal.

"c:/temp/xilinx pci express/pcie-v6-ml605_ise13_user/ipcore_dir_update/tmp/_cg/_dbg/blk_mem_gen_v6_2/blk_mem_gen_generic_cstr.vhd" line 1748: Output port <RDADDRECC> of the instance <has_mux_b.B> is unconnected or connected to loadless signal.

"c:/temp/xilinx pci express/pcie-v6-ml605_ise13_user/ipcore_dir_update/tmp/_cg/_dbg/blk_mem_gen_v6_2/blk_mem_gen_generic_cstr.vhd" line 1748: Output port <SBITERR> of the instance <has_mux_b.B> is unconnected or connected to loadless signal.

"c:/temp/xilinx pci express/pcie-v6-ml605_ise13_user/ipcore_dir_update/tmp/_cg/_dbg/blk_mem_gen_v6_2/blk_mem_gen_generic_cstr.vhd" line 1748: Output port <DBITERR> of the instance <has_mux_b.B> is unconnected or connected to loadless signal.

Signal <RDADDRECC> is used but never assigned. This sourceless signal will be automatically connected to value GND.

Signal 'sbiterr_array', unconnected in block 'blk_mem_gen_generic_cstr', is tied to its initial value (0000000000000000).

Signal 'dbiterr_array', unconnected in block 'blk_mem_gen_generic_cstr', is tied to its initial value (0000000000000000).

Signal <SBITERR> is used but never assigned. This sourceless signal will be automatically connected to value GND.

Signal <DBITERR> is used but never assigned. This sourceless signal will be automatically connected to value GND.

Signal 'dina_pad<8>', unconnected in block 'blk_mem_gen_prim_width_1', is tied to its initial value (0).

Signal 'dinb_pad<8>', unconnected in block 'blk_mem_gen_prim_width_1', is tied to its initial value (0).

Input <SSRA> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.

Input <SSRB> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.

Input <INJECTSBITERR> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.

Input <INJECTDBITERR> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.

Signal <SBITERR> is used but never assigned. This sourceless signal will be automatically connected to value GND.

Signal <DBITERR> is used but never assigned. This sourceless signal will be automatically connected to value GND.

Signal 'dina_pad<8>', unconnected in block 'blk_mem_gen_prim_width_2', is tied to its initial value (0).

Signal 'dinb_pad<8>', unconnected in block 'blk_mem_gen_prim_width_2', is tied to its initial value (0).

Input <SSRA> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.

Input <SSRB> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.

Input <INJECTSBITERR> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.

Input <INJECTDBITERR> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.

Signal <SBITERR> is used but never assigned. This sourceless signal will be automatically connected to value GND.

Signal <DBITERR> is used but never assigned. This sourceless signal will be automatically connected to value GND.

Signal 'dina_pad<8>', unconnected in block 'blk_mem_gen_prim_width_3', is tied to its initial value (0).

Signal 'dinb_pad<8>', unconnected in block 'blk_mem_gen_prim_width_3', is tied to its initial value (0).

Input <SSRA> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.

Input <SSRB> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.

Input <INJECTSBITERR> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.

Input <INJECTDBITERR> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.

Signal <SBITERR> is used but never assigned. This sourceless signal will be automatically connected to value GND.

Signal <DBITERR> is used but never assigned. This sourceless signal will be automatically connected to value GND.

Signal 'dina_pad<8>', unconnected in block 'blk_mem_gen_prim_width_4', is tied to its initial value (0).

Signal 'dinb_pad<8>', unconnected in block 'blk_mem_gen_prim_width_4', is tied to its initial value (0).

Input <SSRA> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.

Input <SSRB> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.

Input <INJECTSBITERR> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.

Input <INJECTDBITERR> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.

Signal <SBITERR> is used but never assigned. This sourceless signal will be automatically connected to value GND.

Signal <DBITERR> is used but never assigned. This sourceless signal will be automatically connected to value GND.

Signal 'dina_pad<8>', unconnected in block 'blk_mem_gen_prim_width_5', is tied to its initial value (0).

Signal 'dinb_pad<8>', unconnected in block 'blk_mem_gen_prim_width_5', is tied to its initial value (0).

Input <SSRA> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.

Input <SSRB> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.

Input <INJECTSBITERR> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.

Input <INJECTDBITERR> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.

Signal <SBITERR> is used but never assigned. This sourceless signal will be automatically connected to value GND.

Signal <DBITERR> is used but never assigned. This sourceless signal will be automatically connected to value GND.

Signal 'dina_pad<8>', unconnected in block 'blk_mem_gen_prim_width_6', is tied to its initial value (0).

Signal 'dinb_pad<8>', unconnected in block 'blk_mem_gen_prim_width_6', is tied to its initial value (0).

Input <SSRA> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.

Input <SSRB> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.

Input <INJECTSBITERR> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.

Input <INJECTDBITERR> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.

Signal <SBITERR> is used but never assigned. This sourceless signal will be automatically connected to value GND.

Signal <DBITERR> is used but never assigned. This sourceless signal will be automatically connected to value GND.

Signal 'dina_pad<8>', unconnected in block 'blk_mem_gen_prim_width_7', is tied to its initial value (0).

Signal 'dinb_pad<8>', unconnected in block 'blk_mem_gen_prim_width_7', is tied to its initial value (0).

Input <SSRA> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.

Input <SSRB> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.

Input <INJECTSBITERR> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.

Input <INJECTDBITERR> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.

Signal <SBITERR> is used but never assigned. This sourceless signal will be automatically connected to value GND.

Signal <DBITERR> is used but never assigned. This sourceless signal will be automatically connected to value GND.

Signal 'dina_pad<8>', unconnected in block 'blk_mem_gen_prim_width_8', is tied to its initial value (0).

Signal 'dinb_pad<8>', unconnected in block 'blk_mem_gen_prim_width_8', is tied to its initial value (0).

Input <SSRA> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.

Input <SSRB> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.

Input <INJECTSBITERR> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.

Input <INJECTDBITERR> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.

Signal <SBITERR> is used but never assigned. This sourceless signal will be automatically connected to value GND.

Signal <DBITERR> is used but never assigned. This sourceless signal will be automatically connected to value GND.

Input <MUX_RST<0:0>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.

Input <MUX_REGCE<0:0>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.

Input <ADDR_IN<11:0>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.

Input <SBITERRIN<15:0>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.

Input <DBITERRIN<15:0>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.

Input <MEM_LAT_RST> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.

Input <MEM_REG_RST> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.

Input <MEM_REGCE> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.

Input <WE> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.

Input <RDADDRECC_I<11:0>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.

Input <CLKB> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.

Input <SBITERR_I> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.

Input <DBITERR_I> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.

Signal <RDADDRECC> is used but never assigned. This sourceless signal will be automatically connected to value GND.

Signal <SBITERR> is used but never assigned. This sourceless signal will be automatically connected to value GND.

Signal <DBITERR> is used but never assigned. This sourceless signal will be automatically connected to value GND.

Node <has_mux_b.B/sel_pipe_0> of sequential type is unconnected in block <blk_mem_gen_generic_cstr>.

Node <has_mux_a.A/sel_pipe_0> of sequential type is unconnected in block <blk_mem_gen_generic_cstr>.

HDL ADVISOR - Some clock signals were not automatically buffered by XST with BUFG/BUFR resources. Please use the buffer_type constraint in order to insert these buffers to the clock signals to help prevent skew problems.