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[/] [pcie_sg_dma/] [branches/] [Virtex6/] [ML605_ISE12.3/] [iseconfig/] [v6pcie.projectmgr] - Blame information for rev 11

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         /PCIe_UserLogic_03 - structural C:|Temp|Xilinx PCI Express|pcie-v6-ml605_ISE12_User|MyUserLogicMultiTiming|PCIe_UserLogic_03.vhd
11
         /PCIe_UserLogic_04 - structural C:|Temp|Xilinx PCI Express|pcie-v6-ml605_ISE12_User|MyUserLogicMultiTiming_New|PCIe_UserLogic_04.vhd
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         /PCIe_UserLogic_05 - structural C:|Temp|Xilinx PCI Express|pcie-v6-ml605_ISE12_User|MyUserLogic|PCIe_UserLogic_05.vhd
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         /PCIe_UserLogic_06 - structural C:|Temp|Xilinx PCI Express|pcie-v6-ml605_ISE12_User|MyUserLogic06|PCIe_UserLogic_06.vhd
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         /Unassigned User Library Modules
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         /abb_dgen - Behavioral C:|Temp|Xilinx PCI Express|pcie-v6-ml605_ISE12_Clean|abb_dgen.vhd
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         /bram_DDRs_Control - Behavioral C:|Temp|Xilinx PCI Express|pcie-v6-ml605_ISE12_OpenCores|bram_DDRs_Control_Loopback.vhd
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         /bram_DDRs_loopback - Behavioral C:|Temp|Xilinx PCI Express|pcie-v6-ml605_ISE12_OpenCores|bram_DDRs_Control_Loopback.vhd
18
         /class_ctl - Behavioral C:|Temp|Xilinx PCI Express|pcie-v6-ml605_ISE12_Clean|class_ctl.vhd
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         /class_daq - Behavioral C:|Temp|Xilinx PCI Express|pcie-v6-ml605_ISE12_Clean|class_daq.vhd
20
         /class_dlm - Behavioral C:|Temp|Xilinx PCI Express|pcie-v6-ml605_ISE12_Clean|class_dlm.vhd
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         /pcie_2_0_v6 C:|Temp|Xilinx PCI Express|pcie-v6-ml605_ISE12_User|v6_pcie_v1_3|source|pcie_2_0_v6.v
22
         /pcie_userlogic_01 - structural C:|Temp|Xilinx PCI Express|pcie-v6-ml605_ISE12_Clean|MyUserLogic|pcie_userlogic_01.vhd/chipscope - xlchipscope - behavior
23
         /pcie_userlogic_01 - structural C:|Temp|Xilinx PCI Express|pcie-v6-ml605_ISE12_Clean|MyUserLogic|pcie_userlogic_01.vhd/rise_detector_3_513dad66ef - rise_detector_3_entity_513dad66ef - structural
24
         /pcie_userlogic_01_cw - structural C:|Temp|Xilinx PCI Express|pcie-v6-ml605_ISE12_Clean|MyUserLogic|pcie_userlogic_01_cw.vhd/default_clock_driver_x0 - default_clock_driver - structural
25
         /pcie_userlogic_01_cw - structural C:|Temp|Xilinx PCI Express|pcie-v6-ml605_ISE12_Clean|MyUserLogic|pcie_userlogic_01_cw.vhd/pcie_userlogic_01_x0 - pcie_userlogic_01 - structural
26
         /pcie_userlogic_02_cw - structural C:|Temp|Xilinx PCI Express|pcie-v6-ml605_ISE12_Clean|MyUserLogic|pcie_userlogic_02_cw.vhd
27
         /pcie_userlogic_02_cw - structural C:|Temp|Xilinx PCI Express|pcie-v6-ml605_ISE12_User|MyUserLogic|pcie_userlogic_02_cw.vhd/default_clock_driver_x0 - default_clock_driver - structural
28
         /pcie_userlogic_02_cw - structural C:|Temp|Xilinx PCI Express|pcie-v6-ml605_ISE12_User|MyUserLogic|pcie_userlogic_02_cw.vhd/pcie_userlogic_02_x0 - pcie_userlogic_02 - structural
29
         /pcie_userlogic_02_mcw - structural C:|Temp|Xilinx PCI Express|pcie-v6-ml605_ISE12_User|MyUserLogic|pcie_userlogic_02_mcw.vhd/pcie_userlogic_02_x0 - pcie_userlogic_02 - structural
30
         /protocol_IF - Behavioral C:|Temp|Xilinx PCI Express|pcie-v6-ml605_ISE12_Clean|protocol_if.vhd
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         /synth_reg - structural C:|Temp|Xilinx PCI Express|pcie-v6-ml605_ISE12_Clean|MyUserLogic|pcie_userlogic_02.vhd
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         /synth_reg - structural C:|Temp|Xilinx PCI Express|pcie-v6-ml605_ISE12_User|MyUserLogic|pcie_userlogic_02.vhd
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         /synth_reg_w_init - structural C:|Temp|Xilinx PCI Express|pcie-v6-ml605_ISE12_User|MyUserLogic06|PCIe_UserLogic_06.vhd
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         /synth_reg_w_init - structural C:|Temp|Xilinx PCI Express|pcie-v6-ml605_ISE12_User|MyUserLogic06|PCIe_UserLogic_07.vhd
35
         /synth_reg_w_init - structural C:|Temp|Xilinx PCI Express|pcie-v6-ml605_ISE12_User|MyUserLogic|pcie_userlogic_02.vhd
36
         /tf64_pcie_trn C:|Temp|Xilinx PCI Express|pcie-v6-ml605_ISE12_Clean|MySim|tf64_pcie_trn.v
37
         /v6_pcie_v1_3 C:|Temp|Xilinx PCI Express|pcie-v6-ml605_ISE12_User|v6_pcie_v1_3|source|v6_pcie_v1_3.v
38
         /v6_pcie_v1_3 C:|Temp|Xilinx PCI Express|pcie-v6-ml605_ISE12_User|v6_pcie_v1_3|source|v6_pcie_v1_3.v/pcie_2_0_i - pcie_2_0_v6/pcie_bram_i - pcie_bram_top_v6
39
         /v6_pcie_v1_3 C:|Temp|Xilinx PCI Express|pcie-v6-ml605_ISE12_User|v6_pcie_v1_3|source|v6_pcie_v1_3.v/pcie_2_0_i - pcie_2_0_v6/pcie_gt_i - pcie_gtx_v6
40
         /v6_pcie_v1_3 C:|Temp|Xilinx PCI Express|pcie-v6-ml605_ISE12_User|v6_pcie_v1_3|source|v6_pcie_v1_3.v/pcie_2_0_i - pcie_2_0_v6/pcie_pipe_i - pcie_pipe_v6
41
         /v6_pcie_v1_3x8 C:|Temp|Xilinx PCI Express|pcie-v6-ml605_ISE12_Clean|v6_pcie_v1_3|source|v6_pcie_v1_3x8.v
42
         /v6_pcie_v1_6 - v6_pcie C:|Temp|Xilinx PCI Express|pcie-v6-ml605_ISE12_User|ipcore_dir|v6_pcie_v1_6|source|v6_pcie_v1_6.vhd
43
         /v6_pcie_v1_6 - v6_pcie C:|Temp|Xilinx PCI Express|pcie-v6-ml605_ISE12_User|ipcore_dir|v6_pcie_v1_6|source|v6_pcie_v1_6.vhd/pcie_2_0_i - pcie_2_0_v6 - v6_pcie/pcie_bram_i - pcie_bram_top_v6 - v6_pcie
44
         /v6_pcie_v1_6 - v6_pcie C:|Temp|Xilinx PCI Express|pcie-v6-ml605_ISE12_User|ipcore_dir|v6_pcie_v1_6|source|v6_pcie_v1_6.vhd/pcie_2_0_i - pcie_2_0_v6 - v6_pcie/pcie_gt_i - pcie_gtx_v6 - v6_pcie/gtx_v6_i - gtx_wrapper_v6 - v6_pcie
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         /v6_pcie_v1_6 - v6_pcie C:|Temp|Xilinx PCI Express|pcie-v6-ml605_ISE12_User|ipcore_dir|v6_pcie_v1_6|source|v6_pcie_v1_6.vhd/pcie_2_0_i - pcie_2_0_v6 - v6_pcie/pcie_pipe_i - pcie_pipe_v6 - v6_pcie
46
         /v6pcieDMA - Behavioral C:|Temp|Xilinx PCI Express|pcie-v6-ml605_ISE12_Clean|v6eb_pcie.vhd/DDRs_ctrl_module - bram_DDRs_Control - Behavioral
47
         /v6pcieDMA - Behavioral C:|Temp|Xilinx PCI Express|pcie-v6-ml605_ISE12_Clean|v6eb_pcie.vhd/my_pcie_userlogic_01_cw - pcie_userlogic_01_cw - structural
48
         /v6pcieDMA - Behavioral C:|Temp|Xilinx PCI Express|pcie-v6-ml605_ISE12_Clean|v6eb_pcie.vhd/pcieCore - v6_pcie_v1_3
49
         /v6pcieDMA - Behavioral C:|Temp|Xilinx PCI Express|pcie-v6-ml605_ISE12_Clean|v6eb_pcie.vhd/queue_buffer0 - eb_wrapper - Behavioral
50
         /v6pcieDMA - Behavioral C:|Temp|Xilinx PCI Express|pcie-v6-ml605_ISE12_Clean|v6eb_pcie.vhd/theTlpControl - tlpControl - Behavioral/rx_Itf - rx_Transact - Behavioral
51
         /v6pcieDMA - Behavioral C:|Temp|Xilinx PCI Express|pcie-v6-ml605_ISE12_OpenCores|v6eb_pcie.vhd/DDRs_ctrl_module - bram_DDRs_Control - Behavioral
52
         /v6pcieDMA - Behavioral C:|Temp|Xilinx PCI Express|pcie-v6-ml605_ISE12_OpenCores|v6eb_pcie.vhd/DDRs_ctrl_module - bram_DDRs_Control_loopback - Behavioral
53
         /v6pcieDMA - Behavioral C:|Temp|Xilinx PCI Express|pcie-v6-ml605_ISE12_OpenCores|v6eb_pcie.vhd/pcieCore - v6_pcie_v1_6 - v6_pcie
54
         /v6pcieDMA - Behavioral C:|Temp|Xilinx PCI Express|pcie-v6-ml605_ISE12_OpenCores|v6eb_pcie.vhd/pcie_userlogic_07_x0 - PCIe_UserLogic_07 - structural
55
         /v6pcieDMA - Behavioral C:|Temp|Xilinx PCI Express|pcie-v6-ml605_ISE12_OpenCores|v6eb_pcie.vhd/queue_buffer0 - eb_wrapper - Behavioral
56
         /v6pcieDMA - Behavioral C:|Temp|Xilinx PCI Express|pcie-v6-ml605_ISE12_OpenCores|v6eb_pcie.vhd/queue_buffer0 - eb_wrapper_loopback - Behavioral
57
         /v6pcieDMA - Behavioral C:|Temp|Xilinx PCI Express|pcie-v6-ml605_ISE12_OpenCores|v6eb_pcie.vhd/theTlpControl - tlpControl - Behavioral
58
         /v6pcieDMA - Behavioral C:|Temp|Xilinx PCI Express|pcie-v6-ml605_ISE12_OpenCores|v6eb_pcie.vhd/theTlpControl - tlpControl - Behavioral/rx_Itf - rx_Transact - Behavioral
59
         /v6pcieDMA - Behavioral C:|Temp|Xilinx PCI Express|pcie-v6-ml605_ISE12_OpenCores|v6eb_pcie.vhd/theTlpControl - tlpControl - Behavioral/rx_Itf - rx_Transact - Behavioral/CplD_Channel - rx_CplD_Transact - Behavioral
60
         /v6pcieDMA - Behavioral C:|Temp|Xilinx PCI Express|pcie-v6-ml605_ISE12_OpenCores|v6eb_pcie.vhd/theTlpControl - tlpControl - Behavioral/rx_Itf - rx_Transact - Behavioral/Downstream_DMA_Engine - dsDMA_Transact - Behavioral
61
         /v6pcieDMA - Behavioral C:|Temp|Xilinx PCI Express|pcie-v6-ml605_ISE12_OpenCores|v6eb_pcie.vhd/theTlpControl - tlpControl - Behavioral/rx_Itf - rx_Transact - Behavioral/MRd_Channel - rx_MRd_Transact - Behavioral
62
         /v6pcieDMA - Behavioral C:|Temp|Xilinx PCI Express|pcie-v6-ml605_ISE12_OpenCores|v6eb_pcie.vhd/theTlpControl - tlpControl - Behavioral/rx_Itf - rx_Transact - Behavioral/Upstream_DMA_Engine - usDMA_Transact - Behavioral
63
         /v6pcieDMA - Behavioral C:|Temp|Xilinx PCI Express|pcie-v6-ml605_ISE12_OpenCores|v6eb_pcie.vhd/theTlpControl - tlpControl - Behavioral/tx_Itf - tx_Transact - Behavioral
64
         /v6pcieDMA - Behavioral C:|Temp|Xilinx PCI Express|pcie-v6-ml605_ISE12_Original|v6eb_pcie.vhd/ABB_DCB_Interface0 - protocol_IF - Behavioral
65
         /v6pcieDMA - Behavioral C:|Temp|Xilinx PCI Express|pcie-v6-ml605_ISE12_Original|v6eb_pcie.vhd/DDRs_ctrl_module - bram_DDRs_Control - Behavioral
66
         /v6pcieDMA - Behavioral C:|Temp|Xilinx PCI Express|pcie-v6-ml605_ISE12_Original|v6eb_pcie.vhd/event_buffer0 - eb_wrapper - Behavioral
67
         /v6pcieDMA - Behavioral C:|Temp|Xilinx PCI Express|pcie-v6-ml605_ISE12_Original|v6eb_pcie.vhd/my_pcie_userlogic_01_cw - pcie_userlogic_01_cw - structural
68
         /v6pcieDMA - Behavioral C:|Temp|Xilinx PCI Express|pcie-v6-ml605_ISE12_Original|v6eb_pcie.vhd/pcieCore - v6_pcie_v1_3
69
         /v6pcieDMA - Behavioral C:|Temp|Xilinx PCI Express|pcie-v6-ml605_ISE12_Original|v6eb_pcie.vhd/pcieCore - v6_pcie_v1_3x8
70
         /v6pcieDMA - Behavioral C:|Temp|Xilinx PCI Express|pcie-v6-ml605_ISE12_Original|v6eb_pcie.vhd/theTlpControl - tlpControl - Behavioral
71
         /v6pcieDMA - Behavioral C:|Temp|Xilinx PCI Express|pcie-v6-ml605_ISE12_User|v6eb_pcie.vhd/DDRs_ctrl_module - bram_DDRs_Control - Behavioral
72
         /v6pcieDMA - Behavioral C:|Temp|Xilinx PCI Express|pcie-v6-ml605_ISE12_User|v6eb_pcie.vhd/pcieCore - v6_pcie_v1_3
73
         /v6pcieDMA - Behavioral C:|Temp|Xilinx PCI Express|pcie-v6-ml605_ISE12_User|v6eb_pcie.vhd/pcieCore - v6_pcie_v1_3/pcie_2_0_i - pcie_2_0_v6
74
         /v6pcieDMA - Behavioral C:|Temp|Xilinx PCI Express|pcie-v6-ml605_ISE12_User|v6eb_pcie.vhd/pcieCore - v6_pcie_v1_3/pcie_2_0_i - pcie_2_0_v6/pcie_bram_i - pcie_bram_top_v6
75
         /v6pcieDMA - Behavioral C:|Temp|Xilinx PCI Express|pcie-v6-ml605_ISE12_User|v6eb_pcie.vhd/pcieCore - v6_pcie_v1_3/pcie_2_0_i - pcie_2_0_v6/pcie_pipe_i - pcie_pipe_v6
76
         /v6pcieDMA - Behavioral C:|Temp|Xilinx PCI Express|pcie-v6-ml605_ISE12_User|v6eb_pcie.vhd/pcieCore - v6_pcie_v1_6 - v6_pcie
77
         /v6pcieDMA - Behavioral C:|Temp|Xilinx PCI Express|pcie-v6-ml605_ISE12_User|v6eb_pcie.vhd/pcieCore - v6_pcie_v1_6 - v6_pcie/pcie_2_0_i - pcie_2_0_v6 - v6_pcie/pcie_bram_i - pcie_bram_top_v6 - v6_pcie
78
         /v6pcieDMA - Behavioral C:|Temp|Xilinx PCI Express|pcie-v6-ml605_ISE12_User|v6eb_pcie.vhd/pcieCore - v6_pcie_v1_6 - v6_pcie/pcie_2_0_i - pcie_2_0_v6 - v6_pcie/pcie_gt_i - pcie_gtx_v6 - v6_pcie/gtx_v6_i - gtx_wrapper_v6 - v6_pcie
79
         /v6pcieDMA - Behavioral C:|Temp|Xilinx PCI Express|pcie-v6-ml605_ISE12_User|v6eb_pcie.vhd/pcieCore - v6_pcie_v1_6 - v6_pcie/pcie_2_0_i - pcie_2_0_v6 - v6_pcie/pcie_pipe_i - pcie_pipe_v6 - v6_pcie
80
         /v6pcieDMA - Behavioral C:|Temp|Xilinx PCI Express|pcie-v6-ml605_ISE12_User|v6eb_pcie.vhd/pcie_userlogic_02_x0 - pcie_userlogic_02_mcw - structural
81
         /v6pcieDMA - Behavioral C:|Temp|Xilinx PCI Express|pcie-v6-ml605_ISE12_User|v6eb_pcie.vhd/pcie_userlogic_03_x0 - PCIe_UserLogic_03 - structural
82
         /v6pcieDMA - Behavioral C:|Temp|Xilinx PCI Express|pcie-v6-ml605_ISE12_User|v6eb_pcie.vhd/pcie_userlogic_03_x0 - PCIe_UserLogic_03 - structural/debug1i - synth_reg_w_init - structural
83
         /v6pcieDMA - Behavioral C:|Temp|Xilinx PCI Express|pcie-v6-ml605_ISE12_User|v6eb_pcie.vhd/pcie_userlogic_03_x0 - PCIe_UserLogic_03 - structural/debug2i - synth_reg_w_init - structural
84
         /v6pcieDMA - Behavioral C:|Temp|Xilinx PCI Express|pcie-v6-ml605_ISE12_User|v6eb_pcie.vhd/pcie_userlogic_03_x0 - PCIe_UserLogic_03 - structural/debug3i - synth_reg_w_init - structural
85
         /v6pcieDMA - Behavioral C:|Temp|Xilinx PCI Express|pcie-v6-ml605_ISE12_User|v6eb_pcie.vhd/pcie_userlogic_03_x0 - PCIe_UserLogic_03 - structural/register01rd - synth_reg_w_init - structural
86
         /v6pcieDMA - Behavioral C:|Temp|Xilinx PCI Express|pcie-v6-ml605_ISE12_User|v6eb_pcie.vhd/pcie_userlogic_03_x0 - PCIe_UserLogic_03 - structural/register01rv - synth_reg_w_init - structural
87
         /v6pcieDMA - Behavioral C:|Temp|Xilinx PCI Express|pcie-v6-ml605_ISE12_User|v6eb_pcie.vhd/pcie_userlogic_03_x0 - PCIe_UserLogic_03 - structural/register01td - synth_reg_w_init - structural
88
         /v6pcieDMA - Behavioral C:|Temp|Xilinx PCI Express|pcie-v6-ml605_ISE12_User|v6eb_pcie.vhd/pcie_userlogic_03_x0 - PCIe_UserLogic_03 - structural/register01tv - synth_reg_w_init - structural
89
         /v6pcieDMA - Behavioral C:|Temp|Xilinx PCI Express|pcie-v6-ml605_ISE12_User|v6eb_pcie.vhd/pcie_userlogic_03_x0 - PCIe_UserLogic_03 - structural/register02rd - synth_reg_w_init - structural
90
         /v6pcieDMA - Behavioral C:|Temp|Xilinx PCI Express|pcie-v6-ml605_ISE12_User|v6eb_pcie.vhd/pcie_userlogic_03_x0 - PCIe_UserLogic_03 - structural/register02rv - synth_reg_w_init - structural
91
         /v6pcieDMA - Behavioral C:|Temp|Xilinx PCI Express|pcie-v6-ml605_ISE12_User|v6eb_pcie.vhd/pcie_userlogic_03_x0 - PCIe_UserLogic_03 - structural/register02td - synth_reg_w_init - structural
92
         /v6pcieDMA - Behavioral C:|Temp|Xilinx PCI Express|pcie-v6-ml605_ISE12_User|v6eb_pcie.vhd/pcie_userlogic_03_x0 - PCIe_UserLogic_03 - structural/register02tv - synth_reg_w_init - structural
93
         /v6pcieDMA - Behavioral C:|Temp|Xilinx PCI Express|pcie-v6-ml605_ISE12_User|v6eb_pcie.vhd/pcie_userlogic_03_x0 - PCIe_UserLogic_03 - structural/register03rd - synth_reg_w_init - structural
94
         /v6pcieDMA - Behavioral C:|Temp|Xilinx PCI Express|pcie-v6-ml605_ISE12_User|v6eb_pcie.vhd/pcie_userlogic_03_x0 - PCIe_UserLogic_03 - structural/register03rv - synth_reg_w_init - structural
95
         /v6pcieDMA - Behavioral C:|Temp|Xilinx PCI Express|pcie-v6-ml605_ISE12_User|v6eb_pcie.vhd/pcie_userlogic_03_x0 - PCIe_UserLogic_03 - structural/register03td - synth_reg_w_init - structural
96
         /v6pcieDMA - Behavioral C:|Temp|Xilinx PCI Express|pcie-v6-ml605_ISE12_User|v6eb_pcie.vhd/pcie_userlogic_03_x0 - PCIe_UserLogic_03 - structural/register03tv - synth_reg_w_init - structural
97
         /v6pcieDMA - Behavioral C:|Temp|Xilinx PCI Express|pcie-v6-ml605_ISE12_User|v6eb_pcie.vhd/pcie_userlogic_04_x0 - PCIe_UserLogic_04 - structural
98
         /v6pcieDMA - Behavioral C:|Temp|Xilinx PCI Express|pcie-v6-ml605_ISE12_User|v6eb_pcie.vhd/pcie_userlogic_04_x0 - PCIe_UserLogic_05 - structural
99
         /v6pcieDMA - Behavioral C:|Temp|Xilinx PCI Express|pcie-v6-ml605_ISE12_User|v6eb_pcie.vhd/pcie_userlogic_06_x0 - PCIe_UserLogic_06 - structural
100
         /v6pcieDMA - Behavioral C:|Temp|Xilinx PCI Express|pcie-v6-ml605_ISE12_User|v6eb_pcie.vhd/pcie_userlogic_06_x0 - PCIe_UserLogic_06 - structural/DMA_Host2Board_Busy_x0 - synth_reg_w_init - structural
101
         /v6pcieDMA - Behavioral C:|Temp|Xilinx PCI Express|pcie-v6-ml605_ISE12_User|v6eb_pcie.vhd/pcie_userlogic_06_x0 - PCIe_UserLogic_06 - structural/DMA_Host2Board_Done_x0 - synth_reg_w_init - structural
102
         /v6pcieDMA - Behavioral C:|Temp|Xilinx PCI Express|pcie-v6-ml605_ISE12_User|v6eb_pcie.vhd/pcie_userlogic_06_x0 - PCIe_UserLogic_06 - structural/debug1i - synth_reg_w_init - structural
103
         /v6pcieDMA - Behavioral C:|Temp|Xilinx PCI Express|pcie-v6-ml605_ISE12_User|v6eb_pcie.vhd/pcie_userlogic_06_x0 - PCIe_UserLogic_06 - structural/debug2i - synth_reg_w_init - structural
104
         /v6pcieDMA - Behavioral C:|Temp|Xilinx PCI Express|pcie-v6-ml605_ISE12_User|v6eb_pcie.vhd/pcie_userlogic_06_x0 - PCIe_UserLogic_06 - structural/debug3i - synth_reg_w_init - structural
105
         /v6pcieDMA - Behavioral C:|Temp|Xilinx PCI Express|pcie-v6-ml605_ISE12_User|v6eb_pcie.vhd/pcie_userlogic_06_x0 - PCIe_UserLogic_06 - structural/debug4i - synth_reg_w_init - structural
106
         /v6pcieDMA - Behavioral C:|Temp|Xilinx PCI Express|pcie-v6-ml605_ISE12_User|v6eb_pcie.vhd/pcie_userlogic_06_x0 - PCIe_UserLogic_06 - structural/register01rd - synth_reg_w_init - structural
107
         /v6pcieDMA - Behavioral C:|Temp|Xilinx PCI Express|pcie-v6-ml605_ISE12_User|v6eb_pcie.vhd/pcie_userlogic_06_x0 - PCIe_UserLogic_06 - structural/register01rv - synth_reg_w_init - structural
108
         /v6pcieDMA - Behavioral C:|Temp|Xilinx PCI Express|pcie-v6-ml605_ISE12_User|v6eb_pcie.vhd/pcie_userlogic_06_x0 - PCIe_UserLogic_06 - structural/register01td - synth_reg_w_init - structural
109
         /v6pcieDMA - Behavioral C:|Temp|Xilinx PCI Express|pcie-v6-ml605_ISE12_User|v6eb_pcie.vhd/pcie_userlogic_06_x0 - PCIe_UserLogic_06 - structural/register01tv - synth_reg_w_init - structural
110
         /v6pcieDMA - Behavioral C:|Temp|Xilinx PCI Express|pcie-v6-ml605_ISE12_User|v6eb_pcie.vhd/pcie_userlogic_06_x0 - PCIe_UserLogic_06 - structural/register02rd - synth_reg_w_init - structural
111
         /v6pcieDMA - Behavioral C:|Temp|Xilinx PCI Express|pcie-v6-ml605_ISE12_User|v6eb_pcie.vhd/pcie_userlogic_06_x0 - PCIe_UserLogic_06 - structural/register02rv - synth_reg_w_init - structural
112
         /v6pcieDMA - Behavioral C:|Temp|Xilinx PCI Express|pcie-v6-ml605_ISE12_User|v6eb_pcie.vhd/pcie_userlogic_06_x0 - PCIe_UserLogic_06 - structural/register02td - synth_reg_w_init - structural
113
         /v6pcieDMA - Behavioral C:|Temp|Xilinx PCI Express|pcie-v6-ml605_ISE12_User|v6eb_pcie.vhd/pcie_userlogic_06_x0 - PCIe_UserLogic_06 - structural/register02tv - synth_reg_w_init - structural
114
         /v6pcieDMA - Behavioral C:|Temp|Xilinx PCI Express|pcie-v6-ml605_ISE12_User|v6eb_pcie.vhd/pcie_userlogic_06_x0 - PCIe_UserLogic_06 - structural/register03rd - synth_reg_w_init - structural
115
         /v6pcieDMA - Behavioral C:|Temp|Xilinx PCI Express|pcie-v6-ml605_ISE12_User|v6eb_pcie.vhd/pcie_userlogic_06_x0 - PCIe_UserLogic_06 - structural/register03rv - synth_reg_w_init - structural
116
         /v6pcieDMA - Behavioral C:|Temp|Xilinx PCI Express|pcie-v6-ml605_ISE12_User|v6eb_pcie.vhd/pcie_userlogic_06_x0 - PCIe_UserLogic_06 - structural/register03td - synth_reg_w_init - structural
117
         /v6pcieDMA - Behavioral C:|Temp|Xilinx PCI Express|pcie-v6-ml605_ISE12_User|v6eb_pcie.vhd/pcie_userlogic_06_x0 - PCIe_UserLogic_06 - structural/register03tv - synth_reg_w_init - structural
118
         /v6pcieDMA - Behavioral C:|Temp|Xilinx PCI Express|pcie-v6-ml605_ISE12_User|v6eb_pcie.vhd/pcie_userlogic_06_x0 - PCIe_UserLogic_06 - structural/register04rd - synth_reg_w_init - structural
119
         /v6pcieDMA - Behavioral C:|Temp|Xilinx PCI Express|pcie-v6-ml605_ISE12_User|v6eb_pcie.vhd/pcie_userlogic_06_x0 - PCIe_UserLogic_06 - structural/register04rv - synth_reg_w_init - structural
120
         /v6pcieDMA - Behavioral C:|Temp|Xilinx PCI Express|pcie-v6-ml605_ISE12_User|v6eb_pcie.vhd/pcie_userlogic_06_x0 - PCIe_UserLogic_06 - structural/register04td - synth_reg_w_init - structural
121
         /v6pcieDMA - Behavioral C:|Temp|Xilinx PCI Express|pcie-v6-ml605_ISE12_User|v6eb_pcie.vhd/pcie_userlogic_06_x0 - PCIe_UserLogic_06 - structural/register04tv - synth_reg_w_init - structural
122
         /v6pcieDMA - Behavioral C:|Temp|Xilinx PCI Express|pcie-v6-ml605_ISE12_User|v6eb_pcie.vhd/pcie_userlogic_06_x0 - PCIe_UserLogic_06 - structural/register05rd - synth_reg_w_init - structural
123
         /v6pcieDMA - Behavioral C:|Temp|Xilinx PCI Express|pcie-v6-ml605_ISE12_User|v6eb_pcie.vhd/pcie_userlogic_06_x0 - PCIe_UserLogic_06 - structural/register05rv - synth_reg_w_init - structural
124
         /v6pcieDMA - Behavioral C:|Temp|Xilinx PCI Express|pcie-v6-ml605_ISE12_User|v6eb_pcie.vhd/pcie_userlogic_06_x0 - PCIe_UserLogic_06 - structural/register05td - synth_reg_w_init - structural
125
         /v6pcieDMA - Behavioral C:|Temp|Xilinx PCI Express|pcie-v6-ml605_ISE12_User|v6eb_pcie.vhd/pcie_userlogic_06_x0 - PCIe_UserLogic_06 - structural/register05tv - synth_reg_w_init - structural
126
         /v6pcieDMA - Behavioral C:|Temp|Xilinx PCI Express|pcie-v6-ml605_ISE12_User|v6eb_pcie.vhd/pcie_userlogic_06_x0 - PCIe_UserLogic_06 - structural/register06rd - synth_reg_w_init - structural
127
         /v6pcieDMA - Behavioral C:|Temp|Xilinx PCI Express|pcie-v6-ml605_ISE12_User|v6eb_pcie.vhd/pcie_userlogic_06_x0 - PCIe_UserLogic_06 - structural/register06rv - synth_reg_w_init - structural
128
         /v6pcieDMA - Behavioral C:|Temp|Xilinx PCI Express|pcie-v6-ml605_ISE12_User|v6eb_pcie.vhd/pcie_userlogic_06_x0 - PCIe_UserLogic_06 - structural/register06td - synth_reg_w_init - structural
129
         /v6pcieDMA - Behavioral C:|Temp|Xilinx PCI Express|pcie-v6-ml605_ISE12_User|v6eb_pcie.vhd/pcie_userlogic_06_x0 - PCIe_UserLogic_06 - structural/register06tv - synth_reg_w_init - structural
130
         /v6pcieDMA - Behavioral C:|Temp|Xilinx PCI Express|pcie-v6-ml605_ISE12_User|v6eb_pcie.vhd/pcie_userlogic_06_x0 - PCIe_UserLogic_06 - structural/register07rd - synth_reg_w_init - structural
131
         /v6pcieDMA - Behavioral C:|Temp|Xilinx PCI Express|pcie-v6-ml605_ISE12_User|v6eb_pcie.vhd/pcie_userlogic_06_x0 - PCIe_UserLogic_06 - structural/register07rv - synth_reg_w_init - structural
132
         /v6pcieDMA - Behavioral C:|Temp|Xilinx PCI Express|pcie-v6-ml605_ISE12_User|v6eb_pcie.vhd/pcie_userlogic_06_x0 - PCIe_UserLogic_06 - structural/register07td - synth_reg_w_init - structural
133
         /v6pcieDMA - Behavioral C:|Temp|Xilinx PCI Express|pcie-v6-ml605_ISE12_User|v6eb_pcie.vhd/pcie_userlogic_06_x0 - PCIe_UserLogic_06 - structural/register07tv - synth_reg_w_init - structural
134
         /v6pcieDMA - Behavioral C:|Temp|Xilinx PCI Express|pcie-v6-ml605_ISE12_User|v6eb_pcie.vhd/pcie_userlogic_06_x0 - PCIe_UserLogic_06 - structural/register08rd - synth_reg_w_init - structural
135
         /v6pcieDMA - Behavioral C:|Temp|Xilinx PCI Express|pcie-v6-ml605_ISE12_User|v6eb_pcie.vhd/pcie_userlogic_06_x0 - PCIe_UserLogic_06 - structural/register08rv - synth_reg_w_init - structural
136
         /v6pcieDMA - Behavioral C:|Temp|Xilinx PCI Express|pcie-v6-ml605_ISE12_User|v6eb_pcie.vhd/pcie_userlogic_06_x0 - PCIe_UserLogic_06 - structural/register08td - synth_reg_w_init - structural
137
         /v6pcieDMA - Behavioral C:|Temp|Xilinx PCI Express|pcie-v6-ml605_ISE12_User|v6eb_pcie.vhd/pcie_userlogic_06_x0 - PCIe_UserLogic_06 - structural/register08tv - synth_reg_w_init - structural
138
         /v6pcieDMA - Behavioral C:|Temp|Xilinx PCI Express|pcie-v6-ml605_ISE12_User|v6eb_pcie.vhd/pcie_userlogic_06_x0 - PCIe_UserLogic_06 - structural/register09rd - synth_reg_w_init - structural
139
         /v6pcieDMA - Behavioral C:|Temp|Xilinx PCI Express|pcie-v6-ml605_ISE12_User|v6eb_pcie.vhd/pcie_userlogic_06_x0 - PCIe_UserLogic_06 - structural/register09rv - synth_reg_w_init - structural
140
         /v6pcieDMA - Behavioral C:|Temp|Xilinx PCI Express|pcie-v6-ml605_ISE12_User|v6eb_pcie.vhd/pcie_userlogic_06_x0 - PCIe_UserLogic_06 - structural/register09td - synth_reg_w_init - structural
141
         /v6pcieDMA - Behavioral C:|Temp|Xilinx PCI Express|pcie-v6-ml605_ISE12_User|v6eb_pcie.vhd/pcie_userlogic_06_x0 - PCIe_UserLogic_06 - structural/register09tv - synth_reg_w_init - structural
142
         /v6pcieDMA - Behavioral C:|Temp|Xilinx PCI Express|pcie-v6-ml605_ISE12_User|v6eb_pcie.vhd/pcie_userlogic_06_x0 - PCIe_UserLogic_06 - structural/register10rd - synth_reg_w_init - structural
143
         /v6pcieDMA - Behavioral C:|Temp|Xilinx PCI Express|pcie-v6-ml605_ISE12_User|v6eb_pcie.vhd/pcie_userlogic_06_x0 - PCIe_UserLogic_06 - structural/register10rv - synth_reg_w_init - structural
144
         /v6pcieDMA - Behavioral C:|Temp|Xilinx PCI Express|pcie-v6-ml605_ISE12_User|v6eb_pcie.vhd/pcie_userlogic_06_x0 - PCIe_UserLogic_06 - structural/register10td - synth_reg_w_init - structural
145
         /v6pcieDMA - Behavioral C:|Temp|Xilinx PCI Express|pcie-v6-ml605_ISE12_User|v6eb_pcie.vhd/pcie_userlogic_06_x0 - PCIe_UserLogic_06 - structural/register10tv - synth_reg_w_init - structural
146
         /v6pcieDMA - Behavioral C:|Temp|Xilinx PCI Express|pcie-v6-ml605_ISE12_User|v6eb_pcie.vhd/pcie_userlogic_07_x0 - PCIe_UserLogic_07 - structural
147
         /v6pcieDMA - Behavioral C:|Temp|Xilinx PCI Express|pcie-v6-ml605_ISE12_User|v6eb_pcie.vhd/queue_buffer0 - eb_wrapper - Behavioral
148
         /v6pcieDMA - Behavioral C:|Temp|Xilinx PCI Express|pcie-v6-ml605_ISE12_User|v6eb_pcie.vhd/theTlpControl - tlpControl - Behavioral
149
         /v6pcieDMA - Behavioral C:|Temp|Xilinx PCI Express|pcie-v6-ml605_ISE12_User|v6eb_pcie.vhd/theTlpControl - tlpControl - Behavioral/rx_Itf - rx_Transact - Behavioral
150
         /v6pcieDMA - Behavioral C:|Temp|Xilinx PCI Express|pcie-v6-ml605_ISE12_User|v6eb_pcie.vhd/theTlpControl - tlpControl - Behavioral/rx_Itf - rx_Transact - Behavioral/CplD_Channel - rx_CplD_Transact - Behavioral
151
         /v6pcieDMA - Behavioral C:|Temp|Xilinx PCI Express|pcie-v6-ml605_ISE12_User|v6eb_pcie.vhd/theTlpControl - tlpControl - Behavioral/rx_Itf - rx_Transact - Behavioral/Downstream_DMA_Engine - dsDMA_Transact - Behavioral
152
         /v6pcieDMA - Behavioral C:|Temp|Xilinx PCI Express|pcie-v6-ml605_ISE12_User|v6eb_pcie.vhd/theTlpControl - tlpControl - Behavioral/rx_Itf - rx_Transact - Behavioral/MRd_Channel - rx_MRd_Transact - Behavioral
153
         /v6pcieDMA - Behavioral C:|Temp|Xilinx PCI Express|pcie-v6-ml605_ISE12_User|v6eb_pcie.vhd/theTlpControl - tlpControl - Behavioral/rx_Itf - rx_Transact - Behavioral/Upstream_DMA_Engine - usDMA_Transact - Behavioral
154
         /v6pcieDMA - Behavioral C:|Temp|Xilinx PCI Express|pcie-v6-ml605_ISE12_User|v6eb_pcie.vhd/theTlpControl - tlpControl - Behavioral/tx_Itf - tx_Transact - Behavioral
155
      
156
      
157
         v6pcieDMA - Behavioral (C:/Temp/Xilinx PCI Express/pcie-v6-ml605_ISE12_OpenCores/v6eb_pcie.vhd)
158
      
159
      0
160
      0
161
      000000ff00000000000000010000000100000000000000000000000000000000020200000001000000010000006400000296000000020000000000000000000000000000000064ffffffff000000810000000000000002000002960000000100000000000000000000000100000000
162
      false
163
      v6pcieDMA - Behavioral (C:/Temp/Xilinx PCI Express/pcie-v6-ml605_ISE12_OpenCores/v6eb_pcie.vhd)
164
   
165
   
166
      
167
         1
168
         Configure Target Device
169
         Design Utilities/Compile HDL Simulation Libraries
170
         Implement Design/Map
171
         Implement Design/Place & Route
172
         Implement Design/Place & Route/Back-annotate Pin Locations
173
         Implement Design/Place & Route/Generate IBIS Model
174
         Implement Design/Translate
175
         User Constraints
176
      
177
      
178
         
179
      
180
      3
181
      0
182
      000000ff000000000000000100000001000000000000000000000000000000000000000000000001e5000000010000000100000000000000000000000064ffffffff000000810000000000000001000001e50000000100000000
183
      false
184
      
185
   
186
   
187
      
188
         1
189
      
190
      
191
         v6abb64Package_efifo_elink.vhd
192
      
193
      10
194
      0
195
      000000ff0000000000000001000000000000000001000000000000000000000000000000000000038f000000040101000100000000000000000000000064ffffffff0000008100000000000000040000015900000001000000000000014500000001000000000000006600000001000000000000008b0000000100000000
196
      false
197
      v6abb64Package_efifo_elink.vhd
198
   
199
   
200
      
201
         1
202
         work
203
      
204
      
205
      0
206
      0
207
      000000ff00000000000000010000000000000000010000000000000000000000000000000000000109000000010001000100000000000000000000000064ffffffff000000810000000000000001000001090000000100000000
208
      false
209
      work
210
   
211
   
212
      
213
         1
214
      
215
      
216
         
217
      
218
      0
219
      0
220
      000000ff00000000000000010000000100000000000000000000000000000000000000000000000158000000010000000100000000000000000000000064ffffffff000000810000000000000001000001580000000100000000
221
      false
222
      
223
   
224
   000000ff0000000000000002000001a80000012001000000040100000002
225
   Implementation
226
   
227
      
228
         1
229
      
230
      
231
         
232
      
233
      0
234
      0
235
      000000ff00000000000000010000000100000000000000000000000000000000000000000000000252000000010000000100000000000000000000000064ffffffff000000810000000000000001000002520000000100000000
236
      false
237
      
238
   
239
   
240
      
241
         1
242
         Design Utilities/Compile HDL Simulation Libraries
243
      
244
      
245
         
246
      
247
      0
248
      0
249
      000000ff000000000000000100000001000000000000000000000000000000000000000000000001f7000000010000000100000000000000000000000064ffffffff000000810000000000000001000001f70000000100000000
250
      false
251
      
252
   
253
   
254
      
255
         1
256
      
257
      
258
         CORE Generator
259
      
260
      0
261
      0
262
      000000ff000000000000000100000001000000000000000000000000000000000000000000000001ab000000010000000100000000000000000000000064ffffffff000000810000000000000001000001ab0000000100000000
263
      false
264
      CORE Generator
265
   
266
   
267
      
268
         1
269
      
270
      
271
         
272
      
273
      0
274
      0
275
      000000ff000000000000000100000001000000000000000000000000000000000000000000000001ce000000010000000100000000000000000000000064ffffffff000000810000000000000001000001ce0000000100000000
276
      false
277
      
278
   
279
   
280
      
281
         2
282
         /PCIe_UserLogic_07 - structural C:|Temp|Xilinx PCI Express|pcie-v6-ml605_ISE12_OpenCores|MyUserLogic06|PCIe_UserLogic_07.vhd
283
         /bram_DDRs_Control - Behavioral C:|Temp|Xilinx PCI Express|pcie-v6-ml605_ISE12_OpenCores|bram_DDRs_Control.vhd
284
         /eb_wrapper - Behavioral C:|Temp|Xilinx PCI Express|pcie-v6-ml605_ISE12_OpenCores|FIFO_Wrapper.vhd
285
         /tf64_pcie_trn C:|Temp|Xilinx PCI Express|pcie-v6-ml605_ISE12_OpenCores|MySim|tf64_pcie_trn.v
286
         /tf64_pcie_trn C:|Temp|Xilinx PCI Express|pcie-v6-ml605_ISE12_OpenCores|MySim|tf64_pcie_trn.v/DDRs_ctrl_module - bram_DDRs_Control - Behavioral
287
         /tf64_pcie_trn C:|Temp|Xilinx PCI Express|pcie-v6-ml605_ISE12_OpenCores|MySim|tf64_pcie_trn.v/DDRs_ctrl_module - bram_DDRs_Control_loopback - Behavioral
288
         /tf64_pcie_trn C:|Temp|Xilinx PCI Express|pcie-v6-ml605_ISE12_OpenCores|MySim|tf64_pcie_trn.v/queue_buffer - eb_wrapper - Behavioral
289
         /tf64_pcie_trn C:|Temp|Xilinx PCI Express|pcie-v6-ml605_ISE12_OpenCores|MySim|tf64_pcie_trn.v/queue_buffer - eb_wrapper_loopback - Behavioral
290
         /tf64_pcie_trn C:|Temp|Xilinx PCI Express|pcie-v6-ml605_ISE12_OpenCores|MySim|tf64_pcie_trn.v/uut - tlpControl - Behavioral
291
         /v6_pcie_v1_6 - v6_pcie C:|Temp|Xilinx PCI Express|pcie-v6-ml605_ISE12_OpenCores|ipcore_dir_update|v6_pcie_v1_6|source|v6_pcie_v1_6.vhd
292
         /v6pcieDMA - Behavioral C:|Temp|Xilinx PCI Express|pcie-v6-ml605_ISE12_OpenCores|v6eb_pcie.vhd
293
         /v6pcieDMA - Behavioral C:|Temp|Xilinx PCI Express|pcie-v6-ml605_ISE12_User|v6eb_pcie.vhd
294
      
295
      
296
         tf64_pcie_trn (C:/Temp/Xilinx PCI Express/pcie-v6-ml605_ISE12_OpenCores/MySim/tf64_pcie_trn.v)
297
      
298
      0
299
      0
300
      000000ff00000000000000010000000100000000000000000000000000000000020200000001000000010000006400000129000000020000000000000000000000000000000064ffffffff000000810000000000000002000001290000000100000000000000000000000100000000
301
      false
302
      tf64_pcie_trn (C:/Temp/Xilinx PCI Express/pcie-v6-ml605_ISE12_OpenCores/MySim/tf64_pcie_trn.v)
303
   
304
   
305
      
306
         1
307
         Design Utilities
308
         ISim Simulator
309
      
310
      
311
         
312
      
313
      0
314
      0
315
      000000ff000000000000000100000001000000000000000000000000000000000000000000000001f7000000010000000100000000000000000000000064ffffffff000000810000000000000001000001f70000000100000000
316
      false
317
      
318
   
319
   
320
      
321
         1
322
      
323
      
324
         
325
      
326
      0
327
      0
328
      000000ff0000000000000001000000010000000000000000000000000000000000000000000000021a000000010000000100000000000000000000000064ffffffff0000008100000000000000010000021a0000000100000000
329
      false
330
      
331
   
332
   
333
      
334
         1
335
      
336
      
337
         Simulate Behavioral Model
338
      
339
      0
340
      0
341
      000000ff000000000000000100000001000000000000000000000000000000000000000000000001f7000000010000000100000000000000000000000064ffffffff000000810000000000000001000001f70000000100000000
342
      false
343
      Simulate Behavioral Model
344
   
345
   
346
      
347
         1
348
         ISim Simulator
349
      
350
      
351
         
352
      
353
      0
354
      0
355
      000000ff000000000000000100000001000000000000000000000000000000000000000000000001f7000000010000000100000000000000000000000064ffffffff000000810000000000000001000001f70000000100000000
356
      false
357
      
358
   
359

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