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[/] [pcie_sg_dma/] [branches/] [Virtex6/] [ML605_ISE12.3/] [pcie_sg_dma/] [Virtex6/] [ML605/] [FIFO_Wrapper.vhd] - Blame information for rev 11

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----------------------------------------------------------------------------------
-- Company:  ZITI
-- Engineer:  wgao
-- 
-- Create Date:    16:37:22 12 Feb 2009
-- Design Name: 
-- Module Name:    eb_wrapper - Behavioral 
-- Project Name: 
-- Target Devices: 
-- Tool versions: 
-- Description: 
--
-- Dependencies: 
--
-- Revision: 
-- Revision 0.01 - File Created
-- Additional Comments: 
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
 
library work;
use work.abb64Package.all;
 
---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
 
entity eb_wrapper is
    Generic (
             C_ASYNFIFO_WIDTH  :  integer  :=  72
            );
    Port (
          wr_clk      : IN  std_logic;
          wr_en       : IN  std_logic;
          din         : IN  std_logic_VECTOR(C_ASYNFIFO_WIDTH-1 downto 0);
          pfull       : OUT std_logic;
          full        : OUT std_logic;
 
          rd_clk      : IN  std_logic;
          rd_en       : IN  std_logic;
          dout        : OUT std_logic_VECTOR(C_ASYNFIFO_WIDTH-1 downto 0);
          pempty      : OUT std_logic;
          empty       : OUT std_logic;
 
          data_count  : OUT std_logic_VECTOR(C_EMU_FIFO_DC_WIDTH-1 downto 0);
          rst         : IN  std_logic
          );
end entity eb_wrapper;
 
 
architecture Behavioral of eb_wrapper is
 
  ---  16384 x 72
  component eb_fifo
    port (
      wr_clk      : IN  std_logic;
      wr_en       : IN  std_logic;
      din         : IN  std_logic_VECTOR(C_ASYNFIFO_WIDTH-1 downto 0);
      prog_full   : OUT std_logic;
      full        : OUT std_logic;
 
      rd_clk      : IN  std_logic;
      rd_en       : IN  std_logic;
      dout        : OUT std_logic_VECTOR(C_ASYNFIFO_WIDTH-1 downto 0);
      prog_empty  : OUT std_logic;
      empty       : OUT std_logic;
 
      rst         : IN  std_logic
      );
  end component;
 
  ---  16384 x 72, with data count synchronized to rd_clk
  component v6_eb_fifo_counted
    port (
      wr_clk      : IN  std_logic;
      wr_en       : IN  std_logic;
      din         : IN  std_logic_VECTOR(C_ASYNFIFO_WIDTH-1 downto 0);
      prog_full   : OUT std_logic;
      full        : OUT std_logic;
 
      rd_clk      : IN  std_logic;
      rd_en       : IN  std_logic;
      dout        : OUT std_logic_VECTOR(C_ASYNFIFO_WIDTH-1 downto 0);
      prog_empty  : OUT std_logic;
      empty       : OUT std_logic;
      rd_data_count  : OUT std_logic_VECTOR(C_EMU_FIFO_DC_WIDTH-1 downto 0);
 
      rst         : IN  std_logic
      );
  end component;
 
  signal data_count_wire    : std_logic_VECTOR(C_EMU_FIFO_DC_WIDTH-1 downto 0);
  signal data_count_i       : std_logic_VECTOR(C_EMU_FIFO_DC_WIDTH-1 downto 0);
 
begin
 
  data_count     <= data_count_i;
 
  --  ------------------------------------------
  Syn_EB_FIFO_data_count:
  process (rd_clk)
  begin
    if rd_clk'event and rd_clk = '1' then
       data_count_i    <= data_count_wire;
    end if;
  end process;
 
  --  ------------------------------------------
  U0:
  v6_eb_fifo_counted
    port map (
         wr_clk     => wr_clk   ,
         wr_en      => wr_en    ,
         din        => din      ,
         prog_full  => pfull    ,
         full       => full     ,
 
         rd_clk     => rd_clk   ,
         rd_en      => rd_en    ,
         dout       => dout     ,
         prog_empty => pempty   ,
         empty      => empty    ,
         rd_data_count  =>  data_count_wire  ,
 
         rst        => rst
         );
 
end architecture Behavioral;

Line No.	Rev	Author	Line
1	11	barabba	`----------------------------------------------------------------------------------`
2			`-- Company: ZITI`
3			`-- Engineer: wgao`
4			`--`
5			`-- Create Date: 16:37:22 12 Feb 2009`
6			`-- Design Name:`
7			`-- Module Name: eb_wrapper - Behavioral`
8			`-- Project Name:`
9			`-- Target Devices:`
10			`-- Tool versions:`
11			`-- Description:`
12			`--`
13			`-- Dependencies:`
14			`--`
15			`-- Revision:`
16			`-- Revision 0.01 - File Created`
17			`-- Additional Comments:`
18			`--`
19			`----------------------------------------------------------------------------------`
20			`library IEEE;`
21			`use IEEE.STD_LOGIC_1164.ALL;`
22			`use IEEE.STD_LOGIC_ARITH.ALL;`
23			`use IEEE.STD_LOGIC_UNSIGNED.ALL;`
24
25			`library work;`
26			`use work.abb64Package.all;`
27
28			`---- Uncomment the following library declaration if instantiating`
29			`---- any Xilinx primitives in this code.`
30			`--library UNISIM;`
31			`--use UNISIM.VComponents.all;`
32
33			`entity eb_wrapper is`
34			`Generic (`
35			`C_ASYNFIFO_WIDTH : integer := 72`
36			`);`
37			`Port (`
38			`wr_clk : IN std_logic;`
39			`wr_en : IN std_logic;`
40			`din : IN std_logic_VECTOR(C_ASYNFIFO_WIDTH-1 downto 0);`
41			`pfull : OUT std_logic;`
42			`full : OUT std_logic;`
43
44			`rd_clk : IN std_logic;`
45			`rd_en : IN std_logic;`
46			`dout : OUT std_logic_VECTOR(C_ASYNFIFO_WIDTH-1 downto 0);`
47			`pempty : OUT std_logic;`
48			`empty : OUT std_logic;`
49
50			`data_count : OUT std_logic_VECTOR(C_EMU_FIFO_DC_WIDTH-1 downto 0);`
51			`rst : IN std_logic`
52			`);`
53			`end entity eb_wrapper;`
54
55
56			`architecture Behavioral of eb_wrapper is`
57
58			`--- 16384 x 72`
59			`component eb_fifo`
60			`port (`
61			`wr_clk : IN std_logic;`
62			`wr_en : IN std_logic;`
63			`din : IN std_logic_VECTOR(C_ASYNFIFO_WIDTH-1 downto 0);`
64			`prog_full : OUT std_logic;`
65			`full : OUT std_logic;`
66
67			`rd_clk : IN std_logic;`
68			`rd_en : IN std_logic;`
69			`dout : OUT std_logic_VECTOR(C_ASYNFIFO_WIDTH-1 downto 0);`
70			`prog_empty : OUT std_logic;`
71			`empty : OUT std_logic;`
72
73			`rst : IN std_logic`
74			`);`
75			`end component;`
76
77			`--- 16384 x 72, with data count synchronized to rd_clk`
78			`component v6_eb_fifo_counted`
79			`port (`
80			`wr_clk : IN std_logic;`
81			`wr_en : IN std_logic;`
82			`din : IN std_logic_VECTOR(C_ASYNFIFO_WIDTH-1 downto 0);`
83			`prog_full : OUT std_logic;`
84			`full : OUT std_logic;`
85
86			`rd_clk : IN std_logic;`
87			`rd_en : IN std_logic;`
88			`dout : OUT std_logic_VECTOR(C_ASYNFIFO_WIDTH-1 downto 0);`
89			`prog_empty : OUT std_logic;`
90			`empty : OUT std_logic;`
91			`rd_data_count : OUT std_logic_VECTOR(C_EMU_FIFO_DC_WIDTH-1 downto 0);`
92
93			`rst : IN std_logic`
94			`);`
95			`end component;`
96
97			`signal data_count_wire : std_logic_VECTOR(C_EMU_FIFO_DC_WIDTH-1 downto 0);`
98			`signal data_count_i : std_logic_VECTOR(C_EMU_FIFO_DC_WIDTH-1 downto 0);`
99
100			`begin`
101
102			`data_count <= data_count_i;`
103
104			`-- ------------------------------------------`
105			`Syn_EB_FIFO_data_count:`
106			`process (rd_clk)`
107			`begin`
108			`if rd_clk'event and rd_clk = '1' then`
109			`data_count_i <= data_count_wire;`
110			`end if;`
111			`end process;`
112
113			`-- ------------------------------------------`
114			`U0:`
115			`v6_eb_fifo_counted`
116			`port map (`
117			`wr_clk => wr_clk ,`
118			`wr_en => wr_en ,`
119			`din => din ,`
120			`prog_full => pfull ,`
121			`full => full ,`
122
123			`rd_clk => rd_clk ,`
124			`rd_en => rd_en ,`
125			`dout => dout ,`
126			`prog_empty => pempty ,`
127			`empty => empty ,`
128			`rd_data_count => data_count_wire ,`
129
130			`rst => rst`
131			`);`
132
133			`end architecture Behavioral;`

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[/] [pcie_sg_dma/] [branches/] [Virtex6/] [ML605_ISE12.3/] [pcie_sg_dma/] [Virtex6/] [ML605/] [FIFO_Wrapper.vhd] - Blame information for rev 11