OpenCores
URL https://opencores.org/ocsvn/pcie_sg_dma/pcie_sg_dma/trunk

Subversion Repositories pcie_sg_dma

[/] [pcie_sg_dma/] [branches/] [Virtex6/] [ML605_ISE12.3/] [pcie_sg_dma/] [Virtex6/] [ML605/] [Registers.vhd] - Blame information for rev 11

Details | Compare with Previous | View Log

Line No. Rev Author Line
1 11 barabba 
----------------------------------------------------------------------------------
2 
-- Company:
3 
-- Engineer:
4 
--
5 
-- Design Name:
6 
-- Module Name:    Regs_Group - Behavioral
7 
-- Project Name:
8 
-- Target Devices:
9 
-- Tool versions:
10 
-- Description:
11 
--
12 
-- Dependencies:
13 
--
14 
-- Revision:
15 
--
16 
-- Revision 1.10 - Readability improved by FOR-LOOP used  19.03.2007
17 
--
18 
-- Revision 1.00 - File Created  06.02.2007
19 
--
20 
-- Additional Comments:
21 
--
22 
----------------------------------------------------------------------------------
23 
 
24 
library IEEE;
25 
use IEEE.STD_LOGIC_1164.ALL;
26 
use IEEE.STD_LOGIC_ARITH.ALL;
27 
use IEEE.STD_LOGIC_UNSIGNED.ALL;
28 
 
29 
 
30 
library work;
31 
use work.abb64Package.all;
32 
 
33 
---- Uncomment the following library declaration if instantiating
34 
---- any Xilinx primitives in this code.
35 
library UNISIM;
36 
use UNISIM.VComponents.all;
37 
 
38 
entity Regs_Group is
39 
    port (
40 
 
41 
      -- DCB protocol interface
42 
      protocol_link_act        : IN  std_logic_vector(2-1 downto 0);
43 
      protocol_rst             : OUT std_logic;
44 
 
45 
      -- Fabric side: CTL Rx
46 
      ctl_rv                   : OUT std_logic;
47 
      ctl_rd                   : OUT std_logic_vector(C_DBUS_WIDTH/2-1 downto 0);
48 
 
49 
      -- Fabric side: CTL Tx
50 
      ctl_ttake                : OUT std_logic;
51 
      ctl_tv                   : IN  std_logic;
52 
      ctl_td                   : IN  std_logic_vector(C_DBUS_WIDTH/2-1 downto 0);
53 
      ctl_tstop                : OUT std_logic;
54 
 
55 
      ctl_reset                : OUT std_logic;
56 
      ctl_status               : IN  std_logic_vector(C_DBUS_WIDTH/2-1 downto 0);
57 
 
58 
      -- Fabric side: DLM Rx
59 
      dlm_tv                   : OUT std_logic;
60 
      dlm_td                   : OUT std_logic_vector(C_DBUS_WIDTH/2-1 downto 0);
61 
 
62 
      -- Fabric side: DLM Tx
63 
      dlm_rv                   : IN  std_logic;
64 
      dlm_rd                   : IN  std_logic_vector(C_DBUS_WIDTH/2-1 downto 0);
65 
 
66 
      -- Event Buffer status + reset
67 
      eb_FIFO_Status           : IN  std_logic_vector(C_DBUS_WIDTH-1 downto 0);
68 
      eb_FIFO_Rst              : OUT std_logic;
69 
      eb_FIFO_ow               : IN  std_logic;
70 
 
71 
      -- Write interface
72 
      Regs_WrEnA               : IN  std_logic;
73 
      Regs_WrMaskA             : IN  std_logic_vector(2-1 downto 0);
74 
      Regs_WrAddrA             : IN  std_logic_vector(C_EP_AWIDTH-1 downto 0);
75 
      Regs_WrDinA              : IN  std_logic_vector(C_DBUS_WIDTH-1 downto 0);
76 
 
77 
      Regs_WrEnB               : IN  std_logic;
78 
      Regs_WrMaskB             : IN  std_logic_vector(2-1 downto 0);
79 
      Regs_WrAddrB             : IN  std_logic_vector(C_EP_AWIDTH-1 downto 0);
80 
      Regs_WrDinB              : IN  std_logic_vector(C_DBUS_WIDTH-1 downto 0);
81 
 
82 
      -- Register Read interface
83 
      Regs_RdAddr              : IN  std_logic_vector(C_EP_AWIDTH-1 downto 0);
84 
      Regs_RdQout              : OUT std_logic_vector(C_DBUS_WIDTH-1 downto 0);
85 
 
86 
      -- Downstream DMA transferred bytes count up
87 
      ds_DMA_Bytes_Add         : IN  std_logic;
88 
      ds_DMA_Bytes             : IN  std_logic_vector(C_TLP_FLD_WIDTH_OF_LENG+2 downto 0);
89 
 
90 
     -- Registers to/from Downstream Engine
91 
      DMA_ds_PA                : OUT std_logic_vector(C_DBUS_WIDTH-1 downto 0);
92 
      DMA_ds_HA                : OUT std_logic_vector(C_DBUS_WIDTH-1 downto 0);
93 
      DMA_ds_BDA               : OUT std_logic_vector(C_DBUS_WIDTH-1 downto 0);
94 
      DMA_ds_Length            : OUT std_logic_vector(C_DBUS_WIDTH-1 downto 0);
95 
      DMA_ds_Control           : OUT std_logic_vector(C_DBUS_WIDTH-1 downto 0);
96 
      dsDMA_BDA_eq_Null        : OUT std_logic;      -- obsolete
97 
      DMA_ds_Status            : IN  std_logic_vector(C_DBUS_WIDTH-1 downto 0);
98 
      DMA_ds_Done              : IN  std_logic;
99 
      DMA_ds_Tout              : IN  std_logic;
100 
 
101 
      -- Calculation in advance, for better timing
102 
      dsHA_is_64b              : OUT std_logic;
103 
      dsBDA_is_64b             : OUT std_logic;
104 
 
105 
      -- Calculation in advance, for better timing
106 
      dsLeng_Hi19b_True        : OUT std_logic;
107 
      dsLeng_Lo7b_True         : OUT std_logic;
108 
 
109 
      -- Downstream Control Signals
110 
      dsDMA_Start              : OUT std_logic;
111 
      dsDMA_Stop               : OUT std_logic;
112 
      dsDMA_Start2             : OUT std_logic;
113 
      dsDMA_Stop2              : OUT std_logic;
114 
      dsDMA_Channel_Rst        : OUT std_logic;
115 
      dsDMA_Cmd_Ack            : IN  std_logic;
116 
 
117 
 
118 
      -- Upstream DMA transferred bytes count up
119 
      us_DMA_Bytes_Add         : IN  std_logic;
120 
      us_DMA_Bytes             : IN  std_logic_vector(C_TLP_FLD_WIDTH_OF_LENG+2 downto 0);
121 
 
122 
      -- Registers to/from Upstream Engine
123 
      DMA_us_PA                : OUT std_logic_vector(C_DBUS_WIDTH-1 downto 0);
124 
      DMA_us_HA                : OUT std_logic_vector(C_DBUS_WIDTH-1 downto 0);
125 
      DMA_us_BDA               : OUT std_logic_vector(C_DBUS_WIDTH-1 downto 0);
126 
      DMA_us_Length            : OUT std_logic_vector(C_DBUS_WIDTH-1 downto 0);
127 
      DMA_us_Control           : OUT std_logic_vector(C_DBUS_WIDTH-1 downto 0);
128 
      usDMA_BDA_eq_Null        : OUT std_logic;      -- obsolete
129 
      us_MWr_Param_Vec         : OUT std_logic_vector(6-1 downto 0);
130 
      DMA_us_Status            : IN  std_logic_vector(C_DBUS_WIDTH-1 downto 0);
131 
      DMA_us_Done              : IN  std_logic;
132 
      DMA_us_Tout              : IN  std_logic;
133 
 
134 
      -- Calculation in advance, for better timing
135 
      usHA_is_64b              : OUT std_logic;
136 
      usBDA_is_64b             : OUT std_logic;
137 
 
138 
      -- Calculation in advance, for better timing
139 
      usLeng_Hi19b_True        : OUT std_logic;
140 
      usLeng_Lo7b_True         : OUT std_logic;
141 
 
142 
      -- Upstream Control Signals
143 
      usDMA_Start              : OUT std_logic;
144 
      usDMA_Stop               : OUT std_logic;
145 
      usDMA_Start2             : OUT std_logic;
146 
      usDMA_Stop2              : OUT std_logic;
147 
      usDMA_Channel_Rst        : OUT std_logic;
148 
      usDMA_Cmd_Ack            : IN  std_logic;
149 
 
150 
      -- MRd Channel Reset
151 
      MRd_Channel_Rst          : OUT std_logic;
152 
 
153 
      -- Tx module reset
154 
      Tx_Reset                 : OUT std_logic;
155 
 
156 
                -- to Interrupts Module
157 
      Sys_IRQ                  : OUT std_logic_vector(C_DBUS_WIDTH-1 downto 0);
158 
      DAQ_irq                  : IN  std_logic;
159 
      CTL_irq                  : IN  std_logic;
160 
      DLM_irq                  : IN  std_logic;
161 
 
162 
      -- System error and info
163 
      Tx_TimeOut               : IN  std_logic;
164 
      Tx_eb_TimeOut            : IN  std_logic;
165 
      Msg_Routing              : OUT std_logic_vector(C_GCR_MSG_ROUT_BIT_TOP-C_GCR_MSG_ROUT_BIT_BOT downto 0);
166 
      pcie_link_width          : IN  std_logic_vector(CINT_BIT_LWIDTH_IN_GSR_TOP-CINT_BIT_LWIDTH_IN_GSR_BOT downto 0);
167 
      cfg_dcommand             : IN  std_logic_vector(16-1 downto 0);
168 
 
169 
      -- Interrupt Generation Signals
170 
      IG_Reset                 : OUT std_logic;
171 
      IG_Host_Clear            : OUT std_logic;
172 
      IG_Latency               : OUT std_logic_vector(C_DBUS_WIDTH-1 downto 0);
173 
      IG_Num_Assert            : IN  std_logic_vector(C_DBUS_WIDTH-1 downto 0);
174 
      IG_Num_Deassert          : IN  std_logic_vector(C_DBUS_WIDTH-1 downto 0);
175 
      IG_Asserting             : IN  std_logic;
176 
 
177 
      -- Data generator control
178 
      DG_is_Running            : IN  std_logic;
179 
      DG_Reset                 : OUT std_logic;
180 
      DG_Mask                  : OUT std_logic;
181 
 
182 
      -- Clock and reset
183 
      trn_clk                  : IN  std_logic;
184 
      trn_lnk_up_n             : IN  std_logic;
185 
      trn_reset_n              : IN  std_logic
186 
 
187 
    );
188 
end Regs_Group;
189 
 
190 
 
191 
architecture Behavioral of Regs_Group is
192 
 
193 
  type    icapStates is        ( icapST_Reset
194 
                               , icapST_Idle
195 
                               , icapST_Access
196 
                               , icapST_Abort
197 
                               );
198 
 
199 
  -- State variables of ICAP
200 
  signal  FSM_icap             : icapStates;
201 
 
202 
 
203 
  ----------------------------------------------------------------------------
204 
  ----------------------------------------------------------------------------
205 
  signal  Regs_WrDin_i         : std_logic_vector(C_DBUS_WIDTH-1   downto 0);
206 
  signal  Regs_WrAddr_i        : std_logic_vector(C_EP_AWIDTH-1   downto 0);
207 
  signal  Regs_WrMask_i        : std_logic_vector(2-1   downto 0);
208 
 
209 
  ------  Delay signals
210 
  signal  Regs_WrEn_r1         : std_logic;
211 
  signal  Regs_WrAddr_r1       : std_logic_vector(C_EP_AWIDTH-1   downto 0);
212 
  signal  Regs_WrMask_r1       : std_logic_vector(2-1   downto 0);
213 
  signal  Regs_WrDin_r1        : std_logic_vector(C_DBUS_WIDTH-1   downto 0);
214 
  signal  Regs_WrEn_r2         : std_logic;
215 
  signal  Regs_WrDin_r2        : std_logic_vector(C_DBUS_WIDTH-1   downto 0);
216 
  signal  Regs_Wr_dma_V_hi_r2     : std_logic;
217 
  signal  Regs_Wr_dma_nV_hi_r2    : std_logic;
218 
  signal  Regs_Wr_dma_V_nE_hi_r2  : std_logic;
219 
  signal  Regs_Wr_dma_V_lo_r2     : std_logic;
220 
  signal  Regs_Wr_dma_nV_lo_r2    : std_logic;
221 
  signal  Regs_Wr_dma_V_nE_lo_r2  : std_logic;
222 
  signal  WrDin_r1_not_Zero_Hi    : std_logic_vector(4-1 downto 0);
223 
  signal  WrDin_r2_not_Zero_Hi    : std_logic;
224 
  signal  WrDin_r1_not_Zero_Lo    : std_logic_vector(4-1 downto 0);
225 
  signal  WrDin_r2_not_Zero_Lo    : std_logic;
226 
 
227 
  --      Calculation in advance, just for better timing
228 
  signal  Regs_WrDin_Hi19b_True_hq_r2 : std_logic;
229 
  signal  Regs_WrDin_Lo7b_True_hq_r2  : std_logic;
230 
  signal  Regs_WrDin_Hi19b_True_lq_r2 : std_logic;
231 
  signal  Regs_WrDin_Lo7b_True_lq_r2  : std_logic;
232 
 
233 
  signal  Regs_WrEnA_r1           : std_logic;
234 
  signal  Regs_WrEnB_r1           : std_logic;
235 
  signal  Regs_WrEnA_r2           : std_logic;
236 
  signal  Regs_WrEnB_r2           : std_logic;
237 
 
238 
  --      Register write mux signals
239 
  signal  Reg_WrMuxer_Hi          : std_logic_vector(C_NUM_OF_ADDRESSES-1 downto 0);
240 
  signal  Reg_WrMuxer_Lo          : std_logic_vector(C_NUM_OF_ADDRESSES-1 downto 0);
241 
 
242 
 
243 
  -- Signals for Tx reading
244 
  signal  Regs_RdAddr_i           : std_logic_vector(C_EP_AWIDTH-1   downto 0);
245 
  signal  Regs_RdQout_i           : std_logic_vector(C_DBUS_WIDTH-1   downto 0);
246 
 
247 
  --      Register read mux signals
248 
  signal  Reg_RdMuxer_Hi          : std_logic_vector(C_NUM_OF_ADDRESSES-1 downto 0);
249 
  signal  Reg_RdMuxer_Lo          : std_logic_vector(C_NUM_OF_ADDRESSES-1 downto 0);
250 
 
251 
  -- Optical Link status
252 
  signal  Opto_Link_Status_i      : std_logic_vector(C_DBUS_WIDTH-1 downto 0);
253 
  signal  Opto_Link_Status_o_Hi   : std_logic_vector(C_DBUS_WIDTH-1 downto 0);
254 
  signal  Opto_Link_Status_o_Lo   : std_logic_vector(C_DBUS_WIDTH-1 downto 0);
255 
  -- Event Buffer
256 
  signal  eb_FIFO_Status_r1       : std_logic_vector(C_DBUS_WIDTH-1 downto 0);
257 
  signal  eb_FIFO_Status_o_Hi     : std_logic_vector(C_DBUS_WIDTH-1 downto 0);
258 
  signal  eb_FIFO_Status_o_Lo     : std_logic_vector(C_DBUS_WIDTH-1 downto 0);
259 
  signal  eb_FIFO_Rst_i           : std_logic;
260 
  signal  eb_FIFO_Rst_b1          : std_logic;
261 
  signal  eb_FIFO_Rst_b2          : std_logic;
262 
  signal  eb_FIFO_Rst_b3          : std_logic;
263 
  signal  eb_FIFO_OverWritten     : std_logic;
264 
 
265 
  -- Downstream DMA registers
266 
  signal  DMA_ds_PA_o_Hi          : std_logic_vector(C_DBUS_WIDTH-1 downto 0);
267 
  signal  DMA_ds_HA_o_Hi          : std_logic_vector(C_DBUS_WIDTH-1 downto 0);
268 
  signal  DMA_ds_BDA_o_Hi         : std_logic_vector(C_DBUS_WIDTH-1 downto 0);
269 
  signal  DMA_ds_Length_o_Hi      : std_logic_vector(C_DBUS_WIDTH-1 downto 0);
270 
  signal  DMA_ds_Control_o_Hi     : std_logic_vector(C_DBUS_WIDTH-1 downto 0);
271 
  signal  DMA_ds_Status_o_Hi      : std_logic_vector(C_DBUS_WIDTH-1 downto 0);
272 
  signal  DMA_ds_Transf_Bytes_o_Hi      : std_logic_vector(C_DBUS_WIDTH-1 downto 0);
273 
  signal  DMA_ds_PA_o_Lo          : std_logic_vector(C_DBUS_WIDTH-1 downto 0);
274 
  signal  DMA_ds_HA_o_Lo          : std_logic_vector(C_DBUS_WIDTH-1 downto 0);
275 
  signal  DMA_ds_BDA_o_Lo         : std_logic_vector(C_DBUS_WIDTH-1 downto 0);
276 
  signal  DMA_ds_Length_o_Lo      : std_logic_vector(C_DBUS_WIDTH-1 downto 0);
277 
  signal  DMA_ds_Control_o_Lo     : std_logic_vector(C_DBUS_WIDTH-1 downto 0);
278 
  signal  DMA_ds_Status_o_Lo      : std_logic_vector(C_DBUS_WIDTH-1 downto 0);
279 
  signal  DMA_ds_Transf_Bytes_o_Lo      : std_logic_vector(C_DBUS_WIDTH-1 downto 0);
280 
 
281 
  -- Upstream DMA registers
282 
  signal  DMA_us_PA_o_Hi          : std_logic_vector(C_DBUS_WIDTH-1 downto 0);
283 
  signal  DMA_us_HA_o_Hi          : std_logic_vector(C_DBUS_WIDTH-1 downto 0);
284 
  signal  DMA_us_BDA_o_Hi         : std_logic_vector(C_DBUS_WIDTH-1 downto 0);
285 
  signal  DMA_us_Length_o_Hi      : std_logic_vector(C_DBUS_WIDTH-1 downto 0);
286 
  signal  DMA_us_Control_o_Hi     : std_logic_vector(C_DBUS_WIDTH-1 downto 0);
287 
  signal  DMA_us_Status_o_Hi      : std_logic_vector(C_DBUS_WIDTH-1 downto 0);
288 
  signal  DMA_us_Transf_Bytes_o_Hi      : std_logic_vector(C_DBUS_WIDTH-1 downto 0);
289 
  signal  DMA_us_PA_o_Lo          : std_logic_vector(C_DBUS_WIDTH-1 downto 0);
290 
  signal  DMA_us_HA_o_Lo          : std_logic_vector(C_DBUS_WIDTH-1 downto 0);
291 
  signal  DMA_us_BDA_o_Lo         : std_logic_vector(C_DBUS_WIDTH-1 downto 0);
292 
  signal  DMA_us_Length_o_Lo      : std_logic_vector(C_DBUS_WIDTH-1 downto 0);
293 
  signal  DMA_us_Control_o_Lo     : std_logic_vector(C_DBUS_WIDTH-1 downto 0);
294 
  signal  DMA_us_Status_o_Lo      : std_logic_vector(C_DBUS_WIDTH-1 downto 0);
295 
  signal  DMA_us_Transf_Bytes_o_Lo      : std_logic_vector(C_DBUS_WIDTH-1 downto 0);
296 
 
297 
 
298 
  -- System Interrupt Status/Control
299 
  signal  Sys_IRQ_i               : std_logic_vector(C_DBUS_WIDTH-1 downto 0);
300 
  signal  Sys_Int_Status_i        : std_logic_vector(C_DBUS_WIDTH-1 downto 0);
301 
  signal  Sys_Int_Status_o_Hi     : std_logic_vector(C_DBUS_WIDTH-1 downto 0);
302 
  signal  Sys_Int_Status_o_Lo     : std_logic_vector(C_DBUS_WIDTH-1 downto 0);
303 
 
304 
  signal  Sys_Int_Enable_i        : std_logic_vector(C_DBUS_WIDTH-1 downto 0);
305 
  signal  Sys_Int_Enable_o_Hi     : std_logic_vector(C_DBUS_WIDTH-1 downto 0);
306 
  signal  Sys_Int_Enable_o_Lo     : std_logic_vector(C_DBUS_WIDTH-1 downto 0);
307 
 
308 
 
309 
  -- Data generator control
310 
  signal  DG_Reset_i              : std_logic;
311 
  signal  DG_Mask_i               : std_logic;
312 
  signal  DG_is_Available         : std_logic;
313 
  signal  DG_Rst_Counter          : std_logic_vector(8-1 downto 0);
314 
  signal  DG_Status_i             : std_logic_vector(C_DBUS_WIDTH-1 downto 0);
315 
  signal  DG_Status_o_Hi          : std_logic_vector(C_DBUS_WIDTH-1 downto 0);
316 
  signal  DG_Status_o_Lo          : std_logic_vector(C_DBUS_WIDTH-1 downto 0);
317 
 
318 
  -- General Control and Status
319 
  signal  Sys_Error_i             : std_logic_vector(C_DBUS_WIDTH-1   downto 0);
320 
  signal  Sys_Error_o_Hi          : std_logic_vector(C_DBUS_WIDTH-1   downto 0);
321 
  signal  Sys_Error_o_Lo          : std_logic_vector(C_DBUS_WIDTH-1   downto 0);
322 
 
323 
  signal  General_Control_i       : std_logic_vector(C_DBUS_WIDTH-1   downto 0);
324 
  signal  General_Control_o_Hi    : std_logic_vector(C_DBUS_WIDTH-1   downto 0);
325 
  signal  General_Control_o_Lo    : std_logic_vector(C_DBUS_WIDTH-1   downto 0);
326 
 
327 
  signal  General_Status_i        : std_logic_vector(C_DBUS_WIDTH-1   downto 0);
328 
  signal  General_Status_o_Hi     : std_logic_vector(C_DBUS_WIDTH-1   downto 0);
329 
  signal  General_Status_o_Lo     : std_logic_vector(C_DBUS_WIDTH-1   downto 0);
330 
 
331 
  -- Hardward version
332 
  signal  HW_Version_o_Hi         : std_logic_vector(C_DBUS_WIDTH-1   downto 0);
333 
  signal  HW_Version_o_Lo         : std_logic_vector(C_DBUS_WIDTH-1   downto 0);
334 
 
335 
  -- Signal as the source of interrupts
336 
  signal  IG_Host_Clear_i         : std_logic;
337 
  signal  IG_Reset_i              : std_logic;
338 
 
339 
  -- Interrupt Generator Control
340 
  signal  IG_Control_i            : std_logic_vector(C_DBUS_WIDTH-1   downto 0);
341 
 
342 
  -- Interrupt Generator Latency
343 
  signal  IG_Latency_i            : std_logic_vector(C_DBUS_WIDTH-1   downto 0);
344 
  signal  IG_Latency_o_Hi         : std_logic_vector(C_DBUS_WIDTH-1   downto 0);
345 
  signal  IG_Latency_o_Lo         : std_logic_vector(C_DBUS_WIDTH-1   downto 0);
346 
 
347 
  -- Interrupt Generator Statistic: Assert number
348 
  signal  IG_Num_Assert_i         : std_logic_vector(C_DBUS_WIDTH-1   downto 0);
349 
  signal  IG_Num_Assert_o_Hi      : std_logic_vector(C_DBUS_WIDTH-1   downto 0);
350 
  signal  IG_Num_Assert_o_Lo      : std_logic_vector(C_DBUS_WIDTH-1   downto 0);
351 
 
352 
  -- Interrupt Generator Statistic: Deassert number
353 
  signal  IG_Num_Deassert_i       : std_logic_vector(C_DBUS_WIDTH-1   downto 0);
354 
  signal  IG_Num_Deassert_o_Hi    : std_logic_vector(C_DBUS_WIDTH-1   downto 0);
355 
  signal  IG_Num_Deassert_o_Lo    : std_logic_vector(C_DBUS_WIDTH-1   downto 0);
356 
 
357 
  -- IntClr character is written
358 
  signal  Command_is_Host_iClr_Hi : std_logic;
359 
  signal  Command_is_Host_iClr_Lo : std_logic;
360 
 
361 
  -- Downstream Registers
362 
  signal  DMA_ds_PA_i          : std_logic_vector(C_DBUS_WIDTH-1 downto 0);
363 
  signal  DMA_ds_HA_i          : std_logic_vector(C_DBUS_WIDTH-1 downto 0);
364 
  signal  DMA_ds_BDA_i         : std_logic_vector(C_DBUS_WIDTH-1 downto 0);
365 
  signal  DMA_ds_Length_i      : std_logic_vector(C_DBUS_WIDTH-1   downto 0);
366 
  signal  DMA_ds_Control_i     : std_logic_vector(C_DBUS_WIDTH-1   downto 0);
367 
  signal  DMA_ds_Status_i      : std_logic_vector(C_DBUS_WIDTH-1   downto 0);
368 
  signal  DMA_ds_Transf_Bytes_i      : std_logic_vector(C_DBUS_WIDTH-1   downto 0);
369 
 
370 
  signal  Last_Ctrl_Word_ds    : std_logic_vector(C_DBUS_WIDTH-1   downto 0);
371 
 
372 
  -- Calculation in advance, for better timing
373 
  signal  dsHA_is_64b_i        : std_logic;
374 
  signal  dsBDA_is_64b_i       : std_logic;
375 
 
376 
  -- Calculation in advance, for better timing
377 
  signal  dsLeng_Hi19b_True_i  : std_logic;
378 
  signal  dsLeng_Lo7b_True_i   : std_logic;
379 
 
380 
  -- Downstream Control Signals
381 
  signal  dsDMA_Start_i        : std_logic;
382 
  signal  dsDMA_Stop_i         : std_logic;
383 
  signal  dsDMA_Start2_i       : std_logic;
384 
  signal  dsDMA_Start2_r1      : std_logic;
385 
  signal  dsDMA_Stop2_i        : std_logic;
386 
  signal  dsDMA_Channel_Rst_i  : std_logic;
387 
  signal  ds_Param_Modified    : std_logic;
388 
 
389 
 
390 
  -- Upstream Registers
391 
  signal  DMA_us_PA_i          : std_logic_vector(C_DBUS_WIDTH-1 downto 0);
392 
  signal  DMA_us_HA_i          : std_logic_vector(C_DBUS_WIDTH-1 downto 0);
393 
  signal  DMA_us_BDA_i         : std_logic_vector(C_DBUS_WIDTH-1 downto 0);
394 
  signal  DMA_us_Length_i      : std_logic_vector(C_DBUS_WIDTH-1   downto 0);
395 
  signal  DMA_us_Control_i     : std_logic_vector(C_DBUS_WIDTH-1   downto 0);
396 
  signal  DMA_us_Status_i      : std_logic_vector(C_DBUS_WIDTH-1   downto 0);
397 
  signal  DMA_us_Transf_Bytes_i      : std_logic_vector(C_DBUS_WIDTH-1   downto 0);
398 
 
399 
  signal  Last_Ctrl_Word_us    : std_logic_vector(C_DBUS_WIDTH-1   downto 0);
400 
 
401 
  -- Calculation in advance, for better timing
402 
  signal  usHA_is_64b_i        : std_logic;
403 
  signal  usBDA_is_64b_i       : std_logic;
404 
 
405 
  -- Calculation in advance, for better timing
406 
  signal  usLeng_Hi19b_True_i  : std_logic;
407 
  signal  usLeng_Lo7b_True_i   : std_logic;
408 
 
409 
 
410 
  -- Upstream Control Signals
411 
  signal  usDMA_Start_i        : std_logic;
412 
  signal  usDMA_Stop_i         : std_logic;
413 
  signal  usDMA_Start2_i       : std_logic;
414 
  signal  usDMA_Start2_r1      : std_logic;
415 
  signal  usDMA_Stop2_i        : std_logic;
416 
  signal  usDMA_Channel_Rst_i  : std_logic;
417 
  signal  us_Param_Modified    : std_logic;
418 
 
419 
  -- Reset character is written
420 
  signal  Command_is_Reset_Hi  : std_logic;
421 
  signal  Command_is_Reset_Lo  : std_logic;
422 
 
423 
  -- MRd channel reset
424 
  signal  MRd_Channel_Rst_i    : std_logic;
425 
 
426 
  -- Tx module reset
427 
  signal  Tx_Reset_i           : std_logic;
428 
 
429 
 
430 
  -- ICAP
431 
  signal  icap_CLK             : std_logic;
432 
  signal  icap_I               : std_logic_vector(C_DBUS_WIDTH-1 downto 0);
433 
  signal  icap_CE              : std_logic;
434 
  signal  icap_Write           : std_logic;
435 
  signal  icap_O               : std_logic_vector(C_DBUS_WIDTH-1 downto 0);
436 
  signal  icap_O_o_Hi          : std_logic_vector(C_DBUS_WIDTH-1 downto 0);
437 
  signal  icap_O_o_Lo          : std_logic_vector(C_DBUS_WIDTH-1 downto 0);
438 
  signal  icap_BUSY            : std_logic;
439 
 
440 
  -- DCB protocol interface
441 
  signal  protocol_rst_i       : std_logic;
442 
  signal  protocol_rst_b1      : std_logic;
443 
  signal  protocol_rst_b2      : std_logic;
444 
 
445 
  -- Protocol : CTL
446 
  signal  ctl_rv_i             : std_logic;
447 
  signal  ctl_rd_i             : std_logic_vector(C_DBUS_WIDTH/2-1 downto 0);
448 
 
449 
  signal  class_CTL_Status_i   : std_logic_vector(C_DBUS_WIDTH-1 downto 0);
450 
  signal  class_CTL_Status_o_Hi: std_logic_vector(C_DBUS_WIDTH-1 downto 0);
451 
  signal  class_CTL_Status_o_Lo: std_logic_vector(C_DBUS_WIDTH-1 downto 0);
452 
 
453 
  signal  ctl_td_o_Hi          : std_logic_vector(C_DBUS_WIDTH/2-1 downto 0);
454 
  signal  ctl_td_o_Lo          : std_logic_vector(C_DBUS_WIDTH/2-1 downto 0);
455 
  signal  ctl_td_r             : std_logic_vector(C_DBUS_WIDTH/2-1 downto 0);
456 
 
457 
  signal  ctl_reset_i          : std_logic;
458 
  signal  ctl_ttake_i          : std_logic;
459 
  signal  ctl_tstop_i          : std_logic;
460 
  signal  ctl_t_read_Hi_r1     : std_logic;
461 
  signal  ctl_t_read_Lo_r1     : std_logic;
462 
  signal  CTL_read_counter     : std_logic_vector(6-1 downto 0);
463 
 
464 
  -- Protocol : DLM
465 
  signal  dlm_tv_i             : std_logic;
466 
  signal  dlm_td_i             : std_logic_vector(C_DBUS_WIDTH/2-1 downto 0);
467 
 
468 
  signal  dlm_rd_o_Hi          : std_logic_vector(C_DBUS_WIDTH/2-1 downto 0);
469 
  signal  dlm_rd_o_Lo          : std_logic_vector(C_DBUS_WIDTH/2-1 downto 0);
470 
  signal  dlm_rd_r             : std_logic_vector(C_DBUS_WIDTH/2-1 downto 0);
471 
 
472 
begin
473 
 
474 
   DG_Available_Bit: if IMP_DATA_GENERATOR generate
475 
      DG_is_Available   <= '1';
476 
   end generate;
477 
 
478 
   DG_Unavailable_Bit: if not IMP_DATA_GENERATOR generate
479 
      DG_is_Available   <= '0';
480 
   end generate;
481 
 
482 
   -- protocol interface reset
483 
   protocol_rst         <= protocol_rst_i;
484 
 
485 
   ctl_rv               <= ctl_rv_i;
486 
   ctl_rd               <= ctl_rd_i;
487 
 
488 
   ctl_ttake            <= ctl_ttake_i;
489 
   ctl_tstop            <= ctl_tstop_i;
490 
   ctl_reset            <= ctl_reset_i;
491 
 
492 
   ctl_tstop_i          <= '0';   -- ???
493 
 
494 
   dlm_tv               <= dlm_tv_i;
495 
   dlm_td               <= dlm_td_i;
496 
 
497 
   -- Data generator control
498 
   DG_Reset             <= DG_Reset_i;
499 
   DG_Mask              <= DG_Mask_i;
500 
 
501 
   -- Event buffer reset
502 
   eb_FIFO_Rst          <= eb_FIFO_Rst_i;
503 
 
504 
   -- MRd channel reset
505 
   MRd_Channel_Rst      <= MRd_Channel_Rst_i;
506 
 
507 
   -- Tx module reset
508 
   Tx_Reset             <= Tx_Reset_i;
509 
 
510 
   -- Upstream DMA engine reset
511 
   usDMA_Channel_Rst    <= usDMA_Channel_Rst_i;
512 
 
513 
   -- Downstream DMA engine reset
514 
   dsDMA_Channel_Rst    <= dsDMA_Channel_Rst_i;
515 
 
516 
 
517 
   -- Upstream DMA registers
518 
   DMA_us_PA            <= DMA_us_PA_i;
519 
   DMA_us_HA            <= DMA_us_HA_i;
520 
   DMA_us_BDA           <= DMA_us_BDA_i;
521 
   DMA_us_Length        <= DMA_us_Length_i;
522 
   DMA_us_Control       <= DMA_us_Control_i;
523 
   usDMA_BDA_eq_Null    <= '0';
524 
   DMA_us_Status_i      <= DMA_us_Status;
525 
 
526 
   usHA_is_64b          <= usHA_is_64b_i;
527 
   usBDA_is_64b         <= usBDA_is_64b_i;
528 
 
529 
   usLeng_Hi19b_True    <= usLeng_Hi19b_True_i;
530 
   usLeng_Lo7b_True     <= usLeng_Lo7b_True_i;
531 
 
532 
   usDMA_Start          <= usDMA_Start_i;
533 
   usDMA_Stop           <= usDMA_Stop_i;
534 
   usDMA_Start2         <= usDMA_Start2_r1;
535 
--   usDMA_Start2         <= usDMA_Start2_i;
536 
   usDMA_Stop2          <= usDMA_Stop2_i;
537 
 
538 
   -- Downstream DMA registers
539 
   DMA_ds_PA            <= DMA_ds_PA_i;
540 
   DMA_ds_HA            <= DMA_ds_HA_i;
541 
   DMA_ds_BDA           <= DMA_ds_BDA_i;
542 
   DMA_ds_Length        <= DMA_ds_Length_i;
543 
   DMA_ds_Control       <= DMA_ds_Control_i;
544 
   dsDMA_BDA_eq_Null    <= '0';
545 
   DMA_ds_Status_i      <= DMA_ds_Status;
546 
 
547 
   dsHA_is_64b          <= dsHA_is_64b_i;
548 
   dsBDA_is_64b         <= dsBDA_is_64b_i;
549 
 
550 
   dsLeng_Hi19b_True    <= dsLeng_Hi19b_True_i;
551 
   dsLeng_Lo7b_True     <= dsLeng_Lo7b_True_i;
552 
 
553 
   dsDMA_Start          <= dsDMA_Start_i;
554 
   dsDMA_Stop           <= dsDMA_Stop_i;
555 
   dsDMA_Start2         <= dsDMA_Start2_r1;
556 
--   dsDMA_Start2         <= dsDMA_Start2_i;
557 
   dsDMA_Stop2          <= dsDMA_Stop2_i;
558 
 
559 
 
560 
   -- Register to Interrupt handler module
561 
   Sys_IRQ              <= Sys_IRQ_i;
562 
 
563 
   -- Message routing method
564 
   Msg_Routing          <= General_Control_i(C_GCR_MSG_ROUT_BIT_TOP downto C_GCR_MSG_ROUT_BIT_BOT);
565 
 
566 
   -- us_MWr_TLP_Param
567 
   us_MWr_Param_Vec     <= General_Control_i(13 downto 8);
568 
 
569 
 
570 
   -- -------------   Interrupt generator generation    ----------------------
571 
   Gen_IG:  if IMP_INT_GENERATOR generate
572 
 
573 
   IG_Reset             <= IG_Reset_i;
574 
   IG_Host_Clear        <= IG_Host_Clear_i;  -- and Sys_Int_Enable_i(CINT_BIT_INTGEN_IN_ISR);
575 
   IG_Latency           <= IG_Latency_i;
576 
   IG_Num_Assert_i      <= IG_Num_Assert;
577 
   IG_Num_Deassert_i    <= IG_Num_Deassert;
578 
 
579 
 
580 
-- -----------------------------------------------
581 
-- Synchronous Registered: IG_Control_i
582 
   SysReg_IntGen_Control:
583 
   process ( trn_clk, trn_lnk_up_n)
584 
   begin
585 
      if trn_lnk_up_n = '1' then
586 
         IG_Control_i          <= (OTHERS => '0');
587 
         IG_Reset_i            <= '1';
588 
         IG_Host_Clear_i       <= '0';
589 
 
590 
      elsif trn_clk'event and trn_clk = '1' then
591 
 
592 
        if Regs_WrEn_r2='1'
593 
                    and Reg_WrMuxer_Hi(CINT_ADDR_IG_CONTROL)='1'
594 
                         then
595 
            IG_Control_i(32-1 downto 0)       <=  Regs_WrDin_r2(64-1 downto 32);
596 
            IG_Reset_i         <=  Command_is_Reset_Hi;
597 
            IG_Host_Clear_i    <=  Command_is_Host_iClr_Hi;
598 
        elsif Regs_WrEn_r2='1'
599 
                    and Reg_WrMuxer_Lo(CINT_ADDR_IG_CONTROL)='1'
600 
                         then
601 
            IG_Control_i(32-1 downto 0)       <=  Regs_WrDin_r2(32-1 downto 0);
602 
            IG_Reset_i         <=  Command_is_Reset_Lo;
603 
            IG_Host_Clear_i    <=  Command_is_Host_iClr_Lo;
604 
        else
605 
            IG_Control_i       <=  IG_Control_i;
606 
            IG_Reset_i         <=  '0';
607 
            IG_Host_Clear_i    <=  '0';
608 
        end if;
609 
 
610 
      end if;
611 
   end process;
612 
 
613 
 
614 
-- -----------------------------------------------
615 
-- Synchronous Registered: IG_Latency_i
616 
   SysReg_IntGen_Latency:
617 
   process ( trn_clk, trn_lnk_up_n)
618 
   begin
619 
      if trn_lnk_up_n = '1' then
620 
         IG_Latency_i       <= (OTHERS => '0');
621 
 
622 
      elsif trn_clk'event and trn_clk = '1' then
623 
 
624 
        if IG_Reset_i='1' then
625 
            IG_Latency_i    <=  (OTHERS => '0');
626 
        elsif Regs_WrEn_r2='1'
627 
                    and Reg_WrMuxer_Hi(CINT_ADDR_IG_LATENCY)='1'
628 
                         then
629 
            IG_Latency_i(32-1 downto 0)    <=  Regs_WrDin_r2(64-1 downto 32);
630 
        elsif Regs_WrEn_r2='1'
631 
                    and Reg_WrMuxer_Lo(CINT_ADDR_IG_LATENCY)='1'
632 
                         then
633 
            IG_Latency_i(32-1 downto 0)    <=  Regs_WrDin_r2(32-1 downto 0);
634 
        else
635 
            IG_Latency_i    <=  IG_Latency_i;
636 
        end if;
637 
 
638 
      end if;
639 
   end process;
640 
 
641 
   end generate;
642 
 
643 
   NotGen_IG:  if not IMP_INT_GENERATOR generate
644 
 
645 
   IG_Reset             <= '0';
646 
   IG_Host_Clear        <= '0';
647 
   IG_Latency           <= (OTHERS=>'0');
648 
   IG_Num_Assert_i      <= (OTHERS=>'0');
649 
   IG_Num_Deassert_i    <= (OTHERS=>'0');
650 
 
651 
   IG_Control_i         <= (OTHERS=>'0');
652 
   IG_Reset_i           <= '0';
653 
   IG_Host_Clear_i      <= '0';
654 
   IG_Latency_i         <= (OTHERS=>'0');
655 
 
656 
   end generate;
657 
 
658 
 
659 
 
660 
-- ----------------------------------------------
661 
-- Synchronous Delay : Sys_IRQ_i
662 
--
663 
   Synch_Delay_Sys_IRQ:
664 
   process ( trn_clk, trn_lnk_up_n )
665 
   begin
666 
      if trn_lnk_up_n = '1' then
667 
         Sys_IRQ_i   <=  (OTHERS=>'0');
668 
 
669 
      elsif trn_clk'event and trn_clk = '1' then
670 
         Sys_IRQ_i(C_NUM_OF_INTERRUPTS-1 downto 0)
671 
                     <= Sys_Int_Enable_i(C_NUM_OF_INTERRUPTS-1 downto 0)
672 
                    and Sys_Int_Status_i(C_NUM_OF_INTERRUPTS-1 downto 0);
673 
 
674 
      end if;
675 
   end process;
676 
 
677 
 
678 
-- ----------------------------------------------
679 
-- Registers writing
680 
--
681 
   Regs_WrAddr_i        <= Regs_WrAddrA and Regs_WrAddrB;
682 
   Regs_WrMask_i        <= Regs_WrMaskA or  Regs_WrMaskB;
683 
   Regs_WrDin_i         <= Regs_WrDinA  or  Regs_WrDinB;
684 
 
685 
-- ----------------------------------------------
686 
-- Registers reading
687 
--
688 
   Regs_RdAddr_i        <= Regs_RdAddr;
689 
   Regs_RdQout          <= Regs_RdQout_i;
690 
 
691 
-- ----------------------------------------------
692 
-- Synchronous Delay : Regs_WrEn
693 
--
694 
   Synch_Delay_Regs_WrEn:
695 
   process ( trn_clk )
696 
   begin
697 
      if trn_clk'event and trn_clk = '1' then
698 
         Regs_WrEn_r1   <= Regs_WrEnA or Regs_WrEnB;
699 
         Regs_WrEn_r2   <= Regs_WrEn_r1;
700 
 
701 
         Regs_WrEnA_r1  <= Regs_WrEnA;
702 
         Regs_WrEnA_r2  <= Regs_WrEnA_r1;
703 
 
704 
         Regs_WrEnB_r1  <= Regs_WrEnB;
705 
         Regs_WrEnB_r2  <= Regs_WrEnB_r1;
706 
 
707 
      end if;
708 
   end process;
709 
 
710 
-- ----------------------------------------------
711 
-- Synchronous Delay : Opto_Link_Status
712 
--
713 
   Synch_Delay_Opto_Link_Status:
714 
   process ( trn_clk )
715 
   begin
716 
      if trn_clk'event and trn_clk = '1' then
717 
         Opto_Link_Status_i(C_DBUS_WIDTH-1 downto 2)   <= (OTHERS=>'0');
718 
         Opto_Link_Status_i(2-1 downto 0)   <= protocol_link_act;
719 
      end if;
720 
   end process;
721 
 
722 
-- ----------------------------------------------
723 
-- Synchronous Delay : eb_FIFO_Status
724 
--
725 
   Synch_Delay_eb_FIFO_Status:
726 
   process ( trn_clk )
727 
   begin
728 
      if trn_clk'event and trn_clk = '1' then
729 
         eb_FIFO_Status_r1   <= eb_FIFO_Status;
730 
      end if;
731 
   end process;
732 
 
733 
-- ----------------------------------------------
734 
-- Synchronous Delay : Regs_WrAddr
735 
--
736 
   Synch_Delay_Regs_WrAddr:
737 
   process ( trn_clk )
738 
   begin
739 
      if trn_clk'event and trn_clk = '1' then
740 
         Regs_WrAddr_r1   <= Regs_WrAddr_i;
741 
         Regs_WrMask_r1   <= Regs_WrMask_i;
742 
      end if;
743 
   end process;
744 
 
745 
-- ----------------------------------------------------
746 
-- Synchronous Delay : dsDMA_Start2
747 
--                     usDMA_Start2
748 
--   (Special recipe for 64-bit successive descriptors)
749 
--
750 
   Synch_Delay_DMA_Start2:
751 
   process ( trn_clk )
752 
   begin
753 
      if trn_clk'event and trn_clk = '1' then
754 
         dsDMA_Start2_r1   <= dsDMA_Start2_i and not dsDMA_Cmd_Ack;
755 
         usDMA_Start2_r1   <= usDMA_Start2_i and not usDMA_Cmd_Ack;
756 
      end if;
757 
   end process;
758 
 
759 
 
760 
-- ----------------------------------------------
761 
-- Synchronous Delay : Regs_WrDin_i
762 
--
763 
   Synch_Delay_Regs_WrDin:
764 
   process ( trn_clk )
765 
   begin
766 
      if trn_clk'event and trn_clk = '1' then
767 
         Regs_WrDin_r1   <= Regs_WrDin_i;
768 
         Regs_WrDin_r2   <= Regs_WrDin_r1;
769 
 
770 
         if Regs_WrDin_i(31+32 downto 24+32) = C_ALL_ZEROS(31+32 downto 24+32) then
771 
            WrDin_r1_not_Zero_Hi(3) <= '0';
772 
         else
773 
            WrDin_r1_not_Zero_Hi(3) <= '1';
774 
         end if;
775 
         if Regs_WrDin_i(23+32 downto 16+32) = C_ALL_ZEROS(23+32 downto 16+32) then
776 
            WrDin_r1_not_Zero_Hi(2) <= '0';
777 
         else
778 
            WrDin_r1_not_Zero_Hi(2) <= '1';
779 
         end if;
780 
         if Regs_WrDin_i(15+32 downto 8+32) = C_ALL_ZEROS(15+32 downto 8+32) then
781 
            WrDin_r1_not_Zero_Hi(1) <= '0';
782 
         else
783 
            WrDin_r1_not_Zero_Hi(1) <= '1';
784 
         end if;
785 
         if Regs_WrDin_i(7+32 downto 0+32) = C_ALL_ZEROS(7+32 downto 0+32) then
786 
            WrDin_r1_not_Zero_Hi(0) <= '0';
787 
         else
788 
            WrDin_r1_not_Zero_Hi(0) <= '1';
789 
         end if;
790 
 
791 
         if WrDin_r1_not_Zero_Hi = C_ALL_ZEROS(3 downto 0) then
792 
            WrDin_r2_not_Zero_Hi <= '0';
793 
         else
794 
            WrDin_r2_not_Zero_Hi <= '1';
795 
         end if;
796 
 
797 
 
798 
         if Regs_WrDin_i(31 downto 24) = C_ALL_ZEROS(31 downto 24) then
799 
            WrDin_r1_not_Zero_Lo(3) <= '0';
800 
         else
801 
            WrDin_r1_not_Zero_Lo(3) <= '1';
802 
         end if;
803 
         if Regs_WrDin_i(23 downto 16) = C_ALL_ZEROS(23 downto 16) then
804 
            WrDin_r1_not_Zero_Lo(2) <= '0';
805 
         else
806 
            WrDin_r1_not_Zero_Lo(2) <= '1';
807 
         end if;
808 
         if Regs_WrDin_i(15 downto 8) = C_ALL_ZEROS(15 downto 8) then
809 
            WrDin_r1_not_Zero_Lo(1) <= '0';
810 
         else
811 
            WrDin_r1_not_Zero_Lo(1) <= '1';
812 
         end if;
813 
         if Regs_WrDin_i(7 downto 0) = C_ALL_ZEROS(7 downto 0) then
814 
            WrDin_r1_not_Zero_Lo(0) <= '0';
815 
         else
816 
            WrDin_r1_not_Zero_Lo(0) <= '1';
817 
         end if;
818 
 
819 
         if WrDin_r1_not_Zero_Lo = C_ALL_ZEROS(3 downto 0) then
820 
            WrDin_r2_not_Zero_Lo <= '0';
821 
         else
822 
            WrDin_r2_not_Zero_Lo <= '1';
823 
         end if;
824 
      end if;
825 
   end process;
826 
 
827 
 
828 
-- -----------------------------------------------------------
829 
-- Synchronous Delay : DMA Commands Write Valid and not End
830 
--
831 
   Synch_Delay_dmaCmd_Wr_Valid_and_End:
832 
   process ( trn_clk )
833 
   begin
834 
      if trn_clk'event and trn_clk = '1' then
835 
         Regs_Wr_dma_V_hi_r2      <= Regs_WrEn_r1
836 
                               and Regs_WrDin_r1(CINT_BIT_DMA_CTRL_VALID+32)
837 
                               ;
838 
         Regs_Wr_dma_nV_hi_r2     <= Regs_WrEn_r1
839 
                               and not Regs_WrDin_r1(CINT_BIT_DMA_CTRL_VALID+32)
840 
                               ;
841 
         Regs_Wr_dma_V_nE_hi_r2   <= Regs_WrEn_r1
842 
                               and Regs_WrDin_r1(CINT_BIT_DMA_CTRL_VALID+32)
843 
                               and not Regs_WrDin_r1(CINT_BIT_DMA_CTRL_END+32)
844 
                               ;
845 
 
846 
 
847 
         Regs_Wr_dma_V_lo_r2      <= Regs_WrEn_r1
848 
                               and Regs_WrDin_r1(CINT_BIT_DMA_CTRL_VALID)
849 
                               ;
850 
         Regs_Wr_dma_nV_lo_r2     <= Regs_WrEn_r1
851 
                               and not Regs_WrDin_r1(CINT_BIT_DMA_CTRL_VALID)
852 
                               ;
853 
         Regs_Wr_dma_V_nE_lo_r2   <= Regs_WrEn_r1
854 
                               and Regs_WrDin_r1(CINT_BIT_DMA_CTRL_VALID)
855 
                               and not Regs_WrDin_r1(CINT_BIT_DMA_CTRL_END)
856 
                               ;
857 
      end if;
858 
   end process;
859 
 
860 
 
861 
 
862 
-- ------------------------------------------------
863 
-- Synchronous Delay : Regs_WrDin_Hi19b_True_r2 x2
864 
--                     Regs_WrDin_Lo7b_True_r2 x2
865 
--
866 
   Synch_Delay_Regs_WrDin_Hi19b_and_Lo7b_True:
867 
   process ( trn_clk )
868 
   begin
869 
      if trn_clk'event and trn_clk = '1' then
870 
 
871 
         if Regs_WrDin_r1(C_DBUS_WIDTH-1 downto C_MAXSIZE_FLD_BIT_TOP+1+32)
872 
            = C_ALL_ZEROS(C_DBUS_WIDTH-1 downto C_MAXSIZE_FLD_BIT_TOP+1+32)
873 
            then
874 
            Regs_WrDin_Hi19b_True_hq_r2  <= '0';
875 
         else
876 
            Regs_WrDin_Hi19b_True_hq_r2  <= '1';
877 
         end if;
878 
 
879 
         if Regs_WrDin_r1(C_MAXSIZE_FLD_BIT_BOT-1+32 downto 2+32)
880 
            = C_ALL_ZEROS(C_MAXSIZE_FLD_BIT_BOT-1+32 downto 2+32)
881 
            then                               -- ! Lowest 2 bits ignored !
882 
            Regs_WrDin_Lo7b_True_hq_r2  <= '0';
883 
         else
884 
            Regs_WrDin_Lo7b_True_hq_r2  <= '1';
885 
         end if;
886 
 
887 
         if Regs_WrDin_r1(C_DBUS_WIDTH-1-32 downto C_MAXSIZE_FLD_BIT_TOP+1)
888 
            = C_ALL_ZEROS(C_DBUS_WIDTH-1-32 downto C_MAXSIZE_FLD_BIT_TOP+1)
889 
            then
890 
            Regs_WrDin_Hi19b_True_lq_r2  <= '0';
891 
         else
892 
            Regs_WrDin_Hi19b_True_lq_r2  <= '1';
893 
         end if;
894 
 
895 
         if Regs_WrDin_r1(C_MAXSIZE_FLD_BIT_BOT-1 downto 2)
896 
            = C_ALL_ZEROS(C_MAXSIZE_FLD_BIT_BOT-1 downto 2)
897 
            then                               -- ! Lowest 2 bits ignored !
898 
            Regs_WrDin_Lo7b_True_lq_r2  <= '0';
899 
         else
900 
            Regs_WrDin_Lo7b_True_lq_r2  <= '1';
901 
         end if;
902 
 
903 
      end if;
904 
   end process;
905 
 
906 
 
907 
 
908 
-- ---------------------------------------
909 
--
910 
   Write_DMA_Registers_Mux:
911 
   process ( trn_clk, trn_lnk_up_n)
912 
   begin
913 
      if trn_lnk_up_n = '1' then
914 
         Reg_WrMuxer_Hi <= (Others => '0');
915 
         Reg_WrMuxer_Lo <= (Others => '0');
916 
 
917 
      elsif trn_clk'event and trn_clk = '1' then
918 
 
919 
         if -- Regs_WrAddr_r1(C_DECODE_BIT_TOP downto C_DECODE_BIT_BOT)=C_REGS_BASE_ADDR(C_DECODE_BIT_TOP downto C_DECODE_BIT_BOT)
920 
            -- and
921 
            Regs_WrAddr_r1(C_DECODE_BIT_BOT-1 downto 2)=CONV_STD_LOGIC_VECTOR(0, C_DECODE_BIT_BOT-2)
922 
            -- and Regs_WrAddr_r1(2-1 downto 0)="00"
923 
            then
924 
            Reg_WrMuxer_Hi(0)   <= not Regs_WrMask_r1(1);
925 
         else
926 
            Reg_WrMuxer_Hi(0)   <= '0';
927 
         end if;
928 
 
929 
         FOR k IN 1 TO C_NUM_OF_ADDRESSES-1 LOOP
930 
 
931 
            if -- Regs_WrAddr_r1(C_DECODE_BIT_TOP downto C_DECODE_BIT_BOT)=C_REGS_BASE_ADDR(C_DECODE_BIT_TOP downto C_DECODE_BIT_BOT)
932 
               -- and
933 
               Regs_WrAddr_r1(C_DECODE_BIT_BOT-1 downto 2)=CONV_STD_LOGIC_VECTOR(k, C_DECODE_BIT_BOT-2)
934 
               -- and Regs_WrAddr_r1(2-1 downto 0)="00"
935 
               then
936 
               Reg_WrMuxer_Hi(k)   <= not Regs_WrMask_r1(1);
937 
            else
938 
               Reg_WrMuxer_Hi(k)   <= '0';
939 
            end if;
940 
 
941 
            if -- Regs_WrAddr_r1(C_DECODE_BIT_TOP downto C_DECODE_BIT_BOT)=C_REGS_BASE_ADDR(C_DECODE_BIT_TOP downto C_DECODE_BIT_BOT)
942 
               -- and
943 
               Regs_WrAddr_r1(C_DECODE_BIT_BOT-1 downto 2)=CONV_STD_LOGIC_VECTOR(k-1, C_DECODE_BIT_BOT-2)
944 
               -- and Regs_WrAddr_r1(2-1 downto 0)="00"
945 
               then
946 
               Reg_WrMuxer_Lo(k)   <= not Regs_WrMask_r1(0);
947 
            else
948 
               Reg_WrMuxer_Lo(k)   <= '0';
949 
            end if;
950 
 
951 
         END LOOP;
952 
 
953 
      end if;
954 
   end process;
955 
 
956 
 
957 
 
958 
--  -----------------------------------------------
959 
--  System Interrupt Status Control
960 
--  -----------------------------------------------
961 
 
962 
-- -------------------------------------------------------
963 
-- Synchronous Registered: Sys_Int_Enable_i
964 
   SysReg_Sys_Int_Enable:
965 
   process ( trn_clk, trn_lnk_up_n)
966 
   begin
967 
      if trn_lnk_up_n = '1' then
968 
         Sys_Int_Enable_i     <= (OTHERS => '0');
969 
      elsif trn_clk'event and trn_clk = '1' then
970 
 
971 
        if Regs_WrEn_r2='1'
972 
                    and Reg_WrMuxer_Hi(CINT_ADDR_IRQ_EN)='1'
973 
                         then
974 
            Sys_Int_Enable_i(32-1 downto 0) <=  Regs_WrDin_r2(64-1 downto 32);
975 
        elsif Regs_WrEn_r2='1'
976 
                    and Reg_WrMuxer_Lo(CINT_ADDR_IRQ_EN)='1'
977 
                         then
978 
            Sys_Int_Enable_i(32-1 downto 0) <=  Regs_WrDin_r2(32-1 downto 0);
979 
        else
980 
            Sys_Int_Enable_i <=  Sys_Int_Enable_i;
981 
        end if;
982 
 
983 
 
984 
      end if;
985 
   end process;
986 
 
987 
 
988 
--  -----------------------------------------------
989 
--    System General Control Register
990 
--  -----------------------------------------------
991 
-- -----------------------------------------------
992 
-- Synchronous Registered: General_Control
993 
   SysReg_General_Control:
994 
   process ( trn_clk, trn_lnk_up_n)
995 
   begin
996 
      if trn_lnk_up_n = '1' then
997 
         General_Control_i     <= (OTHERS => '0');
998 
         General_Control_i(C_GCR_MSG_ROUT_BIT_TOP downto C_GCR_MSG_ROUT_BIT_BOT)
999 
                               <= C_TYPE_OF_MSG(C_TLP_TYPE_BIT_BOT+C_GCR_MSG_ROUT_BIT_TOP-C_GCR_MSG_ROUT_BIT_BOT
1000 
                                  downto C_TLP_TYPE_BIT_BOT);
1001 
 
1002 
      elsif trn_clk'event and trn_clk = '1' then
1003 
 
1004 
        if Regs_WrEn_r2='1'
1005 
           and Reg_WrMuxer_Hi(CINT_ADDR_CONTROL)='1'
1006 
           then
1007 
            General_Control_i(32-1 downto 0)  <=  Regs_WrDin_r2(64-1 downto 32);
1008 
        elsif Regs_WrEn_r2='1'
1009 
           and Reg_WrMuxer_Lo(CINT_ADDR_CONTROL)='1'
1010 
           then
1011 
            General_Control_i(32-1 downto 0)  <=  Regs_WrDin_r2(32-1 downto 0);
1012 
        else
1013 
            General_Control_i  <=  General_Control_i;
1014 
        end if;
1015 
 
1016 
      end if;
1017 
   end process;
1018 
 
1019 
-- -----------------------------------------------
1020 
-- Synchronous Registered: DG_Reset_i
1021 
   SysReg_DGen_Reset:
1022 
   process ( trn_clk, trn_lnk_up_n)
1023 
   begin
1024 
      if trn_lnk_up_n = '1' then
1025 
         DG_Reset_i            <= '1';
1026 
         DG_Rst_Counter        <= (OTHERS=>'0');
1027 
 
1028 
      elsif trn_clk'event and trn_clk = '1' then
1029 
 
1030 
        if DG_Rst_Counter=X"FF" then
1031 
           DG_Rst_Counter  <= DG_Rst_Counter;
1032 
        else
1033 
           DG_Rst_Counter  <= DG_Rst_Counter + '1';
1034 
        end if;
1035 
 
1036 
        if DG_Rst_Counter(7)='0' then
1037 
            DG_Reset_i         <=  '1';
1038 
        elsif Regs_WrEn_r2='1'
1039 
                    and Reg_WrMuxer_Hi(CINT_ADDR_DG_CTRL)='1'
1040 
                         then
1041 
            DG_Reset_i         <=  Command_is_Reset_Hi;
1042 
        elsif Regs_WrEn_r2='1'
1043 
                    and Reg_WrMuxer_Lo(CINT_ADDR_DG_CTRL)='1'
1044 
                         then
1045 
            DG_Reset_i         <=  Command_is_Reset_Lo;
1046 
        else
1047 
            DG_Reset_i         <=  '0';
1048 
        end if;
1049 
 
1050 
      end if;
1051 
   end process;
1052 
 
1053 
-- -----------------------------------------------
1054 
-- Synchronous Registered: DG_Mask_i
1055 
   SysReg_DGen_Mask:
1056 
   process ( trn_clk, trn_lnk_up_n)
1057 
   begin
1058 
      if trn_lnk_up_n = '1' then
1059 
         DG_Mask_i     <= '0';
1060 
      elsif trn_clk'event and trn_clk = '1' then
1061 
 
1062 
        if Regs_WrEn_r2='1'
1063 
           and Reg_WrMuxer_Hi(CINT_ADDR_DG_CTRL)='1'
1064 
           then
1065 
           DG_Mask_i  <=  Regs_WrDin_r2(32+CINT_BIT_DG_MASK);
1066 
        elsif Regs_WrEn_r2='1'
1067 
           and Reg_WrMuxer_Lo(CINT_ADDR_DG_CTRL)='1'
1068 
           then
1069 
           DG_Mask_i  <=  Regs_WrDin_r2(CINT_BIT_DG_MASK);
1070 
        else
1071 
           DG_Mask_i  <=  DG_Mask_i;
1072 
        end if;
1073 
 
1074 
      end if;
1075 
   end process;
1076 
 
1077 
--------------------------------------------------------------------------
1078 
--  Data generator status
1079 
--
1080 
   Synch_DG_Status_i:
1081 
   process ( trn_clk, DG_Reset_i )
1082 
   begin
1083 
     if DG_Reset_i = '1' then
1084 
        DG_Status_i    <= (OTHERS=>'0');
1085 
     elsif trn_clk'event and trn_clk = '1' then
1086 
        DG_Status_i(CINT_BIT_DG_MASK)    <= DG_Mask_i;
1087 
        DG_Status_i(CINT_BIT_DG_BUSY)    <= DG_is_Running;
1088 
     end if;
1089 
   end process;
1090 
 
1091 
-- -----------------------------------------------
1092 
-- Synchronous Registered: IG_Control_i
1093 
   SysReg_IntGen_Control:
1094 
   process ( trn_clk, trn_lnk_up_n)
1095 
   begin
1096 
      if trn_lnk_up_n = '1' then
1097 
         IG_Control_i          <= (OTHERS => '0');
1098 
         IG_Reset_i            <= '1';
1099 
         IG_Host_Clear_i       <= '0';
1100 
 
1101 
      elsif trn_clk'event and trn_clk = '1' then
1102 
 
1103 
        if Regs_WrEn_r2='1'
1104 
                    and Reg_WrMuxer_Hi(CINT_ADDR_IG_CONTROL)='1'
1105 
                         then
1106 
            IG_Control_i(32-1 downto 0)       <=  Regs_WrDin_r2(64-1 downto 32);
1107 
            IG_Reset_i         <=  Command_is_Reset_Hi;
1108 
            IG_Host_Clear_i    <=  Command_is_Host_iClr_Hi;
1109 
        elsif Regs_WrEn_r2='1'
1110 
                    and Reg_WrMuxer_Lo(CINT_ADDR_IG_CONTROL)='1'
1111 
                         then
1112 
            IG_Control_i(32-1 downto 0)       <=  Regs_WrDin_r2(32-1 downto 0);
1113 
            IG_Reset_i         <=  Command_is_Reset_Lo;
1114 
            IG_Host_Clear_i    <=  Command_is_Host_iClr_Lo;
1115 
        else
1116 
            IG_Control_i       <=  IG_Control_i;
1117 
            IG_Reset_i         <=  '0';
1118 
            IG_Host_Clear_i    <=  '0';
1119 
        end if;
1120 
 
1121 
      end if;
1122 
   end process;
1123 
 
1124 
 
1125 
-- -----------------------------------------------
1126 
-- Synchronous Registered: IG_Latency_i
1127 
   SysReg_IntGen_Latency:
1128 
   process ( trn_clk, trn_lnk_up_n)
1129 
   begin
1130 
      if trn_lnk_up_n = '1' then
1131 
         IG_Latency_i       <= (OTHERS => '0');
1132 
 
1133 
      elsif trn_clk'event and trn_clk = '1' then
1134 
 
1135 
        if IG_Reset_i='1' then
1136 
            IG_Latency_i    <=  (OTHERS => '0');
1137 
        elsif Regs_WrEn_r2='1'
1138 
                    and Reg_WrMuxer_Hi(CINT_ADDR_IG_LATENCY)='1'
1139 
                         then
1140 
            IG_Latency_i(32-1 downto 0)    <=  Regs_WrDin_r2(64-1 downto 32);
1141 
        elsif Regs_WrEn_r2='1'
1142 
                    and Reg_WrMuxer_Lo(CINT_ADDR_IG_LATENCY)='1'
1143 
                         then
1144 
            IG_Latency_i(32-1 downto 0)    <=  Regs_WrDin_r2(32-1 downto 0);
1145 
        else
1146 
            IG_Latency_i    <=  IG_Latency_i;
1147 
        end if;
1148 
 
1149 
      end if;
1150 
   end process;
1151 
 
1152 
 
1153 
 
1154 
 
1155 
--  ------------------------------------------------------
1156 
--      Protocol CTL interface
1157 
--  ------------------------------------------------------
1158 
 
1159 
-- -------------------------------------------------------
1160 
-- Synchronous Registered: ctl_rd
1161 
   Syn_CTL_rd:
1162 
   process ( trn_clk, trn_lnk_up_n)
1163 
   begin
1164 
      if trn_lnk_up_n = '1' then
1165 
         ctl_rd_i     <= (OTHERS => '0');
1166 
         ctl_rv_i     <= '0';
1167 
      elsif trn_clk'event and trn_clk = '1' then
1168 
 
1169 
         if Regs_WrEn_r2='1' and Reg_WrMuxer_Hi(CINT_ADDR_CTL_CLASS)='1' then
1170 
            ctl_rd_i     <= Regs_WrDin_r2(C_DBUS_WIDTH-1 downto 32);
1171 
            ctl_rv_i     <= '1';
1172 
         elsif Regs_WrEn_r2='1' and Reg_WrMuxer_Lo(CINT_ADDR_CTL_CLASS)='1' then
1173 
            ctl_rd_i     <= Regs_WrDin_r2(32-1 downto 0);
1174 
            ctl_rv_i     <= '1';
1175 
         else
1176 
            ctl_rd_i     <= ctl_rd_i;
1177 
            ctl_rv_i     <= '0';
1178 
         end if;
1179 
 
1180 
      end if;
1181 
   end process;
1182 
 
1183 
 
1184 
-- -----------------------------------------------
1185 
-- Synchronous Registered: ctl_reset
1186 
   SysReg_ctl_reset:
1187 
   process ( trn_clk, trn_lnk_up_n)
1188 
   begin
1189 
      if trn_lnk_up_n = '1' then
1190 
         ctl_reset_i            <= '1';
1191 
 
1192 
      elsif trn_clk'event and trn_clk = '1' then
1193 
 
1194 
        if Regs_WrEn_r2='1'
1195 
                    and Reg_WrMuxer_Hi(CINT_ADDR_TC_STATUS)='1'
1196 
                         then
1197 
            ctl_reset_i         <=  Command_is_Reset_Hi;
1198 
        elsif Regs_WrEn_r2='1'
1199 
                    and Reg_WrMuxer_Lo(CINT_ADDR_TC_STATUS)='1'
1200 
                         then
1201 
            ctl_reset_i         <=  Command_is_Reset_Lo;
1202 
        else
1203 
            ctl_reset_i         <=  '0';
1204 
        end if;
1205 
 
1206 
      end if;
1207 
   end process;
1208 
 
1209 
 
1210 
 
1211 
-- -------------------------------------------------------
1212 
-- Synchronous Registered: ctl_td
1213 
--    ++++++++++++ INT triggering  ++++++++++++++++++
1214 
   Syn_CTL_td:
1215 
   process ( trn_clk, trn_lnk_up_n)
1216 
   begin
1217 
      if trn_lnk_up_n = '1' then
1218 
         ctl_td_r     <= (OTHERS => '0');
1219 
      elsif trn_clk'event and trn_clk = '1' then
1220 
 
1221 
         if ctl_tv='1' then
1222 
            ctl_td_r     <= ctl_td;
1223 
         else
1224 
            ctl_td_r     <= ctl_td_r;
1225 
         end if;
1226 
 
1227 
      end if;
1228 
   end process;
1229 
 
1230 
 
1231 
 
1232 
--  ------------------------------------------------------
1233 
--      Protocol DLM interface
1234 
--  ------------------------------------------------------
1235 
 
1236 
-- -------------------------------------------------------
1237 
-- Synchronous Registered: dlm_td
1238 
   Syn_DLM_td:
1239 
   process ( trn_clk, trn_lnk_up_n)
1240 
   begin
1241 
      if trn_lnk_up_n = '1' then
1242 
         dlm_td_i     <= (OTHERS => '0');
1243 
         dlm_tv_i     <= '0';
1244 
      elsif trn_clk'event and trn_clk = '1' then
1245 
 
1246 
         if Regs_WrEn_r2='1' and Reg_WrMuxer_Hi(CINT_ADDR_DLM_CLASS)='1' then
1247 
            dlm_td_i     <= Regs_WrDin_r2(C_DBUS_WIDTH-1 downto 32);
1248 
            dlm_tv_i     <= '1';
1249 
         elsif Regs_WrEn_r2='1' and Reg_WrMuxer_Lo(CINT_ADDR_DLM_CLASS)='1' then
1250 
            dlm_td_i     <= Regs_WrDin_r2(32-1 downto 0);
1251 
            dlm_tv_i     <= '1';
1252 
         else
1253 
            dlm_td_i     <= dlm_td_i;
1254 
            dlm_tv_i     <= '0';
1255 
         end if;
1256 
 
1257 
      end if;
1258 
   end process;
1259 
 
1260 
 
1261 
-- -------------------------------------------------------
1262 
-- Synchronous Registered: dlm_rd
1263 
--    ++++++++++++ INT triggering  ++++++++++++++++++
1264 
   Syn_DLM_rd:
1265 
   process ( trn_clk, trn_lnk_up_n)
1266 
   begin
1267 
      if trn_lnk_up_n = '1' then
1268 
         dlm_rd_r     <= (OTHERS => '0');
1269 
      elsif trn_clk'event and trn_clk = '1' then
1270 
 
1271 
         if dlm_rv='1' then
1272 
            dlm_rd_r     <= dlm_rd;
1273 
         else
1274 
            dlm_rd_r     <= dlm_rd_r;
1275 
         end if;
1276 
 
1277 
      end if;
1278 
   end process;
1279 
 
1280 
 
1281 
--  ------------------------------------------------------
1282 
--  DMA Upstream Registers
1283 
--  ------------------------------------------------------
1284 
 
1285 
-- -------------------------------------------------------
1286 
-- Synchronous Registered: DMA_us_PA_i
1287 
   RxTrn_DMA_us_PA:
1288 
   process ( trn_clk, trn_lnk_up_n)
1289 
   begin
1290 
      if trn_lnk_up_n = '1' then
1291 
         DMA_us_PA_i  <= (OTHERS => '0');
1292 
      elsif trn_clk'event and trn_clk = '1' then
1293 
 
1294 
        if usDMA_Channel_Rst_i = '1' then
1295 
            DMA_us_PA_i <= (OTHERS => '0');
1296 
        else
1297 
 
1298 
          if Regs_WrEn_r2='1' and Reg_WrMuxer_Hi(CINT_ADDR_DMA_US_PAH)='1' then
1299 
            DMA_us_PA_i(C_DBUS_WIDTH-1 downto 32)  <= Regs_WrDin_r2(64-1 downto 32);
1300 
          elsif Regs_WrEn_r2='1' and Reg_WrMuxer_Lo(CINT_ADDR_DMA_US_PAH)='1' then
1301 
            DMA_us_PA_i(C_DBUS_WIDTH-1 downto 32)  <= Regs_WrDin_r2(32-1 downto 0);
1302 
          else
1303 
            DMA_us_PA_i(C_DBUS_WIDTH-1 downto 32)  <= DMA_us_PA_i(C_DBUS_WIDTH-1 downto 32);
1304 
          end if;
1305 
 
1306 
          if Regs_WrEn_r2='1' and Reg_WrMuxer_Hi(CINT_ADDR_DMA_US_PAL)='1' then
1307 
            DMA_us_PA_i(32-1 downto 0)  <= Regs_WrDin_r2(64-1 downto 32);
1308 
          elsif Regs_WrEn_r2='1' and Reg_WrMuxer_Lo(CINT_ADDR_DMA_US_PAL)='1' then
1309 
            DMA_us_PA_i(32-1 downto 0)  <= Regs_WrDin_r2(32-1 downto 0);
1310 
          else
1311 
            DMA_us_PA_i(32-1 downto 0)  <= DMA_us_PA_i(32-1 downto 0);
1312 
          end if;
1313 
 
1314 
        end if;
1315 
 
1316 
      end if;
1317 
   end process;
1318 
 
1319 
 
1320 
-- -------------------------------------------------------
1321 
-- Synchronous Registered: DMA_us_HA_i
1322 
   RxTrn_DMA_us_HA:
1323 
   process ( trn_clk, trn_lnk_up_n)
1324 
   begin
1325 
      if trn_lnk_up_n = '1' then
1326 
         DMA_us_HA_i     <= (OTHERS => '1');
1327 
         usHA_is_64b_i   <= '0';
1328 
 
1329 
      elsif trn_clk'event and trn_clk = '1' then
1330 
 
1331 
        if usDMA_Channel_Rst_i = '1' then
1332 
            DMA_us_HA_i <= (OTHERS => '1');
1333 
            usHA_is_64b_i <= '0';
1334 
        else
1335 
 
1336 
          if Regs_WrEn_r2='1' and Reg_WrMuxer_Hi(CINT_ADDR_DMA_US_HAH)='1' then
1337 
            DMA_us_HA_i(C_DBUS_WIDTH-1 downto 32)  <= Regs_WrDin_r2(64-1 downto 32);
1338 
            usHA_is_64b_i   <=  WrDin_r2_not_Zero_Hi;
1339 
          elsif Regs_WrEn_r2='1' and Reg_WrMuxer_Lo(CINT_ADDR_DMA_US_HAH)='1' then
1340 
            DMA_us_HA_i(C_DBUS_WIDTH-1 downto 32)  <= Regs_WrDin_r2(32-1 downto 0);
1341 
            usHA_is_64b_i   <=  WrDin_r2_not_Zero_Lo;
1342 
          else
1343 
            DMA_us_HA_i(C_DBUS_WIDTH-1 downto 32)  <= DMA_us_HA_i(C_DBUS_WIDTH-1 downto 32);
1344 
            usHA_is_64b_i   <=  usHA_is_64b_i;
1345 
          end if;
1346 
 
1347 
          if Regs_WrEn_r2='1' and Reg_WrMuxer_Hi(CINT_ADDR_DMA_US_HAL)='1' then
1348 
            DMA_us_HA_i(32-1 downto 0)  <= Regs_WrDin_r2(64-1 downto 32);
1349 
          elsif Regs_WrEn_r2='1' and Reg_WrMuxer_Lo(CINT_ADDR_DMA_US_HAL)='1' then
1350 
            DMA_us_HA_i(32-1 downto 0)  <= Regs_WrDin_r2(32-1 downto 0);
1351 
          else
1352 
            DMA_us_HA_i(32-1 downto 0)  <= DMA_us_HA_i(32-1 downto 0);
1353 
          end if;
1354 
 
1355 
        end if;
1356 
 
1357 
      end if;
1358 
   end process;
1359 
 
1360 
 
1361 
-- -------------------------------------------------------
1362 
-- Synchronous output: DMA_us_BDA_i
1363 
   Syn_Output_DMA_us_BDA:
1364 
   process ( trn_clk, trn_lnk_up_n)
1365 
   begin
1366 
      if trn_lnk_up_n = '1' then
1367 
         DMA_us_BDA_i    <= (OTHERS =>'0');
1368 
         usBDA_is_64b_i  <= '0';
1369 
      elsif trn_clk'event and trn_clk = '1' then
1370 
 
1371 
        if usDMA_Channel_Rst_i = '1' then
1372 
           DMA_us_BDA_i <= (OTHERS => '0');
1373 
           usBDA_is_64b_i <= '0';
1374 
        else
1375 
 
1376 
          if Regs_WrEn_r2='1' and Reg_WrMuxer_Hi(CINT_ADDR_DMA_US_BDAH)='1' then
1377 
            DMA_us_BDA_i(C_DBUS_WIDTH-1 downto 32)  <= Regs_WrDin_r2(C_DBUS_WIDTH-1 downto 32);
1378 
            usBDA_is_64b_i   <=  WrDin_r2_not_Zero_Hi;
1379 
          elsif Regs_WrEn_r2='1' and Reg_WrMuxer_Lo(CINT_ADDR_DMA_US_BDAH)='1' then
1380 
            DMA_us_BDA_i(C_DBUS_WIDTH-1 downto 32)  <= Regs_WrDin_r2(32-1 downto 0);
1381 
            usBDA_is_64b_i   <=  WrDin_r2_not_Zero_Lo;
1382 
          else
1383 
            DMA_us_BDA_i(C_DBUS_WIDTH-1 downto 32)  <= DMA_us_BDA_i(C_DBUS_WIDTH-1 downto 32);
1384 
            usBDA_is_64b_i   <=  usBDA_is_64b_i;
1385 
          end if;
1386 
 
1387 
          if Regs_WrEn_r2='1' and Reg_WrMuxer_Hi(CINT_ADDR_DMA_US_BDAL)='1' then
1388 
            DMA_us_BDA_i(32-1 downto 0)  <= Regs_WrDin_r2(C_DBUS_WIDTH-1 downto 32);
1389 
          elsif Regs_WrEn_r2='1' and Reg_WrMuxer_Lo(CINT_ADDR_DMA_US_BDAL)='1' then
1390 
            DMA_us_BDA_i(32-1 downto 0)  <= Regs_WrDin_r2(32-1 downto 0);
1391 
          else
1392 
            DMA_us_BDA_i(32-1 downto 0)  <= DMA_us_BDA_i(32-1 downto 0);
1393 
          end if;
1394 
 
1395 
        end if;
1396 
 
1397 
      end if;
1398 
   end process;
1399 
 
1400 
 
1401 
 
1402 
-- -------------------------------------------------------
1403 
-- Synchronous Registered: DMA_us_Length_i
1404 
   RxTrn_DMA_us_Length:
1405 
   process ( trn_clk, trn_lnk_up_n)
1406 
   begin
1407 
      if trn_lnk_up_n = '1' then
1408 
         DMA_us_Length_i     <= (OTHERS => '0');
1409 
         usLeng_Hi19b_True_i <= '0';
1410 
         usLeng_Lo7b_True_i  <= '0';
1411 
      elsif trn_clk'event and trn_clk = '1' then
1412 
 
1413 
         if usDMA_Channel_Rst_i = '1' then
1414 
            DMA_us_Length_i     <= (OTHERS => '0');
1415 
            usLeng_Hi19b_True_i <= '0';
1416 
            usLeng_Lo7b_True_i  <= '0';
1417 
 
1418 
         elsif Regs_WrEn_r2='1' and  Reg_WrMuxer_Hi(CINT_ADDR_DMA_US_LENG)='1' then
1419 
            DMA_us_Length_i(32-1 downto 0)     <= Regs_WrDin_r2(64-1 downto 32);
1420 
            usLeng_Hi19b_True_i <= Regs_WrDin_Hi19b_True_hq_r2;
1421 
            usLeng_Lo7b_True_i  <= Regs_WrDin_Lo7b_True_hq_r2;
1422 
         elsif Regs_WrEn_r2='1' and  Reg_WrMuxer_Lo(CINT_ADDR_DMA_US_LENG)='1' then
1423 
            DMA_us_Length_i(32-1 downto 0)     <= Regs_WrDin_r2(32-1 downto 0);
1424 
            usLeng_Hi19b_True_i <= Regs_WrDin_Hi19b_True_lq_r2;
1425 
            usLeng_Lo7b_True_i  <= Regs_WrDin_Lo7b_True_lq_r2;
1426 
         else
1427 
            DMA_us_Length_i     <= DMA_us_Length_i;
1428 
            usLeng_Hi19b_True_i <= usLeng_Hi19b_True_i;
1429 
            usLeng_Lo7b_True_i  <= usLeng_Lo7b_True_i;
1430 
 
1431 
         end if;
1432 
 
1433 
      end if;
1434 
   end process;
1435 
 
1436 
 
1437 
 
1438 
-- -------------------------------------------------------
1439 
-- Synchronous us_Param_Modified
1440 
   SynReg_us_Param_Modified:
1441 
   process ( trn_clk, trn_lnk_up_n)
1442 
   begin
1443 
      if trn_lnk_up_n = '1' then
1444 
         us_Param_Modified     <= '0';
1445 
 
1446 
      elsif trn_clk'event and trn_clk = '1' then
1447 
 
1448 
        if usDMA_Channel_Rst_i = '1'
1449 
           or usDMA_Start_i = '1'
1450 
           or usDMA_Start2_i = '1'
1451 
           then
1452 
             us_Param_Modified     <= '0';
1453 
        elsif Regs_WrEn_r2='1' and
1454 
                (
1455 
                    Reg_WrMuxer_Hi(CINT_ADDR_DMA_US_PAL) ='1'
1456 
                 or Reg_WrMuxer_Lo(CINT_ADDR_DMA_US_PAL) ='1'
1457 
                 or Reg_WrMuxer_Hi(CINT_ADDR_DMA_US_HAH) ='1'
1458 
                 or Reg_WrMuxer_Lo(CINT_ADDR_DMA_US_HAH) ='1'
1459 
                 or Reg_WrMuxer_Hi(CINT_ADDR_DMA_US_HAL) ='1'
1460 
                 or Reg_WrMuxer_Lo(CINT_ADDR_DMA_US_HAL) ='1'
1461 
                 or Reg_WrMuxer_Hi(CINT_ADDR_DMA_US_BDAH)='1'
1462 
                 or Reg_WrMuxer_Lo(CINT_ADDR_DMA_US_BDAH)='1'
1463 
                 or Reg_WrMuxer_Hi(CINT_ADDR_DMA_US_BDAL)='1'
1464 
                 or Reg_WrMuxer_Lo(CINT_ADDR_DMA_US_BDAL)='1'
1465 
                 or Reg_WrMuxer_Hi(CINT_ADDR_DMA_US_LENG)='1'
1466 
                 or Reg_WrMuxer_Lo(CINT_ADDR_DMA_US_LENG)='1'
1467 
                )
1468 
           then
1469 
             us_Param_Modified     <= '1';
1470 
        else
1471 
             us_Param_Modified     <= us_Param_Modified;
1472 
 
1473 
        end if;
1474 
 
1475 
      end if;
1476 
   end process;
1477 
 
1478 
 
1479 
 
1480 
-- -------------------------------------------------------
1481 
-- Synchronous output: DMA_us_Control_i
1482 
   Syn_Output_DMA_us_Control:
1483 
   process ( trn_clk, trn_lnk_up_n)
1484 
   begin
1485 
      if trn_lnk_up_n = '1' then
1486 
         DMA_us_Control_i <= (OTHERS =>'0');
1487 
      elsif trn_clk'event and trn_clk = '1' then
1488 
 
1489 
         if     Regs_Wr_dma_V_nE_Hi_r2='1'
1490 
            and Reg_WrMuxer_Hi(CINT_ADDR_DMA_US_CTRL)='1'
1491 
--            and Regs_WrDin_r2(CINT_BIT_DMA_CTRL_VALID)='1'
1492 
--            and Regs_WrDin_r2(CINT_BIT_DMA_CTRL_END)='0'
1493 
            and us_Param_Modified='1'
1494 
            and usDMA_Stop_i='0'
1495 
            then
1496 
               DMA_us_Control_i(32-1 downto 0) <= Regs_WrDin_r2(C_DBUS_WIDTH-1 downto 8+32)& X"00";
1497 
         elsif Regs_Wr_dma_V_nE_Lo_r2='1'
1498 
            and Reg_WrMuxer_Lo(CINT_ADDR_DMA_US_CTRL)='1'
1499 
--            and Regs_WrDin_r2(CINT_BIT_DMA_CTRL_VALID)='1'
1500 
--            and Regs_WrDin_r2(CINT_BIT_DMA_CTRL_END)='0'
1501 
            and us_Param_Modified='1'
1502 
            and usDMA_Stop_i='0'
1503 
            then
1504 
               DMA_us_Control_i(32-1 downto 0) <= Regs_WrDin_r2(32-1 downto 8)& X"00";
1505 
         elsif  Regs_Wr_dma_nV_Hi_r2='1'
1506 
            and Reg_WrMuxer_Hi(CINT_ADDR_DMA_US_CTRL)='1'
1507 
--            and Regs_WrDin_r2(CINT_BIT_DMA_CTRL_VALID)='0'
1508 
            then
1509 
               DMA_us_Control_i(32-1 downto 0) <= Last_Ctrl_Word_us(32-1 downto 0);
1510 
         elsif  Regs_Wr_dma_nV_Lo_r2='1'
1511 
            and Reg_WrMuxer_Lo(CINT_ADDR_DMA_US_CTRL)='1'
1512 
--            and Regs_WrDin_r2(CINT_BIT_DMA_CTRL_VALID)='0'
1513 
            then
1514 
               DMA_us_Control_i(32-1 downto 0) <= Last_Ctrl_Word_us(32-1 downto 0);
1515 
         else
1516 
            DMA_us_Control_i  <= DMA_us_Control_i;
1517 
         end if;
1518 
 
1519 
      end if;
1520 
   end process;
1521 
 
1522 
 
1523 
-- -------------------------------------------------------
1524 
-- Synchronous Register: Last_Ctrl_Word_us
1525 
   Hold_Last_Ctrl_Word_us:
1526 
   process ( trn_clk, trn_lnk_up_n)
1527 
   begin
1528 
      if trn_lnk_up_n = '1' then
1529 
         Last_Ctrl_Word_us  <= C_DEF_DMA_CTRL_WORD;
1530 
      elsif trn_clk'event and trn_clk = '1' then
1531 
 
1532 
        if usDMA_Channel_Rst_i = '1' then
1533 
            Last_Ctrl_Word_us <= C_DEF_DMA_CTRL_WORD;
1534 
        elsif Regs_Wr_dma_V_nE_Hi_r2='1'
1535 
          and Reg_WrMuxer_Hi(CINT_ADDR_DMA_US_CTRL)='1'
1536 
--          and Regs_WrDin_r2(CINT_BIT_DMA_CTRL_VALID)='1'
1537 
--          and Regs_WrDin_r2(CINT_BIT_DMA_CTRL_END)='0'
1538 
          and us_Param_Modified='1'
1539 
          and usDMA_Stop_i='0'
1540 
          then
1541 
            Last_Ctrl_Word_us(32-1 downto 0) <= Regs_WrDin_r2(C_DBUS_WIDTH-1 downto 8+32) & X"00";
1542 
        elsif Regs_Wr_dma_V_nE_Lo_r2='1'
1543 
          and Reg_WrMuxer_Lo(CINT_ADDR_DMA_US_CTRL)='1'
1544 
--          and Regs_WrDin_r2(CINT_BIT_DMA_CTRL_VALID)='1'
1545 
--          and Regs_WrDin_r2(CINT_BIT_DMA_CTRL_END)='0'
1546 
          and us_Param_Modified='1'
1547 
          and usDMA_Stop_i='0'
1548 
          then
1549 
            Last_Ctrl_Word_us(32-1 downto 0) <= Regs_WrDin_r2(32-1 downto 8) & X"00";
1550 
        elsif Regs_Wr_dma_V_nE_Hi_r2='1'
1551 
          and Reg_WrMuxer_Hi(CINT_ADDR_DMA_US_CTRL)='1'
1552 
--          and Regs_WrDin_r2(CINT_BIT_DMA_CTRL_VALID)='1'
1553 
--          and Regs_WrDin_r2(CINT_BIT_DMA_CTRL_END)='0'
1554 
          and us_Param_Modified='1'
1555 
          and usDMA_Stop_i='0'
1556 
          then
1557 
            Last_Ctrl_Word_us(32-1 downto 0) <= Regs_WrDin_r2(C_DBUS_WIDTH-1 downto 8+32) & X"00";
1558 
        elsif Regs_Wr_dma_V_nE_Lo_r2='1'
1559 
          and Reg_WrMuxer_Lo(CINT_ADDR_DMA_US_CTRL)='1'
1560 
--          and Regs_WrDin_r2(CINT_BIT_DMA_CTRL_VALID)='1'
1561 
--          and Regs_WrDin_r2(CINT_BIT_DMA_CTRL_END)='0'
1562 
          and us_Param_Modified='1'
1563 
          and usDMA_Stop_i='0'
1564 
          then
1565 
            Last_Ctrl_Word_us(32-1 downto 0) <= Regs_WrDin_r2(32-1 downto 8) & X"00";
1566 
        else
1567 
            Last_Ctrl_Word_us <= Last_Ctrl_Word_us;
1568 
        end if;
1569 
 
1570 
      end if;
1571 
   end process;
1572 
 
1573 
 
1574 
-- -------------------------------------------------------
1575 
-- Synchronous output: DMA_us_Start_Stop
1576 
   Syn_Output_DMA_us_Start_Stop:
1577 
   process ( trn_clk, trn_lnk_up_n)
1578 
   begin
1579 
      if trn_lnk_up_n = '1' then
1580 
         usDMA_Start_i  <= '0';
1581 
         usDMA_Stop_i   <= '0';
1582 
      elsif trn_clk'event and trn_clk = '1' then
1583 
 
1584 
         if     Regs_WrEnA_r2='1'
1585 
            and Reg_WrMuxer_Hi(CINT_ADDR_DMA_US_CTRL)='1'
1586 
            and Regs_WrDin_r2(CINT_BIT_DMA_CTRL_VALID+32)='1'
1587 
            then
1588 
               usDMA_Start_i <= not Regs_WrDin_r2(CINT_BIT_DMA_CTRL_END+32)
1589 
                            and not usDMA_Stop_i
1590 
                            and not Command_is_Reset_Hi
1591 
                            and us_Param_Modified
1592 
                            ;
1593 
               usDMA_Stop_i  <= Regs_WrDin_r2(CINT_BIT_DMA_CTRL_END+32)
1594 
                            and not Command_is_Reset_Hi
1595 
                            ;
1596 
         elsif Regs_WrEnA_r2='1'
1597 
            and Reg_WrMuxer_Lo(CINT_ADDR_DMA_US_CTRL)='1'
1598 
            and Regs_WrDin_r2(CINT_BIT_DMA_CTRL_VALID)='1'
1599 
            then
1600 
               usDMA_Start_i <= not Regs_WrDin_r2(CINT_BIT_DMA_CTRL_END)
1601 
                            and not usDMA_Stop_i
1602 
                            and not Command_is_Reset_Lo
1603 
                            and us_Param_Modified
1604 
                            ;
1605 
               usDMA_Stop_i  <= Regs_WrDin_r2(CINT_BIT_DMA_CTRL_END)
1606 
                            and not Command_is_Reset_Lo
1607 
                            ;
1608 
         elsif  Regs_WrEnA_r2='1'
1609 
            and Reg_WrMuxer_Hi(CINT_ADDR_DMA_US_CTRL)='1'
1610 
            and Regs_WrDin_r2(CINT_BIT_DMA_CTRL_VALID)='0'
1611 
            then
1612 
               usDMA_Start_i <= not Last_Ctrl_Word_us(CINT_BIT_DMA_CTRL_END)
1613 
                            and us_Param_Modified;
1614 
               usDMA_Stop_i  <= Last_Ctrl_Word_us(CINT_BIT_DMA_CTRL_END);
1615 
         elsif  Regs_WrEnA_r2='1'
1616 
            and Reg_WrMuxer_Lo(CINT_ADDR_DMA_US_CTRL)='1'
1617 
            and Regs_WrDin_r2(CINT_BIT_DMA_CTRL_VALID)='0'
1618 
            then
1619 
               usDMA_Start_i <= not Last_Ctrl_Word_us(CINT_BIT_DMA_CTRL_END)
1620 
                            and us_Param_Modified;
1621 
               usDMA_Stop_i  <= Last_Ctrl_Word_us(CINT_BIT_DMA_CTRL_END);
1622 
         elsif usDMA_Cmd_Ack='1'
1623 
            then
1624 
               usDMA_Start_i <= '0';
1625 
               usDMA_Stop_i  <= usDMA_Stop_i;
1626 
         else
1627 
               usDMA_Start_i <= usDMA_Start_i;
1628 
               usDMA_Stop_i  <= usDMA_Stop_i;
1629 
         end if;
1630 
 
1631 
      end if;
1632 
   end process;
1633 
 
1634 
 
1635 
-- -------------------------------------------------------
1636 
-- Synchronous output: DMA_us_Start2_Stop2
1637 
   Syn_Output_DMA_us_Start2_Stop2:
1638 
   process ( trn_clk, trn_lnk_up_n)
1639 
   begin
1640 
      if trn_lnk_up_n = '1' then
1641 
         usDMA_Start2_i <= '0';
1642 
         usDMA_Stop2_i  <= '0';
1643 
      elsif trn_clk'event and trn_clk = '1' then
1644 
 
1645 
         if usDMA_Channel_Rst_i='1' then
1646 
               usDMA_Start2_i <= '0';
1647 
               usDMA_Stop2_i  <= '0';
1648 
         elsif     Regs_WrEnB_r2='1'
1649 
            and Reg_WrMuxer_Hi(CINT_ADDR_DMA_US_CTRL)='1'
1650 
            and Regs_WrDin_r2(CINT_BIT_DMA_CTRL_VALID+32)='1'
1651 
            then
1652 
               usDMA_Start2_i <= not Regs_WrDin_r2(CINT_BIT_DMA_CTRL_END+32) and not Command_is_Reset_Hi;
1653 
               usDMA_Stop2_i  <= Regs_WrDin_r2(CINT_BIT_DMA_CTRL_END+32) and not Command_is_Reset_Lo;
1654 
         elsif  Regs_WrEnB_r2='1'
1655 
            and Reg_WrMuxer_Lo(CINT_ADDR_DMA_US_CTRL)='1'
1656 
            and Regs_WrDin_r2(CINT_BIT_DMA_CTRL_VALID)='1'
1657 
            then
1658 
               usDMA_Start2_i <= not Regs_WrDin_r2(CINT_BIT_DMA_CTRL_END) and not Command_is_Reset_Lo;
1659 
               usDMA_Stop2_i  <= Regs_WrDin_r2(CINT_BIT_DMA_CTRL_END) and not Command_is_Reset_Lo;
1660 
         elsif  Regs_WrEnB_r2='1'
1661 
            and Reg_WrMuxer_Hi(CINT_ADDR_DMA_US_CTRL)='1'
1662 
            and Regs_WrDin_r2(CINT_BIT_DMA_CTRL_VALID+32)='0'
1663 
            then
1664 
               usDMA_Start2_i <= not Last_Ctrl_Word_us(CINT_BIT_DMA_CTRL_END);
1665 
               usDMA_Stop2_i  <= Last_Ctrl_Word_us(CINT_BIT_DMA_CTRL_END);
1666 
         elsif  Regs_WrEnB_r2='1'
1667 
            and Reg_WrMuxer_Lo(CINT_ADDR_DMA_US_CTRL)='1'
1668 
            and Regs_WrDin_r2(CINT_BIT_DMA_CTRL_VALID)='0'
1669 
            then
1670 
               usDMA_Start2_i <= not Last_Ctrl_Word_us(CINT_BIT_DMA_CTRL_END);
1671 
               usDMA_Stop2_i  <= Last_Ctrl_Word_us(CINT_BIT_DMA_CTRL_END);
1672 
         elsif usDMA_Cmd_Ack='1' then
1673 
               usDMA_Start2_i <= '0';
1674 
               usDMA_Stop2_i  <= usDMA_Stop2_i;
1675 
         else
1676 
               usDMA_Start2_i <= usDMA_Start2_i;
1677 
               usDMA_Stop2_i  <= usDMA_Stop2_i;
1678 
         end if;
1679 
 
1680 
      end if;
1681 
   end process;
1682 
 
1683 
 
1684 
--  ------------------------------------------------------
1685 
--  DMA Downstream Registers
1686 
--  ------------------------------------------------------
1687 
 
1688 
-- -------------------------------------------------------
1689 
-- Synchronous Registered: DMA_ds_PA_i
1690 
   RxTrn_DMA_ds_PA:
1691 
   process ( trn_clk, trn_lnk_up_n)
1692 
   begin
1693 
      if trn_lnk_up_n = '1' then
1694 
         DMA_ds_PA_i     <= (OTHERS => '0');
1695 
      elsif trn_clk'event and trn_clk = '1' then
1696 
 
1697 
        if dsDMA_Channel_Rst_i = '1' then
1698 
            DMA_ds_PA_i <= (OTHERS => '0');
1699 
        else
1700 
 
1701 
          if Regs_WrEn_r2='1' and Reg_WrMuxer_Hi(CINT_ADDR_DMA_DS_PAH)='1' then
1702 
            DMA_ds_PA_i(C_DBUS_WIDTH-1 downto 32)  <= Regs_WrDin_r2(C_DBUS_WIDTH-1 downto 32);
1703 
          elsif Regs_WrEn_r2='1' and Reg_WrMuxer_Lo(CINT_ADDR_DMA_DS_PAH)='1' then
1704 
            DMA_ds_PA_i(C_DBUS_WIDTH-1 downto 32)  <= Regs_WrDin_r2(32-1 downto 0);
1705 
          else
1706 
            DMA_ds_PA_i(C_DBUS_WIDTH-1 downto 32)  <= DMA_ds_PA_i(C_DBUS_WIDTH-1 downto 32);
1707 
          end if;
1708 
 
1709 
          if Regs_WrEn_r2='1' and Reg_WrMuxer_Hi(CINT_ADDR_DMA_DS_PAL)='1' then
1710 
            DMA_ds_PA_i(32-1 downto 0)  <= Regs_WrDin_r2(C_DBUS_WIDTH-1 downto 32);
1711 
          elsif Regs_WrEn_r2='1' and Reg_WrMuxer_Lo(CINT_ADDR_DMA_DS_PAL)='1' then
1712 
            DMA_ds_PA_i(32-1 downto 0)  <= Regs_WrDin_r2(32-1 downto 0);
1713 
          else
1714 
            DMA_ds_PA_i(32-1 downto 0)  <= DMA_ds_PA_i(32-1 downto 0);
1715 
          end if;
1716 
 
1717 
        end if;
1718 
 
1719 
      end if;
1720 
   end process;
1721 
 
1722 
 
1723 
-- -------------------------------------------------------
1724 
-- Synchronous Registered: DMA_ds_HA_i
1725 
   RxTrn_DMA_ds_HA:
1726 
   process ( trn_clk, trn_lnk_up_n)
1727 
   begin
1728 
      if trn_lnk_up_n = '1' then
1729 
         DMA_ds_HA_i     <= (OTHERS => '1');
1730 
         dsHA_is_64b_i   <= '0';
1731 
      elsif trn_clk'event and trn_clk = '1' then
1732 
 
1733 
        if dsDMA_Channel_Rst_i = '1' then
1734 
            DMA_ds_HA_i <= (OTHERS => '1');
1735 
            dsHA_is_64b_i <= '0';
1736 
        else
1737 
 
1738 
          if Regs_WrEn_r2='1' and Reg_WrMuxer_Hi(CINT_ADDR_DMA_DS_HAH)='1' then
1739 
            DMA_ds_HA_i(C_DBUS_WIDTH-1 downto 32)  <= Regs_WrDin_r2(C_DBUS_WIDTH-1 downto 32);
1740 
            dsHA_is_64b_i   <=  WrDin_r2_not_Zero_Hi;
1741 
          elsif Regs_WrEn_r2='1' and Reg_WrMuxer_Lo(CINT_ADDR_DMA_DS_HAH)='1' then
1742 
            DMA_ds_HA_i(C_DBUS_WIDTH-1 downto 32)  <= Regs_WrDin_r2(32-1 downto 0);
1743 
            dsHA_is_64b_i   <=  WrDin_r2_not_Zero_Lo;
1744 
          else
1745 
            DMA_ds_HA_i(C_DBUS_WIDTH-1 downto 32)  <= DMA_ds_HA_i(C_DBUS_WIDTH-1 downto 32);
1746 
            dsHA_is_64b_i   <=  dsHA_is_64b_i;
1747 
          end if;
1748 
 
1749 
          if Regs_WrEn_r2='1' and Reg_WrMuxer_Hi(CINT_ADDR_DMA_DS_HAL)='1' then
1750 
            DMA_ds_HA_i(32-1 downto 0)  <= Regs_WrDin_r2(C_DBUS_WIDTH-1 downto 32);
1751 
          elsif Regs_WrEn_r2='1' and Reg_WrMuxer_Lo(CINT_ADDR_DMA_DS_HAL)='1' then
1752 
            DMA_ds_HA_i(32-1 downto 0)  <= Regs_WrDin_r2(32-1 downto 0);
1753 
          else
1754 
            DMA_ds_HA_i(32-1 downto 0)  <= DMA_ds_HA_i(32-1 downto 0);
1755 
          end if;
1756 
 
1757 
        end if;
1758 
 
1759 
      end if;
1760 
   end process;
1761 
 
1762 
 
1763 
-- -------------------------------------------------------
1764 
-- Synchronous output: DMA_ds_BDA_i
1765 
   Syn_Output_DMA_ds_BDA:
1766 
   process ( trn_clk, trn_lnk_up_n)
1767 
   begin
1768 
      if trn_lnk_up_n = '1' then
1769 
         DMA_ds_BDA_i    <= (OTHERS =>'0');
1770 
         dsBDA_is_64b_i  <= '0';
1771 
      elsif trn_clk'event and trn_clk = '1' then
1772 
 
1773 
        if dsDMA_Channel_Rst_i = '1' then
1774 
            DMA_ds_BDA_i <= (OTHERS => '0');
1775 
            dsBDA_is_64b_i <= '0';
1776 
        else
1777 
 
1778 
          if Regs_WrEn_r2='1' and Reg_WrMuxer_Hi(CINT_ADDR_DMA_DS_BDAH)='1' then
1779 
            DMA_ds_BDA_i(C_DBUS_WIDTH-1 downto 32)  <= Regs_WrDin_r2(C_DBUS_WIDTH-1 downto 32);
1780 
            dsBDA_is_64b_i   <=  WrDin_r2_not_Zero_Hi;
1781 
          elsif Regs_WrEn_r2='1' and Reg_WrMuxer_Lo(CINT_ADDR_DMA_DS_BDAH)='1' then
1782 
            DMA_ds_BDA_i(C_DBUS_WIDTH-1 downto 32)  <= Regs_WrDin_r2(32-1 downto 0);
1783 
            dsBDA_is_64b_i   <=  WrDin_r2_not_Zero_Lo;
1784 
          else
1785 
            DMA_ds_BDA_i(C_DBUS_WIDTH-1 downto 32)  <= DMA_ds_BDA_i(C_DBUS_WIDTH-1 downto 32);
1786 
            dsBDA_is_64b_i   <=  dsBDA_is_64b_i;
1787 
          end if;
1788 
 
1789 
          if Regs_WrEn_r2='1' and Reg_WrMuxer_Hi(CINT_ADDR_DMA_DS_BDAL)='1' then
1790 
            DMA_ds_BDA_i(32-1 downto 0)  <= Regs_WrDin_r2(C_DBUS_WIDTH-1 downto 32);
1791 
          elsif Regs_WrEn_r2='1' and Reg_WrMuxer_Lo(CINT_ADDR_DMA_DS_BDAL)='1' then
1792 
            DMA_ds_BDA_i(32-1 downto 0)  <= Regs_WrDin_r2(32-1 downto 0);
1793 
          else
1794 
            DMA_ds_BDA_i(32-1 downto 0)  <= DMA_ds_BDA_i(32-1 downto 0);
1795 
          end if;
1796 
 
1797 
        end if;
1798 
      end if;
1799 
   end process;
1800 
 
1801 
 
1802 
 
1803 
-- Synchronous Registered: DMA_ds_Length_i
1804 
   RxTrn_DMA_ds_Length:
1805 
   process ( trn_clk, trn_lnk_up_n)
1806 
   begin
1807 
      if trn_lnk_up_n = '1' then
1808 
         DMA_ds_Length_i     <= (OTHERS => '0');
1809 
         dsLeng_Hi19b_True_i <= '0';
1810 
         dsLeng_Lo7b_True_i  <= '0';
1811 
      elsif trn_clk'event and trn_clk = '1' then
1812 
 
1813 
         if dsDMA_Channel_Rst_i = '1' then
1814 
            DMA_ds_Length_i <= (OTHERS => '0');
1815 
            dsLeng_Hi19b_True_i <= '0';
1816 
            dsLeng_Lo7b_True_i  <= '0';
1817 
 
1818 
         elsif Regs_WrEn_r2='1' and Reg_WrMuxer_Hi(CINT_ADDR_DMA_DS_LENG)='1' then
1819 
            DMA_ds_Length_i(32-1 downto 0)     <= Regs_WrDin_r2(C_DBUS_WIDTH-1 downto 32);
1820 
            dsLeng_Hi19b_True_i <= Regs_WrDin_Hi19b_True_hq_r2;
1821 
            dsLeng_Lo7b_True_i  <= Regs_WrDin_Lo7b_True_hq_r2;
1822 
         elsif Regs_WrEn_r2='1' and Reg_WrMuxer_Lo(CINT_ADDR_DMA_DS_LENG)='1' then
1823 
            DMA_ds_Length_i(32-1 downto 0)     <= Regs_WrDin_r2(32-1 downto 0);
1824 
            dsLeng_Hi19b_True_i <= Regs_WrDin_Hi19b_True_lq_r2;
1825 
            dsLeng_Lo7b_True_i  <= Regs_WrDin_Lo7b_True_lq_r2;
1826 
         else
1827 
            DMA_ds_Length_i     <= DMA_ds_Length_i;
1828 
            dsLeng_Hi19b_True_i <= dsLeng_Hi19b_True_i;
1829 
            dsLeng_Lo7b_True_i  <= dsLeng_Lo7b_True_i;
1830 
 
1831 
         end if;
1832 
 
1833 
      end if;
1834 
   end process;
1835 
 
1836 
 
1837 
 
1838 
-- -------------------------------------------------------
1839 
-- Synchronous ds_Param_Modified
1840 
   SynReg_ds_Param_Modified:
1841 
   process ( trn_clk, trn_lnk_up_n)
1842 
   begin
1843 
      if trn_lnk_up_n = '1' then
1844 
         ds_Param_Modified     <= '0';
1845 
 
1846 
      elsif trn_clk'event and trn_clk = '1' then
1847 
 
1848 
        if dsDMA_Channel_Rst_i = '1'
1849 
           or dsDMA_Start_i = '1'
1850 
           or dsDMA_Start2_i = '1'
1851 
           then
1852 
             ds_Param_Modified     <= '0';
1853 
        elsif Regs_WrEn_r2='1' and
1854 
                (
1855 
--                    Reg_WrMuxer(CINT_ADDR_DMA_DS_PAH) ='1'
1856 
--                 or
1857 
                    Reg_WrMuxer_Hi(CINT_ADDR_DMA_DS_PAL) ='1'
1858 
                 or Reg_WrMuxer_Lo(CINT_ADDR_DMA_DS_PAL) ='1'
1859 
                 or Reg_WrMuxer_Hi(CINT_ADDR_DMA_DS_HAH) ='1'
1860 
                 or Reg_WrMuxer_Lo(CINT_ADDR_DMA_DS_HAH) ='1'
1861 
                 or Reg_WrMuxer_Hi(CINT_ADDR_DMA_DS_HAL) ='1'
1862 
                 or Reg_WrMuxer_Lo(CINT_ADDR_DMA_DS_HAL) ='1'
1863 
                 or Reg_WrMuxer_Hi(CINT_ADDR_DMA_DS_BDAH)='1'
1864 
                 or Reg_WrMuxer_Lo(CINT_ADDR_DMA_DS_BDAH)='1'
1865 
                 or Reg_WrMuxer_Hi(CINT_ADDR_DMA_DS_BDAL)='1'
1866 
                 or Reg_WrMuxer_Lo(CINT_ADDR_DMA_DS_BDAL)='1'
1867 
                 or Reg_WrMuxer_Hi(CINT_ADDR_DMA_DS_LENG)='1'
1868 
                 or Reg_WrMuxer_Lo(CINT_ADDR_DMA_DS_LENG)='1'
1869 
                )
1870 
           then
1871 
             ds_Param_Modified     <= '1';
1872 
        else
1873 
             ds_Param_Modified     <= ds_Param_Modified;
1874 
 
1875 
        end if;
1876 
 
1877 
      end if;
1878 
   end process;
1879 
 
1880 
 
1881 
 
1882 
-- -------------------------------------------------------
1883 
-- Synchronous output: DMA_ds_Control_i
1884 
   Syn_Output_DMA_ds_Control:
1885 
   process ( trn_clk, trn_lnk_up_n)
1886 
   begin
1887 
      if trn_lnk_up_n = '1' then
1888 
         DMA_ds_Control_i <= (OTHERS =>'0');
1889 
 
1890 
      elsif trn_clk'event and trn_clk = '1' then
1891 
 
1892 
         if     Regs_Wr_dma_V_nE_Hi_r2='1'
1893 
            and Reg_WrMuxer_Hi(CINT_ADDR_DMA_DS_CTRL)='1'
1894 
--            and Regs_WrDin_r2(CINT_BIT_DMA_CTRL_VALID+32)='1'
1895 
--            and Regs_WrDin_r2(CINT_BIT_DMA_CTRL_END+32)='0'
1896 
            and ds_Param_Modified='1'
1897 
            and dsDMA_Stop_i='0'
1898 
            then
1899 
               DMA_ds_Control_i(32-1 downto 0) <= Regs_WrDin_r2(C_DBUS_WIDTH-1 downto 8+32)& X"00";
1900 
         elsif  Regs_Wr_dma_V_nE_Lo_r2='1'
1901 
            and Reg_WrMuxer_Lo(CINT_ADDR_DMA_DS_CTRL)='1'
1902 
--            and Regs_WrDin_r2(CINT_BIT_DMA_CTRL_VALID)='1'
1903 
--            and Regs_WrDin_r2(CINT_BIT_DMA_CTRL_END)='0'
1904 
            and ds_Param_Modified='1'
1905 
            and dsDMA_Stop_i='0'
1906 
            then
1907 
               DMA_ds_Control_i(32-1 downto 0) <= Regs_WrDin_r2(32-1 downto 8)& X"00";
1908 
         elsif  Regs_Wr_dma_nV_Hi_r2='1'
1909 
            and (Reg_WrMuxer_Hi(CINT_ADDR_DMA_DS_CTRL)='1' or Reg_WrMuxer_Lo(CINT_ADDR_DMA_DS_CTRL)='1')
1910 
--            and Regs_WrDin_r2(CINT_BIT_DMA_CTRL_VALID)='0'
1911 
            then
1912 
               DMA_ds_Control_i <= Last_Ctrl_Word_ds;
1913 
         else
1914 
            DMA_ds_Control_i  <= DMA_ds_Control_i;
1915 
         end if;
1916 
 
1917 
      end if;
1918 
   end process;
1919 
 
1920 
 
1921 
-- -------------------------------------------------------
1922 
-- Synchronous Register: Last_Ctrl_Word_ds
1923 
   Hold_Last_Ctrl_Word_ds:
1924 
   process ( trn_clk, trn_lnk_up_n)
1925 
   begin
1926 
      if trn_lnk_up_n = '1' then
1927 
         Last_Ctrl_Word_ds  <= C_DEF_DMA_CTRL_WORD;
1928 
      elsif trn_clk'event and trn_clk = '1' then
1929 
 
1930 
        if dsDMA_Channel_Rst_i = '1' then
1931 
            Last_Ctrl_Word_ds <= C_DEF_DMA_CTRL_WORD;
1932 
        elsif Regs_Wr_dma_V_nE_Hi_r2='1'
1933 
          and Reg_WrMuxer_Hi(CINT_ADDR_DMA_DS_CTRL)='1'
1934 
--          and Regs_WrDin_r2(CINT_BIT_DMA_CTRL_VALID+32)='1'
1935 
--          and Regs_WrDin_r2(CINT_BIT_DMA_CTRL_END+32)='0'
1936 
          and ds_Param_Modified='1'
1937 
          and dsDMA_Stop_i='0'
1938 
          then
1939 
            Last_Ctrl_Word_ds(32-1 downto 0) <= Regs_WrDin_r2(C_DBUS_WIDTH-1 downto 8+32) & X"00";
1940 
        elsif Regs_Wr_dma_V_nE_Lo_r2='1'
1941 
          and Reg_WrMuxer_Lo(CINT_ADDR_DMA_DS_CTRL)='1'
1942 
--          and Regs_WrDin_r2(CINT_BIT_DMA_CTRL_VALID)='1'
1943 
--          and Regs_WrDin_r2(CINT_BIT_DMA_CTRL_END)='0'
1944 
          and ds_Param_Modified='1'
1945 
          and dsDMA_Stop_i='0'
1946 
          then
1947 
            Last_Ctrl_Word_ds(32-1 downto 0) <= Regs_WrDin_r2(32-1 downto 8) & X"00";
1948 
        else
1949 
            Last_Ctrl_Word_ds <= Last_Ctrl_Word_ds;
1950 
        end if;
1951 
 
1952 
      end if;
1953 
   end process;
1954 
 
1955 
 
1956 
-- -------------------------------------------------------
1957 
-- Synchronous output: DMA_ds_Start_Stop
1958 
   Syn_Output_DMA_ds_Start_Stop:
1959 
   process ( trn_clk, trn_lnk_up_n)
1960 
   begin
1961 
      if trn_lnk_up_n = '1' then
1962 
         dsDMA_Start_i  <= '0';
1963 
         dsDMA_Stop_i   <= '0';
1964 
 
1965 
      elsif trn_clk'event and trn_clk = '1' then
1966 
 
1967 
         if     Regs_WrEnA_r2='1'
1968 
            and Reg_WrMuxer_Hi(CINT_ADDR_DMA_DS_CTRL)='1'
1969 
            and Regs_WrDin_r2(CINT_BIT_DMA_CTRL_VALID+32)='1'
1970 
            then
1971 
               dsDMA_Start_i <= not Regs_WrDin_r2(CINT_BIT_DMA_CTRL_END+32)
1972 
                            and not dsDMA_Stop_i
1973 
                            and not Command_is_Reset_Hi
1974 
                            and ds_Param_Modified
1975 
                            ;
1976 
               dsDMA_Stop_i  <= Regs_WrDin_r2(CINT_BIT_DMA_CTRL_END+32)
1977 
                            and not Command_is_Reset_Hi
1978 
                            ;
1979 
         elsif  Regs_WrEnA_r2='1'
1980 
            and Reg_WrMuxer_Lo(CINT_ADDR_DMA_DS_CTRL)='1'
1981 
            and Regs_WrDin_r2(CINT_BIT_DMA_CTRL_VALID)='1'
1982 
            then
1983 
               dsDMA_Start_i <= not Regs_WrDin_r2(CINT_BIT_DMA_CTRL_END)
1984 
                            and not dsDMA_Stop_i
1985 
                            and not Command_is_Reset_Lo
1986 
                            and ds_Param_Modified
1987 
                            ;
1988 
               dsDMA_Stop_i  <= Regs_WrDin_r2(CINT_BIT_DMA_CTRL_END)
1989 
                            and not Command_is_Reset_Lo
1990 
                            ;
1991 
         elsif  Regs_WrEnA_r2='1'
1992 
            and (Reg_WrMuxer_Hi(CINT_ADDR_DMA_DS_CTRL)='1' or Reg_WrMuxer_Lo(CINT_ADDR_DMA_DS_CTRL)='1')
1993 
            and Regs_WrDin_r2(CINT_BIT_DMA_CTRL_VALID+32)='0'
1994 
            then
1995 
               dsDMA_Start_i <= not Last_Ctrl_Word_ds(CINT_BIT_DMA_CTRL_END)
1996 
                            and ds_Param_Modified
1997 
                            ;
1998 
               dsDMA_Stop_i  <= Last_Ctrl_Word_ds(CINT_BIT_DMA_CTRL_END);
1999 
         elsif dsDMA_Cmd_Ack='1'
2000 
            then
2001 
               dsDMA_Start_i <= '0';
2002 
               dsDMA_Stop_i  <= dsDMA_Stop_i;
2003 
         else
2004 
               dsDMA_Start_i <= dsDMA_Start_i;
2005 
               dsDMA_Stop_i  <= dsDMA_Stop_i;
2006 
         end if;
2007 
 
2008 
      end if;
2009 
   end process;
2010 
 
2011 
 
2012 
-- -------------------------------------------------------
2013 
-- Synchronous output: DMA_ds_Start2_Stop2
2014 
   Syn_Output_DMA_ds_Start2_Stop2:
2015 
   process ( trn_clk, trn_lnk_up_n)
2016 
   begin
2017 
      if trn_lnk_up_n = '1' then
2018 
         dsDMA_Start2_i <= '0';
2019 
         dsDMA_Stop2_i  <= '0';
2020 
 
2021 
      elsif trn_clk'event and trn_clk = '1' then
2022 
 
2023 
         if dsDMA_Channel_Rst_i='1' then
2024 
               dsDMA_Start2_i <= '0';
2025 
               dsDMA_Stop2_i  <= '0';
2026 
         elsif     Regs_WrEnB_r2='1'
2027 
            and Reg_WrMuxer_Hi(CINT_ADDR_DMA_DS_CTRL)='1'
2028 
            and Regs_WrDin_r2(CINT_BIT_DMA_CTRL_VALID+32)='1'
2029 
            then
2030 
               dsDMA_Start2_i <= not Regs_WrDin_r2(CINT_BIT_DMA_CTRL_END+32) and not Command_is_Reset_Hi;
2031 
               dsDMA_Stop2_i  <= Regs_WrDin_r2(CINT_BIT_DMA_CTRL_END+32) and not Command_is_Reset_Hi;
2032 
         elsif  Regs_WrEnB_r2='1'
2033 
            and Reg_WrMuxer_Lo(CINT_ADDR_DMA_DS_CTRL)='1'
2034 
            and Regs_WrDin_r2(CINT_BIT_DMA_CTRL_VALID)='1'
2035 
            then
2036 
               dsDMA_Start2_i <= not Regs_WrDin_r2(CINT_BIT_DMA_CTRL_END) and not Command_is_Reset_Lo;
2037 
               dsDMA_Stop2_i  <= Regs_WrDin_r2(CINT_BIT_DMA_CTRL_END) and not Command_is_Reset_Lo;
2038 
         elsif  Regs_WrEnB_r2='1'
2039 
            and Reg_WrMuxer_Hi(CINT_ADDR_DMA_DS_CTRL)='1'
2040 
            and Regs_WrDin_r2(CINT_BIT_DMA_CTRL_VALID+32)='0'
2041 
            then
2042 
               dsDMA_Start2_i <= not Last_Ctrl_Word_ds(CINT_BIT_DMA_CTRL_END);
2043 
               dsDMA_Stop2_i  <= Last_Ctrl_Word_ds(CINT_BIT_DMA_CTRL_END);
2044 
         elsif  Regs_WrEnB_r2='1'
2045 
            and Reg_WrMuxer_Lo(CINT_ADDR_DMA_DS_CTRL)='1'
2046 
            and Regs_WrDin_r2(CINT_BIT_DMA_CTRL_VALID)='0'
2047 
            then
2048 
               dsDMA_Start2_i <= not Last_Ctrl_Word_ds(CINT_BIT_DMA_CTRL_END);
2049 
               dsDMA_Stop2_i  <= Last_Ctrl_Word_ds(CINT_BIT_DMA_CTRL_END);
2050 
         elsif dsDMA_Cmd_Ack='1' then
2051 
               dsDMA_Start2_i <= '0';
2052 
               dsDMA_Stop2_i  <= dsDMA_Stop2_i;
2053 
         else
2054 
               dsDMA_Start2_i <= dsDMA_Start2_i;
2055 
               dsDMA_Stop2_i  <= dsDMA_Stop2_i;
2056 
         end if;
2057 
 
2058 
      end if;
2059 
   end process;
2060 
 
2061 
 
2062 
------------------------------------------------------------------------
2063 
--                          Reset signals                             --
2064 
------------------------------------------------------------------------
2065 
 
2066 
-- --------------------------------------
2067 
-- Identification: Command_is_Reset
2068 
--
2069 
   Synch_Capture_Command_is_Reset:
2070 
   process ( trn_clk, trn_lnk_up_n)
2071 
   begin
2072 
      if trn_lnk_up_n = '1' then
2073 
         Command_is_Reset_Hi    <= '0';
2074 
         Command_is_Reset_Lo    <= '0';
2075 
 
2076 
      elsif trn_clk'event and trn_clk = '1' then
2077 
         if Regs_WrDin_r1(C_FEAT_BITS_WIDTH-1+32 downto 32)=C_CHANNEL_RST_BITS then
2078 
            Command_is_Reset_Hi    <= '1';
2079 
         else
2080 
            Command_is_Reset_Hi    <= '0';
2081 
         end if;
2082 
 
2083 
         if Regs_WrDin_r1(C_FEAT_BITS_WIDTH-1 downto 0)=C_CHANNEL_RST_BITS then
2084 
            Command_is_Reset_Lo    <= '1';
2085 
         else
2086 
            Command_is_Reset_Lo    <= '0';
2087 
         end if;
2088 
      end if;
2089 
   end process;
2090 
 
2091 
 
2092 
-- --------------------------------------
2093 
-- Identification: Command_is_Host_iClr
2094 
--
2095 
   Synch_Capture_Command_is_Host_iClr:
2096 
   process ( trn_clk, trn_lnk_up_n)
2097 
   begin
2098 
      if trn_lnk_up_n = '1' then
2099 
         Command_is_Host_iClr_Hi    <= '0';
2100 
         Command_is_Host_iClr_Lo    <= '0';
2101 
 
2102 
      elsif trn_clk'event and trn_clk = '1' then
2103 
         if Regs_WrDin_r1(C_FEAT_BITS_WIDTH-1+32 downto 32)=C_HOST_ICLR_BITS then
2104 
            Command_is_Host_iClr_Hi    <= '1';
2105 
         else
2106 
            Command_is_Host_iClr_Hi    <= '0';
2107 
         end if;
2108 
 
2109 
         if Regs_WrDin_r1(C_FEAT_BITS_WIDTH-1 downto 0)=C_HOST_ICLR_BITS then
2110 
            Command_is_Host_iClr_Lo    <= '1';
2111 
         else
2112 
            Command_is_Host_iClr_Lo    <= '0';
2113 
         end if;
2114 
      end if;
2115 
   end process;
2116 
 
2117 
-------------------------------------------
2118 
-- Synchronous output: usDMA_Channel_Rst_i
2119 
--
2120 
   Syn_Output_usDMA_Channel_Rst:
2121 
   process ( trn_clk, trn_lnk_up_n)
2122 
   begin
2123 
      if trn_lnk_up_n = '1' then
2124 
         usDMA_Channel_Rst_i <= '1';
2125 
      elsif trn_clk'event and trn_clk = '1' then
2126 
 
2127 
         usDMA_Channel_Rst_i <= (Regs_Wr_dma_V_Hi_r2
2128 
                            and Reg_WrMuxer_Hi(CINT_ADDR_DMA_US_CTRL)
2129 
--                            and Regs_WrDin_r2(CINT_BIT_DMA_CTRL_VALID+32)
2130 
                            and Command_is_Reset_Hi
2131 
                                )
2132 
                            or  (Regs_Wr_dma_V_LO_r2
2133 
                            and Reg_WrMuxer_Lo(CINT_ADDR_DMA_US_CTRL)
2134 
--                            and Regs_WrDin_r2(CINT_BIT_DMA_CTRL_VALID)
2135 
                            and Command_is_Reset_Lo
2136 
                                )
2137 
                            ;
2138 
      end if;
2139 
   end process;
2140 
 
2141 
 
2142 
 
2143 
-------------------------------------------
2144 
-- Synchronous output: dsDMA_Channel_Rst_i
2145 
--
2146 
   Syn_Output_dsDMA_Channel_Rst:
2147 
   process ( trn_clk, trn_lnk_up_n)
2148 
   begin
2149 
      if trn_lnk_up_n = '1' then
2150 
         dsDMA_Channel_Rst_i <= '1';
2151 
      elsif trn_clk'event and trn_clk = '1' then
2152 
 
2153 
         dsDMA_Channel_Rst_i <= (Regs_Wr_dma_V_Hi_r2
2154 
                            and Reg_WrMuxer_Hi(CINT_ADDR_DMA_DS_CTRL)
2155 
--                            and Regs_WrDin_r2(CINT_BIT_DMA_CTRL_VALID+32)
2156 
                            and Command_is_Reset_Hi
2157 
                            )
2158 
                            or
2159 
                           (Regs_Wr_dma_V_Lo_r2
2160 
                            and Reg_WrMuxer_Lo(CINT_ADDR_DMA_DS_CTRL)
2161 
--                            and Regs_WrDin_r2(CINT_BIT_DMA_CTRL_VALID)
2162 
                            and Command_is_Reset_Lo
2163 
                            )
2164 
                            ;
2165 
      end if;
2166 
   end process;
2167 
 
2168 
 
2169 
-- -----------------------------------------------
2170 
-- Synchronous output: MRd_Channel_Rst_i
2171 
--
2172 
   Syn_Output_MRd_Channel_Rst:
2173 
   process ( trn_clk, trn_lnk_up_n)
2174 
   begin
2175 
      if trn_lnk_up_n = '1' then
2176 
         MRd_Channel_Rst_i <= '1';
2177 
      elsif trn_clk'event and trn_clk = '1' then
2178 
 
2179 
         MRd_Channel_Rst_i    <= Regs_WrEn_r2
2180 
                             and (
2181 
                                 (Reg_WrMuxer_Hi(CINT_ADDR_MRD_CTRL)
2182 
                                  and Command_is_Reset_Hi)
2183 
                             or
2184 
                                 (Reg_WrMuxer_Lo(CINT_ADDR_MRD_CTRL)
2185 
                                  and Command_is_Reset_Lo)
2186 
                             )
2187 
                             ;
2188 
      end if;
2189 
   end process;
2190 
 
2191 
 
2192 
-- -----------------------------------------------
2193 
-- Synchronous output: Tx_Reset_i
2194 
--
2195 
   Syn_Output_Tx_Reset:
2196 
   process ( trn_clk, trn_lnk_up_n)
2197 
   begin
2198 
      if trn_lnk_up_n = '1' then
2199 
         Tx_Reset_i   <= '1';
2200 
      elsif trn_clk'event and trn_clk = '1' then
2201 
 
2202 
         Tx_Reset_i   <= Regs_WrEn_r2
2203 
                     and ((Reg_WrMuxer_Hi(CINT_ADDR_TX_CTRL)
2204 
                     and Command_is_Reset_Hi)
2205 
                     or  (Reg_WrMuxer_Lo(CINT_ADDR_TX_CTRL)
2206 
                     and Command_is_Reset_Lo))
2207 
                     ;
2208 
      end if;
2209 
   end process;
2210 
 
2211 
 
2212 
-- -----------------------------------------------
2213 
-- Synchronous output: eb_FIFO_Rst_i
2214 
--
2215 
   Syn_Output_eb_FIFO_Rst:
2216 
   process ( trn_clk, trn_lnk_up_n)
2217 
   begin
2218 
      if trn_lnk_up_n = '1' then
2219 
         eb_FIFO_Rst_i    <= '1';
2220 
         eb_FIFO_Rst_b3   <= '1';
2221 
         eb_FIFO_Rst_b2   <= '1';
2222 
         eb_FIFO_Rst_b1   <= '1';
2223 
      elsif trn_clk'event and trn_clk = '1' then
2224 
 
2225 
         eb_FIFO_Rst_i   <= eb_FIFO_Rst_b1 or eb_FIFO_Rst_b2 or eb_FIFO_Rst_b3;
2226 
         eb_FIFO_Rst_b3  <= eb_FIFO_Rst_b2;
2227 
         eb_FIFO_Rst_b2  <= eb_FIFO_Rst_b1;
2228 
         eb_FIFO_Rst_b1  <= Regs_WrEn_r2
2229 
                         and ((Reg_WrMuxer_Hi(CINT_ADDR_EB_STACON)
2230 
                         and Command_is_Reset_Hi)
2231 
                         or  (Reg_WrMuxer_Lo(CINT_ADDR_EB_STACON)
2232 
                         and Command_is_Reset_Lo))
2233 
                         ;
2234 
      end if;
2235 
   end process;
2236 
 
2237 
 
2238 
-- -----------------------------------------------
2239 
-- Synchronous output: protocol_rst
2240 
--
2241 
--            !!!  reset by trn_reset_n  !!!
2242 
--
2243 
   Syn_Output_protocol_rst:
2244 
   process ( trn_clk, trn_reset_n)
2245 
   begin
2246 
      if trn_reset_n = '0' then
2247 
         protocol_rst_i   <= '1';
2248 
         protocol_rst_b1  <= '1';
2249 
         protocol_rst_b2  <= '1';
2250 
      elsif trn_clk'event and trn_clk = '1' then
2251 
 
2252 
         protocol_rst_i  <= protocol_rst_b1 or protocol_rst_b2;
2253 
         protocol_rst_b1 <= protocol_rst_b2;
2254 
         protocol_rst_b2 <= Regs_WrEn_r2
2255 
                         and ((Reg_WrMuxer_Hi(CINT_ADDR_PROTOCOL_STACON)
2256 
                         and Command_is_Reset_Hi)
2257 
                         or  (Reg_WrMuxer_Lo(CINT_ADDR_PROTOCOL_STACON)
2258 
                         and Command_is_Reset_Lo))
2259 
                         ;
2260 
      end if;
2261 
   end process;
2262 
 
2263 
 
2264 
-- -----------------------------------------------
2265 
-- Synchronous Calculation: DMA_us_Transf_Bytes
2266 
--
2267 
   Syn_Calc_DMA_us_Transf_Bytes:
2268 
   process ( trn_clk, trn_lnk_up_n)
2269 
   begin
2270 
      if trn_lnk_up_n = '1' then
2271 
         DMA_us_Transf_Bytes_i   <= (OTHERS=>'0');
2272 
      elsif trn_clk'event and trn_clk = '1' then
2273 
 
2274 
         if usDMA_Channel_Rst_i='1' then
2275 
            DMA_us_Transf_Bytes_i   <= (OTHERS=>'0');
2276 
         elsif us_DMA_Bytes_Add='1' then
2277 
            DMA_us_Transf_Bytes_i(32-1 downto 0)
2278 
                                    <= DMA_us_Transf_Bytes_i(32-1 downto 0)
2279 
                                    +  us_DMA_Bytes;
2280 
         else
2281 
            DMA_us_Transf_Bytes_i   <= DMA_us_Transf_Bytes_i;
2282 
         end if;
2283 
      end if;
2284 
   end process;
2285 
 
2286 
 
2287 
-- -----------------------------------------------
2288 
-- Synchronous Calculation: DMA_ds_Transf_Bytes
2289 
--
2290 
   Syn_Calc_DMA_ds_Transf_Bytes:
2291 
   process ( trn_clk, trn_lnk_up_n)
2292 
   begin
2293 
      if trn_lnk_up_n = '1' then
2294 
         DMA_ds_Transf_Bytes_i   <= (OTHERS=>'0');
2295 
      elsif trn_clk'event and trn_clk = '1' then
2296 
 
2297 
         if dsDMA_Channel_Rst_i='1' then
2298 
            DMA_ds_Transf_Bytes_i   <= (OTHERS=>'0');
2299 
         elsif ds_DMA_Bytes_Add='1' then
2300 
            DMA_ds_Transf_Bytes_i(32-1 downto 0)
2301 
                                    <= DMA_ds_Transf_Bytes_i(32-1 downto 0)
2302 
                                    +  ds_DMA_Bytes;
2303 
         else
2304 
            DMA_ds_Transf_Bytes_i   <= DMA_ds_Transf_Bytes_i;
2305 
         end if;
2306 
      end if;
2307 
   end process;
2308 
 
2309 
---- -------------------------------------------------------
2310 
---- Synchronous Registers: icap_Write_i
2311 
--   RxTrn_icap_Write:
2312 
--   process ( trn_clk, trn_lnk_up_n)
2313 
--   begin
2314 
--      if trn_lnk_up_n = '1' then
2315 
--         icap_CLK      <= '0';
2316 
--         icap_I        <= (OTHERS => '0');
2317 
--         icap_Write    <= '1';
2318 
--         icap_CE       <= '1';
2319 
--         FSM_icap      <= icapST_Reset;
2320 
--
2321 
--      elsif trn_clk'event and trn_clk = '1' then
2322 
--
2323 
--        case FSM_icap is
2324 
--
2325 
--          when icapST_Reset =>
2326 
--            icap_CLK      <= '0';
2327 
--            icap_I        <= (OTHERS => '0');
2328 
--            icap_Write    <= '1';
2329 
--            icap_CE       <= '1';
2330 
--            FSM_icap      <= icapST_Idle;
2331 
--
2332 
--          when icapST_Idle =>
2333 
--
2334 
--            if Regs_WrEn_r2='1' and  Reg_WrMuxer(CINT_ADDR_ICAP)='1' then
2335 
--               icap_CLK   <= '1';
2336 
--               icap_I     <= Regs_WrDin_r2;
2337 
--               icap_Write <= '0';
2338 
--               icap_CE    <= '0';
2339 
--               FSM_icap   <= icapST_Access;
2340 
--            elsif Reg_RdMuxer(CINT_ADDR_ICAP)='1' then
2341 
--               icap_CLK   <= '1';
2342 
--               icap_I     <= icap_I;
2343 
--               icap_Write <= '1';
2344 
--               icap_CE    <= '0';
2345 
--               FSM_icap   <= icapST_Access;
2346 
--            else
2347 
--               icap_CLK   <= icap_CLK;
2348 
--               icap_I     <= icap_I;
2349 
--               icap_Write <= icap_Write;
2350 
--               icap_CE    <= icap_CE;
2351 
--               FSM_icap   <= icapST_Idle;
2352 
--            end if;
2353 
--
2354 
--
2355 
--          when icapST_Access =>
2356 
--               icap_CLK   <= '1';
2357 
--               icap_I     <= icap_I;
2358 
--               icap_Write <= icap_Write;
2359 
--               icap_CE    <= icap_CE;
2360 
--               FSM_icap   <= icapST_Abort;
2361 
--
2362 
--          when icapST_Abort =>
2363 
--               icap_CLK   <= '0';
2364 
--               icap_I     <= icap_I;
2365 
--               icap_Write <= icap_Write;
2366 
--               icap_CE    <= icap_CE;
2367 
--               FSM_icap   <= icapST_Idle;
2368 
--
2369 
--          when Others =>
2370 
--            icap_CLK      <= '0';
2371 
--            icap_I        <= (OTHERS => '0');
2372 
--            icap_Write    <= '1';
2373 
--            icap_CE       <= '1';
2374 
--            FSM_icap      <= icapST_Idle;
2375 
--
2376 
--        end case;
2377 
--
2378 
--      end if;
2379 
--   end process;
2380 
--
2381 
 
2382 
 
2383 
----------------------------------------------------------
2384 
---------------  Tx reading registers  -------------------
2385 
----------------------------------------------------------
2386 
 
2387 
----------------------------------------------------------
2388 
-- Synch Register:  Read Selection
2389 
--
2390 
   Tx_DMA_Reg_RdMuxer:
2391 
   process ( trn_clk, trn_lnk_up_n)
2392 
   begin
2393 
      if trn_lnk_up_n = '1' then
2394 
           Reg_RdMuxer_Hi     <= (Others =>'0');
2395 
           Reg_RdMuxer_Lo     <= (Others =>'0');
2396 
 
2397 
      elsif trn_clk'event and trn_clk = '1' then
2398 
 
2399 
         FOR k IN 0 TO C_NUM_OF_ADDRESSES-1 LOOP
2400 
            if Regs_RdAddr_i(C_DECODE_BIT_TOP downto C_DECODE_BIT_BOT)= C_REGS_BASE_ADDR(C_DECODE_BIT_TOP downto C_DECODE_BIT_BOT)
2401 
               and Regs_RdAddr_i(C_DECODE_BIT_BOT-1 downto 2)=CONV_STD_LOGIC_VECTOR(k, C_DECODE_BIT_BOT-2)
2402 
               and Regs_RdAddr_i(2-1 downto 0)="00"
2403 
               then
2404 
               Reg_RdMuxer_Hi(k) <= '1';
2405 
            else
2406 
               Reg_RdMuxer_Hi(k) <= '0';
2407 
            end if;
2408 
         END LOOP;
2409 
 
2410 
         if Regs_RdAddr_i(C_DECODE_BIT_TOP downto C_DECODE_BIT_BOT)= C_ALL_ONES(C_DECODE_BIT_TOP downto C_DECODE_BIT_BOT)
2411 
            and Regs_RdAddr_i(C_DECODE_BIT_BOT-1 downto 2)=C_ALL_ONES(C_DECODE_BIT_BOT-1 downto 2)
2412 
            and Regs_RdAddr_i(2-1 downto 0)="00"
2413 
            then
2414 
            Reg_RdMuxer_Lo(0) <= '1';
2415 
         else
2416 
            Reg_RdMuxer_Lo(0) <= '0';
2417 
         end if;
2418 
         FOR k IN 1 TO C_NUM_OF_ADDRESSES-1 LOOP
2419 
            if Regs_RdAddr_i(C_DECODE_BIT_TOP downto C_DECODE_BIT_BOT)= C_REGS_BASE_ADDR(C_DECODE_BIT_TOP downto C_DECODE_BIT_BOT)
2420 
               and Regs_RdAddr_i(C_DECODE_BIT_BOT-1 downto 2)=CONV_STD_LOGIC_VECTOR(k-1, C_DECODE_BIT_BOT-2)
2421 
               and Regs_RdAddr_i(2-1 downto 0)="00"
2422 
               then
2423 
               Reg_RdMuxer_Lo(k) <= '1';
2424 
            else
2425 
               Reg_RdMuxer_Lo(k) <= '0';
2426 
            end if;
2427 
         END LOOP;
2428 
 
2429 
      end if;
2430 
   end process;
2431 
 
2432 
 
2433 
----------------------------------------------------------
2434 
-- Synch Register:  CTL_TTake
2435 
--
2436 
   Syn_CTL_ttake:
2437 
   process ( trn_clk, trn_lnk_up_n)
2438 
   begin
2439 
      if trn_lnk_up_n = '1' then
2440 
         ctl_ttake_i      <= '0';
2441 
         ctl_t_read_Hi_r1 <= '0';
2442 
         ctl_t_read_Lo_r1 <= '0';
2443 
         CTL_read_counter <= (OTHERS=>'0');
2444 
 
2445 
      elsif trn_clk'event and trn_clk = '1' then
2446 
         ctl_t_read_Hi_r1 <= Reg_RdMuxer_Hi(CINT_ADDR_CTL_CLASS);
2447 
         ctl_t_read_Lo_r1 <= Reg_RdMuxer_Lo(CINT_ADDR_CTL_CLASS);
2448 
         ctl_ttake_i  <= (Reg_RdMuxer_Hi(CINT_ADDR_CTL_CLASS) and not ctl_t_read_Hi_r1)
2449 
                      or (Reg_RdMuxer_Lo(CINT_ADDR_CTL_CLASS) and not ctl_t_read_Lo_r1)
2450 
                      ;
2451 
         if ctl_reset_i='1' then
2452 
            CTL_read_counter <= (OTHERS=>'0');
2453 
         else
2454 
            CTL_read_counter <= CTL_read_counter + ctl_ttake_i;
2455 
         end if;
2456 
 
2457 
      end if;
2458 
   end process;
2459 
 
2460 
----------------------------------------------------------
2461 
-- Synch Register:  class_CTL_Status
2462 
--
2463 
   Syn_class_CTL_Status:
2464 
   process ( trn_clk, trn_lnk_up_n)
2465 
   begin
2466 
      if trn_lnk_up_n = '1' then
2467 
         class_CTL_Status_i      <= (OTHERS=>'0');
2468 
 
2469 
      elsif trn_clk'event and trn_clk = '1' then
2470 
         class_CTL_Status_i(C_DBUS_WIDTH/2-1 downto 0)      <= ctl_status;
2471 
 
2472 
      end if;
2473 
   end process;
2474 
 
2475 
 
2476 
-- -------------------------------------------------------
2477 
--
2478 
   Sys_Int_Status_i     <= (
2479 
                            CINT_BIT_DLM_IN_ISR     => DLM_irq     ,
2480 
                            CINT_BIT_CTL_IN_ISR     => CTL_irq     ,
2481 
                            CINT_BIT_DAQ_IN_ISR     => DAQ_irq     ,
2482 
 
2483 
                            CINT_BIT_DSTOUT_IN_ISR  => DMA_ds_Tout ,
2484 
                            CINT_BIT_USTOUT_IN_ISR  => DMA_us_Tout ,
2485 
 
2486 
                            CINT_BIT_INTGEN_IN_ISR  => IG_Asserting,
2487 
                            CINT_BIT_DS_DONE_IN_ISR => DMA_ds_Done ,
2488 
                            CINT_BIT_US_DONE_IN_ISR => DMA_us_Done ,
2489 
                            OTHERS                  => '0'
2490 
                           );
2491 
 
2492 
   --------------------------------------------------------------------------
2493 
   -- Upstream Registers
2494 
   --------------------------------------------------------------------------
2495 
 
2496 
   --  Peripheral Address Start point
2497 
   DMA_us_PA_o_Hi(C_DBUS_WIDTH-1 downto C_DBUS_WIDTH/2)
2498 
      <= DMA_us_PA_i(C_DBUS_WIDTH-1 downto C_DBUS_WIDTH/2) when Reg_RdMuxer_Hi(CINT_ADDR_DMA_US_PAH)='1'
2499 
         else (Others=>'0');
2500 
 
2501 
   DMA_us_PA_o_Hi(C_DBUS_WIDTH/2-1 downto 0)
2502 
      <= DMA_us_PA_i(C_DBUS_WIDTH/2-1 downto 0) when Reg_RdMuxer_Hi(CINT_ADDR_DMA_US_PAL)='1'
2503 
         else (Others=>'0');
2504 
 
2505 
 
2506 
   --  Host Address Start point
2507 
   DMA_us_HA_o_Hi(C_DBUS_WIDTH-1 downto C_DBUS_WIDTH/2)
2508 
      <= DMA_us_HA_i(C_DBUS_WIDTH-1 downto C_DBUS_WIDTH/2) when Reg_RdMuxer_Hi(CINT_ADDR_DMA_US_HAH)='1'
2509 
         else (Others=>'0');
2510 
 
2511 
   DMA_us_HA_o_Hi(C_DBUS_WIDTH/2-1 downto 0)
2512 
      <= DMA_us_HA_i(C_DBUS_WIDTH/2-1 downto 0) when Reg_RdMuxer_Hi(CINT_ADDR_DMA_US_HAL)='1'
2513 
         else (Others=>'0');
2514 
 
2515 
 
2516 
   --  Next Descriptor Address
2517 
   DMA_us_BDA_o_Hi(C_DBUS_WIDTH-1 downto C_DBUS_WIDTH/2)
2518 
      <= DMA_us_BDA_i(C_DBUS_WIDTH-1 downto C_DBUS_WIDTH/2) when Reg_RdMuxer_Hi(CINT_ADDR_DMA_US_BDAH)='1'
2519 
         else (Others=>'0');
2520 
 
2521 
   DMA_us_BDA_o_Hi(C_DBUS_WIDTH/2-1 downto 0)
2522 
      <= DMA_us_BDA_i(C_DBUS_WIDTH/2-1 downto 0) when Reg_RdMuxer_Hi(CINT_ADDR_DMA_US_BDAL)='1'
2523 
         else (Others=>'0');
2524 
 
2525 
   --  Length
2526 
   DMA_us_Length_o_Hi(32-1 downto 0)
2527 
      <= DMA_us_Length_i(32-1 downto 0) when Reg_RdMuxer_Hi(CINT_ADDR_DMA_US_LENG)='1'
2528 
         else (Others=>'0');
2529 
 
2530 
   --  Control word
2531 
   DMA_us_Control_o_Hi(32-1 downto 0)
2532 
      <= DMA_us_Control_i(32-1 downto 0) when Reg_RdMuxer_Hi(CINT_ADDR_DMA_US_CTRL)='1'
2533 
         else (Others=>'0');
2534 
 
2535 
   --  Status (Read only)
2536 
   DMA_us_Status_o_Hi(32-1 downto 0)
2537 
      <= DMA_us_Status_i(32-1 downto 0) when Reg_RdMuxer_Hi(CINT_ADDR_DMA_US_STA)='1'
2538 
         else (Others=>'0');
2539 
 
2540 
   --  Tranferred bytes (Read only)
2541 
   DMA_us_Transf_Bytes_o_Hi(32-1 downto 0)
2542 
      <= DMA_us_Transf_Bytes_i(32-1 downto 0) when Reg_RdMuxer_Hi(CINT_ADDR_US_TRANSF_BC)='1'
2543 
         else (Others=>'0');
2544 
 
2545 
 
2546 
   --  Peripheral Address Start point
2547 
   DMA_us_PA_o_Lo(C_DBUS_WIDTH-1 downto C_DBUS_WIDTH/2)
2548 
      <= DMA_us_PA_i(C_DBUS_WIDTH-1 downto C_DBUS_WIDTH/2) when Reg_RdMuxer_Lo(CINT_ADDR_DMA_US_PAH)='1'
2549 
         else (Others=>'0');
2550 
 
2551 
   DMA_us_PA_o_Lo(C_DBUS_WIDTH/2-1 downto 0)
2552 
      <= DMA_us_PA_i(C_DBUS_WIDTH/2-1 downto 0) when Reg_RdMuxer_Lo(CINT_ADDR_DMA_US_PAL)='1'
2553 
         else (Others=>'0');
2554 
 
2555 
 
2556 
   --  Host Address Start point
2557 
   DMA_us_HA_o_Lo(C_DBUS_WIDTH-1 downto C_DBUS_WIDTH/2)
2558 
      <= DMA_us_HA_i(C_DBUS_WIDTH-1 downto C_DBUS_WIDTH/2) when Reg_RdMuxer_Lo(CINT_ADDR_DMA_US_HAH)='1'
2559 
         else (Others=>'0');
2560 
 
2561 
   DMA_us_HA_o_Lo(C_DBUS_WIDTH/2-1 downto 0)
2562 
      <= DMA_us_HA_i(C_DBUS_WIDTH/2-1 downto 0) when Reg_RdMuxer_Lo(CINT_ADDR_DMA_US_HAL)='1'
2563 
         else (Others=>'0');
2564 
 
2565 
 
2566 
   --  Next Descriptor Address
2567 
   DMA_us_BDA_o_Lo(C_DBUS_WIDTH-1 downto C_DBUS_WIDTH/2)
2568 
      <= DMA_us_BDA_i(C_DBUS_WIDTH-1 downto C_DBUS_WIDTH/2) when Reg_RdMuxer_Lo(CINT_ADDR_DMA_US_BDAH)='1'
2569 
         else (Others=>'0');
2570 
 
2571 
   DMA_us_BDA_o_Lo(C_DBUS_WIDTH/2-1 downto 0)
2572 
      <= DMA_us_BDA_i(C_DBUS_WIDTH/2-1 downto 0) when Reg_RdMuxer_Lo(CINT_ADDR_DMA_US_BDAL)='1'
2573 
         else (Others=>'0');
2574 
 
2575 
   --  Length
2576 
   DMA_us_Length_o_Lo(32-1 downto 0)
2577 
      <= DMA_us_Length_i(32-1 downto 0) when Reg_RdMuxer_Lo(CINT_ADDR_DMA_US_LENG)='1'
2578 
         else (Others=>'0');
2579 
 
2580 
   --  Control word
2581 
   DMA_us_Control_o_Lo(32-1 downto 0)
2582 
      <= DMA_us_Control_i(32-1 downto 0) when Reg_RdMuxer_Lo(CINT_ADDR_DMA_US_CTRL)='1'
2583 
         else (Others=>'0');
2584 
 
2585 
   --  Status (Read only)
2586 
   DMA_us_Status_o_Lo(32-1 downto 0)
2587 
      <= DMA_us_Status_i(32-1 downto 0) when Reg_RdMuxer_Lo(CINT_ADDR_DMA_US_STA)='1'
2588 
         else (Others=>'0');
2589 
 
2590 
   --  Tranferred bytes (Read only)
2591 
   DMA_us_Transf_Bytes_o_Lo(32-1 downto 0)
2592 
      <= DMA_us_Transf_Bytes_i(32-1 downto 0) when Reg_RdMuxer_Lo(CINT_ADDR_US_TRANSF_BC)='1'
2593 
         else (Others=>'0');
2594 
 
2595 
   --------------------------------------------------------------------------
2596 
   -- Downstream Registers
2597 
   --------------------------------------------------------------------------
2598 
 
2599 
   --  Peripheral Address Start point
2600 
   DMA_ds_PA_o_Hi(C_DBUS_WIDTH-1 downto C_DBUS_WIDTH/2)
2601 
      <= DMA_ds_PA_i(C_DBUS_WIDTH-1 downto C_DBUS_WIDTH/2) when Reg_RdMuxer_Hi(CINT_ADDR_DMA_DS_PAH)='1'
2602 
         else (Others=>'0');
2603 
 
2604 
   DMA_ds_PA_o_Hi(C_DBUS_WIDTH/2-1 downto 0)
2605 
      <= DMA_ds_PA_i(C_DBUS_WIDTH/2-1 downto 0) when Reg_RdMuxer_Hi(CINT_ADDR_DMA_DS_PAL)='1'
2606 
         else (Others=>'0');
2607 
 
2608 
   --  Host Address Start point
2609 
   DMA_ds_HA_o_Hi(C_DBUS_WIDTH-1 downto C_DBUS_WIDTH/2)
2610 
      <= DMA_ds_HA_i(C_DBUS_WIDTH-1 downto C_DBUS_WIDTH/2) when Reg_RdMuxer_Hi(CINT_ADDR_DMA_DS_HAH)='1'
2611 
         else (Others=>'0');
2612 
 
2613 
   DMA_ds_HA_o_Hi(C_DBUS_WIDTH/2-1 downto 0)
2614 
      <= DMA_ds_HA_i(C_DBUS_WIDTH/2-1 downto 0) when Reg_RdMuxer_Hi(CINT_ADDR_DMA_DS_HAL)='1'
2615 
         else (Others=>'0');
2616 
 
2617 
   --  Next Descriptor Address
2618 
   DMA_ds_BDA_o_Hi(C_DBUS_WIDTH-1 downto C_DBUS_WIDTH/2)
2619 
      <= DMA_ds_BDA_i(C_DBUS_WIDTH-1 downto C_DBUS_WIDTH/2) when Reg_RdMuxer_Hi(CINT_ADDR_DMA_DS_BDAH)='1'
2620 
         else (Others=>'0');
2621 
 
2622 
   DMA_ds_BDA_o_Hi(C_DBUS_WIDTH/2-1 downto 0)
2623 
      <= DMA_ds_BDA_i(C_DBUS_WIDTH/2-1 downto 0) when Reg_RdMuxer_Hi(CINT_ADDR_DMA_DS_BDAL)='1'
2624 
         else (Others=>'0');
2625 
 
2626 
   --  Length
2627 
   DMA_ds_Length_o_Hi(32-1 downto 0)
2628 
      <= DMA_ds_Length_i(32-1 downto 0) when Reg_RdMuxer_Hi(CINT_ADDR_DMA_DS_LENG)='1'
2629 
         else (Others=>'0');
2630 
 
2631 
   --  Control word
2632 
   DMA_ds_Control_o_Hi(32-1 downto 0)
2633 
      <= DMA_ds_Control_i(32-1 downto 0) when Reg_RdMuxer_Hi(CINT_ADDR_DMA_DS_CTRL)='1'
2634 
         else (Others=>'0');
2635 
 
2636 
   --  Status (Read only)
2637 
   DMA_ds_Status_o_Hi(32-1 downto 0)
2638 
      <= DMA_ds_Status_i(32-1 downto 0) when Reg_RdMuxer_Hi(CINT_ADDR_DMA_DS_STA)='1'
2639 
         else (Others=>'0');
2640 
 
2641 
   --  Tranferred bytes (Read only)
2642 
   DMA_ds_Transf_Bytes_o_Hi(32-1 downto 0)
2643 
      <= DMA_ds_Transf_Bytes_i(32-1 downto 0) when Reg_RdMuxer_Hi(CINT_ADDR_DS_TRANSF_BC)='1'
2644 
         else (Others=>'0');
2645 
 
2646 
   --  Peripheral Address Start point
2647 
   DMA_ds_PA_o_Lo(C_DBUS_WIDTH-1 downto C_DBUS_WIDTH/2)
2648 
      <= DMA_ds_PA_i(C_DBUS_WIDTH-1 downto C_DBUS_WIDTH/2) when Reg_RdMuxer_Lo(CINT_ADDR_DMA_DS_PAH)='1'
2649 
         else (Others=>'0');
2650 
 
2651 
   DMA_ds_PA_o_Lo(C_DBUS_WIDTH/2-1 downto 0)
2652 
      <= DMA_ds_PA_i(C_DBUS_WIDTH/2-1 downto 0) when Reg_RdMuxer_Lo(CINT_ADDR_DMA_DS_PAL)='1'
2653 
         else (Others=>'0');
2654 
 
2655 
   --  Host Address Start point
2656 
   DMA_ds_HA_o_Lo(C_DBUS_WIDTH-1 downto C_DBUS_WIDTH/2)
2657 
      <= DMA_ds_HA_i(C_DBUS_WIDTH-1 downto C_DBUS_WIDTH/2) when Reg_RdMuxer_Lo(CINT_ADDR_DMA_DS_HAH)='1'
2658 
         else (Others=>'0');
2659 
 
2660 
   DMA_ds_HA_o_Lo(C_DBUS_WIDTH/2-1 downto 0)
2661 
      <= DMA_ds_HA_i(C_DBUS_WIDTH/2-1 downto 0) when Reg_RdMuxer_Lo(CINT_ADDR_DMA_DS_HAL)='1'
2662 
         else (Others=>'0');
2663 
 
2664 
   --  Next Descriptor Address
2665 
   DMA_ds_BDA_o_Lo(C_DBUS_WIDTH-1 downto C_DBUS_WIDTH/2)
2666 
      <= DMA_ds_BDA_i(C_DBUS_WIDTH-1 downto C_DBUS_WIDTH/2) when Reg_RdMuxer_Lo(CINT_ADDR_DMA_DS_BDAH)='1'
2667 
         else (Others=>'0');
2668 
 
2669 
   DMA_ds_BDA_o_Lo(C_DBUS_WIDTH/2-1 downto 0)
2670 
      <= DMA_ds_BDA_i(C_DBUS_WIDTH/2-1 downto 0) when Reg_RdMuxer_Lo(CINT_ADDR_DMA_DS_BDAL)='1'
2671 
         else (Others=>'0');
2672 
 
2673 
   --  Length
2674 
   DMA_ds_Length_o_Lo(32-1 downto 0)
2675 
      <= DMA_ds_Length_i(32-1 downto 0) when Reg_RdMuxer_Lo(CINT_ADDR_DMA_DS_LENG)='1'
2676 
         else (Others=>'0');
2677 
 
2678 
   --  Control word
2679 
   DMA_ds_Control_o_Lo(32-1 downto 0)
2680 
      <= DMA_ds_Control_i(32-1 downto 0) when Reg_RdMuxer_Lo(CINT_ADDR_DMA_DS_CTRL)='1'
2681 
         else (Others=>'0');
2682 
 
2683 
   --  Status (Read only)
2684 
   DMA_ds_Status_o_Lo(32-1 downto 0)
2685 
      <= DMA_ds_Status_i(32-1 downto 0) when Reg_RdMuxer_Lo(CINT_ADDR_DMA_DS_STA)='1'
2686 
         else (Others=>'0');
2687 
 
2688 
   --  Tranferred bytes (Read only)
2689 
   DMA_ds_Transf_Bytes_o_Lo(32-1 downto 0)
2690 
      <= DMA_ds_Transf_Bytes_i(32-1 downto 0) when Reg_RdMuxer_Lo(CINT_ADDR_DS_TRANSF_BC)='1'
2691 
         else (Others=>'0');
2692 
 
2693 
 
2694 
   --------------------------------------------------------------------------
2695 
   -- CTL
2696 
   --------------------------------------------------------------------------
2697 
   ctl_td_o_Hi(32-1 downto 0)
2698 
      <= ctl_td_r(32-1 downto 0) when Reg_RdMuxer_Hi(CINT_ADDR_CTL_CLASS)='1'
2699 
         else (Others=>'0');
2700 
 
2701 
   ctl_td_o_Lo(32-1 downto 0)
2702 
      <= ctl_td_r(32-1 downto 0) when Reg_RdMuxer_Lo(CINT_ADDR_CTL_CLASS)='1'
2703 
         else (Others=>'0');
2704 
 
2705 
   --------------------------------------------------------------------------
2706 
   -- DLM
2707 
   --------------------------------------------------------------------------
2708 
   dlm_rd_o_Hi(32-1 downto 0)
2709 
      <= dlm_rd_r(32-1 downto 0) when Reg_RdMuxer_Hi(CINT_ADDR_DLM_CLASS)='1'
2710 
         else (Others=>'0');
2711 
 
2712 
   dlm_rd_o_Lo(32-1 downto 0)
2713 
      <= dlm_rd_r(32-1 downto 0) when Reg_RdMuxer_Lo(CINT_ADDR_DLM_CLASS)='1'
2714 
         else (Others=>'0');
2715 
 
2716 
 
2717 
   --------------------------------------------------------------------------
2718 
   -- System Interrupt Status
2719 
   --------------------------------------------------------------------------
2720 
   Sys_Int_Status_o_Hi(32-1 downto 0)
2721 
      <= (Sys_Int_Status_i(32-1 downto 0) and Sys_Int_Enable_i(32-1 downto 0)) when Reg_RdMuxer_Hi(CINT_ADDR_IRQ_STAT)='1'
2722 
         else (Others=>'0');
2723 
 
2724 
   Sys_Int_Enable_o_Hi(32-1 downto 0)
2725 
      <= Sys_Int_Enable_i(32-1 downto 0) when Reg_RdMuxer_Hi(CINT_ADDR_IRQ_EN)='1'
2726 
         else (Others=>'0');
2727 
 
2728 
   Sys_Int_Status_o_Lo(32-1 downto 0)
2729 
      <= (Sys_Int_Status_i(32-1 downto 0) and Sys_Int_Enable_i(32-1 downto 0)) when Reg_RdMuxer_Lo(CINT_ADDR_IRQ_STAT)='1'
2730 
         else (Others=>'0');
2731 
 
2732 
   Sys_Int_Enable_o_Lo(32-1 downto 0)
2733 
      <= Sys_Int_Enable_i(32-1 downto 0) when Reg_RdMuxer_Lo(CINT_ADDR_IRQ_EN)='1'
2734 
         else (Others=>'0');
2735 
 
2736 
 
2737 
   -- ----------------------------------------------------------------------------------
2738 
   -- ----------------------------------------------------------------------------------
2739 
   Gen_IG_Read:  if IMP_INT_GENERATOR generate
2740 
 
2741 
   --------------------------------------------------------------------------
2742 
   -- Interrupt Generator Latency
2743 
   --------------------------------------------------------------------------
2744 
   IG_Latency_o_Hi(32-1 downto 0)
2745 
      <= IG_Latency_i(32-1 downto 0) when Reg_RdMuxer_Hi(CINT_ADDR_IG_LATENCY)='1'
2746 
         else (Others=>'0');
2747 
 
2748 
   IG_Latency_o_Lo(32-1 downto 0)
2749 
      <= IG_Latency_i(32-1 downto 0) when Reg_RdMuxer_Lo(CINT_ADDR_IG_LATENCY)='1'
2750 
         else (Others=>'0');
2751 
   --------------------------------------------------------------------------
2752 
   -- Interrupt Generator Statistics
2753 
   --------------------------------------------------------------------------
2754 
   IG_Num_Assert_o_Hi(32-1 downto 0)
2755 
      <= IG_Num_Assert_i(32-1 downto 0) when Reg_RdMuxer_Hi(CINT_ADDR_IG_NUM_ASSERT)='1'
2756 
         else (Others=>'0');
2757 
 
2758 
   IG_Num_Deassert_o_Hi(32-1 downto 0)
2759 
      <= IG_Num_Deassert_i(32-1 downto 0) when Reg_RdMuxer_Hi(CINT_ADDR_IG_NUM_DEASSERT)='1'
2760 
         else (Others=>'0');
2761 
 
2762 
   IG_Num_Assert_o_Lo(32-1 downto 0)
2763 
      <= IG_Num_Assert_i(32-1 downto 0) when Reg_RdMuxer_Lo(CINT_ADDR_IG_NUM_ASSERT)='1'
2764 
         else (Others=>'0');
2765 
 
2766 
   IG_Num_Deassert_o_Lo(32-1 downto 0)
2767 
      <= IG_Num_Deassert_i(32-1 downto 0) when Reg_RdMuxer_Lo(CINT_ADDR_IG_NUM_DEASSERT)='1'
2768 
         else (Others=>'0');
2769 
 
2770 
   end generate;
2771 
 
2772 
 
2773 
   NotGen_IG_Read:  if not IMP_INT_GENERATOR generate
2774 
 
2775 
   IG_Latency_o_Hi(32-1 downto 0)      <= (Others=>'0');
2776 
   IG_Latency_o_Lo(32-1 downto 0)      <= (Others=>'0');
2777 
   IG_Num_Assert_o_Hi(32-1 downto 0)   <= (Others=>'0');
2778 
   IG_Num_Deassert_o_Hi(32-1 downto 0) <= (Others=>'0');
2779 
   IG_Num_Assert_o_Lo(32-1 downto 0)   <= (Others=>'0');
2780 
   IG_Num_Deassert_o_Lo(32-1 downto 0) <= (Others=>'0');
2781 
 
2782 
   end generate;
2783 
 
2784 
 
2785 
   --------------------------------------------------------------------------
2786 
   --  System Error
2787 
   --------------------------------------------------------------------------
2788 
   Synch_Sys_Error_i:
2789 
   process ( trn_clk, trn_lnk_up_n)
2790 
   begin
2791 
     if trn_lnk_up_n = '1' then
2792 
        Sys_Error_i                            <= (OTHERS => '0');
2793 
        eb_FIFO_OverWritten                    <= '0';
2794 
     elsif trn_clk'event and trn_clk = '1' then
2795 
        Sys_Error_i(CINT_BIT_TX_TOUT_IN_SER)   <= Tx_TimeOut;
2796 
        Sys_Error_i(CINT_BIT_EB_TOUT_IN_SER)   <= Tx_eb_TimeOut;
2797 
        Sys_Error_i(CINT_BIT_EB_OVERWRITTEN)   <= eb_FIFO_OverWritten;
2798 
        --  !!!!!!!!!!!!!! capture eb_FIFO overflow, temp cleared by MRd_Channel_Rst_i
2799 
        eb_FIFO_OverWritten      <= (not MRd_Channel_Rst_i) and (eb_FIFO_ow or eb_FIFO_OverWritten);
2800 
     end if;
2801 
   end process;
2802 
 
2803 
 
2804 
   --------------------------------------------------------------------------
2805 
   --  General Status and Control
2806 
   --------------------------------------------------------------------------
2807 
   Synch_General_Status_i:
2808 
   process ( trn_clk, trn_lnk_up_n)
2809 
   begin
2810 
     if trn_lnk_up_n = '1' then
2811 
       General_Status_i  <= (OTHERS => '0');
2812 
     elsif trn_clk'event and trn_clk = '1' then
2813 
       General_Status_i(32-1 downto 32-16)
2814 
                       <= cfg_dcommand;
2815 
       General_Status_i(CINT_BIT_LWIDTH_IN_GSR_TOP downto CINT_BIT_LWIDTH_IN_GSR_BOT)
2816 
                       <= pcie_link_width;
2817 
       General_Status_i(CINT_BIT_ICAP_BUSY_IN_GSR)
2818 
                       <= icap_Busy;
2819 
       General_Status_i(CINT_BIT_DG_AVAIL_IN_GSR)
2820 
                       <= DG_is_Available;
2821 
       General_Status_i(CINT_BIT_LINK_ACT_IN_GSR+1 downto CINT_BIT_LINK_ACT_IN_GSR)
2822 
                       <= protocol_link_act;
2823 
 
2824 
--       General_Status_i(8) <= CTL_read_counter(6-1);   ---- DEBUG !!!
2825 
     end if;
2826 
   end process;
2827 
 
2828 
 
2829 
 
2830 
   Sys_Error_o_Hi(32-1 downto 0)
2831 
      <= Sys_Error_i(32-1 downto 0) when Reg_RdMuxer_Hi(CINT_ADDR_ERROR)='1'
2832 
         else (Others=>'0');
2833 
 
2834 
   General_Status_o_Hi(32-1 downto 0)
2835 
      <= General_Status_i(32-1 downto 0) when Reg_RdMuxer_Hi(CINT_ADDR_STATUS)='1'
2836 
         else (Others=>'0');
2837 
 
2838 
   General_Control_o_Hi(32-1 downto 0)
2839 
      <= General_Control_i(32-1 downto 0) when Reg_RdMuxer_Hi(CINT_ADDR_CONTROL)='1'
2840 
         else (Others=>'0');
2841 
 
2842 
   Sys_Error_o_Lo(32-1 downto 0)
2843 
      <= Sys_Error_i(32-1 downto 0) when Reg_RdMuxer_Lo(CINT_ADDR_ERROR)='1'
2844 
         else (Others=>'0');
2845 
 
2846 
   General_Status_o_Lo(32-1 downto 0)
2847 
      <= General_Status_i(32-1 downto 0) when Reg_RdMuxer_Lo(CINT_ADDR_STATUS)='1'
2848 
         else (Others=>'0');
2849 
 
2850 
   General_Control_o_Lo(32-1 downto 0)
2851 
      <= General_Control_i(32-1 downto 0) when Reg_RdMuxer_Lo(CINT_ADDR_CONTROL)='1'
2852 
         else (Others=>'0');
2853 
 
2854 
 
2855 
   --------------------------------------------------------------------------
2856 
   -- ICAP
2857 
   --------------------------------------------------------------------------
2858 
   icap_O_o_Hi(32-1 downto 0)
2859 
      <= icap_O(32-1 downto 0) when Reg_RdMuxer_Hi(CINT_ADDR_ICAP)='1'
2860 
         else (Others=>'0');
2861 
 
2862 
   icap_O_o_Lo(32-1 downto 0)
2863 
      <= icap_O(32-1 downto 0) when Reg_RdMuxer_Lo(CINT_ADDR_ICAP)='1'
2864 
         else (Others=>'0');
2865 
 
2866 
   --------------------------------------------------------------------------
2867 
   -- FIFO Statuses (read only)
2868 
   --------------------------------------------------------------------------
2869 
   eb_FIFO_Status_o_Hi(32-1 downto 0)
2870 
      <= eb_FIFO_Status_r1(32-1 downto 0) when Reg_RdMuxer_Hi(CINT_ADDR_EB_STACON)='1'
2871 
         else (Others=>'0');
2872 
 
2873 
   eb_FIFO_Status_o_Lo(32-1 downto 0)
2874 
      <= eb_FIFO_Status_r1(32-1 downto 0) when Reg_RdMuxer_Lo(CINT_ADDR_EB_STACON)='1'
2875 
         else (Others=>'0');
2876 
 
2877 
   --------------------------------------------------------------------------
2878 
   -- Optical Link Status
2879 
   --------------------------------------------------------------------------
2880 
   Opto_Link_Status_o_Hi(32-1 downto 0)
2881 
      <= Opto_Link_Status_i(32-1 downto 0) when Reg_RdMuxer_Hi(CINT_ADDR_PROTOCOL_STACON)='1'
2882 
         else (Others=>'0');
2883 
 
2884 
   Opto_link_Status_o_Lo(32-1 downto 0)
2885 
      <= Opto_Link_Status_i(32-1 downto 0) when Reg_RdMuxer_Lo(CINT_ADDR_PROTOCOL_STACON)='1'
2886 
         else (Others=>'0');
2887 
 
2888 
   --------------------------------------------------------------------------
2889 
   -- Class CTL status
2890 
   --------------------------------------------------------------------------
2891 
   class_CTL_Status_o_Hi(32-1 downto 0)
2892 
      <= class_CTL_Status_i(32-1 downto 0) when Reg_RdMuxer_Hi(CINT_ADDR_TC_STATUS)='1'
2893 
         else (Others=>'0');
2894 
 
2895 
   class_CTL_Status_o_Lo(32-1 downto 0)
2896 
      <= class_CTL_Status_i(32-1 downto 0) when Reg_RdMuxer_Lo(CINT_ADDR_TC_STATUS)='1'
2897 
         else (Others=>'0');
2898 
 
2899 
   --------------------------------------------------------------------------
2900 
   -- Data generator Status
2901 
   --------------------------------------------------------------------------
2902 
   DG_Status_o_Hi(32-1 downto 0)
2903 
      <= DG_Status_i(32-1 downto 0) when Reg_RdMuxer_Hi(CINT_ADDR_DG_CTRL)='1'
2904 
         else (Others=>'0');
2905 
 
2906 
   DG_Status_o_Lo(32-1 downto 0)
2907 
      <= DG_Status_i(32-1 downto 0) when Reg_RdMuxer_Lo(CINT_ADDR_DG_CTRL)='1'
2908 
         else (Others=>'0');
2909 
 
2910 
   --------------------------------------------------------------------------
2911 
   -- Hardware version
2912 
   --------------------------------------------------------------------------
2913 
   HW_Version_o_Hi(32-1 downto 0)
2914 
      <= C_DESIGN_ID(32-1 downto 0) when Reg_RdMuxer_Hi(CINT_ADDR_VERSION)='1'
2915 
         else (Others=>'0');
2916 
 
2917 
   HW_Version_o_Lo(32-1 downto 0)
2918 
      <= C_DESIGN_ID(32-1 downto 0) when Reg_RdMuxer_Lo(CINT_ADDR_VERSION)='1'
2919 
         else (Others=>'0');
2920 
 
2921 
-----------------------------------------------------
2922 
-- Sequential : Regs_RdQout_i
2923 
--
2924 
   Synch_Regs_RdQout:
2925 
   process ( trn_clk, trn_lnk_up_n)
2926 
   begin
2927 
      if trn_lnk_up_n = '1' then
2928 
         Regs_RdQout_i <= (OTHERS =>'0');
2929 
 
2930 
      elsif trn_clk'event and trn_clk = '1' then
2931 
 
2932 
         Regs_RdQout_i(64-1 downto 32)        <=
2933 
                                  HW_Version_o_Hi     (32-1 downto 0)
2934 
 
2935 
                              or  Sys_Error_o_Hi      (32-1 downto 0)
2936 
                              or  General_Status_o_Hi (32-1 downto 0)
2937 
                              or  General_Control_o_Hi(32-1 downto 0)
2938 
 
2939 
                              or  Sys_Int_Status_o_Hi (32-1 downto 0)
2940 
                              or  Sys_Int_Enable_o_Hi (32-1 downto 0)
2941 
 
2942 
--                              or  DMA_us_PA_o_Hi      (C_DBUS_WIDTH-1 downto 32)
2943 
                              or  DMA_us_PA_o_Hi      (32-1   downto          0)
2944 
                              or  DMA_us_HA_o_Hi      (C_DBUS_WIDTH-1 downto 32)
2945 
                              or  DMA_us_HA_o_Hi      (32-1   downto          0)
2946 
                              or  DMA_us_BDA_o_Hi     (C_DBUS_WIDTH-1 downto 32)
2947 
                              or  DMA_us_BDA_o_Hi     (32-1   downto          0)
2948 
                              or  DMA_us_Length_o_Hi  (32-1 downto 0)
2949 
                              or  DMA_us_Control_o_Hi (32-1 downto 0)
2950 
                              or  DMA_us_Status_o_Hi  (32-1 downto 0)
2951 
                              or  DMA_us_Transf_Bytes_o_Hi  (32-1 downto 0)
2952 
 
2953 
--                              or  DMA_ds_PA_o_Hi      (C_DBUS_WIDTH-1 downto 32)
2954 
                              or  DMA_ds_PA_o_Hi      (32-1   downto          0)
2955 
                              or  DMA_ds_HA_o_Hi      (C_DBUS_WIDTH-1 downto 32)
2956 
                              or  DMA_ds_HA_o_Hi      (32-1   downto          0)
2957 
                              or  DMA_ds_BDA_o_Hi     (C_DBUS_WIDTH-1 downto 32)
2958 
                              or  DMA_ds_BDA_o_Hi     (32-1   downto          0)
2959 
                              or  DMA_ds_Length_o_Hi  (32-1 downto 0)
2960 
                              or  DMA_ds_Control_o_Hi (32-1 downto 0)
2961 
                              or  DMA_ds_Status_o_Hi  (32-1 downto 0)
2962 
                              or  DMA_ds_Transf_Bytes_o_Hi  (32-1 downto 0)
2963 
 
2964 
                              or  IG_Latency_o_Hi     (32-1 downto 0)
2965 
                              or  IG_Num_Assert_o_Hi  (32-1 downto 0)
2966 
                              or  IG_Num_Deassert_o_Hi(32-1 downto 0)
2967 
 
2968 
                              or  DG_Status_o_Hi      (32-1 downto 0)
2969 
                              or  class_CTL_Status_o_Hi  (32-1 downto 0)
2970 
 
2971 
--                              or  icap_O_o_Hi         (32-1 downto 0)
2972 
                              or  Opto_Link_Status_o_Hi (32-1 downto 0)
2973 
                              or  eb_FIFO_Status_o_Hi (32-1 downto 0)
2974 
                                                                                or  dlm_rd_o_Hi
2975 
                                                                                or  ctl_td_o_Hi
2976 
                              ;
2977 
 
2978 
 
2979 
         Regs_RdQout_i(32-1 downto 0)        <=
2980 
                                  HW_Version_o_Lo     (32-1 downto 0)
2981 
 
2982 
                              or  Sys_Error_o_Lo      (32-1 downto 0)
2983 
                              or  General_Status_o_Lo (32-1 downto 0)
2984 
                              or  General_Control_o_Lo(32-1 downto 0)
2985 
 
2986 
                              or  Sys_Int_Status_o_Lo (32-1 downto 0)
2987 
                              or  Sys_Int_Enable_o_Lo (32-1 downto 0)
2988 
 
2989 
--                              or  DMA_us_PA_o_Lo      (C_DBUS_WIDTH-1 downto 32)
2990 
                              or  DMA_us_PA_o_Lo      (32-1   downto          0)
2991 
                              or  DMA_us_HA_o_Lo      (C_DBUS_WIDTH-1 downto 32)
2992 
                              or  DMA_us_HA_o_Lo      (32-1   downto          0)
2993 
                              or  DMA_us_BDA_o_Lo     (C_DBUS_WIDTH-1 downto 32)
2994 
                              or  DMA_us_BDA_o_Lo     (32-1   downto          0)
2995 
                              or  DMA_us_Length_o_Lo  (32-1 downto 0)
2996 
                              or  DMA_us_Control_o_Lo (32-1 downto 0)
2997 
                              or  DMA_us_Status_o_Lo  (32-1 downto 0)
2998 
                              or  DMA_us_Transf_Bytes_o_Lo  (32-1 downto 0)
2999 
 
3000 
--                              or  DMA_ds_PA_o_Lo      (C_DBUS_WIDTH-1 downto 32)
3001 
                              or  DMA_ds_PA_o_Lo      (32-1   downto          0)
3002 
                              or  DMA_ds_HA_o_Lo      (C_DBUS_WIDTH-1 downto 32)
3003 
                              or  DMA_ds_HA_o_Lo      (32-1   downto          0)
3004 
                              or  DMA_ds_BDA_o_Lo     (C_DBUS_WIDTH-1 downto 32)
3005 
                              or  DMA_ds_BDA_o_Lo     (32-1   downto          0)
3006 
                              or  DMA_ds_Length_o_Lo  (32-1 downto 0)
3007 
                              or  DMA_ds_Control_o_Lo (32-1 downto 0)
3008 
                              or  DMA_ds_Status_o_Lo  (32-1 downto 0)
3009 
                              or  DMA_ds_Transf_Bytes_o_Lo  (32-1 downto 0)
3010 
 
3011 
                              or  IG_Latency_o_Lo     (32-1 downto 0)
3012 
                              or  IG_Num_Assert_o_Lo  (32-1 downto 0)
3013 
                              or  IG_Num_Deassert_o_Lo(32-1 downto 0)
3014 
 
3015 
                              or  DG_Status_o_Lo      (32-1 downto 0)
3016 
                              or  class_CTL_Status_o_Lo  (32-1 downto 0)
3017 
 
3018 
--                              or  icap_O_o_Lo(32-1 downto 0)
3019 
                              or  Opto_Link_Status_o_Lo (32-1 downto 0)
3020 
                              or  eb_FIFO_Status_o_Lo (32-1 downto 0)
3021 
                                                                                or  dlm_rd_o_Lo
3022 
                                                                                or  ctl_td_o_Lo
3023 
                              ;
3024 
 
3025 
      end if;
3026 
   end process;
3027 
 
3028 
 
3029 
-- -----------------------------------------------------------------------------
3030 
-- -- Implementation codes
3031 
-- -----------------------------------------------------------------------------
3032 
--  Gen_ICAP_width_8:
3033 
--  if C_ICAP_WIDTH=8 generate
3034 
--
3035 
--     ICAP_VIRTEX4_pcie :
3036 
--     ICAP_VIRTEX4
3037 
--       generic map (
3038 
--                    ICAP_WIDTH => "X8"    -- "X8" or "X32"
3039 
--                   )
3040 
--          port map (
3041 
--                    BUSY  => icap_BUSY ,   -- Busy output
3042 
--                    O     => icap_O    ,   -- 8-bit data output
3043 
--                    CE    => icap_CE   ,   -- Clock enable input
3044 
--                    CLK   => icap_CLK  ,   -- Clock input
3045 
--                    I     => icap_I    ,   -- 8-bit data input
3046 
--                    WRITE => icap_WRITE    -- Write input
3047 
--                   );
3048 
--
3049 
--  end generate;
3050 
--
3051 
--  Gen_ICAP_width_32:
3052 
--  if C_ICAP_WIDTH=32 generate
3053 
--
3054 
--     ICAP_VIRTEX4_pcie :
3055 
--     ICAP_VIRTEX4
3056 
--       generic map (
3057 
--                    ICAP_WIDTH => "X32"    -- "X8" or "X32"
3058 
--                   )
3059 
--          port map (
3060 
--                    BUSY  => icap_BUSY ,   -- Busy output
3061 
--                    O     => icap_O    ,   -- 32-bit data output
3062 
--                    CE    => icap_CE   ,   -- Clock enable input
3063 
--                    CLK   => icap_CLK  ,   -- Clock input
3064 
--                    I     => icap_I    ,   -- 32-bit data input
3065 
--                    WRITE => icap_WRITE    -- Write input
3066 
--                   );
3067 
--
3068 
--  end generate;
3069 
--
3070 
 
3071 
end Behavioral;

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.