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Subversion Repositories pcie_sg_dma

[/] [pcie_sg_dma/] [branches/] [Virtex6/] [ML605_ISE12.3/] [pcie_sg_dma/] [Virtex6/] [ML605/] [abb_dgen.vhd] - Blame information for rev 11

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----------------------------------------------------------------------------------
-- Company:   ziti
-- Engineer:  wgao
-- 
-- Create Date:    18:29:15 29 Jun 2009 
-- Design Name: 
-- Module Name:    abb_dgen - Behavioral 
-- Project Name: 
-- Target Devices: 
-- Tool versions: 
-- Description: 
--
-- Dependencies: 
--
-- Revision: 
-- Revision 0.01 - File Created
-- Additional Comments: 
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
 
library work;
use work.abb64Package.all;
 
---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
 
entity abb_dgen is
    port (
 
           -- Data generator table write port
           tab_sel            : IN    STD_LOGIC;
           tab_we             : IN    STD_LOGIC_VECTOR (2-1 downto 0);
           tab_wa             : IN    STD_LOGIC_VECTOR (12-1 downto 0);
           tab_wd             : IN    STD_LOGIC_VECTOR (64-1 downto 0);
 
           -- DAQ Rx
           data_rec_start     : OUT   std_logic;
           data_rec_end       : OUT   std_logic;
           data_rec           : OUT   std_logic_vector(64-1 downto 0);
           crc_error_rec      : OUT   std_logic;
           data_rec_stop      : IN    std_logic;
 
           -- CTL Rx
           ctrl_rec_start     : OUT   std_logic;
           ctrl_rec_end       : OUT   std_logic;
           ctrl_rec           : OUT   std_logic_vector(16-1 downto 0);
           ctrl_rec_stop      : IN    std_logic;
 
           -- DLM Rx
           dlm_rec_va         : OUT   std_logic;
           dlm_rec_type       : OUT   std_logic_vector(4-1 downto 0);
 
           -- status signals
           dg_running         : OUT   STD_LOGIC;
           daq_start_led      : OUT   STD_LOGIC;
 
           -- must signals
           dg_clk             : IN    STD_LOGIC;
           dg_mask            : IN    STD_LOGIC;
           dg_rst             : IN    STD_LOGIC
           );
end abb_dgen;
 
 
architecture Behavioral of abb_dgen is
 
  type DGHaltStates is           ( dgST_RESET
                                 , dgST_Run
                                 , dgST_Halt
                                 );
 
  -- State variables
  signal dg_Halt_State      : DGHaltStates;
 
  -- Data generator table, without output registering
  component v6_bram4096x64_fast
    port (
      clka           : IN  std_logic;
      addra          : IN  std_logic_vector(C_PRAM_AWIDTH-1 downto 0);
      wea            : IN  std_logic_vector(C_DBUS_WIDTH/8-1 downto 0);
      dina           : IN  std_logic_vector(C_DBUS_WIDTH-1 downto 0);
      douta          : OUT std_logic_vector(C_DBUS_WIDTH-1 downto 0);
 
      clkb           : IN  std_logic;
      addrb          : IN  std_logic_vector(C_PRAM_AWIDTH-1 downto 0);
      web            : IN  std_logic_vector(C_DBUS_WIDTH/8-1 downto 0);
      dinb           : IN  std_logic_vector(C_DBUS_WIDTH-1 downto 0);
      doutb          : OUT std_logic_vector(C_DBUS_WIDTH-1 downto 0)
    );
  end component;
 
  -- DAQ Rx
  signal  data_rec_start_i : std_logic;
  signal  data_rec_end_i   : std_logic;
  signal  data_rec_i       : std_logic_vector(64-1 downto 0);
  signal  crc_error_rec_i  : std_logic;
 
  -- CTL Rx
  signal  ctrl_rec_start_i : std_logic;
  signal  ctrl_rec_end_i   : std_logic;
  signal  ctrl_rec_i       : std_logic_vector(16-1 downto 0);
 
  -- DLM Rx
  signal  dlm_rec_va_i     : std_logic;
  signal  dlm_rec_type_i   : std_logic_vector(4-1 downto 0);
 
  -- Table signals
  signal  dg_running_i     : std_logic;
  signal  tab_travel       : std_logic;
  signal  tab_halt         : std_logic;
  signal  tab_we_padded    : std_logic_vector(C_DBUS_WIDTH/8-1 downto 0);
  signal  tab_ra           : std_logic_vector(C_PRAM_AWIDTH-1 downto 0);
  signal  tab_ra_r1        : std_logic_vector(C_PRAM_AWIDTH-1 downto 0);
  signal  tab_rb_dummy     : std_logic_vector(C_DBUS_WIDTH/8-1 downto 0);
  signal  tab_rd_dummy     : std_logic_vector(C_DBUS_WIDTH-1 downto 0);
  signal  tab_rq           : std_logic_vector(C_DBUS_WIDTH-1 downto 0);
 
  -- feature bits
  signal  tab_class_bits   : std_logic_vector(2-1 downto 0);
  signal  tab_enable_bit   : std_logic;
  signal  tab_stop_bit     : std_logic;
  signal  tab_cerr_bit     : std_logic;
  signal  tab_sop_bit      : std_logic;
  signal  tab_eop_bit      : std_logic;
 
  -- procedure control
  signal  congest_daq      : std_logic;
  signal  congest_ctl      : std_logic;
  signal  delay_time_over  : std_logic;
  signal  delay_counter    : std_logic_vector(16-1 downto 0);
  signal  dg_mask_r1       : std_logic;
  signal  dg_mask_rise     : std_logic;
 
  -- debug signal
  signal  daq_start_latch  : std_logic;
  signal  daq_start_led_i  : std_logic := '0';
  signal  cnt_daq_start    : std_logic_vector(20-1 downto 0);
 
  -- Constants
  Constant  C_CLASS_DAQ    : std_logic_vector(2-1 downto 0) := "01";
  Constant  C_CLASS_CTL    : std_logic_vector(2-1 downto 0) := "10";
  Constant  C_CLASS_DLM    : std_logic_vector(2-1 downto 0) := "11";
 
begin
 
   dg_running        <= dg_running_i;
   dg_running_i      <= tab_travel;
 
   dg_mask_rise      <= dg_mask and not dg_mask_r1;
 
   data_rec_start    <= data_rec_start_i  when dg_mask_r1='0' else '0';
   data_rec_end      <= (data_rec_end_i or dg_mask_rise)   when dg_mask_r1='0' else '0';
   data_rec          <= data_rec_i        when dg_mask_r1='0' else (OTHERS=>'0');
   crc_error_rec     <= crc_error_rec_i   when dg_mask_r1='0' else '0';
 
   ctrl_rec_start    <= ctrl_rec_start_i  when dg_mask_r1='0' else '0';
   ctrl_rec_end      <= (ctrl_rec_end_i or dg_mask_rise)   when dg_mask_r1='0' else '0';
   ctrl_rec          <= ctrl_rec_i        when dg_mask_r1='0' else (OTHERS=>'0');
 
   dlm_rec_va        <= dlm_rec_va_i      when dg_mask_r1='0' else '0';
   dlm_rec_type      <= dlm_rec_type_i    when dg_mask_r1='0' else (OTHERS=>'0');
 
 
   -- Syn. delay: dg_mask
   Delay_dg_mask:
   process ( dg_clk)
   begin
     if dg_clk'event and dg_clk = '1' then
        dg_mask_r1     <= dg_mask;
     end if;
   end process;
 
 
   -- -------------------------------------------------
   -- Debug LED
   --
   daq_start_latch   <= data_rec_start_i and not dg_mask;
   daq_start_led     <= daq_start_led_i;
 
   SynProc_DGen_Debug_LED:
   process ( dg_clk, daq_start_latch)
   begin
      if daq_start_latch='1' then
        daq_start_led_i   <=  '1';
        cnt_daq_start     <=  (OTHERS=>'0');
      elsif dg_clk'event and dg_clk = '1' then
--        if cnt_daq_start=X"0000F" then
        if cnt_daq_start=X"F0000" then
          daq_start_led_i     <=  '0';
          cnt_daq_start       <=  cnt_daq_start;
        else
          daq_start_led_i     <=  daq_start_led_i;
          cnt_daq_start       <=  cnt_daq_start + '1';
        end if;
      end if;
   end process;
 
 
   -- -------------------------------------------------
   -- Data generator table block RAM instantiate
   -- 
   dgen_RAM:
   v6_bram4096x64_fast
     port map (
         clka      =>    dg_clk  ,
         addra     =>    tab_wa  ,
         wea       =>    tab_we_padded  ,
         dina      =>    tab_wd  ,
         douta     =>    open    ,
 
         clkb      =>    dg_clk  ,
         addrb     =>    tab_ra  ,
         web       =>    tab_rb_dummy ,
         dinb      =>    tab_rd_dummy ,
         doutb     =>    tab_rq
       );
 
   tab_rb_dummy   <= (OTHERS=>'0');
   tab_rd_dummy   <= (OTHERS=>'1');
   tab_we_padded  <= (tab_we(1) & tab_we(1) & tab_we(1) & tab_we(1)
                    & tab_we(0) & tab_we(0) & tab_we(0) & tab_we(0)) when tab_sel='1'
                else (OTHERS=>'0');
 
   tab_ra  <=    tab_rq(59 downto 48) when (tab_travel='1' and delay_time_over='1' and congest_daq='0' and congest_ctl='0')
           else  tab_ra_r1;
 
   tab_class_bits <= tab_rq(61 downto 60);
   tab_enable_bit <= tab_rq(63);
   tab_stop_bit   <= tab_rq(62);
   tab_cerr_bit   <= tab_rq(18);
   tab_sop_bit    <= tab_rq(17);
   tab_eop_bit    <= tab_rq(16);
 
 
   -- table control: travel
   Syn_tab_travel:
   process ( dg_clk, dg_rst)
   begin
      if dg_rst = '1' then
         tab_travel     <= '0';
      elsif dg_clk'event and dg_clk = '1' then
         if tab_enable_bit='1' then
           tab_travel     <= '1';
         elsif tab_halt='1' then
           tab_travel     <= '0';
         else
           tab_travel     <= tab_travel;
         end if;
      end if;
   end process;
 
   -- table control: halt
   Syn_tab_halt:
   process ( dg_clk, dg_rst)
   begin
      if dg_rst = '1' then
         tab_halt        <= '1';
         dg_Halt_State   <= dgST_RESET;
      elsif dg_clk'event and dg_clk = '1' then
 
         case dg_Halt_State  is
           when dgST_RESET =>
             dg_Halt_State  <= dgST_Run;
             tab_halt       <= '0';
 
           when dgST_Run =>
             if tab_stop_bit='1' then
               dg_Halt_State  <= dgST_Halt;
               tab_halt       <= '1';
             else
               dg_Halt_State  <= dgST_Run;
               tab_halt       <= '0';
             end if;
 
           when OTHERS =>  -- dgST_Halt
             dg_Halt_State  <= dgST_Halt;
             tab_halt       <= '1';
 
         end case;
 
      end if;
   end process;
 
 
   -- table read address latch
   Syn_tab_rd_address:
   process ( dg_clk, dg_rst)
   begin
      if dg_rst = '1' then
         tab_ra_r1     <= (OTHERS=>'0');
      elsif dg_clk'event and dg_clk = '1' then
         if tab_travel='1'
            and delay_time_over='1'
            and
            (
              (congest_daq='0' and tab_class_bits=C_CLASS_DAQ)
              or
              (congest_ctl='0' and tab_class_bits=C_CLASS_CTL)
            ) then
            tab_ra_r1     <= tab_rq(59 downto 48);
         else
            tab_ra_r1     <= tab_ra_r1;
         end if;
      end if;
   end process;
 
 
   -- Delay time over
   Syn_delay_time_over:
   process ( dg_clk, dg_rst)
   begin
      if dg_rst = '1' then
         delay_time_over  <= '0';
         delay_counter    <= (OTHERS=>'0');
      elsif dg_clk'event and dg_clk = '1' then
         if delay_time_over='1' then
           if tab_rq(47 downto 32)=C_ALL_ZEROS(47 downto 32)
             or tab_stop_bit='1' then
             delay_counter    <= (OTHERS=>'0');
             delay_time_over  <= '1';
           else
             delay_counter    <= tab_rq(47 downto 32);
             delay_time_over  <= '0';
           end if;
         else
           if delay_counter=C_ALL_ZEROS(47 downto 32) then
             delay_counter    <= (OTHERS=>'0');
             delay_time_over  <= '1';
           else
             delay_counter    <= delay_counter - '1';
             delay_time_over  <= '0';
           end if;
         end if;
 
      end if;
   end process;
 
 
   -- table control: Congestion
   Syn_tab_Congest:
   process ( dg_clk, dg_rst)
   begin
      if dg_rst = '1' then
         congest_daq     <= '0';
         congest_ctl     <= '0';
      elsif dg_clk'event and dg_clk = '1' then
         if tab_class_bits=C_CLASS_DAQ and tab_eop_bit='1' and data_rec_stop='1' then
           congest_daq     <= '1';
         elsif congest_daq='1' and (tab_class_bits/=C_CLASS_DAQ or data_rec_stop='0') then
           congest_daq     <= '0';
         else
           congest_daq     <= congest_daq;
         end if;
 
         if tab_class_bits=C_CLASS_CTL and tab_eop_bit='1' and ctrl_rec_stop='1' then
           congest_ctl     <= '1';
         elsif congest_ctl='1' and (tab_class_bits/=C_CLASS_CTL or ctrl_rec_stop='0') then
           congest_ctl     <= '0';
         else
           congest_ctl     <= congest_ctl;
         end if;
      end if;
   end process;
 
 
   -- table output: daq
   Syn_tab_to_daq:
   process ( dg_clk, dg_rst)
   begin
      if dg_rst = '1' then
         data_rec_start_i <= '0';
         data_rec_end_i   <= '0';
         data_rec_i       <= (OTHERS=>'0');
         crc_error_rec_i  <= '0';
      elsif dg_clk'event and dg_clk = '1' then
         if tab_class_bits=C_CLASS_DAQ then
           if tab_halt='1' then
             data_rec_start_i <= '0';
             data_rec_end_i   <= '0';
             data_rec_i       <= (OTHERS=>'0');
             crc_error_rec_i  <= '0';
           elsif congest_daq='1' then
             data_rec_start_i <= data_rec_start_i;
             data_rec_end_i   <= data_rec_end_i;
             data_rec_i       <= data_rec_i;
             crc_error_rec_i  <= crc_error_rec_i;
           else
             data_rec_start_i <= tab_sop_bit and tab_travel and delay_time_over;
             data_rec_end_i   <= tab_eop_bit and tab_travel and delay_time_over;
             data_rec_i       <= tab_rq(16-1 downto 0)&tab_rq(16-1 downto 0)&tab_rq(16-1 downto 0)&tab_rq(16-1 downto 0);
             crc_error_rec_i  <= tab_cerr_bit and tab_travel and delay_time_over;
           end if;
         else
           data_rec_start_i <= '0';
           data_rec_end_i   <= '0';
           data_rec_i       <= (OTHERS=>'0');
           crc_error_rec_i  <= '0';
         end if;
      end if;
   end process;
 
 
   -- table output: ctl
   Syn_tab_to_ctl:
   process ( dg_clk, dg_rst)
   begin
      if dg_rst = '1' then
         ctrl_rec_start_i <= '0';
         ctrl_rec_end_i   <= '0';
         ctrl_rec_i       <= (OTHERS=>'0');
      elsif dg_clk'event and dg_clk = '1' then
         if tab_class_bits=C_CLASS_CTL then
           if tab_halt='1' then
             ctrl_rec_start_i <= '0';
             ctrl_rec_end_i   <= '0';
             ctrl_rec_i       <= (OTHERS=>'0');
           elsif congest_ctl='1' then
             ctrl_rec_start_i <= ctrl_rec_start_i;
             ctrl_rec_end_i   <= ctrl_rec_end_i;
             ctrl_rec_i       <= ctrl_rec_i;
           else
             ctrl_rec_start_i <= tab_sop_bit and tab_travel and delay_time_over;
             ctrl_rec_end_i   <= tab_eop_bit and tab_travel and delay_time_over;
             ctrl_rec_i       <= tab_rq(16-1 downto 0);
           end if;
         else
           ctrl_rec_start_i <= '0';
           ctrl_rec_end_i   <= '0';
           ctrl_rec_i       <= (OTHERS=>'0');
         end if;
      end if;
   end process;
 
 
   -- table output: dlm
   Syn_tab_to_dlm:
   process ( dg_clk, dg_rst)
   begin
      if dg_rst = '1' then
         dlm_rec_va_i     <= '0';
         dlm_rec_type_i   <= (OTHERS=>'0');
      elsif dg_clk'event and dg_clk = '1' then
         if tab_class_bits=C_CLASS_DLM then
           if tab_halt='1' then
             dlm_rec_va_i     <= '0';
             dlm_rec_type_i   <= (OTHERS=>'0');
           else
             dlm_rec_va_i     <= (tab_sop_bit or tab_eop_bit) and tab_travel and delay_time_over;
             dlm_rec_type_i   <= tab_rq(4-1 downto 0);
           end if;
         else
           dlm_rec_va_i     <= '0';
           dlm_rec_type_i   <= (OTHERS=>'0');
         end if;
      end if;
   end process;
 
 
end Behavioral;

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Subversion Repositories pcie_sg_dma

[/] [pcie_sg_dma/] [branches/] [Virtex6/] [ML605_ISE12.3/] [pcie_sg_dma/] [Virtex6/] [ML605/] [abb_dgen.vhd] - Blame information for rev 11

Line No.	Rev	Author	Line
1	11	barabba	`----------------------------------------------------------------------------------`
2			`-- Company: ziti`
3			`-- Engineer: wgao`
4			`--`
5			`-- Create Date: 18:29:15 29 Jun 2009`
6			`-- Design Name:`
7			`-- Module Name: abb_dgen - Behavioral`
8			`-- Project Name:`
9			`-- Target Devices:`
10			`-- Tool versions:`
11			`-- Description:`
12			`--`
13			`-- Dependencies:`
14			`--`
15			`-- Revision:`
16			`-- Revision 0.01 - File Created`
17			`-- Additional Comments:`
18			`--`
19			`----------------------------------------------------------------------------------`
20			`library IEEE;`
21			`use IEEE.STD_LOGIC_1164.ALL;`
22			`use IEEE.STD_LOGIC_ARITH.ALL;`
23			`use IEEE.STD_LOGIC_UNSIGNED.ALL;`
24
25			`library work;`
26			`use work.abb64Package.all;`
27
28			`---- Uncomment the following library declaration if instantiating`
29			`---- any Xilinx primitives in this code.`
30			`--library UNISIM;`
31			`--use UNISIM.VComponents.all;`
32
33			`entity abb_dgen is`
34			`port (`
35
36			`-- Data generator table write port`
37			`tab_sel : IN STD_LOGIC;`
38			`tab_we : IN STD_LOGIC_VECTOR (2-1 downto 0);`
39			`tab_wa : IN STD_LOGIC_VECTOR (12-1 downto 0);`
40			`tab_wd : IN STD_LOGIC_VECTOR (64-1 downto 0);`
41
42			`-- DAQ Rx`
43			`data_rec_start : OUT std_logic;`
44			`data_rec_end : OUT std_logic;`
45			`data_rec : OUT std_logic_vector(64-1 downto 0);`
46			`crc_error_rec : OUT std_logic;`
47			`data_rec_stop : IN std_logic;`
48
49			`-- CTL Rx`
50			`ctrl_rec_start : OUT std_logic;`
51			`ctrl_rec_end : OUT std_logic;`
52			`ctrl_rec : OUT std_logic_vector(16-1 downto 0);`
53			`ctrl_rec_stop : IN std_logic;`
54
55			`-- DLM Rx`
56			`dlm_rec_va : OUT std_logic;`
57			`dlm_rec_type : OUT std_logic_vector(4-1 downto 0);`
58
59			`-- status signals`
60			`dg_running : OUT STD_LOGIC;`
61			`daq_start_led : OUT STD_LOGIC;`
62
63			`-- must signals`
64			`dg_clk : IN STD_LOGIC;`
65			`dg_mask : IN STD_LOGIC;`
66			`dg_rst : IN STD_LOGIC`
67			`);`
68			`end abb_dgen;`
69
70
71			`architecture Behavioral of abb_dgen is`
72
73			`type DGHaltStates is ( dgST_RESET`
74			`, dgST_Run`
75			`, dgST_Halt`
76			`);`
77
78			`-- State variables`
79			`signal dg_Halt_State : DGHaltStates;`
80
81			`-- Data generator table, without output registering`
82			`component v6_bram4096x64_fast`
83			`port (`
84			`clka : IN std_logic;`
85			`addra : IN std_logic_vector(C_PRAM_AWIDTH-1 downto 0);`
86			`wea : IN std_logic_vector(C_DBUS_WIDTH/8-1 downto 0);`
87			`dina : IN std_logic_vector(C_DBUS_WIDTH-1 downto 0);`
88			`douta : OUT std_logic_vector(C_DBUS_WIDTH-1 downto 0);`
89
90			`clkb : IN std_logic;`
91			`addrb : IN std_logic_vector(C_PRAM_AWIDTH-1 downto 0);`
92			`web : IN std_logic_vector(C_DBUS_WIDTH/8-1 downto 0);`
93			`dinb : IN std_logic_vector(C_DBUS_WIDTH-1 downto 0);`
94			`doutb : OUT std_logic_vector(C_DBUS_WIDTH-1 downto 0)`
95			`);`
96			`end component;`
97
98			`-- DAQ Rx`
99			`signal data_rec_start_i : std_logic;`
100			`signal data_rec_end_i : std_logic;`
101			`signal data_rec_i : std_logic_vector(64-1 downto 0);`
102			`signal crc_error_rec_i : std_logic;`
103
104			`-- CTL Rx`
105			`signal ctrl_rec_start_i : std_logic;`
106			`signal ctrl_rec_end_i : std_logic;`
107			`signal ctrl_rec_i : std_logic_vector(16-1 downto 0);`
108
109			`-- DLM Rx`
110			`signal dlm_rec_va_i : std_logic;`
111			`signal dlm_rec_type_i : std_logic_vector(4-1 downto 0);`
112
113			`-- Table signals`
114			`signal dg_running_i : std_logic;`
115			`signal tab_travel : std_logic;`
116			`signal tab_halt : std_logic;`
117			`signal tab_we_padded : std_logic_vector(C_DBUS_WIDTH/8-1 downto 0);`
118			`signal tab_ra : std_logic_vector(C_PRAM_AWIDTH-1 downto 0);`
119			`signal tab_ra_r1 : std_logic_vector(C_PRAM_AWIDTH-1 downto 0);`
120			`signal tab_rb_dummy : std_logic_vector(C_DBUS_WIDTH/8-1 downto 0);`
121			`signal tab_rd_dummy : std_logic_vector(C_DBUS_WIDTH-1 downto 0);`
122			`signal tab_rq : std_logic_vector(C_DBUS_WIDTH-1 downto 0);`
123
124			`-- feature bits`
125			`signal tab_class_bits : std_logic_vector(2-1 downto 0);`
126			`signal tab_enable_bit : std_logic;`
127			`signal tab_stop_bit : std_logic;`
128			`signal tab_cerr_bit : std_logic;`
129			`signal tab_sop_bit : std_logic;`
130			`signal tab_eop_bit : std_logic;`
131
132			`-- procedure control`
133			`signal congest_daq : std_logic;`
134			`signal congest_ctl : std_logic;`
135			`signal delay_time_over : std_logic;`
136			`signal delay_counter : std_logic_vector(16-1 downto 0);`
137			`signal dg_mask_r1 : std_logic;`
138			`signal dg_mask_rise : std_logic;`
139
140			`-- debug signal`
141			`signal daq_start_latch : std_logic;`
142			`signal daq_start_led_i : std_logic := '0';`
143			`signal cnt_daq_start : std_logic_vector(20-1 downto 0);`
144
145			`-- Constants`
146			`Constant C_CLASS_DAQ : std_logic_vector(2-1 downto 0) := "01";`
147			`Constant C_CLASS_CTL : std_logic_vector(2-1 downto 0) := "10";`
148			`Constant C_CLASS_DLM : std_logic_vector(2-1 downto 0) := "11";`
149
150			`begin`
151
152			`dg_running <= dg_running_i;`
153			`dg_running_i <= tab_travel;`
154
155			`dg_mask_rise <= dg_mask and not dg_mask_r1;`
156
157			`data_rec_start <= data_rec_start_i when dg_mask_r1='0' else '0';`
158			`data_rec_end <= (data_rec_end_i or dg_mask_rise) when dg_mask_r1='0' else '0';`
159			`data_rec <= data_rec_i when dg_mask_r1='0' else (OTHERS=>'0');`
160			`crc_error_rec <= crc_error_rec_i when dg_mask_r1='0' else '0';`
161
162			`ctrl_rec_start <= ctrl_rec_start_i when dg_mask_r1='0' else '0';`
163			`ctrl_rec_end <= (ctrl_rec_end_i or dg_mask_rise) when dg_mask_r1='0' else '0';`
164			`ctrl_rec <= ctrl_rec_i when dg_mask_r1='0' else (OTHERS=>'0');`
165
166			`dlm_rec_va <= dlm_rec_va_i when dg_mask_r1='0' else '0';`
167			`dlm_rec_type <= dlm_rec_type_i when dg_mask_r1='0' else (OTHERS=>'0');`
168
169
170			`-- Syn. delay: dg_mask`
171			`Delay_dg_mask:`
172			`process ( dg_clk)`
173			`begin`
174			`if dg_clk'event and dg_clk = '1' then`
175			`dg_mask_r1 <= dg_mask;`
176			`end if;`
177			`end process;`
178
179
180			`-- -------------------------------------------------`
181			`-- Debug LED`
182			`--`
183			`daq_start_latch <= data_rec_start_i and not dg_mask;`
184			`daq_start_led <= daq_start_led_i;`
185
186			`SynProc_DGen_Debug_LED:`
187			`process ( dg_clk, daq_start_latch)`
188			`begin`
189			`if daq_start_latch='1' then`
190			`daq_start_led_i <= '1';`
191			`cnt_daq_start <= (OTHERS=>'0');`
192			`elsif dg_clk'event and dg_clk = '1' then`
193			`-- if cnt_daq_start=X"0000F" then`
194			`if cnt_daq_start=X"F0000" then`
195			`daq_start_led_i <= '0';`
196			`cnt_daq_start <= cnt_daq_start;`
197			`else`
198			`daq_start_led_i <= daq_start_led_i;`
199			`cnt_daq_start <= cnt_daq_start + '1';`
200			`end if;`
201			`end if;`
202			`end process;`
203
204
205			`-- -------------------------------------------------`
206			`-- Data generator table block RAM instantiate`
207			`--`
208			`dgen_RAM:`
209			`v6_bram4096x64_fast`
210			`port map (`
211			`clka => dg_clk ,`
212			`addra => tab_wa ,`
213			`wea => tab_we_padded ,`
214			`dina => tab_wd ,`
215			`douta => open ,`
216
217			`clkb => dg_clk ,`
218			`addrb => tab_ra ,`
219			`web => tab_rb_dummy ,`
220			`dinb => tab_rd_dummy ,`
221			`doutb => tab_rq`
222			`);`
223
224			`tab_rb_dummy <= (OTHERS=>'0');`
225			`tab_rd_dummy <= (OTHERS=>'1');`
226			`tab_we_padded <= (tab_we(1) & tab_we(1) & tab_we(1) & tab_we(1)`
227			`& tab_we(0) & tab_we(0) & tab_we(0) & tab_we(0)) when tab_sel='1'`
228			`else (OTHERS=>'0');`
229
230			`tab_ra <= tab_rq(59 downto 48) when (tab_travel='1' and delay_time_over='1' and congest_daq='0' and congest_ctl='0')`
231			`else tab_ra_r1;`
232
233			`tab_class_bits <= tab_rq(61 downto 60);`
234			`tab_enable_bit <= tab_rq(63);`
235			`tab_stop_bit <= tab_rq(62);`
236			`tab_cerr_bit <= tab_rq(18);`
237			`tab_sop_bit <= tab_rq(17);`
238			`tab_eop_bit <= tab_rq(16);`
239
240
241			`-- table control: travel`
242			`Syn_tab_travel:`
243			`process ( dg_clk, dg_rst)`
244			`begin`
245			`if dg_rst = '1' then`
246			`tab_travel <= '0';`
247			`elsif dg_clk'event and dg_clk = '1' then`
248			`if tab_enable_bit='1' then`
249			`tab_travel <= '1';`
250			`elsif tab_halt='1' then`
251			`tab_travel <= '0';`
252			`else`
253			`tab_travel <= tab_travel;`
254			`end if;`
255			`end if;`
256			`end process;`
257
258			`-- table control: halt`
259			`Syn_tab_halt:`
260			`process ( dg_clk, dg_rst)`
261			`begin`
262			`if dg_rst = '1' then`
263			`tab_halt <= '1';`
264			`dg_Halt_State <= dgST_RESET;`
265			`elsif dg_clk'event and dg_clk = '1' then`
266
267			`case dg_Halt_State is`
268			`when dgST_RESET =>`
269			`dg_Halt_State <= dgST_Run;`
270			`tab_halt <= '0';`
271
272			`when dgST_Run =>`
273			`if tab_stop_bit='1' then`
274			`dg_Halt_State <= dgST_Halt;`
275			`tab_halt <= '1';`
276			`else`
277			`dg_Halt_State <= dgST_Run;`
278			`tab_halt <= '0';`
279			`end if;`
280
281			`when OTHERS => -- dgST_Halt`
282			`dg_Halt_State <= dgST_Halt;`
283			`tab_halt <= '1';`
284
285			`end case;`
286
287			`end if;`
288			`end process;`
289
290
291			`-- table read address latch`
292			`Syn_tab_rd_address:`
293			`process ( dg_clk, dg_rst)`
294			`begin`
295			`if dg_rst = '1' then`
296			`tab_ra_r1 <= (OTHERS=>'0');`
297			`elsif dg_clk'event and dg_clk = '1' then`
298			`if tab_travel='1'`
299			`and delay_time_over='1'`
300			`and`
301			`(`
302			`(congest_daq='0' and tab_class_bits=C_CLASS_DAQ)`
303			`or`
304			`(congest_ctl='0' and tab_class_bits=C_CLASS_CTL)`
305			`) then`
306			`tab_ra_r1 <= tab_rq(59 downto 48);`
307			`else`
308			`tab_ra_r1 <= tab_ra_r1;`
309			`end if;`
310			`end if;`
311			`end process;`
312
313
314			`-- Delay time over`
315			`Syn_delay_time_over:`
316			`process ( dg_clk, dg_rst)`
317			`begin`
318			`if dg_rst = '1' then`
319			`delay_time_over <= '0';`
320			`delay_counter <= (OTHERS=>'0');`
321			`elsif dg_clk'event and dg_clk = '1' then`
322			`if delay_time_over='1' then`
323			`if tab_rq(47 downto 32)=C_ALL_ZEROS(47 downto 32)`
324			`or tab_stop_bit='1' then`
325			`delay_counter <= (OTHERS=>'0');`
326			`delay_time_over <= '1';`
327			`else`
328			`delay_counter <= tab_rq(47 downto 32);`
329			`delay_time_over <= '0';`
330			`end if;`
331			`else`
332			`if delay_counter=C_ALL_ZEROS(47 downto 32) then`
333			`delay_counter <= (OTHERS=>'0');`
334			`delay_time_over <= '1';`
335			`else`
336			`delay_counter <= delay_counter - '1';`
337			`delay_time_over <= '0';`
338			`end if;`
339			`end if;`
340
341			`end if;`
342			`end process;`
343
344
345			`-- table control: Congestion`
346			`Syn_tab_Congest:`
347			`process ( dg_clk, dg_rst)`
348			`begin`
349			`if dg_rst = '1' then`
350			`congest_daq <= '0';`
351			`congest_ctl <= '0';`
352			`elsif dg_clk'event and dg_clk = '1' then`
353			`if tab_class_bits=C_CLASS_DAQ and tab_eop_bit='1' and data_rec_stop='1' then`
354			`congest_daq <= '1';`
355			`elsif congest_daq='1' and (tab_class_bits/=C_CLASS_DAQ or data_rec_stop='0') then`
356			`congest_daq <= '0';`
357			`else`
358			`congest_daq <= congest_daq;`
359			`end if;`
360
361			`if tab_class_bits=C_CLASS_CTL and tab_eop_bit='1' and ctrl_rec_stop='1' then`
362			`congest_ctl <= '1';`
363			`elsif congest_ctl='1' and (tab_class_bits/=C_CLASS_CTL or ctrl_rec_stop='0') then`
364			`congest_ctl <= '0';`
365			`else`
366			`congest_ctl <= congest_ctl;`
367			`end if;`
368			`end if;`
369			`end process;`
370
371
372			`-- table output: daq`
373			`Syn_tab_to_daq:`
374			`process ( dg_clk, dg_rst)`
375			`begin`
376			`if dg_rst = '1' then`
377			`data_rec_start_i <= '0';`
378			`data_rec_end_i <= '0';`
379			`data_rec_i <= (OTHERS=>'0');`
380			`crc_error_rec_i <= '0';`
381			`elsif dg_clk'event and dg_clk = '1' then`
382			`if tab_class_bits=C_CLASS_DAQ then`
383			`if tab_halt='1' then`
384			`data_rec_start_i <= '0';`
385			`data_rec_end_i <= '0';`
386			`data_rec_i <= (OTHERS=>'0');`
387			`crc_error_rec_i <= '0';`
388			`elsif congest_daq='1' then`
389			`data_rec_start_i <= data_rec_start_i;`
390			`data_rec_end_i <= data_rec_end_i;`
391			`data_rec_i <= data_rec_i;`
392			`crc_error_rec_i <= crc_error_rec_i;`
393			`else`
394			`data_rec_start_i <= tab_sop_bit and tab_travel and delay_time_over;`
395			`data_rec_end_i <= tab_eop_bit and tab_travel and delay_time_over;`
396			`data_rec_i <= tab_rq(16-1 downto 0)&tab_rq(16-1 downto 0)&tab_rq(16-1 downto 0)&tab_rq(16-1 downto 0);`
397			`crc_error_rec_i <= tab_cerr_bit and tab_travel and delay_time_over;`
398			`end if;`
399			`else`
400			`data_rec_start_i <= '0';`
401			`data_rec_end_i <= '0';`
402			`data_rec_i <= (OTHERS=>'0');`
403			`crc_error_rec_i <= '0';`
404			`end if;`
405			`end if;`
406			`end process;`
407
408
409			`-- table output: ctl`
410			`Syn_tab_to_ctl:`
411			`process ( dg_clk, dg_rst)`
412			`begin`
413			`if dg_rst = '1' then`
414			`ctrl_rec_start_i <= '0';`
415			`ctrl_rec_end_i <= '0';`
416			`ctrl_rec_i <= (OTHERS=>'0');`
417			`elsif dg_clk'event and dg_clk = '1' then`
418			`if tab_class_bits=C_CLASS_CTL then`
419			`if tab_halt='1' then`
420			`ctrl_rec_start_i <= '0';`
421			`ctrl_rec_end_i <= '0';`
422			`ctrl_rec_i <= (OTHERS=>'0');`
423			`elsif congest_ctl='1' then`
424			`ctrl_rec_start_i <= ctrl_rec_start_i;`
425			`ctrl_rec_end_i <= ctrl_rec_end_i;`
426			`ctrl_rec_i <= ctrl_rec_i;`
427			`else`
428			`ctrl_rec_start_i <= tab_sop_bit and tab_travel and delay_time_over;`
429			`ctrl_rec_end_i <= tab_eop_bit and tab_travel and delay_time_over;`
430			`ctrl_rec_i <= tab_rq(16-1 downto 0);`
431			`end if;`
432			`else`
433			`ctrl_rec_start_i <= '0';`
434			`ctrl_rec_end_i <= '0';`
435			`ctrl_rec_i <= (OTHERS=>'0');`
436			`end if;`
437			`end if;`
438			`end process;`
439
440
441			`-- table output: dlm`
442			`Syn_tab_to_dlm:`
443			`process ( dg_clk, dg_rst)`
444			`begin`
445			`if dg_rst = '1' then`
446			`dlm_rec_va_i <= '0';`
447			`dlm_rec_type_i <= (OTHERS=>'0');`
448			`elsif dg_clk'event and dg_clk = '1' then`
449			`if tab_class_bits=C_CLASS_DLM then`
450			`if tab_halt='1' then`
451			`dlm_rec_va_i <= '0';`
452			`dlm_rec_type_i <= (OTHERS=>'0');`
453			`else`
454			`dlm_rec_va_i <= (tab_sop_bit or tab_eop_bit) and tab_travel and delay_time_over;`
455			`dlm_rec_type_i <= tab_rq(4-1 downto 0);`
456			`end if;`
457			`else`
458			`dlm_rec_va_i <= '0';`
459			`dlm_rec_type_i <= (OTHERS=>'0');`
460			`end if;`
461			`end if;`
462			`end process;`
463
464
465			`end Behavioral;`