OpenCores
URL https://opencores.org/ocsvn/pcie_sg_dma/pcie_sg_dma/trunk

Subversion Repositories pcie_sg_dma

[/] [pcie_sg_dma/] [branches/] [Virtex6/] [ML605_ISE12.3/] [pcie_sg_dma/] [Virtex6/] [ML605/] [bram_DDRs_Control.vhd] - Blame information for rev 11

Details | Compare with Previous | View Log

Line No. Rev Author Line
1 11 barabba 
----------------------------------------------------------------------------------
2 
-- Company:  ZITI
3 
-- Engineer:  wgao
4 
--
5 
-- Create Date:    12:29:46 04/15/2008
6 
-- Design Name:
7 
-- Module Name:    bram_DDRs_Control - Behavioral
8 
-- Project Name:
9 
-- Target Devices:
10 
-- Tool versions:
11 
-- Description:
12 
--
13 
-- Dependencies:
14 
--
15 
-- Revision:
16 
-- Revision 0.01 - File Created
17 
-- Additional Comments:
18 
--
19 
----------------------------------------------------------------------------------
20 
library IEEE;
21 
use IEEE.STD_LOGIC_1164.ALL;
22 
use IEEE.STD_LOGIC_ARITH.ALL;
23 
use IEEE.STD_LOGIC_UNSIGNED.ALL;
24 
 
25 
library work;
26 
use work.abb64Package.all;
27 
 
28 
---- Uncomment the following library declaration if instantiating
29 
---- any Xilinx primitives in this code.
30 
--library UNISIM;
31 
--use UNISIM.VComponents.all;
32 
 
33 
entity bram_DDRs_Control is
34 
    Generic (
35 
             C_ASYNFIFO_WIDTH  :  integer  :=  72 ;
36 
             P_SIMULATION      :  boolean  :=  TRUE
37 
            );
38 
    Port (
39 
 
40 
--           -- Pins
41 
--           DDR_CLKn                 : OUT   std_logic;
42 
--           DDR_CLK                  : OUT   std_logic;
43 
--           DDR_CKE                  : OUT   std_logic;
44 
--           DDR_CSn                  : OUT   std_logic;
45 
--           DDR_RASn                 : OUT   std_logic;
46 
--           DDR_CASn                 : OUT   std_logic;
47 
--           DDR_WEn                  : OUT   std_logic;
48 
--           DDR_BankAddr             : OUT   std_logic_vector(C_DDR_BANK_AWIDTH-1 downto 0);
49 
--           DDR_Addr                 : OUT   std_logic_vector(C_DDR_AWIDTH-1 downto 0);
50 
--           DDR_DM                   : OUT   std_logic_vector(C_DDR_DWIDTH/8-1 downto 0);
51 
--           DDR_DQ                   : INOUT std_logic_vector(C_DDR_DWIDTH-1 downto 0);
52 
--           DDR_DQS                  : INOUT std_logic_vector(C_DDR_DWIDTH/8-1 downto 0);
53 
 
54 
           -- DMA interface
55 
           DDR_wr_sof               : IN    std_logic;
56 
           DDR_wr_eof               : IN    std_logic;
57 
           DDR_wr_v                 : IN    std_logic;
58 
           DDR_wr_FA                : IN    std_logic;
59 
           DDR_wr_Shift             : IN    std_logic;
60 
           DDR_wr_Mask              : IN    std_logic_vector(2-1 downto 0);
61 
           DDR_wr_din               : IN    std_logic_vector(C_DBUS_WIDTH-1 downto 0);
62 
           DDR_wr_full              : OUT   std_logic;
63 
 
64 
           DDR_rdc_sof              : IN    std_logic;
65 
           DDR_rdc_eof              : IN    std_logic;
66 
           DDR_rdc_v                : IN    std_logic;
67 
           DDR_rdc_FA               : IN    std_logic;
68 
           DDR_rdc_Shift            : IN    std_logic;
69 
           DDR_rdc_din              : IN    std_logic_vector(C_DBUS_WIDTH-1 downto 0);
70 
           DDR_rdc_full             : OUT   std_logic;
71 
 
72 
--           DDR_rdD_sof              : OUT   std_logic;
73 
--           DDR_rdD_eof              : OUT   std_logic;
74 
--           DDR_rdDout_V             : OUT   std_logic;
75 
--           DDR_rdDout               : OUT   std_logic_vector(C_DBUS_WIDTH-1 downto 0);
76 
 
77 
           -- DDR payload FIFO Read Port
78 
           DDR_FIFO_RdEn            : IN    std_logic;
79 
           DDR_FIFO_Empty           : OUT   std_logic;
80 
           DDR_FIFO_RdQout          : OUT   std_logic_vector(C_DBUS_WIDTH-1 downto 0);
81 
 
82 
           -- Common interface
83 
           DDR_Ready                : OUT   std_logic;
84 
           DDR_blinker              : OUT   std_logic;
85 
           Sim_Zeichen              : OUT   std_logic;
86 
 
87 
           mem_clk                  : IN    std_logic;
88 
           trn_clk                  : IN    std_logic;
89 
           trn_reset_n              : IN    std_logic
90 
          );
91 
end entity bram_DDRs_Control;
92 
 
93 
 
94 
architecture Behavioral of bram_DDRs_Control is
95 
 
96 
  -- ----------------------------------------------------------------------------
97 
  --
98 
  -- ----------------------------------------------------------------------------
99 
  COMPONENT DDR_ClkGen
100 
    PORT(
101 
         ddr_Clock              : OUT   std_logic;
102 
         ddr_Clock_n            : OUT   std_logic;
103 
         ddr_Clock90            : OUT   std_logic;
104 
         ddr_Clock90_n          : OUT   std_logic;
105 
         Clk_ddr_rddata         : OUT   std_logic;
106 
         Clk_ddr_rddata_n       : OUT   std_logic;
107 
 
108 
         ddr_DCM_locked         : OUT   std_logic;
109 
 
110 
         clk_in                 : IN    std_logic;
111 
         trn_reset_n            : IN    std_logic
112 
        );
113 
  END COMPONENT;
114 
 
115 
 
116 
  -- ----------------------------------------------------------------------------
117 
  --
118 
  -- ----------------------------------------------------------------------------
119 
 
120 
  COMPONENT asyn_rw_FIFO72
121 
--    GENERIC (
122 
--             OUTPUT_REGISTERED  : BOOLEAN
123 
--            );
124 
    PORT(
125 
        wClk                    : IN     std_logic;
126 
        wEn                     : IN     std_logic;
127 
        Din                     : IN     std_logic_vector(C_ASYNFIFO_WIDTH-1 downto 0);
128 
        aFull                   : OUT    std_logic;
129 
        Full                    : OUT    std_logic;
130 
 
131 
        rClk                    : IN     std_logic;
132 
        rEn                     : IN     std_logic;
133 
        Qout                    : OUT    std_logic_vector(C_ASYNFIFO_WIDTH-1 downto 0);
134 
        aEmpty                  : OUT    std_logic;
135 
        Empty                   : OUT    std_logic;
136 
 
137 
        Rst                     : IN     std_logic
138 
        );
139 
  END COMPONENT;
140 
 
141 
 
142 
  component v6_prime_FIFO_plain
143 
      port (
144 
      wr_clk   : IN  std_logic;
145 
      wr_en    : IN  std_logic;
146 
      din      : IN  std_logic_VECTOR(C_ASYNFIFO_WIDTH-1 downto 0);
147 
      full     : OUT std_logic;
148 
      prog_full: OUT std_logic;
149 
      rd_clk   : IN  std_logic;
150 
      rd_en    : IN  std_logic;
151 
      dout     : OUT std_logic_VECTOR(C_ASYNFIFO_WIDTH-1 downto 0);
152 
      empty    : OUT std_logic;
153 
      rst      : IN  std_logic
154 
      );
155 
  end component;
156 
 
157 
--  component fifo_512x36_v4_2
158 
--    port (
159 
--    wr_clk      : IN  std_logic;
160 
--    wr_en       : IN  std_logic;
161 
--    din         : IN  std_logic_VECTOR(35 downto 0);
162 
--    prog_full   : OUT std_logic;
163 
--    full        : OUT std_logic;
164 
--
165 
--    rd_clk      : IN  std_logic;
166 
--    rd_en       : IN  std_logic;
167 
--    dout        : OUT std_logic_VECTOR(35 downto 0);
168 
--    prog_empty  : OUT std_logic;
169 
--    empty       : OUT std_logic;
170 
--
171 
--    rst         : IN  std_logic
172 
--    );
173 
--  end component;
174 
 
175 
  component fifo_512x72_v4_4
176 
    port (
177 
    wr_clk      : IN  std_logic;
178 
    wr_en       : IN  std_logic;
179 
    din         : IN  std_logic_VECTOR(C_ASYNFIFO_WIDTH-1 downto 0);
180 
    prog_full   : OUT std_logic;
181 
    full        : OUT std_logic;
182 
 
183 
    rd_clk      : IN  std_logic;
184 
    rd_en       : IN  std_logic;
185 
    dout        : OUT std_logic_VECTOR(C_ASYNFIFO_WIDTH-1 downto 0);
186 
--    prog_empty  : OUT std_logic;
187 
    empty       : OUT std_logic;
188 
 
189 
    rst         : IN  std_logic
190 
    );
191 
  end component;
192 
 
193 
 
194 
  ---- Dual-port block RAM for packets
195 
  ---    Core output registered
196 
  --
197 
--  component v5bram4096x32
198 
--    port (
199 
--      clka           : IN  std_logic;
200 
--      addra          : IN  std_logic_vector(C_PRAM_AWIDTH-1 downto 0);
201 
--      wea            : IN  std_logic_vector(0 downto 0);
202 
--      dina           : IN  std_logic_vector(C_DBUS_WIDTH-1 downto 0);
203 
--      douta          : OUT std_logic_vector(C_DBUS_WIDTH-1 downto 0);
204 
--
205 
--      clkb           : IN  std_logic;
206 
--      addrb          : IN  std_logic_vector(C_PRAM_AWIDTH-1 downto 0);
207 
--      web            : IN  std_logic_vector(0 downto 0);
208 
--      dinb           : IN  std_logic_vector(C_DBUS_WIDTH-1 downto 0);
209 
--      doutb          : OUT std_logic_vector(C_DBUS_WIDTH-1 downto 0)
210 
--    );
211 
--  end component;
212 
 
213 
  component v6_bram4096x64
214 
    port (
215 
      clka           : IN  std_logic;
216 
      addra          : IN  std_logic_vector(C_PRAM_AWIDTH-1 downto 0);
217 
      wea            : IN  std_logic_vector(7 downto 0);
218 
      dina           : IN  std_logic_vector(C_DBUS_WIDTH-1 downto 0);
219 
      douta          : OUT std_logic_vector(C_DBUS_WIDTH-1 downto 0);
220 
 
221 
      clkb           : IN  std_logic;
222 
      addrb          : IN  std_logic_vector(C_PRAM_AWIDTH-1 downto 0);
223 
      web            : IN  std_logic_vector(7 downto 0);
224 
      dinb           : IN  std_logic_vector(C_DBUS_WIDTH-1 downto 0);
225 
      doutb          : OUT std_logic_vector(C_DBUS_WIDTH-1 downto 0)
226 
    );
227 
  end component;
228 
 
229 
  -- Blinking  -_-_-_-_-_-_-_-_-_-_-_-_-_-_-
230 
  COMPONENT DDR_Blink
231 
    PORT(
232 
           DDR_Blinker              : OUT   std_logic;
233 
 
234 
           DDR_Write                : IN    std_logic;
235 
           DDR_Read                 : IN    std_logic;
236 
           DDR_Both                 : IN    std_logic;
237 
 
238 
           ddr_Clock                : IN    std_logic;
239 
           DDr_Rst_n                : IN    std_logic
240 
          );
241 
  END COMPONENT;
242 
 
243 
  -- ---------------------------------------------------------------------
244 
  signal  ddr_DCM_locked        :  std_logic;
245 
  --  -- ---------------------------------------------------------------------
246 
  signal  Rst_i                 :  std_logic;
247 
  --  -- ---------------------------------------------------------------------
248 
  signal  DDR_Ready_i           :  std_logic;
249 
  --  -- ---------------------------------------------------------------------
250 
  signal  ddr_Clock             :  std_logic;
251 
  signal  ddr_Clock_n           :  std_logic;
252 
  signal  ddr_Clock90           :  std_logic;
253 
  signal  ddr_Clock90_n         :  std_logic;
254 
 
255 
  signal  Clk_ddr_rddata        :  std_logic;
256 
  signal  Clk_ddr_rddata_n      :  std_logic;
257 
 
258 
  -- -- --  Write Pipe Channel
259 
  signal  wpipe_wEn             :  std_logic;
260 
  signal  wpipe_Din             :  std_logic_vector(C_ASYNFIFO_WIDTH-1 downto 0);
261 
  signal  wpipe_aFull           :  std_logic;
262 
  signal  wpipe_Full            :  std_logic;
263 
  --  Earlier calculate for better timing
264 
  signal  DDR_wr_Cross_Row      :  std_logic;
265 
  signal  DDR_wr_din_r1         :  std_logic_vector(C_DBUS_WIDTH-1 downto 0);
266 
  signal  DDR_write_ALC         :  std_logic_vector(11-1 downto 0);
267 
 
268 
  signal  wpipe_rEn             :  std_logic;
269 
  signal  wpipe_Qout            :  std_logic_vector(C_ASYNFIFO_WIDTH-1 downto 0);
270 
--  signal  wpipe_aEmpty          :  std_logic;
271 
  signal  wpipe_Empty           :  std_logic;
272 
  signal  wpipe_Qout_latch      :  std_logic_vector(C_ASYNFIFO_WIDTH-1 downto 0);
273 
 
274 
  -- -- --  Read Pipe Command Channel
275 
  signal  rpipec_wEn            :  std_logic;
276 
  signal  rpipec_Din            :  std_logic_vector(C_ASYNFIFO_WIDTH-1 downto 0);
277 
  signal  rpipec_aFull          :  std_logic;
278 
  signal  rpipec_Full           :  std_logic;
279 
  --  Earlier calculate for better timing
280 
  signal  DDR_rd_Cross_Row      :  std_logic;
281 
  signal  DDR_rdc_din_r1        :  std_logic_vector(C_DBUS_WIDTH-1 downto 0);
282 
  signal  DDR_read_ALC          :  std_logic_vector(11-1 downto 0);
283 
 
284 
  signal  rpipec_rEn            :  std_logic;
285 
  signal  rpipec_Qout           :  std_logic_vector(C_ASYNFIFO_WIDTH-1 downto 0);
286 
--  signal  rpipec_aEmpty         :  std_logic;
287 
  signal  rpipec_Empty          :  std_logic;
288 
 
289 
  -- -- --  Read Pipe Data Channel
290 
  signal  rpiped_wEn            :  std_logic;
291 
  signal  rpiped_Din            :  std_logic_vector(C_ASYNFIFO_WIDTH-1 downto 0);
292 
  signal  rpiped_aFull          :  std_logic;
293 
  signal  rpiped_Full           :  std_logic;
294 
 
295 
--  signal  rpiped_rEn            :  std_logic;
296 
  signal  rpiped_Qout           :  std_logic_vector(C_ASYNFIFO_WIDTH-1 downto 0);
297 
--  signal  rpiped_aEmpty         :  std_logic;
298 
--  signal  rpiped_Empty          :  std_logic;
299 
 
300 
 
301 
  --   write State machine
302 
  type bram_wrStates is          ( wrST_bram_RESET
303 
                                 , wrST_bram_IDLE
304 
--                                 , wrST_bram_Address
305 
                                 , wrST_bram_1st_Data
306 
                                 , wrST_bram_1st_Data_b2b
307 
                                 , wrST_bram_more_Data
308 
                                 , wrST_bram_last_DW
309 
                                 );
310 
 
311 
  -- State variables
312 
  signal pseudo_DDR_wr_State     : bram_wrStates;
313 
 
314 
  --       Block RAM
315 
  signal   pRAM_weA              : std_logic_vector(7 downto 0);
316 
  signal   pRAM_addrA            : std_logic_vector(C_PRAM_AWIDTH-1 downto 0);
317 
  signal   pRAM_dinA             : std_logic_vector(C_DBUS_WIDTH-1 downto 0);
318 
  signal   pRAM_doutA            : std_logic_vector(C_DBUS_WIDTH-1 downto 0);
319 
 
320 
  signal   pRAM_weB              : std_logic_vector(7 downto 0);
321 
  signal   pRAM_addrB            : std_logic_vector(C_PRAM_AWIDTH-1 downto 0);
322 
  signal   pRAM_dinB             : std_logic_vector(C_DBUS_WIDTH-1 downto 0);
323 
  signal   pRAM_doutB            : std_logic_vector(C_DBUS_WIDTH-1 downto 0);
324 
  signal   pRAM_doutB_r1         : std_logic_vector(C_DBUS_WIDTH-1 downto 0);
325 
  signal   pRAM_doutB_shifted    : std_logic_vector(C_DBUS_WIDTH-1 downto 0);
326 
 
327 
  signal   wpipe_qout_lo32b      : std_logic_vector(33-1 downto 0);
328 
  signal   wpipe_QW_Aligned      : std_logic;
329 
  signal   pRAM_AddrA_Inc        : std_logic;
330 
  signal   wpipe_read_valid      : std_logic;
331 
 
332 
 
333 
  --   read State machine
334 
  type bram_rdStates is          ( rdST_bram_RESET
335 
                                 , rdST_bram_IDLE
336 
                                 , rdST_bram_b4_LA
337 
                                 , rdST_bram_LA
338 
--                                 , rdST_bram_b4_Length
339 
--                                 , rdST_bram_Length
340 
--                                 , rdST_bram_b4_Address
341 
--                                 , rdST_bram_Address
342 
                                 , rdST_bram_Data
343 
--                                 , rdST_bram_Data_shift
344 
                                 );
345 
 
346 
  -- State variables
347 
  signal pseudo_DDR_rd_State     : bram_rdStates;
348 
 
349 
  signal rpiped_rd_counter       : std_logic_vector(10-1 downto 0);
350 
  signal rpiped_wEn_b3           : std_logic;
351 
  signal rpiped_wEn_b2           : std_logic;
352 
  signal rpiped_wEn_b1           : std_logic;
353 
  signal rpiped_wr_EOF           : std_logic;
354 
  signal rpipec_read_valid       : std_logic;
355 
  signal rpiped_wr_skew          : std_logic;
356 
  signal rpiped_wr_postpone      : std_logic;
357 
 
358 
 
359 
begin
360 
 
361 
 
362 
  Rst_i              <=  not trn_reset_n;
363 
  DDR_Ready          <=  DDR_Ready_i;
364 
 
365 
  pRAM_doutB_shifted  <= pRAM_doutB_r1(32-1 downto 0) & pRAM_doutB(64-1 downto 32);
366 
 
367 
  --  Delay
368 
  Syn_Shifting_pRAM_doutB:
369 
  process ( trn_clk)
370 
  begin
371 
     if trn_clk'event and trn_clk = '1' then
372 
        pRAM_doutB_r1 <= pRAM_doutB;
373 
     end if;
374 
  end process;
375 
 
376 
  -- -----------------------------------------------
377 
  --
378 
  Syn_DDR_CKE:
379 
  process (trn_clk, Rst_i)
380 
  begin
381 
    if Rst_i = '1' then
382 
       DDR_Ready_i       <=  '0';
383 
    elsif trn_clk'event and trn_clk = '1' then
384 
       DDR_Ready_i       <=  '1';   -- ddr_DCM_locked;
385 
    end if;
386 
  end process;
387 
 
388 
  -- ----------------------------------------------------------------------------
389 
  --
390 
  -- ----------------------------------------------------------------------------
391 
--  DDR_Clock_Generator:
392 
--  DDR_ClkGen
393 
--  PORT MAP(
394 
--           ddr_Clock            =>  ddr_Clock             , -- OUT   std_logic;
395 
--           ddr_Clock_n          =>  ddr_Clock_n           , -- OUT   std_logic;
396 
--           ddr_Clock90          =>  ddr_Clock90           , -- OUT   std_logic;
397 
--           ddr_Clock90_n        =>  ddr_Clock90_n         , -- OUT   std_logic;
398 
--           Clk_ddr_rddata       =>  Clk_ddr_rddata        , -- OUT   std_logic;
399 
--           Clk_ddr_rddata_n     =>  Clk_ddr_rddata_n      , -- OUT   std_logic;
400 
--           ddr_DCM_locked       =>  ddr_DCM_locked        , -- OUT   std_logic;
401 
--
402 
--           clk_in               =>  mem_clk               , -- IN    std_logic;
403 
--           trn_reset_n          =>  trn_reset_n             -- IN    std_logic
404 
--          );
405 
 
406 
 
407 
  -- ----------------------------------------------------------------------------
408 
  --
409 
  -- ----------------------------------------------------------------------------
410 
--  DDR_pipe_write_fifo:
411 
--  asyn_rw_FIFO
412 
--  GENERIC MAP (
413 
--               OUTPUT_REGISTERED    => TRUE
414 
--              )
415 
--  PORT MAP(
416 
--           wClk          =>  trn_clk         ,
417 
--           wEn           =>  wpipe_wEn       ,
418 
--           Din           =>  wpipe_Din       ,
419 
--           aFull         =>  wpipe_aFull     ,
420 
--           Full          =>  wpipe_Full      ,
421 
--
422 
--           rClk          =>  ddr_Clock       ,  -- ddr_Clock_n     ,
423 
--           rEn           =>  wpipe_rEn       ,
424 
--           Qout          =>  wpipe_Qout      ,
425 
--           aEmpty        =>  wpipe_aEmpty    ,
426 
--           Empty         =>  wpipe_Empty     ,
427 
--
428 
--           Rst           =>  Rst_i
429 
--          );
430 
 
431 
--  DDR_pipe_write_fifo:
432 
--  asyn_rw_FIFO72
433 
--  PORT MAP(
434 
--           wClk          =>  trn_clk       ,
435 
--           wEn           =>  wpipe_wEn     ,
436 
--           Din           =>  wpipe_Din     ,
437 
--           aFull         =>  wpipe_aFull   ,
438 
--           Full          =>  open          ,
439 
--
440 
--           rClk          =>  ddr_Clock     ,
441 
--           rEn           =>  wpipe_rEn     ,
442 
--           Qout          =>  wpipe_Qout    ,
443 
--           aEmpty        =>  open          ,
444 
--           Empty         =>  wpipe_Empty   ,
445 
--
446 
--           Rst           =>  Rst_i
447 
--          );
448 
 
449 
  DDR_pipe_write_fifo:
450 
  v6_prime_FIFO_plain
451 
  PORT MAP(
452 
    wr_clk       =>  trn_clk      , -- IN  std_logic;
453 
    wr_en        =>  wpipe_wEn    , -- IN  std_logic;
454 
    din          =>  wpipe_Din    , -- IN  std_logic_VECTOR(35 downto 0);
455 
    prog_full    =>  wpipe_aFull  , -- OUT std_logic;
456 
    full         =>  wpipe_Full   , -- OUT std_logic;
457 
 
458 
    rd_clk       =>  trn_clk    , -- IN  std_logic;
459 
    rd_en        =>  wpipe_rEn    , -- IN  std_logic;
460 
    dout         =>  wpipe_Qout   , -- OUT std_logic_VECTOR(35 downto 0);
461 
    empty        =>  wpipe_Empty  , -- OUT std_logic;
462 
 
463 
    rst          =>  Rst_i          -- IN  std_logic
464 
    );
465 
 
466 
 
467 
  wpipe_wEn              <=  DDR_wr_v;
468 
  wpipe_Din              <=  DDR_wr_Mask & DDR_wr_Shift & '0' & DDR_wr_sof & DDR_wr_eof & DDR_wr_Cross_Row & DDR_wr_FA & DDR_wr_din;
469 
  DDR_wr_full            <=  wpipe_aFull;
470 
  Sim_Zeichen            <=  wpipe_Empty;
471 
 
472 
 
473 
  Syn_DDR_wrD_Cross_Row:
474 
  process (trn_clk)
475 
  begin
476 
    if trn_clk'event and trn_clk = '1' then
477 
       DDR_wr_din_r1(64-1 downto 10)     <= (OTHERS=>'0');
478 
       DDR_wr_din_r1( 9 downto  0)     <= DDR_wr_din(9 downto  0) - "100";
479 
    end if;
480 
  end process;
481 
 
482 
  DDR_write_ALC      <= (DDR_wr_din_r1(10 downto 2) &"00") + ('0' & DDR_wr_din(9 downto 2) &"00");
483 
  DDR_wr_Cross_Row   <= '0';   -- DDR_write_ALC(10);
484 
 
485 
  -- ----------------------------------------------------------------------------
486 
  --
487 
  -- ----------------------------------------------------------------------------
488 
 
489 
--  DDR_pipe_read_C_fifo:
490 
--  asyn_rw_FIFO
491 
--  GENERIC MAP (
492 
--               OUTPUT_REGISTERED    => TRUE
493 
--              )
494 
--  PORT MAP(
495 
--           wClk          =>  trn_clk         ,
496 
--           wEn           =>  rpipec_wEn      ,
497 
--           Din           =>  rpipec_Din      ,
498 
--           aFull         =>  rpipec_aFull    ,
499 
--           Full          =>  rpipec_Full     ,
500 
--
501 
--           rClk          =>  ddr_Clock       ,  -- ddr_Clock_n     ,
502 
--           rEn           =>  rpipec_rEn      ,
503 
--           Qout          =>  rpipec_Qout     ,
504 
--           aEmpty        =>  rpipec_aEmpty   ,
505 
--           Empty         =>  rpipec_Empty    ,
506 
--
507 
--           Rst           =>  Rst_i
508 
--          );
509 
--
510 
 
511 
--  DDR_pipe_read_C_fifo:
512 
--  asyn_rw_FIFO72
513 
--  PORT MAP(
514 
--           wClk          =>  trn_clk       ,
515 
--           wEn           =>  rpipec_wEn     ,
516 
--           Din           =>  rpipec_Din     ,
517 
--           aFull         =>  rpipec_aFull   ,
518 
--           Full          =>  open          ,
519 
--
520 
--           rClk          =>  ddr_Clock     ,
521 
--           rEn           =>  rpipec_rEn     ,
522 
--           Qout          =>  rpipec_Qout    ,
523 
--           aEmpty        =>  open          ,
524 
--           Empty         =>  rpipec_Empty   ,
525 
--
526 
--           Rst           =>  Rst_i
527 
--          );
528 
 
529 
  DDR_pipe_read_C_fifo:
530 
  v6_prime_FIFO_plain
531 
  PORT MAP(
532 
    wr_clk       =>  trn_clk        , -- IN  std_logic;
533 
    wr_en        =>  rpipec_wEn     , -- IN  std_logic;
534 
    din          =>  rpipec_Din     , -- IN  std_logic_VECTOR(35 downto 0);
535 
    prog_full    =>  rpipec_aFull   , -- OUT std_logic;
536 
    full         =>  open,   --rpipec_Full    , -- OUT std_logic;
537 
 
538 
    rd_clk       =>  trn_clk      , -- IN  std_logic;
539 
    rd_en        =>  rpipec_rEn     , -- IN  std_logic;
540 
    dout         =>  rpipec_Qout    , -- OUT std_logic_VECTOR(35 downto 0);
541 
    empty        =>  rpipec_Empty   , -- OUT std_logic;
542 
 
543 
    rst          =>  Rst_i            -- IN  std_logic
544 
    );
545 
 
546 
 
547 
  rpipec_wEn             <=  DDR_rdc_v;
548 
  rpipec_Din             <=  "00" & DDR_rdc_Shift & '0' & DDR_rdc_sof & DDR_rdc_eof & DDR_rd_Cross_Row & DDR_rdc_FA & DDR_rdc_din;
549 
  DDR_rdc_full           <=  rpipec_aFull;
550 
 
551 
 
552 
  Syn_DDR_rdC_Cross_Row:
553 
  process (trn_clk)
554 
  begin
555 
    if trn_clk'event and trn_clk = '1' then
556 
       DDR_rdc_din_r1(64-1 downto 10)   <= (OTHERS=>'0');
557 
       DDR_rdc_din_r1( 9 downto  0)     <= DDR_rdc_din(9 downto  0) - "100";
558 
    end if;
559 
  end process;
560 
 
561 
  DDR_read_ALC       <= (DDR_rdc_din_r1(10 downto 2) &"00") + ('0' & DDR_rdc_din(9 downto 2) &"00");
562 
  DDR_rd_Cross_Row   <= '0';   -- DDR_read_ALC(10);
563 
 
564 
  -- ----------------------------------------------------------------------------
565 
  --
566 
  -- ----------------------------------------------------------------------------
567 
--  DDR_pipe_read_D_fifo:
568 
--  asyn_rw_FIFO
569 
--  GENERIC MAP (
570 
--               OUTPUT_REGISTERED    => TRUE
571 
--              )
572 
--  PORT MAP(
573 
--           wClk          =>  ddr_Clock,       -- Clk_ddr_rddata  ,  -- ddr_Clock       ,  -- ddr_Clock_n     ,
574 
--           wEn           =>  rpiped_wEn      ,
575 
--           Din           =>  rpiped_Din      ,
576 
--           aFull         =>  rpiped_aFull    ,
577 
--           Full          =>  rpiped_Full     ,
578 
--
579 
--           rClk          =>  trn_clk         ,
580 
--           rEn           =>  DDR_FIFO_RdEn   ,  -- rpiped_rEn      ,
581 
--           Qout          =>  rpiped_Qout     ,
582 
--           aEmpty        =>  open            ,  -- rpiped_aEmpty   ,
583 
--           Empty         =>  DDR_FIFO_Empty  ,  -- rpiped_Empty    ,
584 
--
585 
--           Rst           =>  Rst_i
586 
--          );
587 
 
588 
--  DDR_pipe_read_D_fifo:
589 
--  asyn_rw_FIFO72
590 
--  PORT MAP(
591 
--           wClk          =>  ddr_Clock       ,
592 
--           wEn           =>  rpiped_wEn     ,
593 
--           Din           =>  rpiped_Din     ,
594 
--           aFull         =>  rpiped_aFull   ,
595 
--           Full          =>  open          ,
596 
--
597 
--           rClk          =>  trn_clk     ,
598 
--           rEn           =>  DDR_FIFO_RdEn     ,
599 
--           Qout          =>  rpiped_Qout    ,
600 
--           aEmpty        =>  open          ,
601 
--           Empty         =>  DDR_FIFO_Empty   ,
602 
--
603 
--           Rst           =>  Rst_i
604 
--          );
605 
 
606 
  DDR_pipe_read_D_fifo:
607 
  v6_prime_FIFO_plain
608 
  PORT MAP(
609 
    wr_clk       =>  trn_clk      , -- IN  std_logic;
610 
    wr_en        =>  rpiped_wEn      , -- IN  std_logic;
611 
    din          =>  rpiped_Din      , -- IN  std_logic_VECTOR(35 downto 0);
612 
    prog_full    =>  rpiped_aFull    , -- OUT std_logic;
613 
    full         =>  open,    -- rpiped_Full     , -- OUT std_logic;
614 
 
615 
    rd_clk       =>  trn_clk         , -- IN  std_logic;
616 
    rd_en        =>  DDR_FIFO_RdEn   , -- IN  std_logic;
617 
    dout         =>  rpiped_Qout     , -- OUT std_logic_VECTOR(35 downto 0);
618 
    empty        =>  DDR_FIFO_Empty  , -- OUT std_logic;
619 
 
620 
    rst          =>  Rst_i             -- IN  std_logic
621 
    );
622 
 
623 
 
624 
    DDR_FIFO_RdQout      <=  rpiped_Qout(C_DBUS_WIDTH-1 downto 0);
625 
 
626 
 
627 
 
628 
    -- -------------------------------------------------
629 
    -- pkt_RAM instantiate
630 
    --
631 
    pkt_RAM:
632 
    v6_bram4096x64
633 
      port map (
634 
         clka      =>    trn_clk  ,
635 
         addra     =>    pRAM_addrA ,
636 
         wea       =>    pRAM_weA   ,
637 
         dina      =>    pRAM_dinA  ,
638 
         douta     =>    pRAM_doutA ,
639 
 
640 
         clkb      =>    trn_clk  ,
641 
         addrb     =>    pRAM_addrB ,
642 
         web       =>    pRAM_weB   ,
643 
         dinb      =>    pRAM_dinB  ,
644 
         doutb     =>    pRAM_doutB
645 
       );
646 
 
647 
    pRAM_weB       <= X"00";
648 
    pRAM_dinB      <= (Others =>'0');
649 
 
650 
 
651 
-- ------------------------------------------------
652 
-- write States synchronous
653 
--
654 
   Syn_Pseudo_DDR_wr_States:
655 
   process ( trn_clk, trn_reset_n)
656 
   begin
657 
      if trn_reset_n = '0' then
658 
         pseudo_DDR_wr_State   <= wrST_bram_RESET;
659 
         pRAM_addrA            <= (OTHERS=>'1');
660 
         pRAM_weA              <= (OTHERS=>'0');
661 
         pRAM_dinA             <= (OTHERS=>'0');
662 
         wpipe_qout_lo32b      <= (OTHERS=>'0');
663 
         wpipe_QW_Aligned      <= '1';
664 
         pRAM_AddrA_Inc        <= '1';
665 
 
666 
      elsif trn_clk'event and trn_clk = '1' then
667 
 
668 
        case pseudo_DDR_wr_State  is
669 
 
670 
          when wrST_bram_RESET =>
671 
             pseudo_DDR_wr_State   <= wrST_bram_IDLE;
672 
             pRAM_addrA            <= (OTHERS=>'1');
673 
             wpipe_QW_Aligned      <= '1';
674 
             wpipe_qout_lo32b      <= (OTHERS=>'0');
675 
             pRAM_weA              <= (OTHERS=>'0');
676 
             pRAM_dinA             <= (OTHERS=>'0');
677 
             pRAM_AddrA_Inc        <= '1';
678 
 
679 
          when wrST_bram_IDLE =>
680 
             pRAM_addrA            <= wpipe_Qout(14 downto 3);
681 
             pRAM_AddrA_Inc        <= wpipe_Qout(2);
682 
             wpipe_QW_Aligned      <= not wpipe_Qout(69);
683 
             wpipe_qout_lo32b      <= (32=>'1', OTHERS=>'0');
684 
             pRAM_weA              <= (OTHERS=>'0');
685 
             pRAM_dinA             <= pRAM_dinA;
686 
             if wpipe_read_valid = '1' then
687 
               pseudo_DDR_wr_State   <= wrST_bram_1st_Data;  -- wrST_bram_Address;
688 
             else
689 
               pseudo_DDR_wr_State   <= wrST_bram_IDLE;
690 
             end if;
691 
 
692 
 
693 
          when wrST_bram_1st_Data =>
694 
             pRAM_addrA          <= pRAM_addrA;
695 
             if wpipe_read_valid = '0' then
696 
               pseudo_DDR_wr_State <= wrST_bram_1st_Data;
697 
               pRAM_weA            <= (OTHERS=>'0'); --pRAM_weA;
698 
               pRAM_dinA           <= pRAM_dinA;
699 
             elsif wpipe_Qout(66)='1' then   -- eof
700 
                if wpipe_QW_Aligned='1' then
701 
                  pseudo_DDR_wr_State <= wrST_bram_IDLE;
702 
                  pRAM_weA            <= not ( wpipe_Qout(71) & wpipe_Qout(71) & wpipe_Qout(71) & wpipe_Qout(71)
703 
                                             & wpipe_Qout(70) & wpipe_Qout(70) & wpipe_Qout(70) & wpipe_Qout(70)
704 
                                             );
705 
                  pRAM_dinA           <= wpipe_Qout(C_DBUS_WIDTH-1 downto 0);
706 
                elsif wpipe_Qout(70)='1' then     -- mask(0)
707 
                  pseudo_DDR_wr_State <= wrST_bram_IDLE;
708 
                  pRAM_weA            <= not ( wpipe_qout_lo32b(32) & wpipe_qout_lo32b(32) & wpipe_qout_lo32b(32) & wpipe_qout_lo32b(32)
709 
                                             & wpipe_Qout(71) & wpipe_Qout(71) & wpipe_Qout(71) & wpipe_Qout(71)
710 
                                             );
711 
                  pRAM_dinA           <= wpipe_qout_lo32b(32-1 downto 0) & wpipe_Qout(C_DBUS_WIDTH-1 downto 32);
712 
                elsif wpipe_Qout(71)='1' then     -- mask(1)
713 
                  pseudo_DDR_wr_State <= wrST_bram_IDLE;
714 
                  pRAM_weA            <= X"F0";
715 
                  pRAM_dinA           <= wpipe_Qout(C_DBUS_WIDTH-1-32 downto 0) & X"00000000";
716 
                else
717 
                  pseudo_DDR_wr_State <= wrST_bram_last_DW;
718 
                  pRAM_weA            <= not ( wpipe_qout_lo32b(32) & wpipe_qout_lo32b(32) & wpipe_qout_lo32b(32) & wpipe_qout_lo32b(32)
719 
                                             & wpipe_Qout(71) & wpipe_Qout(71) & wpipe_Qout(71) & wpipe_Qout(71)
720 
                                             );
721 
                  pRAM_dinA           <= wpipe_qout_lo32b(32-1 downto 0) & wpipe_Qout(C_DBUS_WIDTH-1 downto 32);
722 
                  wpipe_qout_lo32b    <= '0' & wpipe_Qout(32-1 downto 0);
723 
                end if;
724 
             else
725 
                if wpipe_QW_Aligned='1' then
726 
                  pseudo_DDR_wr_State <= wrST_bram_more_Data;
727 
                  pRAM_weA            <= not ( wpipe_Qout(71) & wpipe_Qout(71) & wpipe_Qout(71) & wpipe_Qout(71)
728 
                                             & wpipe_Qout(70) & wpipe_Qout(70) & wpipe_Qout(70) & wpipe_Qout(70)
729 
                                             );
730 
                  pRAM_dinA           <= wpipe_Qout(C_DBUS_WIDTH-1 downto 0);
731 
                elsif pRAM_AddrA_Inc='1' then
732 
                  pseudo_DDR_wr_State <= wrST_bram_more_Data;
733 
                  pRAM_weA            <= not ( wpipe_qout_lo32b(32) & wpipe_qout_lo32b(32) & wpipe_qout_lo32b(32) & wpipe_qout_lo32b(32)
734 
                                             & wpipe_Qout(71) & wpipe_Qout(71) & wpipe_Qout(71) & wpipe_Qout(71)
735 
                                             );
736 
                  pRAM_dinA           <= wpipe_qout_lo32b(32-1 downto 0) & wpipe_Qout(C_DBUS_WIDTH-1 downto 32);
737 
                  wpipe_qout_lo32b    <= '0' & wpipe_Qout(32-1 downto 0);
738 
                else
739 
                  pseudo_DDR_wr_State <= wrST_bram_1st_Data;
740 
                  pRAM_AddrA_Inc      <= '1';
741 
                  pRAM_weA            <= X"00";
742 
                  pRAM_dinA           <= pRAM_dinA;
743 
                  wpipe_qout_lo32b    <= wpipe_Qout(70) & wpipe_Qout(32-1 downto 0);
744 
                end if;
745 
             end if;
746 
 
747 
          when wrST_bram_more_Data =>
748 
             if wpipe_read_valid = '0' then
749 
               pseudo_DDR_wr_State <= wrST_bram_more_Data;  -- wrST_bram_1st_Data;
750 
               pRAM_weA            <= (OTHERS=>'0'); --pRAM_weA;
751 
               pRAM_addrA          <= pRAM_addrA;
752 
               pRAM_dinA           <= pRAM_dinA;
753 
             elsif wpipe_Qout(66)='1' then   -- eof
754 
                if wpipe_QW_Aligned='1' then
755 
                  pseudo_DDR_wr_State <= wrST_bram_IDLE;
756 
                  pRAM_weA            <= not ( wpipe_Qout(71) & wpipe_Qout(71) & wpipe_Qout(71) & wpipe_Qout(71)
757 
                                             & wpipe_Qout(70) & wpipe_Qout(70) & wpipe_Qout(70) & wpipe_Qout(70)
758 
                                             );
759 
                  pRAM_addrA          <= pRAM_addrA + '1';
760 
                  pRAM_dinA           <= wpipe_Qout(C_DBUS_WIDTH-1 downto 0);
761 
                elsif wpipe_Qout(70)='1' then  -- mask(0)
762 
                  pseudo_DDR_wr_State <= wrST_bram_IDLE;
763 
                  pRAM_weA            <= not ( wpipe_qout_lo32b(32) & wpipe_qout_lo32b(32) & wpipe_qout_lo32b(32) & wpipe_qout_lo32b(32)
764 
                                             & wpipe_Qout(71) & wpipe_Qout(71) & wpipe_Qout(71) & wpipe_Qout(71)
765 
                                             );
766 
                  pRAM_addrA          <= pRAM_addrA + '1';
767 
                  pRAM_dinA           <= wpipe_qout_lo32b(32-1 downto 0) & wpipe_Qout(C_DBUS_WIDTH-1 downto 32);
768 
                else
769 
                  pseudo_DDR_wr_State <= wrST_bram_last_DW;
770 
                  pRAM_weA            <= not ( wpipe_qout_lo32b(32) & wpipe_qout_lo32b(32) & wpipe_qout_lo32b(32) & wpipe_qout_lo32b(32)
771 
                                             & wpipe_Qout(71) & wpipe_Qout(71) & wpipe_Qout(71) & wpipe_Qout(71)
772 
                                             );
773 
                  pRAM_addrA          <= pRAM_addrA + '1';
774 
                  pRAM_dinA           <= wpipe_qout_lo32b(32-1 downto 0) & wpipe_Qout(C_DBUS_WIDTH-1 downto 32);
775 
                  wpipe_qout_lo32b    <= '0' & wpipe_Qout(32-1 downto 0);
776 
                end if;
777 
             else
778 
                if wpipe_QW_Aligned='1' then
779 
                  pseudo_DDR_wr_State <= wrST_bram_more_Data;
780 
                  pRAM_weA            <= not ( wpipe_Qout(71) & wpipe_Qout(71) & wpipe_Qout(71) & wpipe_Qout(71)
781 
                                             & wpipe_Qout(70) & wpipe_Qout(70) & wpipe_Qout(70) & wpipe_Qout(70)
782 
                                             );
783 
                  pRAM_addrA          <= pRAM_addrA + '1';
784 
                  pRAM_dinA           <= wpipe_Qout(C_DBUS_WIDTH-1 downto 0);
785 
                else
786 
                  pseudo_DDR_wr_State <= wrST_bram_more_Data;
787 
                  pRAM_weA            <= not ( wpipe_qout_lo32b(32) & wpipe_qout_lo32b(32) & wpipe_qout_lo32b(32) & wpipe_qout_lo32b(32)
788 
                                             & wpipe_Qout(71) & wpipe_Qout(71) & wpipe_Qout(71) & wpipe_Qout(71)
789 
                                             );
790 
                  pRAM_addrA          <= pRAM_addrA + '1';
791 
                  pRAM_dinA           <= wpipe_qout_lo32b(32-1 downto 0) & wpipe_Qout(C_DBUS_WIDTH-1 downto 32);
792 
                  wpipe_qout_lo32b    <= '0' & wpipe_Qout(32-1 downto 0);
793 
                end if;
794 
             end if;
795 
 
796 
 
797 
          when wrST_bram_last_DW =>
798 
--             pseudo_DDR_wr_State   <= wrST_bram_IDLE;
799 
             pRAM_weA              <= X"F0";
800 
             pRAM_addrA            <= pRAM_addrA + '1';
801 
             pRAM_dinA             <= wpipe_qout_lo32b(32-1 downto 0) & X"00000000";
802 
             if wpipe_read_valid = '1' then
803 
               pseudo_DDR_wr_State         <= wrST_bram_1st_Data_b2b;  -- wrST_bram_Address;
804 
               wpipe_Qout_latch            <= wpipe_Qout;
805 
             else
806 
               pseudo_DDR_wr_State         <= wrST_bram_IDLE;
807 
               wpipe_Qout_latch            <= wpipe_Qout;
808 
             end if;
809 
 
810 
 
811 
          when wrST_bram_1st_Data_b2b =>
812 
             pRAM_addrA            <= wpipe_Qout_latch(14 downto 3);
813 
             wpipe_QW_Aligned      <= not wpipe_Qout_latch(69);
814 
             if wpipe_read_valid = '0' then
815 
               pseudo_DDR_wr_State <= wrST_bram_1st_Data;
816 
               pRAM_weA            <= (OTHERS=>'0'); --pRAM_weA;
817 
               pRAM_dinA           <= pRAM_dinA;
818 
               pRAM_AddrA_Inc      <= wpipe_Qout_latch(2);
819 
               wpipe_qout_lo32b    <= (32=>'1', OTHERS=>'0');
820 
             elsif wpipe_Qout(66)='1' then   -- eof
821 
                if wpipe_Qout_latch(69)='0' then   -- wpipe_QW_Aligned
822 
                  pseudo_DDR_wr_State <= wrST_bram_IDLE;
823 
                  pRAM_weA            <= not ( wpipe_Qout(71) & wpipe_Qout(71) & wpipe_Qout(71) & wpipe_Qout(71)
824 
                                             & wpipe_Qout(70) & wpipe_Qout(70) & wpipe_Qout(70) & wpipe_Qout(70)
825 
                                             );
826 
                  pRAM_dinA           <= wpipe_Qout(C_DBUS_WIDTH-1 downto 0);
827 
                  pRAM_AddrA_Inc      <= wpipe_Qout_latch(2);
828 
                  wpipe_qout_lo32b    <= (32=>'1', OTHERS=>'0');
829 
                elsif wpipe_Qout(70)='1' then     -- mask(0)
830 
                  pseudo_DDR_wr_State <= wrST_bram_IDLE;
831 
                  pRAM_weA            <= not ( X"f"
832 
                                             & wpipe_Qout(71) & wpipe_Qout(71) & wpipe_Qout(71) & wpipe_Qout(71)
833 
                                             );
834 
                  pRAM_dinA           <= X"00000000" & wpipe_Qout(C_DBUS_WIDTH-1 downto 32);
835 
                  pRAM_AddrA_Inc      <= wpipe_Qout_latch(2);
836 
                  wpipe_qout_lo32b    <= (32=>'1', OTHERS=>'0');
837 
                elsif wpipe_Qout(71)='1' then     -- mask(1)
838 
                  pseudo_DDR_wr_State <= wrST_bram_IDLE;
839 
                  pRAM_weA            <= X"F0";
840 
                  pRAM_dinA           <= wpipe_Qout(C_DBUS_WIDTH-1-32 downto 0) & X"00000000";
841 
                  pRAM_AddrA_Inc      <= wpipe_Qout_latch(2);
842 
                  wpipe_qout_lo32b    <= (32=>'1', OTHERS=>'0');
843 
                else
844 
                  pseudo_DDR_wr_State <= wrST_bram_last_DW;
845 
                  pRAM_weA            <= not ( X"f"
846 
                                             & wpipe_Qout(71) & wpipe_Qout(71) & wpipe_Qout(71) & wpipe_Qout(71)
847 
                                             );
848 
                  pRAM_dinA           <= X"00000000" & wpipe_Qout(C_DBUS_WIDTH-1 downto 32);
849 
                  pRAM_AddrA_Inc      <= wpipe_Qout_latch(2);
850 
                  wpipe_qout_lo32b    <= '0' & wpipe_Qout(32-1 downto 0);
851 
                end if;
852 
             else
853 
                if wpipe_Qout_latch(69)='0' then    -- wpipe_QW_Aligned
854 
                  pseudo_DDR_wr_State <= wrST_bram_more_Data;
855 
                  pRAM_weA            <= not ( wpipe_Qout(71) & wpipe_Qout(71) & wpipe_Qout(71) & wpipe_Qout(71)
856 
                                             & wpipe_Qout(70) & wpipe_Qout(70) & wpipe_Qout(70) & wpipe_Qout(70)
857 
                                             );
858 
                  pRAM_dinA           <= wpipe_Qout(C_DBUS_WIDTH-1 downto 0);
859 
                  pRAM_AddrA_Inc      <= wpipe_Qout_latch(2);
860 
                  wpipe_qout_lo32b    <= (32=>'1', OTHERS=>'0');
861 
                elsif wpipe_Qout_latch(2)='1' then   -- pRAM_AddrA_Inc
862 
                  pseudo_DDR_wr_State <= wrST_bram_more_Data;
863 
                  pRAM_weA            <= not ( X"f"
864 
                                             & wpipe_Qout(71) & wpipe_Qout(71) & wpipe_Qout(71) & wpipe_Qout(71)
865 
                                             );
866 
                  pRAM_dinA           <= X"00000000" & wpipe_Qout(C_DBUS_WIDTH-1 downto 32);
867 
                  pRAM_AddrA_Inc      <= wpipe_Qout_latch(2);
868 
                  wpipe_qout_lo32b    <= '0' & wpipe_Qout(32-1 downto 0);
869 
                else
870 
                  pseudo_DDR_wr_State <= wrST_bram_1st_Data;
871 
                  pRAM_AddrA_Inc      <= '1';
872 
                  pRAM_weA            <= X"00";
873 
                  pRAM_dinA           <= pRAM_dinA;
874 
                  wpipe_qout_lo32b    <= wpipe_Qout(70) & wpipe_Qout(32-1 downto 0);
875 
                end if;
876 
             end if;
877 
 
878 
 
879 
          when OTHERS =>
880 
             pseudo_DDR_wr_State   <= wrST_bram_RESET;
881 
             pRAM_addrA            <= (OTHERS=>'1');
882 
             pRAM_weA              <= (OTHERS=>'0');
883 
             pRAM_dinA             <= (OTHERS=>'0');
884 
             wpipe_qout_lo32b      <= (OTHERS=>'0');
885 
             wpipe_QW_Aligned      <= '1';
886 
             pRAM_AddrA_Inc        <= '1';
887 
 
888 
        end case;
889 
 
890 
      end if;
891 
   end process;
892 
 
893 
 
894 
   --
895 
   Syn_wPipe_read:
896 
   process ( trn_clk, DDR_Ready_i)
897 
   begin
898 
      if DDR_Ready_i = '0' then
899 
         wpipe_rEn         <= '0';
900 
         wpipe_read_valid  <= '0';
901 
 
902 
      elsif trn_clk'event and trn_clk = '1' then
903 
 
904 
         wpipe_rEn         <= '1';
905 
         wpipe_read_valid  <= wpipe_rEn and not wpipe_Empty;
906 
 
907 
      end if;
908 
   end process;
909 
 
910 
 
911 
 
912 
   --
913 
   Syn_rPipeC_read:
914 
   process ( trn_clk, DDR_Ready_i)
915 
   begin
916 
      if DDR_Ready_i = '0' then
917 
         rpipec_read_valid    <= '0';
918 
         rpiped_wr_postpone   <= '0';
919 
         rpiped_wr_skew       <= '0';
920 
 
921 
      elsif trn_clk'event and trn_clk = '1' then
922 
 
923 
         rpipec_read_valid  <= rpipec_rEn and not rpipec_Empty;
924 
         if rpipec_read_valid='1' then
925 
            rpiped_wr_postpone  <= rpipec_Qout(2) and not rpipec_Qout(69);
926 
            rpiped_wr_skew      <= rpipec_Qout(69) xor rpipec_Qout(2);
927 
         else
928 
            rpiped_wr_postpone  <= rpiped_wr_postpone;
929 
            rpiped_wr_skew      <= rpiped_wr_skew;
930 
         end if;
931 
 
932 
      end if;
933 
   end process;
934 
 
935 
-- ------------------------------------------------
936 
-- Read States synchronous
937 
--
938 
   Syn_Pseudo_DDR_rd_States:
939 
   process ( trn_clk, DDR_Ready_i)
940 
   begin
941 
      if DDR_Ready_i = '0' then
942 
         pseudo_DDR_rd_State   <= rdST_bram_RESET;
943 
         rpipec_rEn            <= '0';
944 
         pRAM_addrB            <= (OTHERS=>'1');
945 
         rpiped_rd_counter     <= (OTHERS=>'0');
946 
         rpiped_wEn_b3         <= '0';
947 
         rpiped_wr_EOF         <= '0';
948 
 
949 
      elsif trn_clk'event and trn_clk = '1' then
950 
 
951 
        case pseudo_DDR_rd_State  is
952 
 
953 
          when rdST_bram_RESET =>
954 
             pseudo_DDR_rd_State   <= rdST_bram_IDLE;
955 
             rpipec_rEn            <= '0';
956 
             pRAM_addrB            <= (OTHERS=>'1');
957 
             rpiped_rd_counter     <= (OTHERS=>'0');
958 
             rpiped_wEn_b3         <= '0';
959 
             rpiped_wr_EOF         <= '0';
960 
 
961 
          when rdST_bram_IDLE =>
962 
             pRAM_addrB            <= pRAM_addrB;
963 
             rpiped_rd_counter     <= (OTHERS=>'0');
964 
             rpiped_wEn_b3         <= '0';
965 
             rpiped_wr_EOF         <= '0';
966 
             if rpipec_Empty = '0' then
967 
               rpipec_rEn          <= '1';
968 
               pseudo_DDR_rd_State <= rdST_bram_b4_LA;  --rdST_bram_b4_Length;
969 
             else
970 
               rpipec_rEn          <= '0';
971 
               pseudo_DDR_rd_State <= rdST_bram_IDLE;
972 
             end if;
973 
 
974 
          when rdST_bram_b4_LA =>
975 
             pRAM_addrB            <= pRAM_addrB;
976 
             rpiped_rd_counter     <= (OTHERS=>'0');
977 
             rpiped_wEn_b3         <= '0';
978 
             rpiped_wr_EOF         <= '0';
979 
             rpipec_rEn            <= '0';
980 
             pseudo_DDR_rd_State   <= rdST_bram_LA;
981 
 
982 
          when rdST_bram_LA =>
983 
             rpipec_rEn            <= '0';
984 
             pRAM_addrB            <= rpipec_Qout(14 downto 3);
985 
             rpiped_wr_EOF         <= '0';
986 
             rpiped_wEn_b3         <= '0';
987 
             if rpipec_Qout(2+32)='1' then
988 
               rpiped_rd_counter     <= rpipec_Qout(11+32 downto 2+32) + '1';
989 
             elsif rpipec_Qout(2)='1' and rpipec_Qout(69)='1' then
990 
               rpiped_rd_counter     <= rpipec_Qout(11+32 downto 2+32) + "10";
991 
             elsif rpipec_Qout(2)='0' and rpipec_Qout(69)='1' then
992 
               rpiped_rd_counter     <= rpipec_Qout(11+32 downto 2+32) + "10";
993 
             elsif rpipec_Qout(2)='1' and rpipec_Qout(69)='0' then
994 
               rpiped_rd_counter     <= rpipec_Qout(11+32 downto 2+32);
995 
             else
996 
               rpiped_rd_counter     <= rpipec_Qout(11+32 downto 2+32);
997 
             end if;
998 
 
999 
--             elsif rpipec_Qout(2)='1' then
1000 
--               rpiped_rd_counter     <= rpipec_Qout(11+32 downto 2+32) + "10";
1001 
--             elsif rpipec_Qout(69)='1' then
1002 
--               rpiped_rd_counter     <= rpipec_Qout(11+32 downto 2+32) + "10";
1003 
--             else
1004 
--               rpiped_rd_counter     <= rpipec_Qout(11+32 downto 2+32);
1005 
--             end if;
1006 
             pseudo_DDR_rd_State   <= rdST_bram_Data;
1007 
 
1008 
 
1009 
          when rdST_bram_Data =>
1010 
             rpipec_rEn            <= '0';
1011 
             if rpiped_rd_counter = CONV_STD_LOGIC_VECTOR(2, 10) then
1012 
               pRAM_addrB            <= pRAM_addrB + '1';
1013 
               rpiped_rd_counter     <= rpiped_rd_counter;
1014 
               rpiped_wEn_b3         <= '1';
1015 
               rpiped_wr_EOF         <= '1';
1016 
               pseudo_DDR_rd_State   <= rdST_bram_IDLE;
1017 
             elsif rpiped_aFull = '1' then
1018 
               pRAM_addrB            <= pRAM_addrB;
1019 
               rpiped_rd_counter     <= rpiped_rd_counter;
1020 
               rpiped_wEn_b3         <= '0';
1021 
               rpiped_wr_EOF         <= '0';
1022 
               pseudo_DDR_rd_State   <= rdST_bram_Data;
1023 
             else
1024 
               pRAM_addrB            <= pRAM_addrB + '1';
1025 
               rpiped_rd_counter     <= rpiped_rd_counter - "10";
1026 
               rpiped_wEn_b3         <= '1';
1027 
               rpiped_wr_EOF         <= '0';
1028 
               pseudo_DDR_rd_State   <= rdST_bram_Data;
1029 
             end if;
1030 
 
1031 
 
1032 
          when OTHERS =>
1033 
               rpipec_rEn            <= '0';
1034 
               pRAM_addrB            <= pRAM_addrB;
1035 
               rpiped_rd_counter     <= rpiped_rd_counter;
1036 
               rpiped_wEn_b3         <= '0';
1037 
               rpiped_wr_EOF         <= '0';
1038 
               pseudo_DDR_rd_State   <= rdST_bram_RESET;
1039 
 
1040 
        end case;
1041 
 
1042 
      end if;
1043 
   end process;
1044 
 
1045 
 
1046 
 
1047 
   Syn_Pseudo_DDR_rdd_write:
1048 
   process ( trn_clk, DDR_Ready_i)
1049 
   begin
1050 
      if DDR_Ready_i = '0' then
1051 
         rpiped_wEn_b1      <= '0';
1052 
         rpiped_wEn_b2      <= '0';
1053 
         rpiped_wEn         <= '0';
1054 
         rpiped_Din         <= (OTHERS=>'0');
1055 
 
1056 
      elsif trn_clk'event and trn_clk = '1' then
1057 
 
1058 
         rpiped_wEn_b2      <= rpiped_wEn_b3;
1059 
         rpiped_wEn_b1      <= rpiped_wEn_b2;
1060 
         if rpiped_wr_skew='1' then
1061 
--           rpiped_wEn         <= rpiped_wEn_b2;
1062 
           rpiped_wEn         <= (rpiped_wEn_b2 and not rpiped_wr_postpone)
1063 
                              or (rpiped_wEn_b1 and rpiped_wr_postpone);
1064 
           rpiped_Din         <= "0000" & '0' & rpiped_wr_EOF & "00" & pRAM_doutB_shifted;
1065 
         else
1066 
--           rpiped_wEn         <= rpiped_wEn_b2;
1067 
           rpiped_wEn         <= (rpiped_wEn_b2 and not rpiped_wr_postpone)
1068 
                              or (rpiped_wEn_b1 and rpiped_wr_postpone);
1069 
           rpiped_Din         <= "0000" & '0' & rpiped_wr_EOF & "00" & pRAM_doutB;
1070 
         end if;
1071 
 
1072 
      end if;
1073 
   end process;
1074 
 
1075 
 
1076 
  --
1077 
  DDR_Blinker_Module:
1078 
  DDR_Blink
1079 
  PORT MAP(
1080 
           DDR_Blinker          =>  DDR_Blinker    ,
1081 
 
1082 
           DDR_Write            =>  wpipe_rEn      ,
1083 
           DDR_Read             =>  rpiped_wEn     ,
1084 
           DDR_Both             =>  '0'            ,
1085 
 
1086 
           ddr_Clock            =>  trn_clk      ,
1087 
           DDr_Rst_n            =>  DDR_Ready_i      -- DDR_CKE_i
1088 
          );
1089 
 
1090 
 
1091 
end architecture Behavioral;

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.