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Subversion Repositories pcie_sg_dma

[/] [pcie_sg_dma/] [branches/] [Virtex6/] [ML605_ISE12.3/] [pcie_sg_dma/] [Virtex6/] [ML605/] [class_ctl.vhd] - Blame information for rev 11

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----------------------------------------------------------------------------------
-- Company:   ziti
-- Engineer:  wgao
-- 
-- Create Date:    17:01:32 19 Jun 2009
-- Design Name: 
-- Module Name:    class_ctl - Behavioral 
-- Project Name: 
-- Target Devices: 
-- Tool versions: 
-- Description: 
--
-- Dependencies: 
--
-- Revision: 
-- Revision 0.01 - File Created
-- Additional Comments: 
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
 
library work;
use work.abb64Package.all;
 
---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
 
entity class_ctl is
--    Generic (
--             C_PRO_DAQ_WIDTH  :  integer  :=  16 ;
--             C_PRO_DLM_WIDTH  :  integer  :=   4 ;
--             C_PRO_CTL_WIDTH  :  integer  :=  16
--            );
    Port (
 
           -- CTL Tx
           ctrl2send_start          : OUT   std_logic;
           ctrl2send_end            : OUT   std_logic;
           ctrl2send                : OUT   std_logic_vector(16-1 downto 0);
           ctrl2send_stop           : IN    std_logic;
 
           -- CTL Rx
           ctrl_rec_start           : IN    std_logic;
           ctrl_rec_end             : IN    std_logic;
           ctrl_rec                 : IN    std_logic_vector(16-1 downto 0);
           ctrl_rec_stop            : OUT   std_logic;
 
           -- Common signals
           link_active              : IN    std_logic_vector(2-1 downto 0);
           link_tx_clk              : IN    std_logic;
           link_rx_clk              : IN    std_logic;
 
           -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
 
           -- Fabric side: CTL Rx
           ctl_rv                   : IN    std_logic;
           ctl_rd                   : IN    std_logic_vector(C_DBUS_WIDTH/2-1 downto 0);
           ctl_rstop                : OUT   std_logic;
 
           -- Fabric side: CTL Tx
           ctl_ttake                : IN    std_logic;
           ctl_tv                   : OUT   std_logic;
           ctl_td                   : OUT   std_logic_vector(C_DBUS_WIDTH/2-1 downto 0);
           ctl_tstop                : IN    std_logic;
 
           -- Interrupter trigger
           CTL_irq                  : OUT   std_logic;
           ctl_status               : OUT   std_logic_vector(C_DBUS_WIDTH/2-1 downto 0);
 
           -- Fabric side: Common signals
           trn_clk                  : IN    std_logic;
           protocol_rst             : IN    std_logic
 
          );
end entity class_ctl;
 
 
architecture Behavioral of class_ctl is
 
  -- Standard synchronous FIFO
  component sfifo_256x36
    port (
          wr_en     : IN  std_logic;
          din       : IN  std_logic_VECTOR(36-1 downto 0);
          prog_full : OUT std_logic;
          full      : OUT std_logic;
 
          rd_en     : IN  std_logic;
          dout      : OUT std_logic_VECTOR(36-1 downto 0);
          empty     : OUT std_logic;
          prog_empty: OUT std_logic;
 
          clk       : IN  std_logic;
          rst       : IN  std_logic
          );
  end component;
 
  -- Standard asynchronous FIFO
  component v6_afifo_256x36
    port (
          wr_clk    : IN  std_logic;
          wr_en     : IN  std_logic;
          din       : IN  std_logic_VECTOR(36-1 downto 0);
          prog_full : OUT std_logic;
          full      : OUT std_logic;
 
          rd_clk    : IN  std_logic;
          rd_en     : IN  std_logic;
          dout      : OUT std_logic_VECTOR(36-1 downto 0);
          empty     : OUT std_logic;
          prog_empty: OUT std_logic;
 
          rst       : IN  std_logic
          );
  end component;
 
  -- FWFT synchronous FIFO
  component sfifo_256x36c_fwft
    port (
          wr_en     : IN  std_logic;
          din       : IN  std_logic_VECTOR(36-1 downto 0);
          prog_full : OUT std_logic;
          full      : OUT std_logic;
 
          rd_en     : IN  std_logic;
          dout      : OUT std_logic_VECTOR(36-1 downto 0);
          empty     : OUT std_logic;
          prog_empty: OUT std_logic;
 
          data_count: OUT std_logic_vector (9-1 downto 0);
 
          clk       : IN  std_logic;
          rst       : IN  std_logic
          );
  end component;
 
  -- FWFT asynchronous FIFO
  component v6_afifo_256x36c_fwft
    port (
          wr_clk        : IN  std_logic;
          wr_en         : IN  std_logic;
          din           : IN  std_logic_VECTOR(36-1 downto 0);
          prog_full     : OUT std_logic;
          full          : OUT std_logic;
 
          rd_clk        : IN  std_logic;
          rd_en         : IN  std_logic;
          dout          : OUT std_logic_VECTOR(36-1 downto 0);
          empty         : OUT std_logic;
          prog_empty    : OUT std_logic;
 
          rd_data_count : OUT std_logic_vector (9-1 downto 0);
 
          rst       : IN  std_logic
          );
  end component;
 
  -- Packet counter
  component v6_pkt_counter_1024
  port (
        wr_clk      : IN  std_logic;
        wr_en       : IN  std_logic;
        din         : IN  std_logic_VECTOR(0 downto 0);
        prog_full   : OUT std_logic;
        full        : OUT std_logic;
 
        rd_clk      : IN  std_logic;
        rd_en       : IN  std_logic;
        dout        : OUT std_logic_VECTOR(0 downto 0);
        empty       : OUT std_logic;
        prog_empty  : OUT std_logic;
 
        rst         : IN  std_logic
        );
  end component;
 
  -- Interrupter trigger
  signal  ctl_reset                : std_logic;
  signal  CTL_irq_i                : std_logic;
  signal  ctl_status_i             : std_logic_vector(C_DBUS_WIDTH/2-1 downto 0);
 
  -- Fabric side: CTL Tx       
  signal  ctl_tv_i                 : std_logic;
  signal  ctl_td_i                 : std_logic_vector(C_DBUS_WIDTH/2-1 downto 0);
  signal  ctl_rstop_i              : std_logic;
 
  -- protocol side: CTL Send   
  signal  ctrl2send_start_i        : std_logic;
  signal  ctrl2send_end_i          : std_logic;
  signal  ctrl2send_i              : std_logic_vector(16-1 downto 0);
  signal  ctrl_rec_stop_i          : std_logic;
 
  signal  ctl_down_buf_rden        : std_logic;
  signal  ctl_down_buf_dout        : std_logic_vector(36-1 downto 0);
  signal  ctl_down_buf_empty       : std_logic;
  signal  ctl_down_buf_afull       : std_logic;
 
  signal  ctl_rd_padded            : std_logic_vector(36-1 downto 0);
  signal  ctl_down_buf_rd_valid    : std_logic :='0';
  signal  ctl_down_buf_read_gap    : std_logic;
  signal  ctl_down_buf_eop         : std_logic;
  signal  ctl_down_buf_eop_r1      : std_logic :='0';
 
  signal  ctrl2send_stop_r1        : std_logic :='0';
  signal  ctl_down_buf_frame_rd    : std_logic :='0';
  signal  ctl_down_buf_stop_read   : std_logic;
  signal  pc_ctl_down_push         : std_logic;
  signal  pc_ctl_down_pop          : std_logic;
  signal  no_pkts_in_ctl_down_buf  : std_logic;
  signal  no_pkts_in_ctl_down_buf_r1: std_logic :='0';
 
  signal  ctl_up_buf_wren          : std_logic;
  signal  ctl_up_buf_din           : std_logic_vector(36-1 downto 0);
  signal  ctl_up_buf_din_b1        : std_logic_vector(36-1 downto 0);
  signal  ctl_up_buf_afull         : std_logic;
 
  signal  ctl_up_buf_re            : std_logic;
  signal  ctl_up_buf_dout          : std_logic_vector(36-1 downto 0);
  signal  ctl_up_buf_empty         : std_logic;
  signal  ctl_up_buf_dc_wire       : std_logic_vector (9-1 downto 0);
  signal  ctl_up_buf_dc_r1         : std_logic_vector (9-1 downto 0);
  signal  ctl_up_buf_dc_plus_r1    : std_logic_vector (9-1 downto 0);
  signal  ctl_up_buf_dc_i          : std_logic_vector (9-1 downto 0);
  signal  ctl_up_is_writing        : std_logic;
  signal  ctl_up_is_writing_r1     : std_logic;
 
  signal  ctl_up_buf_rd_valid      : std_logic;
  signal  pc_ctl_up_push           : std_logic;
  signal  pc_ctl_up_pop            : std_logic;
  signal  no_pkts_in_ctl_up_buf    : std_logic;
  signal  no_pkts_in_ctl_up_buf_r1 : std_logic;
 
begin
 
 
  -- Fabric side: CTL Tx
  ctl_tv             <=  ctl_tv_i      ;
  ctl_td             <=  ctl_td_i      ;
 
  ctl_rstop          <=  ctl_rstop_i   ;
 
 
  -- protocol side: CTL Send
  ctrl2send_start    <=  ctrl2send_start_i  ;
  ctrl2send_end      <=  ctrl2send_end_i    ;
  ctrl2send          <=  ctrl2send_i        ;
 
  ctrl_rec_stop      <=  ctrl_rec_stop_i    ;
  ctrl_rec_stop_i    <=  ctl_up_buf_afull;
 
  ctl_rstop_i        <=  ctl_down_buf_afull;
 
  ctl_status         <=  ctl_status_i       ;
 
  CTL_irq            <=  CTL_irq_i          ;
  CTL_irq_i          <=  not ctl_up_buf_empty   ;
 
  ctl_status_i       <=  X"000" & '0' & '0' & ctl_down_buf_afull & ctl_up_buf_empty
                     &   X"0" & '0' & '0' & ctl_up_buf_dc_i & no_pkts_in_ctl_up_buf_r1;
 
 
  -- ------------------------------------------------------------------------------
  -- 
  -- ------------------------------------------------------------------------------
  Synch_Local_Reset:
  process (trn_clk )
  begin
    if trn_clk'event and trn_clk = '1' then
      ctl_reset       <= protocol_rst;
    end if;
  end process;
 
  -- ------------------------------------------------------------------------------
  --   CTL buffer from the host
  -- ------------------------------------------------------------------------------
  ctl_buf_downstream:
  v6_afifo_256x36
  port map (
            wr_clk     => trn_clk            ,  -- IN  std_logic;
            wr_en      => ctl_rv             ,  -- IN  std_logic;
            din        => ctl_rd_padded      ,  -- IN  std_logic_VECTOR(35 downto 0);
            prog_full  => ctl_down_buf_afull ,  -- ctl_rstop_i        ,  -- OUT std_logic;
            full       => open               ,  -- OUT std_logic;
 
            rd_clk     => link_tx_clk        ,  -- IN  std_logic;
            rd_en      => ctl_down_buf_rden  ,  -- IN  std_logic;
            dout       => ctl_down_buf_dout  ,  -- OUT std_logic_VECTOR(35 downto 0);
            prog_empty => open               ,  -- OUT std_logic;
            empty      => ctl_down_buf_empty ,  -- OUT std_logic;
 
            rst        => ctl_reset             -- IN  std_logic
           );
 
  ctl_rd_padded           <= "0000" & ctl_rd;
  ctl_down_buf_eop        <= ctl_down_buf_dout(16);
  ctl_down_buf_read_gap   <= ctl_down_buf_eop and not ctl_down_buf_eop_r1;
  ctl_down_buf_rden       <= ctl_down_buf_frame_rd and not ctl_down_buf_read_gap;
 
 
  -- Packet counter: ABB -> ROC
  pc_ctl_buf_downstream:
  v6_pkt_counter_1024
  port map (
        wr_clk      => trn_clk           , -- IN  std_logic;
        wr_en       => pc_ctl_down_push  , -- IN  std_logic;
        din         => "1"               , -- IN  std_logic_VECTOR(0 downto 0);
        prog_full   => open              , -- OUT std_logic;
        full        => open              , -- OUT std_logic;
 
        rd_clk      => link_tx_clk       , -- IN  std_logic;
        rd_en       => pc_ctl_down_pop   , -- IN  std_logic;
        dout        => open              , -- OUT std_logic_VECTOR(0 downto 0);
        empty       => no_pkts_in_ctl_down_buf  , -- OUT std_logic;
        prog_empty  => open              , -- OUT std_logic;
 
        rst         => ctl_reset           -- IN  std_logic
        );
 
 
  Syn_pc_ctl_down_push:
  process (trn_clk, ctl_reset )
  begin
    if ctl_reset = '1' then
      pc_ctl_down_push  <= '0';
    elsif trn_clk'event and trn_clk = '1' then
      pc_ctl_down_push  <= ctl_rv and ctl_rd(16);
    end if;
  end process;
 
  Syn_pc_ctl_down_pop:
  process (link_tx_clk, ctl_reset )
  begin
    if ctl_reset = '1' then
      pc_ctl_down_pop   <= '0';
    elsif link_tx_clk'event and link_tx_clk = '1' then
      pc_ctl_down_pop   <= ctl_down_buf_rd_valid and ctl_down_buf_eop;
    end if;
  end process;
 
  ---------------------------------------------------
  -- Downstream CTL buffer read and packets number
  --  bit[17] : sof
  --  bit[16] : eof
  -- 
  Delay_CTL_downstream_frame:
  process (link_tx_clk )
  begin
    if link_tx_clk'event and link_tx_clk = '1' then
 
        no_pkts_in_ctl_down_buf_r1 <= no_pkts_in_ctl_down_buf;
        ctrl2send_stop_r1        <= ctrl2send_stop;
        ctl_down_buf_rd_valid    <= ctl_down_buf_rden and not ctl_down_buf_empty;
        ctl_down_buf_eop_r1      <= ctl_down_buf_eop;
        ctl_down_buf_frame_rd    <=  not no_pkts_in_ctl_down_buf_r1
                                 and not ctl_down_buf_read_gap
                                 and not ctl_down_buf_stop_read
                                 ;
    end if;
  end process;
 
  -- 
  Syn_rden_CTL_downstream_buf:
  process (link_tx_clk, ctl_reset )
  begin
    if ctl_reset = '1' then
        ctl_down_buf_stop_read   <= '0';
    elsif link_tx_clk'event and link_tx_clk = '1' then
        if ctl_down_buf_read_gap='1' and ctrl2send_stop_r1='1' then
           ctl_down_buf_stop_read   <= '1';
        elsif ctl_down_buf_stop_read='0' and ctrl2send_stop_r1='1' then
           ctl_down_buf_stop_read   <= '0';
        else
           ctl_down_buf_stop_read   <= ctrl2send_stop_r1;
        end if;
    end if;
  end process;
 
  ctrl2send_start_i  <= ctl_down_buf_dout(17);
  ctrl2send_end_i    <= ctl_down_buf_eop and not ctl_down_buf_eop_r1;
  ctrl2send_i        <= ctl_down_buf_dout(16-1 downto 0);
 
 
  -- ------------------------------------------------------------------------------
  --   CTL buffer to the host
  -- ------------------------------------------------------------------------------
  ctl_buf_upstream:
  v6_afifo_256x36c_fwft
  port map (
            wr_clk        => link_rx_clk         ,  -- IN  std_logic;
            wr_en         => ctl_up_buf_wren     ,  -- IN  std_logic;
            din           => ctl_up_buf_din      ,  -- IN  std_logic_VECTOR(35 downto 0);
            prog_full     => ctl_up_buf_afull    ,  -- ctrl_rec_stop_i  ,  -- OUT std_logic;
            full          => open                ,  -- OUT std_logic;
 
            rd_clk        => trn_clk            ,  -- IN  std_logic;
            rd_en         => ctl_up_buf_re      ,  -- IN  std_logic;
            dout          => ctl_up_buf_dout    ,  -- OUT std_logic_VECTOR(35 downto 0);
            prog_empty    => open               ,  -- OUT std_logic;
            empty         => ctl_up_buf_empty   ,  -- OUT std_logic;
 
            rd_data_count => ctl_up_buf_dc_wire ,  -- OUT std_logic_vector (9-1 downto 0 ); 
 
            rst           => ctl_reset             -- IN  std_logic
           );
 
  ctl_up_buf_re          <= ctl_ttake;
  ctl_up_buf_rd_valid    <= ctl_up_buf_re and not ctl_up_buf_empty;
 
 
  -- Special data count for FWFT FIFO
  Syn_up_fifo_fwft_dc:
  process (trn_clk, ctl_reset )
  begin
    if ctl_reset = '1' then
      ctl_up_buf_dc_i        <= (OTHERS=>'0');
      ctl_up_buf_dc_r1       <= (OTHERS=>'0');
      ctl_up_buf_dc_plus_r1  <= (OTHERS=>'0');
    elsif trn_clk'event and trn_clk = '1' then
      ctl_up_buf_dc_r1       <= ctl_up_buf_dc_wire;
      ctl_up_buf_dc_plus_r1  <= ctl_up_buf_dc_wire + "10";
      if ctl_up_buf_empty='1' then
         ctl_up_buf_dc_i        <= ctl_up_buf_dc_r1;
      else
         ctl_up_buf_dc_i        <= ctl_up_buf_dc_plus_r1;
      end if;
    end if;
  end process;
 
  -- Packet counter: ROC -> ABB
  pc_ctl_buf_upstream:
  v6_pkt_counter_1024
  port map (
        wr_clk      => link_rx_clk     , -- IN  std_logic;
        wr_en       => pc_ctl_up_push  , -- IN  std_logic;
        din         => "1"             , -- IN  std_logic_VECTOR(0 downto 0);
        prog_full   => open            , -- OUT std_logic;
        full        => open            , -- OUT std_logic;
 
        rd_clk      => trn_clk         , -- IN  std_logic;
        rd_en       => pc_ctl_up_pop   , -- IN  std_logic;
        dout        => open            , -- OUT std_logic_VECTOR(0 downto 0);
        empty       => no_pkts_in_ctl_up_buf  , -- OUT std_logic;
        prog_empty  => open            , -- OUT std_logic;
 
        rst         => ctl_reset      -- IN  std_logic
        );
 
 
  Syn_pc_ctl_up_push:
  process (link_rx_clk, ctl_reset )
  begin
    if ctl_reset = '1' then
      pc_ctl_up_push    <= '0';
    elsif link_rx_clk'event and link_rx_clk = '1' then
      pc_ctl_up_push    <= ctl_up_buf_wren and ctl_up_buf_din(16);
    end if;
  end process;
 
  Syn_pc_ctl_up_pop:
  process (trn_clk, ctl_reset )
  begin
    if ctl_reset = '1' then
      pc_ctl_up_pop     <= '0';
      no_pkts_in_ctl_up_buf_r1  <= '1';
    elsif trn_clk'event and trn_clk = '1' then
      pc_ctl_up_pop     <= ctl_up_buf_rd_valid and ctl_up_buf_dout(16);
      no_pkts_in_ctl_up_buf_r1  <= no_pkts_in_ctl_up_buf;
    end if;
  end process;
 
  -- CTL direction: upstream
  --     protocol side
  Transfer_CTL_upstream_protocol:
  process (link_rx_clk, ctl_reset )
  begin
    if ctl_reset = '1' then
      ctl_up_buf_din_b1    <= (OTHERS=>'0');
      ctl_up_buf_din       <= (OTHERS=>'0');
      ctl_up_buf_wren      <= '0';
      ctl_up_is_writing    <= '0';
      ctl_up_is_writing_r1 <= '0';
 
    elsif link_rx_clk'event and link_rx_clk = '1' then
      ctl_up_buf_din_b1  <= X"0000" & "00" & ctrl_rec_start & ctrl_rec_end & ctrl_rec;
      ctl_up_buf_din     <= ctl_up_buf_din_b1;
      ctl_up_buf_wren    <= (ctl_up_is_writing or ctl_up_is_writing_r1);
      if ctrl_rec_start='1' and ctrl_rec_end='1' then
         ctl_up_is_writing    <= '0';
         ctl_up_is_writing_r1 <= '1';
      elsif ctrl_rec_start='1' then
         ctl_up_is_writing    <= '1';
         ctl_up_is_writing_r1 <= ctl_up_is_writing;
      elsif ctrl_rec_end='1' then
         ctl_up_is_writing    <= '0';
         ctl_up_is_writing_r1 <= ctl_up_is_writing;
      else
         ctl_up_is_writing    <= ctl_up_is_writing;
         ctl_up_is_writing_r1 <= ctl_up_is_writing;
      end if;
 
    end if;
  end process;
 
 
  -- CTL direction: upstream
  --     fabric side
  Transfer_CTL_upstream_fabric:
  process (trn_clk, ctl_reset )
  begin
    if ctl_reset = '1' then
      ctl_tv_i   <=  '0';
      ctl_td_i   <=  (OTHERS=>'0');
    elsif trn_clk'event and trn_clk = '1' then
      ctl_tv_i   <=  not ctl_up_buf_empty;
      ctl_td_i   <=  ctl_up_buf_dout(C_DBUS_WIDTH/2-1 downto 0);
    end if;
  end process;
 
 
end architecture Behavioral;

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Subversion Repositories pcie_sg_dma

[/] [pcie_sg_dma/] [branches/] [Virtex6/] [ML605_ISE12.3/] [pcie_sg_dma/] [Virtex6/] [ML605/] [class_ctl.vhd] - Blame information for rev 11

Line No.	Rev	Author	Line
1	11	barabba	`----------------------------------------------------------------------------------`
2			`-- Company: ziti`
3			`-- Engineer: wgao`
4			`--`
5			`-- Create Date: 17:01:32 19 Jun 2009`
6			`-- Design Name:`
7			`-- Module Name: class_ctl - Behavioral`
8			`-- Project Name:`
9			`-- Target Devices:`
10			`-- Tool versions:`
11			`-- Description:`
12			`--`
13			`-- Dependencies:`
14			`--`
15			`-- Revision:`
16			`-- Revision 0.01 - File Created`
17			`-- Additional Comments:`
18			`--`
19			`----------------------------------------------------------------------------------`
20			`library IEEE;`
21			`use IEEE.STD_LOGIC_1164.ALL;`
22			`use IEEE.STD_LOGIC_ARITH.ALL;`
23			`use IEEE.STD_LOGIC_UNSIGNED.ALL;`
24
25			`library work;`
26			`use work.abb64Package.all;`
27
28			`---- Uncomment the following library declaration if instantiating`
29			`---- any Xilinx primitives in this code.`
30			`--library UNISIM;`
31			`--use UNISIM.VComponents.all;`
32
33			`entity class_ctl is`
34			`-- Generic (`
35			`-- C_PRO_DAQ_WIDTH : integer := 16 ;`
36			`-- C_PRO_DLM_WIDTH : integer := 4 ;`
37			`-- C_PRO_CTL_WIDTH : integer := 16`
38			`-- );`
39			`Port (`
40
41			`-- CTL Tx`
42			`ctrl2send_start : OUT std_logic;`
43			`ctrl2send_end : OUT std_logic;`
44			`ctrl2send : OUT std_logic_vector(16-1 downto 0);`
45			`ctrl2send_stop : IN std_logic;`
46
47			`-- CTL Rx`
48			`ctrl_rec_start : IN std_logic;`
49			`ctrl_rec_end : IN std_logic;`
50			`ctrl_rec : IN std_logic_vector(16-1 downto 0);`
51			`ctrl_rec_stop : OUT std_logic;`
52
53			`-- Common signals`
54			`link_active : IN std_logic_vector(2-1 downto 0);`
55			`link_tx_clk : IN std_logic;`
56			`link_rx_clk : IN std_logic;`
57
58			`-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --`
59
60			`-- Fabric side: CTL Rx`
61			`ctl_rv : IN std_logic;`
62			`ctl_rd : IN std_logic_vector(C_DBUS_WIDTH/2-1 downto 0);`
63			`ctl_rstop : OUT std_logic;`
64
65			`-- Fabric side: CTL Tx`
66			`ctl_ttake : IN std_logic;`
67			`ctl_tv : OUT std_logic;`
68			`ctl_td : OUT std_logic_vector(C_DBUS_WIDTH/2-1 downto 0);`
69			`ctl_tstop : IN std_logic;`
70
71			`-- Interrupter trigger`
72			`CTL_irq : OUT std_logic;`
73			`ctl_status : OUT std_logic_vector(C_DBUS_WIDTH/2-1 downto 0);`
74
75			`-- Fabric side: Common signals`
76			`trn_clk : IN std_logic;`
77			`protocol_rst : IN std_logic`
78
79			`);`
80			`end entity class_ctl;`
81
82
83			`architecture Behavioral of class_ctl is`
84
85			`-- Standard synchronous FIFO`
86			`component sfifo_256x36`
87			`port (`
88			`wr_en : IN std_logic;`
89			`din : IN std_logic_VECTOR(36-1 downto 0);`
90			`prog_full : OUT std_logic;`
91			`full : OUT std_logic;`
92
93			`rd_en : IN std_logic;`
94			`dout : OUT std_logic_VECTOR(36-1 downto 0);`
95			`empty : OUT std_logic;`
96			`prog_empty: OUT std_logic;`
97
98			`clk : IN std_logic;`
99			`rst : IN std_logic`
100			`);`
101			`end component;`
102
103			`-- Standard asynchronous FIFO`
104			`component v6_afifo_256x36`
105			`port (`
106			`wr_clk : IN std_logic;`
107			`wr_en : IN std_logic;`
108			`din : IN std_logic_VECTOR(36-1 downto 0);`
109			`prog_full : OUT std_logic;`
110			`full : OUT std_logic;`
111
112			`rd_clk : IN std_logic;`
113			`rd_en : IN std_logic;`
114			`dout : OUT std_logic_VECTOR(36-1 downto 0);`
115			`empty : OUT std_logic;`
116			`prog_empty: OUT std_logic;`
117
118			`rst : IN std_logic`
119			`);`
120			`end component;`
121
122			`-- FWFT synchronous FIFO`
123			`component sfifo_256x36c_fwft`
124			`port (`
125			`wr_en : IN std_logic;`
126			`din : IN std_logic_VECTOR(36-1 downto 0);`
127			`prog_full : OUT std_logic;`
128			`full : OUT std_logic;`
129
130			`rd_en : IN std_logic;`
131			`dout : OUT std_logic_VECTOR(36-1 downto 0);`
132			`empty : OUT std_logic;`
133			`prog_empty: OUT std_logic;`
134
135			`data_count: OUT std_logic_vector (9-1 downto 0);`
136
137			`clk : IN std_logic;`
138			`rst : IN std_logic`
139			`);`
140			`end component;`
141
142			`-- FWFT asynchronous FIFO`
143			`component v6_afifo_256x36c_fwft`
144			`port (`
145			`wr_clk : IN std_logic;`
146			`wr_en : IN std_logic;`
147			`din : IN std_logic_VECTOR(36-1 downto 0);`
148			`prog_full : OUT std_logic;`
149			`full : OUT std_logic;`
150
151			`rd_clk : IN std_logic;`
152			`rd_en : IN std_logic;`
153			`dout : OUT std_logic_VECTOR(36-1 downto 0);`
154			`empty : OUT std_logic;`
155			`prog_empty : OUT std_logic;`
156
157			`rd_data_count : OUT std_logic_vector (9-1 downto 0);`
158
159			`rst : IN std_logic`
160			`);`
161			`end component;`
162
163			`-- Packet counter`
164			`component v6_pkt_counter_1024`
165			`port (`
166			`wr_clk : IN std_logic;`
167			`wr_en : IN std_logic;`
168			`din : IN std_logic_VECTOR(0 downto 0);`
169			`prog_full : OUT std_logic;`
170			`full : OUT std_logic;`
171
172			`rd_clk : IN std_logic;`
173			`rd_en : IN std_logic;`
174			`dout : OUT std_logic_VECTOR(0 downto 0);`
175			`empty : OUT std_logic;`
176			`prog_empty : OUT std_logic;`
177
178			`rst : IN std_logic`
179			`);`
180			`end component;`
181
182			`-- Interrupter trigger`
183			`signal ctl_reset : std_logic;`
184			`signal CTL_irq_i : std_logic;`
185			`signal ctl_status_i : std_logic_vector(C_DBUS_WIDTH/2-1 downto 0);`
186
187			`-- Fabric side: CTL Tx`
188			`signal ctl_tv_i : std_logic;`
189			`signal ctl_td_i : std_logic_vector(C_DBUS_WIDTH/2-1 downto 0);`
190			`signal ctl_rstop_i : std_logic;`
191
192			`-- protocol side: CTL Send`
193			`signal ctrl2send_start_i : std_logic;`
194			`signal ctrl2send_end_i : std_logic;`
195			`signal ctrl2send_i : std_logic_vector(16-1 downto 0);`
196			`signal ctrl_rec_stop_i : std_logic;`
197
198			`signal ctl_down_buf_rden : std_logic;`
199			`signal ctl_down_buf_dout : std_logic_vector(36-1 downto 0);`
200			`signal ctl_down_buf_empty : std_logic;`
201			`signal ctl_down_buf_afull : std_logic;`
202
203			`signal ctl_rd_padded : std_logic_vector(36-1 downto 0);`
204			`signal ctl_down_buf_rd_valid : std_logic :='0';`
205			`signal ctl_down_buf_read_gap : std_logic;`
206			`signal ctl_down_buf_eop : std_logic;`
207			`signal ctl_down_buf_eop_r1 : std_logic :='0';`
208
209			`signal ctrl2send_stop_r1 : std_logic :='0';`
210			`signal ctl_down_buf_frame_rd : std_logic :='0';`
211			`signal ctl_down_buf_stop_read : std_logic;`
212			`signal pc_ctl_down_push : std_logic;`
213			`signal pc_ctl_down_pop : std_logic;`
214			`signal no_pkts_in_ctl_down_buf : std_logic;`
215			`signal no_pkts_in_ctl_down_buf_r1: std_logic :='0';`
216
217			`signal ctl_up_buf_wren : std_logic;`
218			`signal ctl_up_buf_din : std_logic_vector(36-1 downto 0);`
219			`signal ctl_up_buf_din_b1 : std_logic_vector(36-1 downto 0);`
220			`signal ctl_up_buf_afull : std_logic;`
221
222			`signal ctl_up_buf_re : std_logic;`
223			`signal ctl_up_buf_dout : std_logic_vector(36-1 downto 0);`
224			`signal ctl_up_buf_empty : std_logic;`
225			`signal ctl_up_buf_dc_wire : std_logic_vector (9-1 downto 0);`
226			`signal ctl_up_buf_dc_r1 : std_logic_vector (9-1 downto 0);`
227			`signal ctl_up_buf_dc_plus_r1 : std_logic_vector (9-1 downto 0);`
228			`signal ctl_up_buf_dc_i : std_logic_vector (9-1 downto 0);`
229			`signal ctl_up_is_writing : std_logic;`
230			`signal ctl_up_is_writing_r1 : std_logic;`
231
232			`signal ctl_up_buf_rd_valid : std_logic;`
233			`signal pc_ctl_up_push : std_logic;`
234			`signal pc_ctl_up_pop : std_logic;`
235			`signal no_pkts_in_ctl_up_buf : std_logic;`
236			`signal no_pkts_in_ctl_up_buf_r1 : std_logic;`
237
238			`begin`
239
240
241			`-- Fabric side: CTL Tx`
242			`ctl_tv <= ctl_tv_i ;`
243			`ctl_td <= ctl_td_i ;`
244
245			`ctl_rstop <= ctl_rstop_i ;`
246
247
248			`-- protocol side: CTL Send`
249			`ctrl2send_start <= ctrl2send_start_i ;`
250			`ctrl2send_end <= ctrl2send_end_i ;`
251			`ctrl2send <= ctrl2send_i ;`
252
253			`ctrl_rec_stop <= ctrl_rec_stop_i ;`
254			`ctrl_rec_stop_i <= ctl_up_buf_afull;`
255
256			`ctl_rstop_i <= ctl_down_buf_afull;`
257
258			`ctl_status <= ctl_status_i ;`
259
260			`CTL_irq <= CTL_irq_i ;`
261			`CTL_irq_i <= not ctl_up_buf_empty ;`
262
263			`ctl_status_i <= X"000" & '0' & '0' & ctl_down_buf_afull & ctl_up_buf_empty`
264			`& X"0" & '0' & '0' & ctl_up_buf_dc_i & no_pkts_in_ctl_up_buf_r1;`
265
266
267			`-- ------------------------------------------------------------------------------`
268			`--`
269			`-- ------------------------------------------------------------------------------`
270			`Synch_Local_Reset:`
271			`process (trn_clk )`
272			`begin`
273			`if trn_clk'event and trn_clk = '1' then`
274			`ctl_reset <= protocol_rst;`
275			`end if;`
276			`end process;`
277
278			`-- ------------------------------------------------------------------------------`
279			`-- CTL buffer from the host`
280			`-- ------------------------------------------------------------------------------`
281			`ctl_buf_downstream:`
282			`v6_afifo_256x36`
283			`port map (`
284			`wr_clk => trn_clk , -- IN std_logic;`
285			`wr_en => ctl_rv , -- IN std_logic;`
286			`din => ctl_rd_padded , -- IN std_logic_VECTOR(35 downto 0);`
287			`prog_full => ctl_down_buf_afull , -- ctl_rstop_i , -- OUT std_logic;`
288			`full => open , -- OUT std_logic;`
289
290			`rd_clk => link_tx_clk , -- IN std_logic;`
291			`rd_en => ctl_down_buf_rden , -- IN std_logic;`
292			`dout => ctl_down_buf_dout , -- OUT std_logic_VECTOR(35 downto 0);`
293			`prog_empty => open , -- OUT std_logic;`
294			`empty => ctl_down_buf_empty , -- OUT std_logic;`
295
296			`rst => ctl_reset -- IN std_logic`
297			`);`
298
299			`ctl_rd_padded <= "0000" & ctl_rd;`
300			`ctl_down_buf_eop <= ctl_down_buf_dout(16);`
301			`ctl_down_buf_read_gap <= ctl_down_buf_eop and not ctl_down_buf_eop_r1;`
302			`ctl_down_buf_rden <= ctl_down_buf_frame_rd and not ctl_down_buf_read_gap;`
303
304
305			`-- Packet counter: ABB -> ROC`
306			`pc_ctl_buf_downstream:`
307			`v6_pkt_counter_1024`
308			`port map (`
309			`wr_clk => trn_clk , -- IN std_logic;`
310			`wr_en => pc_ctl_down_push , -- IN std_logic;`
311			`din => "1" , -- IN std_logic_VECTOR(0 downto 0);`
312			`prog_full => open , -- OUT std_logic;`
313			`full => open , -- OUT std_logic;`
314
315			`rd_clk => link_tx_clk , -- IN std_logic;`
316			`rd_en => pc_ctl_down_pop , -- IN std_logic;`
317			`dout => open , -- OUT std_logic_VECTOR(0 downto 0);`
318			`empty => no_pkts_in_ctl_down_buf , -- OUT std_logic;`
319			`prog_empty => open , -- OUT std_logic;`
320
321			`rst => ctl_reset -- IN std_logic`
322			`);`
323
324
325			`Syn_pc_ctl_down_push:`
326			`process (trn_clk, ctl_reset )`
327			`begin`
328			`if ctl_reset = '1' then`
329			`pc_ctl_down_push <= '0';`
330			`elsif trn_clk'event and trn_clk = '1' then`
331			`pc_ctl_down_push <= ctl_rv and ctl_rd(16);`
332			`end if;`
333			`end process;`
334
335			`Syn_pc_ctl_down_pop:`
336			`process (link_tx_clk, ctl_reset )`
337			`begin`
338			`if ctl_reset = '1' then`
339			`pc_ctl_down_pop <= '0';`
340			`elsif link_tx_clk'event and link_tx_clk = '1' then`
341			`pc_ctl_down_pop <= ctl_down_buf_rd_valid and ctl_down_buf_eop;`
342			`end if;`
343			`end process;`
344
345			`---------------------------------------------------`
346			`-- Downstream CTL buffer read and packets number`
347			`-- bit[17] : sof`
348			`-- bit[16] : eof`
349			`--`
350			`Delay_CTL_downstream_frame:`
351			`process (link_tx_clk )`
352			`begin`
353			`if link_tx_clk'event and link_tx_clk = '1' then`
354
355			`no_pkts_in_ctl_down_buf_r1 <= no_pkts_in_ctl_down_buf;`
356			`ctrl2send_stop_r1 <= ctrl2send_stop;`
357			`ctl_down_buf_rd_valid <= ctl_down_buf_rden and not ctl_down_buf_empty;`
358			`ctl_down_buf_eop_r1 <= ctl_down_buf_eop;`
359			`ctl_down_buf_frame_rd <= not no_pkts_in_ctl_down_buf_r1`
360			`and not ctl_down_buf_read_gap`
361			`and not ctl_down_buf_stop_read`
362			`;`
363			`end if;`
364			`end process;`
365
366			`--`
367			`Syn_rden_CTL_downstream_buf:`
368			`process (link_tx_clk, ctl_reset )`
369			`begin`
370			`if ctl_reset = '1' then`
371			`ctl_down_buf_stop_read <= '0';`
372			`elsif link_tx_clk'event and link_tx_clk = '1' then`
373			`if ctl_down_buf_read_gap='1' and ctrl2send_stop_r1='1' then`
374			`ctl_down_buf_stop_read <= '1';`
375			`elsif ctl_down_buf_stop_read='0' and ctrl2send_stop_r1='1' then`
376			`ctl_down_buf_stop_read <= '0';`
377			`else`
378			`ctl_down_buf_stop_read <= ctrl2send_stop_r1;`
379			`end if;`
380			`end if;`
381			`end process;`
382
383			`ctrl2send_start_i <= ctl_down_buf_dout(17);`
384			`ctrl2send_end_i <= ctl_down_buf_eop and not ctl_down_buf_eop_r1;`
385			`ctrl2send_i <= ctl_down_buf_dout(16-1 downto 0);`
386
387
388			`-- ------------------------------------------------------------------------------`
389			`-- CTL buffer to the host`
390			`-- ------------------------------------------------------------------------------`
391			`ctl_buf_upstream:`
392			`v6_afifo_256x36c_fwft`
393			`port map (`
394			`wr_clk => link_rx_clk , -- IN std_logic;`
395			`wr_en => ctl_up_buf_wren , -- IN std_logic;`
396			`din => ctl_up_buf_din , -- IN std_logic_VECTOR(35 downto 0);`
397			`prog_full => ctl_up_buf_afull , -- ctrl_rec_stop_i , -- OUT std_logic;`
398			`full => open , -- OUT std_logic;`
399
400			`rd_clk => trn_clk , -- IN std_logic;`
401			`rd_en => ctl_up_buf_re , -- IN std_logic;`
402			`dout => ctl_up_buf_dout , -- OUT std_logic_VECTOR(35 downto 0);`
403			`prog_empty => open , -- OUT std_logic;`
404			`empty => ctl_up_buf_empty , -- OUT std_logic;`
405
406			`rd_data_count => ctl_up_buf_dc_wire , -- OUT std_logic_vector (9-1 downto 0 );`
407
408			`rst => ctl_reset -- IN std_logic`
409			`);`
410
411			`ctl_up_buf_re <= ctl_ttake;`
412			`ctl_up_buf_rd_valid <= ctl_up_buf_re and not ctl_up_buf_empty;`
413
414
415			`-- Special data count for FWFT FIFO`
416			`Syn_up_fifo_fwft_dc:`
417			`process (trn_clk, ctl_reset )`
418			`begin`
419			`if ctl_reset = '1' then`
420			`ctl_up_buf_dc_i <= (OTHERS=>'0');`
421			`ctl_up_buf_dc_r1 <= (OTHERS=>'0');`
422			`ctl_up_buf_dc_plus_r1 <= (OTHERS=>'0');`
423			`elsif trn_clk'event and trn_clk = '1' then`
424			`ctl_up_buf_dc_r1 <= ctl_up_buf_dc_wire;`
425			`ctl_up_buf_dc_plus_r1 <= ctl_up_buf_dc_wire + "10";`
426			`if ctl_up_buf_empty='1' then`
427			`ctl_up_buf_dc_i <= ctl_up_buf_dc_r1;`
428			`else`
429			`ctl_up_buf_dc_i <= ctl_up_buf_dc_plus_r1;`
430			`end if;`
431			`end if;`
432			`end process;`
433
434			`-- Packet counter: ROC -> ABB`
435			`pc_ctl_buf_upstream:`
436			`v6_pkt_counter_1024`
437			`port map (`
438			`wr_clk => link_rx_clk , -- IN std_logic;`
439			`wr_en => pc_ctl_up_push , -- IN std_logic;`
440			`din => "1" , -- IN std_logic_VECTOR(0 downto 0);`
441			`prog_full => open , -- OUT std_logic;`
442			`full => open , -- OUT std_logic;`
443
444			`rd_clk => trn_clk , -- IN std_logic;`
445			`rd_en => pc_ctl_up_pop , -- IN std_logic;`
446			`dout => open , -- OUT std_logic_VECTOR(0 downto 0);`
447			`empty => no_pkts_in_ctl_up_buf , -- OUT std_logic;`
448			`prog_empty => open , -- OUT std_logic;`
449
450			`rst => ctl_reset -- IN std_logic`
451			`);`
452
453
454			`Syn_pc_ctl_up_push:`
455			`process (link_rx_clk, ctl_reset )`
456			`begin`
457			`if ctl_reset = '1' then`
458			`pc_ctl_up_push <= '0';`
459			`elsif link_rx_clk'event and link_rx_clk = '1' then`
460			`pc_ctl_up_push <= ctl_up_buf_wren and ctl_up_buf_din(16);`
461			`end if;`
462			`end process;`
463
464			`Syn_pc_ctl_up_pop:`
465			`process (trn_clk, ctl_reset )`
466			`begin`
467			`if ctl_reset = '1' then`
468			`pc_ctl_up_pop <= '0';`
469			`no_pkts_in_ctl_up_buf_r1 <= '1';`
470			`elsif trn_clk'event and trn_clk = '1' then`
471			`pc_ctl_up_pop <= ctl_up_buf_rd_valid and ctl_up_buf_dout(16);`
472			`no_pkts_in_ctl_up_buf_r1 <= no_pkts_in_ctl_up_buf;`
473			`end if;`
474			`end process;`
475
476			`-- CTL direction: upstream`
477			`-- protocol side`
478			`Transfer_CTL_upstream_protocol:`
479			`process (link_rx_clk, ctl_reset )`
480			`begin`
481			`if ctl_reset = '1' then`
482			`ctl_up_buf_din_b1 <= (OTHERS=>'0');`
483			`ctl_up_buf_din <= (OTHERS=>'0');`
484			`ctl_up_buf_wren <= '0';`
485			`ctl_up_is_writing <= '0';`
486			`ctl_up_is_writing_r1 <= '0';`
487
488			`elsif link_rx_clk'event and link_rx_clk = '1' then`
489			`ctl_up_buf_din_b1 <= X"0000" & "00" & ctrl_rec_start & ctrl_rec_end & ctrl_rec;`
490			`ctl_up_buf_din <= ctl_up_buf_din_b1;`
491			`ctl_up_buf_wren <= (ctl_up_is_writing or ctl_up_is_writing_r1);`
492			`if ctrl_rec_start='1' and ctrl_rec_end='1' then`
493			`ctl_up_is_writing <= '0';`
494			`ctl_up_is_writing_r1 <= '1';`
495			`elsif ctrl_rec_start='1' then`
496			`ctl_up_is_writing <= '1';`
497			`ctl_up_is_writing_r1 <= ctl_up_is_writing;`
498			`elsif ctrl_rec_end='1' then`
499			`ctl_up_is_writing <= '0';`
500			`ctl_up_is_writing_r1 <= ctl_up_is_writing;`
501			`else`
502			`ctl_up_is_writing <= ctl_up_is_writing;`
503			`ctl_up_is_writing_r1 <= ctl_up_is_writing;`
504			`end if;`
505
506			`end if;`
507			`end process;`
508
509
510			`-- CTL direction: upstream`
511			`-- fabric side`
512			`Transfer_CTL_upstream_fabric:`
513			`process (trn_clk, ctl_reset )`
514			`begin`
515			`if ctl_reset = '1' then`
516			`ctl_tv_i <= '0';`
517			`ctl_td_i <= (OTHERS=>'0');`
518			`elsif trn_clk'event and trn_clk = '1' then`
519			`ctl_tv_i <= not ctl_up_buf_empty;`
520			`ctl_td_i <= ctl_up_buf_dout(C_DBUS_WIDTH/2-1 downto 0);`
521			`end if;`
522			`end process;`
523
524
525			`end architecture Behavioral;`