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barabba |
##############################################################
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#
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# Xilinx Core Generator version 11.4
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# Date: Tue Feb 16 13:28:53 2010
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#
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##############################################################
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#
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# This file contains the customisation parameters for a
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# Xilinx CORE Generator IP GUI. It is strongly recommended
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# that you do not manually alter this file as it may cause
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# unexpected and unsupported behavior.
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#
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##############################################################
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#
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# BEGIN Project Options
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SET addpads = False
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SET asysymbol = True
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SET busformat = BusFormatAngleBracketNotRipped
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SET createndf = False
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SET designentry = VHDL
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SET device = xc6vlx240t
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SET devicefamily = virtex6
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SET flowvendor = Foundation_ISE
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SET formalverification = False
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SET foundationsym = False
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SET implementationfiletype = Ngc
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SET package = ff1156
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SET removerpms = False
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SET simulationfiles = Behavioral
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SET speedgrade = -1
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SET verilogsim = True
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SET vhdlsim = True
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# END Project Options
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# BEGIN Select
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SELECT Fifo_Generator family Xilinx,_Inc. 5.3
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# END Select
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# BEGIN Parameters
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CSET almost_empty_flag=false
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CSET almost_full_flag=false
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CSET component_name=v6_prime_fifo_plain
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CSET data_count=false
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CSET data_count_width=9
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CSET disable_timing_violations=false
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CSET dout_reset_value=0
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CSET empty_threshold_assert_value=5
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CSET empty_threshold_negate_value=6
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CSET enable_ecc=false
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CSET enable_int_clk=false
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CSET enable_reset_synchronization=true
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CSET fifo_implementation=Independent_Clocks_Builtin_FIFO
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CSET full_flags_reset_value=0
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CSET full_threshold_assert_value=496
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CSET full_threshold_negate_value=495
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CSET inject_dbit_error=false
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CSET inject_sbit_error=false
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CSET input_data_width=72
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CSET input_depth=512
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CSET output_data_width=72
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CSET output_depth=512
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CSET overflow_flag=false
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CSET overflow_sense=Active_High
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CSET performance_options=Standard_FIFO
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CSET programmable_empty_type=No_Programmable_Empty_Threshold
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CSET programmable_full_type=Single_Programmable_Full_Threshold_Constant
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CSET read_clock_frequency=125
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CSET read_data_count=false
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CSET read_data_count_width=9
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CSET reset_pin=true
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CSET reset_type=Asynchronous_Reset
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CSET underflow_flag=false
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CSET underflow_sense=Active_High
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CSET use_dout_reset=false
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CSET use_embedded_registers=false
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CSET use_extra_logic=false
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CSET valid_flag=false
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CSET valid_sense=Active_High
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CSET write_acknowledge_flag=false
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CSET write_acknowledge_sense=Active_High
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CSET write_clock_frequency=125
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CSET write_data_count=false
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CSET write_data_count_width=9
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# END Parameters
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GENERATE
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# CRC: 8c8c5bd1
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