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[/] [pcie_sg_dma/] [branches/] [Virtex6/] [ML605_ISE12.3/] [pcie_sg_dma/] [Virtex6/] [ML605/] [rx_CplD_Channel.vhd] - Blame information for rev 11

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Line No. Rev Author Line
1 11 barabba 
----------------------------------------------------------------------------------
2 
-- Company:
3 
-- Engineer:
4 
--
5 
-- Design Name:
6 
-- Module Name:    rx_CplD_Transact - Behavioral
7 
-- Project Name:
8 
-- Target Devices:
9 
-- Tool versions:
10 
-- Description:
11 
--
12 
-- Dependencies:
13 
--
14 
-- Revision 1.10 - x4 timing constraints met.   02.02.2007
15 
--
16 
-- Revision 1.04 - Timing improved.     17.01.2007
17 
--
18 
-- Revision 1.02 - FIFO added.    20.12.2006
19 
--
20 
-- Revision 1.00 - first release. 14.12.2006
21 
--
22 
-- Additional Comments:
23 
--
24 
----------------------------------------------------------------------------------
25 
 
26 
library IEEE;
27 
use IEEE.STD_LOGIC_1164.ALL;
28 
use IEEE.STD_LOGIC_ARITH.ALL;
29 
use IEEE.STD_LOGIC_UNSIGNED.ALL;
30 
 
31 
library work;
32 
use work.abb64Package.all;
33 
 
34 
-- Uncomment the following library declaration if instantiating
35 
-- any Xilinx primitives in this code.
36 
--library UNISIM;
37 
--use UNISIM.VComponents.all;
38 
 
39 
entity rx_CplD_Transact is
40 
    port (
41 
      -- Transaction receive interface
42 
      trn_rsof_n         : IN  std_logic;
43 
      trn_reof_n         : IN  std_logic;
44 
      trn_rd             : IN  std_logic_vector(C_DBUS_WIDTH-1 downto 0);
45 
      trn_rrem_n         : IN  std_logic_vector(C_DBUS_WIDTH/8-1 downto 0);
46 
      trn_rerrfwd_n      : IN  std_logic;
47 
      trn_rsrc_rdy_n     : IN  std_logic;
48 
      trn_rdst_rdy_n     : IN  std_logic;  -- !!
49 
      trn_rsrc_dsc_n     : IN  std_logic;
50 
      trn_rbar_hit_n     : IN  std_logic_vector(C_BAR_NUMBER-1 downto 0);
51 
--      trn_rfc_ph_av      : IN  std_logic_vector(7 downto 0);
52 
--      trn_rfc_pd_av      : IN  std_logic_vector(11 downto 0);
53 
--      trn_rfc_nph_av     : IN  std_logic_vector(7 downto 0);
54 
--      trn_rfc_npd_av     : IN  std_logic_vector(11 downto 0);
55 
--      trn_rfc_cplh_av    : IN  std_logic_vector(7 downto 0);
56 
--      trn_rfc_cpld_av    : IN  std_logic_vector(11 downto 0);
57 
 
58 
 
59 
      CplD_Type          : IN  std_logic_vector(3 downto 0);
60 
 
61 
      Req_ID_Match       : IN  std_logic;
62 
      usDex_Tag_Matched  : IN  std_logic;
63 
      dsDex_Tag_Matched  : IN  std_logic;
64 
 
65 
      Tlp_has_4KB        : IN  std_logic;
66 
      Tlp_has_1DW        : IN  std_logic;
67 
      CplD_on_Pool       : IN  std_logic;
68 
      CplD_on_EB         : IN  std_logic;
69 
      CplD_is_the_Last   : IN  std_logic;
70 
      CplD_Tag           : IN  std_logic_vector(C_TAG_WIDTH-1 downto  0);
71 
      FC_pop             : OUT std_logic;
72 
 
73 
 
74 
      -- Downstream DMA transferred bytes count up
75 
      ds_DMA_Bytes_Add   : OUT std_logic;
76 
      ds_DMA_Bytes       : OUT std_logic_vector(C_TLP_FLD_WIDTH_OF_LENG+2 downto 0);
77 
 
78 
 
79 
      -- Tag output to downstream DMA channel
80 
      dsDMA_dex_Tag      : OUT std_logic_vector(C_TAG_WIDTH-1 downto 0);
81 
 
82 
      -- Downstream Handshake Signals with ds Channel for Busy/Done
83 
      Tag_Map_Clear      : OUT std_logic_vector(C_TAG_MAP_WIDTH-1 downto 0);
84 
 
85 
 
86 
      -- Downstream tRAM port A write request
87 
      tRAM_weB           : IN  std_logic;
88 
      tRAM_addrB         : IN  std_logic_vector(C_TAGRAM_AWIDTH-1 downto 0);
89 
      tRAM_dinB          : IN  std_logic_vector(C_TAGRAM_DWIDTH-1 downto 0);
90 
 
91 
      -- Tag output to upstream DMA channel
92 
      usDMA_dex_Tag      : OUT std_logic_vector(C_TAG_WIDTH-1 downto 0);
93 
 
94 
      -- Event Buffer write port
95 
      eb_FIFO_we         : OUT std_logic;
96 
      eb_FIFO_wsof       : OUT std_logic;
97 
      eb_FIFO_weof       : OUT std_logic;
98 
      eb_FIFO_din        : OUT std_logic_vector(C_DBUS_WIDTH-1 downto 0);
99 
 
100 
      -- Registers Write Port
101 
      Regs_WrEn          : OUT std_logic;
102 
      Regs_WrMask        : OUT std_logic_vector(2-1 downto 0);
103 
      Regs_WrAddr        : OUT std_logic_vector(C_EP_AWIDTH-1 downto 0);
104 
      Regs_WrDin         : OUT std_logic_vector(C_DBUS_WIDTH-1 downto 0);
105 
 
106 
      -- DDR write port
107 
      DDR_wr_sof         : OUT std_logic;
108 
      DDR_wr_eof         : OUT std_logic;
109 
      DDR_wr_v           : OUT std_logic;
110 
      DDR_wr_FA          : OUT std_logic;
111 
      DDR_wr_Shift       : OUT std_logic;
112 
      DDR_wr_Mask        : OUT std_logic_vector(2-1 downto 0);
113 
      DDR_wr_din         : OUT std_logic_vector(C_DBUS_WIDTH-1 downto 0);
114 
      DDR_wr_full        : IN  std_logic;
115 
 
116 
      -- Common ports
117 
      trn_clk            : IN  std_logic;
118 
      trn_reset_n        : IN  std_logic;
119 
      trn_lnk_up_n       : IN  std_logic
120 
 
121 
    );
122 
 
123 
end entity rx_CplD_Transact;
124 
 
125 
 
126 
 
127 
architecture Behavioral of rx_CplD_Transact is
128 
 
129 
  type RxCplDEBStates is ( ST_EBWR_IDLE
130 
                         , ST_EBWR_TAG
131 
                         , ST_EBWR_DATA
132 
                         );
133 
 
134 
  signal EB_Write_State  : RxCplDEBStates;
135 
 
136 
 
137 
  type RxCplDTrnStates is ( ST_CplD_RESET
138 
                          , ST_CplD_IDLE
139 
--                          , ST_Cpl_HEAD1            -- Cpl Header #1  (not used)
140 
--                          , ST_CplD_HEAD1           -- CplD Header #1
141 
                          , ST_Cpl_HEAD2            -- Cpl Header #2  (not used)
142 
                          , ST_CplD_HEAD2           -- CplD Header #2
143 
                          , ST_CplD_AFetch_Special  --
144 
                          , ST_CplD_AFetch_Special_Tail  --
145 
                          , ST_CplD_AFetch          -- Target address fetch from tRAM/registers
146 
                          , ST_CplD_AFetch_THROTTLE -- Target address fetch throttled
147 
                          , ST_CplD_ONLY_1DW        -- Current CplD has only 1 DW
148 
--                          , ST_CplD_ONLY_1DW_THROTTLE        -- Current CplD has only 1 DW, throttled
149 
                          , ST_CplD_1ST_DATA        -- 1st data payload of the CplD
150 
                          , ST_CplD_1ST_DATA_THROTTLE        -- 1st data payload of the CplD
151 
                          , ST_CplD_DATA            -- data receiving
152 
                          , ST_CplD_DATA_THROTTLE   -- data receiving throttled
153 
                          , ST_CplD_LAST_DATA       -- Last data payload of the CplD
154 
                          );
155 
 
156 
  -- State variables
157 
  signal RxCplDTrn_NextState  : RxCplDTrnStates;
158 
  signal RxCplDTrn_State      : RxCplDTrnStates;
159 
 
160 
  -- State delay
161 
  signal RxCplDTrn_State_r1   : RxCplDTrnStates;
162 
  signal RxCplDTrn_State_r2   : RxCplDTrnStates;
163 
 
164 
  signal CplD_State_is_AFetch : std_logic;
165 
  signal CplD_State_is_after_AFetch : std_logic;
166 
  signal CplD_State_is_AFetch_r1 : std_logic;
167 
 
168 
 
169 
  -- Shifted-glued payload
170 
  signal concat_rd            : std_logic_vector (C_DBUS_WIDTH-1 downto 0);
171 
 
172 
  -- trn_rx stubs
173 
  signal trn_rd_i             : std_logic_vector (C_DBUS_WIDTH-1 downto 0);
174 
  signal trn_rd_r1            : std_logic_vector (C_DBUS_WIDTH-1 downto 0);
175 
  signal trn_rd_r2            : std_logic_vector (C_DBUS_WIDTH-1 downto 0);
176 
  signal trn_rd_r3            : std_logic_vector (C_DBUS_WIDTH-1 downto 0);
177 
  signal trn_rd_r4            : std_logic_vector (C_DBUS_WIDTH-1 downto 0);
178 
 
179 
  -- trn_rd_*  in little endian
180 
  signal trn_rd_Little        : std_logic_vector (C_DBUS_WIDTH-1 downto 0);
181 
  signal trn_rd_Little_r1     : std_logic_vector (C_DBUS_WIDTH-1 downto 0);
182 
  signal trn_rd_Little_r2     : std_logic_vector (C_DBUS_WIDTH-1 downto 0);
183 
  signal trn_rd_Little_r3     : std_logic_vector (C_DBUS_WIDTH-1 downto 0);
184 
  signal trn_rd_Little_r4     : std_logic_vector (C_DBUS_WIDTH-1 downto 0);
185 
 
186 
  --  signal  trn_rbar_hit_n_i   : std_logic_vector(C_BAR_NUMBER-1 downto 0);
187 
  signal trn_rerrfwd_n_i      : std_logic;
188 
  signal trn_rsrc_dsc_n_i     : std_logic;
189 
 
190 
  signal trn_rsof_n_i         : std_logic;
191 
  signal trn_reof_n_i         : std_logic;
192 
  signal trn_reof_n_r1        : std_logic;
193 
  signal trn_reof_n_r2        : std_logic;
194 
  signal trn_reof_n_r3        : std_logic;
195 
  signal trn_reof_n_r4        : std_logic;
196 
 
197 
--  signal Tlp_has_4KB_r1       : std_logic;
198 
  signal trn_rrem_n_i         : std_logic_vector(C_DBUS_WIDTH/8-1 downto 0);
199 
  signal trn_rrem_n_r1        : std_logic_vector(C_DBUS_WIDTH/8-1 downto 0);
200 
  signal trn_rrem_n_r2        : std_logic_vector(C_DBUS_WIDTH/8-1 downto 0);
201 
  signal trn_rrem_n_r3        : std_logic_vector(C_DBUS_WIDTH/8-1 downto 0);
202 
  signal trn_rrem_n_r4        : std_logic_vector(C_DBUS_WIDTH/8-1 downto 0);
203 
 
204 
  --  Whether address increases
205 
  signal Addr_Inc             : std_logic;
206 
 
207 
  --  Spaces hit
208 
--  signal FIFO_Space_Hit       : std_logic;
209 
  signal DDR_Space_Hit        : std_logic;
210 
 
211 
 
212 
  -- DDR write port
213 
  signal DDR_wr_sof_i         : std_logic;
214 
  signal DDR_wr_eof_i         : std_logic;
215 
  signal DDR_wr_v_i           : std_logic;
216 
  signal DDR_wr_FA_i          : std_logic;
217 
  signal DDR_wr_Shift_i       : std_logic;
218 
  signal DDR_wr_Mask_i        : std_logic_vector(2-1 downto 0);
219 
  signal DDR_wr_din_i         : std_logic_vector(C_DBUS_WIDTH-1 downto 0);
220 
  signal DDR_wr_full_i        : std_logic;
221 
 
222 
 
223 
  -- Event Buffer write port
224 
  signal eb_FIFO_we_i         : std_logic;
225 
  signal eb_FIFO_wsof_i       : std_logic;
226 
  signal eb_FIFO_weof_i       : std_logic;
227 
  signal eb_FIFO_sof_marker   : std_logic;
228 
  signal eb_FIFO_din_i        : std_logic_vector(C_DBUS_WIDTH-1 downto 0);
229 
 
230 
  --  Register write port
231 
  signal Regs_WrEn_i          : std_logic;
232 
  signal Regs_WrMask_i        : std_logic_vector(2-1 downto 0);
233 
  signal Regs_WrAddr_i        : std_logic_vector(C_EP_AWIDTH-1 downto 0);
234 
  signal Regs_WrDin_i         : std_logic_vector(C_DBUS_WIDTH-1 downto 0);
235 
 
236 
  --  Calculation @ trn_rsof_n=0
237 
  signal Dex_CplD_Illegal     : std_logic;
238 
  signal Reg_WrAddr_if_last_us: std_logic_vector(C_EP_AWIDTH-1 downto 0);
239 
  signal Reg_WrAddr_if_last_ds: std_logic_vector(C_EP_AWIDTH-1 downto 0);
240 
 
241 
 
242 
  -- Flow control signals
243 
  signal trn_rdst_rdy_n_i     : std_logic;
244 
  signal trn_rsrc_rdy_n_i     : std_logic;
245 
  signal trn_rsrc_rdy_n_r1    : std_logic;
246 
  signal trn_rsrc_rdy_n_r2    : std_logic;
247 
  signal trn_rsrc_rdy_n_r3    : std_logic;
248 
  signal trn_rsrc_rdy_n_r4    : std_logic;
249 
 
250 
 
251 
  signal trn_rx_throttle      : std_logic;
252 
  signal trn_rx_throttle_r1   : std_logic;
253 
  signal trn_rx_throttle_r2   : std_logic;
254 
  signal trn_rx_throttle_r3   : std_logic;
255 
  signal trn_rx_throttle_r4   : std_logic;
256 
 
257 
 
258 
  -- Downstream DMA transferred bytes count up
259 
  signal ds_DMA_Bytes_Add_i   : std_logic;
260 
  signal ds_DMA_Bytes_i       : std_logic_vector(C_TLP_FLD_WIDTH_OF_LENG+2 downto 0);
261 
  signal CplD_is_Payloaded    : std_logic;
262 
 
263 
  -- Alias for header resolution
264 
  signal CplD_Length          : std_logic_vector(C_TLP_FLD_WIDTH_OF_LENG downto 0);
265 
  signal CplD_Leng_in_Bytes   : std_logic_vector(C_DBUS_WIDTH/2-1 downto 0);
266 
  signal CplD_Leng_in_Bytes_r1: std_logic_vector(C_DBUS_WIDTH/2-1 downto 0);
267 
  signal CplD_is_1DW          : std_logic;
268 
  --     Small_CplD means CplD with less than 4 DW payload
269 
  signal Small_CplD           : std_logic;
270 
  signal Small_CplD_r1        : std_logic;
271 
 
272 
 
273 
  signal RegAddr_us_Dex       : std_logic_vector(C_EP_AWIDTH-1 downto 0);
274 
  signal RegAddr_ds_Dex       : std_logic_vector(C_EP_AWIDTH-1 downto 0);
275 
 
276 
  signal CplD_Tag_on_Dex      : std_logic;
277 
 
278 
  -- ----------------------------------------------------------------------
279 
  signal Req_ID_Match_i       : std_logic;
280 
  signal Dex_Tag_Matched_i    : std_logic;
281 
 
282 
  -- The top bit of the CplD_Tag is for distinguishing data CplD or descriptor CplD
283 
  signal MSB_DSP_Tag          : std_logic;
284 
  signal MSB_DSP_Tag_r1       : std_logic;
285 
  signal DSP_Tag_on_RAM       : std_logic;
286 
  signal DSP_Tag_on_RAM_r1    : std_logic;
287 
  signal DSP_Tag_on_RAM_r2    : std_logic;
288 
  signal DSP_Tag_on_RAM_r3    : std_logic;
289 
  signal DSP_Tag_on_RAM_r4p   : std_logic;
290 
  signal DSP_Tag_on_FIFO      : std_logic;
291 
  -- ----------------------------------------------------------------------
292 
  signal FC_pop_i              : std_logic;
293 
 
294 
 
295 
  signal Tag_Map_Clear_i      : std_logic_vector(C_TAG_MAP_WIDTH-1 downto 0);
296 
 
297 
  signal Local_Reset_i        : std_logic;
298 
 
299 
 
300 
  -- upstream Descriptors' tags
301 
  signal usDMA_dex_Tag_i      :  std_logic_vector(C_TAG_WIDTH-1 downto 0);
302 
 
303 
  -- downstream Descriptors' tags
304 
  signal dsDMA_dex_Tag_i      : std_logic_vector(C_TAG_WIDTH-1 downto  0);
305 
 
306 
 
307 
--  --- ------------------------------------------
308 
--  ---   Dual port Block Memory, used as tag RAM
309 
--  component
310 
--    v5tagram64x36
311 
--    port (
312 
--            clka     : IN  std_logic;
313 
--            addra    : IN  std_logic_VECTOR(C_TAGRAM_AWIDTH-1 downto 0);
314 
--            wea      : IN  std_logic_vector(0 downto 0);
315 
--            dina     : IN  std_logic_VECTOR(C_TAGRAM_DWIDTH-1 downto 0);
316 
--            douta    : OUT std_logic_VECTOR(C_TAGRAM_DWIDTH-1 downto 0);
317 
--            clkb     : IN  std_logic;
318 
--            addrb    : IN  std_logic_VECTOR(C_TAGRAM_AWIDTH-1 downto 0);
319 
--            web      : IN  std_logic_vector(0 downto 0);
320 
--            dinb     : IN  std_logic_VECTOR(C_TAGRAM_DWIDTH-1 downto 0);
321 
--            doutb    : OUT std_logic_VECTOR(C_TAGRAM_DWIDTH-1 downto 0)
322 
--         );
323 
--  end component;
324 
 
325 
  --- ------------------------------------------
326 
  ---   Dual port Block Memory, used as tag RAM
327 
  component
328 
    FF_TagRam64x36
329 
    port (
330 
            clk      : IN  std_logic;
331 
            addra    : IN  std_logic_VECTOR(C_TAGRAM_AWIDTH-1 downto 0);
332 
            wea      : IN  std_logic;
333 
            dina     : IN  std_logic_VECTOR(C_TAGRAM_DWIDTH-1 downto 0);
334 
            douta    : OUT std_logic_VECTOR(C_TAGRAM_DWIDTH-1 downto 0);
335 
            addrb    : IN  std_logic_VECTOR(C_TAGRAM_AWIDTH-1 downto 0);
336 
            web      : IN  std_logic;
337 
            dinb     : IN  std_logic_VECTOR(C_TAGRAM_DWIDTH-1 downto 0);
338 
            doutb    : OUT std_logic_VECTOR(C_TAGRAM_DWIDTH-1 downto 0)
339 
         );
340 
  end component;
341 
 
342 
  signal tRAM_wea             : std_logic_vector(0 downto 0);
343 
  signal tRAM_addra           : std_logic_vector(C_TAGRAM_AWIDTH-1 downto 0);
344 
  signal tRAM_dina            : std_logic_vector(C_TAGRAM_DWIDTH-1 downto 0);
345 
  signal tRAM_doutA           : std_logic_vector(C_TAGRAM_DWIDTH-1 downto 0);
346 
  signal tRAM_weB_i           : std_logic_vector(0 downto 0);
347 
 
348 
  signal tRAM_DoutA_r1        : std_logic_vector(C_TAGRAM_DWIDTH-1 downto 0);
349 
  signal tRAM_DoutA_r2        : std_logic_vector(C_TAGRAM_DWIDTH-1 downto 0);
350 
  signal tRAM_dina_aInc       : std_logic_vector(C_TAGRAM_DWIDTH-1 downto 0);
351 
  signal tRAM_DoutA_latch     : std_logic_vector(C_TAGRAM_DWIDTH-1 downto 0);
352 
 
353 
  --  updates the tag RAM as soon as possible
354 
  signal CplD_is_the_Last_r1  : std_logic;
355 
  signal Updates_tRAM         : std_logic;
356 
  signal Updates_tRAM_r1      : std_logic;
357 
  signal Update_was_too_late  : std_logic;
358 
 
359 
  signal hazard_update        : std_logic;
360 
  signal hazard_update_r1     : std_logic;
361 
  signal hazard_update_r2     : std_logic;
362 
  signal hazard_update_r3     : std_logic;
363 
  signal hazard_tag           : std_logic_vector(C_TAG_WIDTH-1 downto  0);
364 
  signal hazard_content       : std_logic_vector(C_TAGRAM_DWIDTH-1 downto 0);
365 
  signal tag_matches_hazard   : std_logic;
366 
 
367 
  --  aka TLB unit
368 
  signal TLB_Addr             : std_logic_vector(C_TAGRAM_AWIDTH-1 downto 0);
369 
  signal TLB_Content          : std_logic_vector(C_TAGRAM_DWIDTH-1 downto 0);
370 
  signal TLB_cnt              : std_logic_vector(4-1 downto 0);
371 
  signal TLB_Valid            : std_logic;
372 
  signal TLB_Hit              : std_logic;
373 
 
374 
  Constant C_TLB_VALID_CNT    : std_logic_vector(4-1 downto 0)       := X"6";
375 
 
376 
begin
377 
 
378 
   -- Event Buffer write
379 
   eb_FIFO_we         <=  eb_FIFO_we_i   ;
380 
   eb_FIFO_wsof       <=  eb_FIFO_wsof_i ;
381 
   eb_FIFO_weof       <=  eb_FIFO_weof_i ;
382 
   eb_FIFO_din        <=  eb_FIFO_din_i  ;
383 
 
384 
   -- DDR
385 
   DDR_wr_sof         <=  DDR_wr_sof_i   ;
386 
   DDR_wr_eof         <=  DDR_wr_eof_i   ;
387 
   DDR_wr_v           <=  DDR_wr_v_i     ;
388 
   DDR_wr_FA          <=  DDR_wr_FA_i    ;
389 
   DDR_wr_Shift       <=  DDR_wr_Shift_i ;
390 
   DDR_wr_Mask        <=  DDR_wr_Mask_i  ;
391 
   DDR_wr_din         <=  DDR_wr_din_i   ;
392 
   DDR_wr_full_i      <=  DDR_wr_full    ;
393 
 
394 
   ds_DMA_Bytes_Add   <=  ds_DMA_Bytes_Add_i ;
395 
   ds_DMA_Bytes       <=  ds_DMA_Bytes_i     ;
396 
 
397 
   --
398 
   Tag_Map_Clear      <=  Tag_Map_Clear_i;
399 
 
400 
   --
401 
   FC_pop             <=  FC_pop_i;
402 
   -- ----------------------------------------------
403 
   --
404 
   Syn_FC_pop:
405 
   process ( trn_clk, Local_Reset_i)
406 
   begin
407 
      if Local_Reset_i = '1' then
408 
         FC_pop_i   <= '0';
409 
      elsif trn_clk'event and trn_clk = '1' then
410 
         FC_pop_i   <=  (CplD_on_Pool or CplD_on_EB)
411 
                    and CplD_is_the_Last
412 
                    and not MSB_DSP_Tag
413 
                    and not trn_reof_n_i
414 
                    and trn_reof_n_r1      -- Catch the falling edge of trn_reof_n
415 
--                    and not trn_rx_throttle
416 
                    ;
417 
      end if;
418 
 
419 
   end process;
420 
 
421 
   -- ----------------------------------------------
422 
   -- Synchronous: CplD_is_Payloaded
423 
   --
424 
   Syn_CplD_is_Payloaded:
425 
   process ( trn_clk, Local_Reset_i)
426 
   begin
427 
      if Local_Reset_i = '1' then
428 
         CplD_is_Payloaded   <= '0';
429 
      elsif trn_clk'event and trn_clk = '1' then
430 
         if trn_rsof_n_i='0' and trn_rx_throttle='0' then
431 
            CplD_is_Payloaded   <= CplD_Type(3) or CplD_Type(1);
432 
         else
433 
            CplD_is_Payloaded   <= CplD_is_Payloaded;
434 
         end if;
435 
      end if;
436 
 
437 
   end process;
438 
 
439 
 
440 
   -- ----------------------------------------------
441 
   -- Synchronous Accumulation: us_DMA_Bytes
442 
   --
443 
   Syn_ds_DMA_Bytes_Add:
444 
   process ( trn_clk, Local_Reset_i)
445 
   begin
446 
      if Local_Reset_i = '1' then
447 
         ds_DMA_Bytes_Add_i <=  '0' ;
448 
         ds_DMA_Bytes_i     <=  (OTHERS=>'0');
449 
      elsif trn_clk'event and trn_clk = '1' then
450 
         if trn_reof_n_i='0' and trn_rx_throttle='0'
451 
            and CplD_is_Payloaded='1' and MSB_DSP_Tag='0'
452 
            then
453 
            ds_DMA_Bytes_Add_i <=  '1' ;
454 
            ds_DMA_Bytes_i     <=  CplD_Leng_in_Bytes(C_TLP_FLD_WIDTH_OF_LENG+2 downto 0);
455 
         else
456 
            ds_DMA_Bytes_Add_i <=  '0' ;
457 
            ds_DMA_Bytes_i     <=  (OTHERS=>'0');
458 
         end if;
459 
      end if;
460 
 
461 
   end process;
462 
 
463 
 
464 
   -- Registers writing
465 
   Regs_WrEn          <=  Regs_WrEn_i;
466 
   Regs_WrMask        <=  Regs_WrMask_i;
467 
   Regs_WrAddr        <=  Regs_WrAddr_i;
468 
   Regs_WrDin         <=  Regs_WrDin_i;
469 
 
470 
 
471 
   ---  Dex Tag output to us DMA channel
472 
   usDMA_dex_Tag      <=  usDMA_dex_Tag_i;
473 
 
474 
   ---  Dex Tag output to ds DMA channel
475 
   dsDMA_dex_Tag      <=  dsDMA_dex_Tag_i;
476 
 
477 
 
478 
   ---------------------------------------------------
479 
   Req_ID_Match_i     <= Req_ID_Match;
480 
 
481 
   Dex_Tag_Matched_i  <= usDex_Tag_Matched or dsDex_Tag_Matched;
482 
 
483 
   -- positive reset
484 
   Local_Reset_i      <= not trn_reset_n;
485 
 
486 
 
487 
   -- Frame signals
488 
   trn_rsof_n_i       <= trn_rsof_n;
489 
   trn_reof_n_i       <= trn_reof_n;
490 
   trn_rd_i           <= trn_rd;
491 
   trn_rrem_n_i       <= trn_rrem_n;
492 
   trn_rsrc_rdy_n_i   <= trn_rsrc_rdy_n;
493 
   trn_rdst_rdy_n_i   <= trn_rdst_rdy_n;
494 
 
495 
 
496 
   --  BC of the current TLP payloads
497 
   CplD_Leng_in_Bytes <= C_ALL_ZEROS(C_DBUS_WIDTH/2-1 downto C_TLP_FLD_WIDTH_OF_LENG+3)
498 
                       & CplD_Length & "00";
499 
 
500 
 
501 
   -- Exception signals
502 
   trn_rerrfwd_n_i    <= trn_rerrfwd_n;
503 
   trn_rsrc_dsc_n_i   <= trn_rsrc_dsc_n;
504 
 
505 
 
506 
   -- ( trn_rsrc_rdy_n seems never deasserted during packet)
507 
   trn_rx_throttle    <= trn_rsrc_rdy_n_i or trn_rdst_rdy_n_i;
508 
 
509 
 
510 
 
511 
-- ---------------------------------------------
512 
-- Synchronous bit: CplD_State_is_AFetch
513 
--
514 
   RxFSM_CplD_State_is_AFetch:
515 
   process ( trn_clk )
516 
   begin
517 
      if trn_clk'event and trn_clk = '1' then
518 
 
519 
         CplD_State_is_AFetch_r1  <= CplD_State_is_AFetch;
520 
 
521 
         case RxCplDTrn_State is
522 
           when  ST_CplD_AFetch  =>
523 
             CplD_State_is_AFetch     <= '1';
524 
           when  ST_CplD_AFetch_Special  =>
525 
             CplD_State_is_AFetch     <= '1';
526 
           when  OTHERS =>
527 
             CplD_State_is_AFetch     <= '0';
528 
         end case;
529 
 
530 
      end if;
531 
   end process;
532 
 
533 
 
534 
-- ---------------------------------------------
535 
-- Synchronous bit: CplD_State_is_after_AFetch
536 
--
537 
   RxFSM_CplD_State_is_after_AFetch:
538 
   process ( trn_clk )
539 
   begin
540 
      if trn_clk'event and trn_clk = '1' then
541 
 
542 
         case RxCplDTrn_State is
543 
           when  ST_CplD_AFetch_Special_Tail  =>
544 
             CplD_State_is_after_AFetch     <= '1';
545 
           when  ST_CplD_ONLY_1DW  =>
546 
             CplD_State_is_after_AFetch     <= '1';
547 
           when  ST_CplD_1ST_DATA  =>
548 
             CplD_State_is_after_AFetch     <= '1';
549 
           when  OTHERS =>
550 
             CplD_State_is_after_AFetch     <= '0';
551 
         end case;
552 
 
553 
      end if;
554 
   end process;
555 
 
556 
 
557 
-- ---------------------------------------------
558 
-- Delay Synchronous Delay: trn_r*
559 
--
560 
   Syn_Delay_trn_r_x:
561 
   process ( trn_clk )
562 
   begin
563 
       if trn_clk'event and trn_clk = '1' then
564 
         trn_reof_n_r1         <= trn_reof_n_i;
565 
         trn_reof_n_r2         <= trn_reof_n_r1;
566 
         trn_reof_n_r3         <= trn_reof_n_r2;
567 
         trn_reof_n_r4         <= trn_reof_n_r3;
568 
 
569 
         trn_rsrc_rdy_n_r1     <= trn_rx_throttle;  -- trn_rsrc_rdy_n_i;
570 
         trn_rsrc_rdy_n_r2     <= trn_rsrc_rdy_n_r1;
571 
         trn_rsrc_rdy_n_r3     <= trn_rsrc_rdy_n_r2;
572 
         trn_rsrc_rdy_n_r4     <= trn_rsrc_rdy_n_r3;
573 
 
574 
         trn_rx_throttle_r1     <= trn_rx_throttle;
575 
         trn_rx_throttle_r2     <= trn_rx_throttle_r1;
576 
         trn_rx_throttle_r3     <= trn_rx_throttle_r2;
577 
         trn_rx_throttle_r4     <= trn_rx_throttle_r3;
578 
 
579 
--         DDR_wr_full_r1        <= DDR_wr_full_i;
580 
--         DDR_wr_full_r2        <= DDR_wr_full_r1;
581 
 
582 
         trn_rd_r1             <= trn_rd_i;
583 
         trn_rd_r2             <= trn_rd_r1;
584 
         trn_rd_r3             <= trn_rd_r2;
585 
         trn_rd_r4             <= trn_rd_r3;
586 
 
587 
         trn_rrem_n_r1         <= trn_rrem_n_i;
588 
         trn_rrem_n_r2         <= trn_rrem_n_r1;
589 
         trn_rrem_n_r3         <= trn_rrem_n_r2;
590 
         trn_rrem_n_r4         <= trn_rrem_n_r3;
591 
 
592 
      end if;
593 
   end process;
594 
 
595 
 
596 
   -- Endian reversed
597 
   trn_rd_Little      <= Endian_Invert_64 (trn_rd_i);
598 
   trn_rd_Little_r1   <= Endian_Invert_64 (trn_rd_r1);
599 
   trn_rd_Little_r2   <= Endian_Invert_64 (trn_rd_r2);
600 
   trn_rd_Little_r3   <= Endian_Invert_64 (trn_rd_r3);
601 
   trn_rd_Little_r4   <= Endian_Invert_64 (trn_rd_r4);
602 
 
603 
 
604 
-- ---------------------------------------------
605 
   MSB_DSP_Tag        <= CplD_Tag(C_TAG_WIDTH-1);
606 
   DSP_Tag_on_RAM     <= not CplD_Tag(C_TAG_WIDTH-1) and not CplD_Tag(C_TAG_WIDTH-2);
607 
   DSP_Tag_on_FIFO    <= not CplD_Tag(C_TAG_WIDTH-1) and CplD_Tag(C_TAG_WIDTH-2);
608 
 
609 
--
610 
-- Delay Synchronous: MSB_DSP_Tag_r1
611 
--
612 
   Syn_Delay_MSB_DSP_Tag_r1:
613 
   process ( trn_clk )
614 
   begin
615 
      if trn_clk'event and trn_clk = '1' then
616 
         MSB_DSP_Tag_r1     <= MSB_DSP_Tag;
617 
         DSP_Tag_on_RAM_r1  <= DSP_Tag_on_RAM;
618 
         DSP_Tag_on_RAM_r2  <= DSP_Tag_on_RAM_r1;
619 
         DSP_Tag_on_RAM_r3  <= DSP_Tag_on_RAM_r2;
620 
         DSP_Tag_on_RAM_r4p <= DSP_Tag_on_RAM_r2 or DSP_Tag_on_RAM_r3;
621 
      end if;
622 
   end process;
623 
 
624 
 
625 
--
626 
-- Delay Synchronous: CplD_Leng_in_Bytes
627 
--
628 
   Syn_Delay_CplD_Leng_in_Bytes:
629 
   process ( trn_clk )
630 
   begin
631 
      if trn_clk'event and trn_clk = '1' then
632 
         CplD_Leng_in_Bytes_r1     <= CplD_Leng_in_Bytes;
633 
      end if;
634 
   end process;
635 
 
636 
 
637 
-- ---------------------------------------------
638 
-- Delay Synchronous Delay: RxCplDTrn_State
639 
--
640 
   RxFSM_Delay_RxTrn_State:
641 
   process ( trn_clk )
642 
   begin
643 
      if trn_clk'event and trn_clk = '1' then
644 
         RxCplDTrn_State_r1     <= RxCplDTrn_State;
645 
         RxCplDTrn_State_r2     <= RxCplDTrn_State_r1;
646 
      end if;
647 
   end process;
648 
 
649 
 
650 
-- ----------------------------------------------
651 
-- States synchronous
652 
--
653 
   Syn_RxTrn_States:
654 
   process ( trn_clk, Local_Reset_i)
655 
   begin
656 
      if Local_Reset_i = '1' then
657 
         RxCplDTrn_State   <= ST_CplD_RESET;
658 
      elsif trn_clk'event and trn_clk = '1' then
659 
         RxCplDTrn_State   <= RxCplDTrn_NextState;
660 
      end if;
661 
 
662 
   end process;
663 
 
664 
 
665 
-- Next States
666 
   Comb_RxTrn_NextStates:
667 
   process (
668 
             RxCplDTrn_State
669 
           , CplD_Type
670 
           , MSB_DSP_Tag
671 
           , trn_reof_n_i
672 
           , trn_rx_throttle
673 
           , Req_ID_Match_i
674 
           , Dex_Tag_Matched_i
675 
           )
676 
   begin
677 
     case RxCplDTrn_State  is
678 
 
679 
        when ST_CplD_RESET =>
680 
              RxCplDTrn_NextState <= ST_CplD_IDLE;
681 
 
682 
        when ST_CplD_IDLE =>
683 
 
684 
          if trn_rx_throttle='0' then
685 
            case CplD_Type is
686 
              when C_TLP_TYPE_IS_CPLD =>
687 
                RxCplDTrn_NextState <= ST_CplD_HEAD2;
688 
              when C_TLP_TYPE_IS_CPL =>
689 
                RxCplDTrn_NextState <= ST_Cpl_HEAD2;
690 
              when C_TLP_TYPE_IS_CPLDLK =>
691 
                RxCplDTrn_NextState <= ST_CplD_HEAD2;
692 
              when C_TLP_TYPE_IS_CPLLK =>
693 
                RxCplDTrn_NextState <= ST_Cpl_HEAD2;
694 
              when OTHERS =>
695 
                RxCplDTrn_NextState <= ST_CplD_IDLE;
696 
            end case;  -- CplD_Type
697 
          else
698 
            RxCplDTrn_NextState <= ST_CplD_IDLE;
699 
          end if;
700 
 
701 
 
702 
 
703 
        when ST_Cpl_HEAD2 =>   -- further processing to be done ...
704 
           RxCplDTrn_NextState <= ST_CplD_IDLE;
705 
 
706 
 
707 
        when ST_CplD_HEAD2 =>
708 
           if trn_rx_throttle = '1' then
709 
              RxCplDTrn_NextState <= ST_CplD_HEAD2;
710 
           elsif Req_ID_Match_i='1' and Dex_Tag_Matched_i='1' then
711 
              if trn_reof_n_i='0' then
712 
                RxCplDTrn_NextState <= ST_CplD_AFetch_Special;
713 
              else
714 
                RxCplDTrn_NextState <= ST_CplD_AFetch;
715 
              end if;
716 
           elsif Req_ID_Match_i='1' and MSB_DSP_Tag='0' then
717 
              if trn_reof_n_i='0' then
718 
                RxCplDTrn_NextState <= ST_CplD_AFetch_Special;
719 
              else
720 
                RxCplDTrn_NextState <= ST_CplD_AFetch;
721 
              end if;
722 
           else
723 
              RxCplDTrn_NextState <= ST_CplD_IDLE;
724 
           end if;
725 
 
726 
 
727 
        when ST_CplD_AFetch =>
728 
           if trn_reof_n_i='0' then
729 
              RxCplDTrn_NextState <= ST_CplD_ONLY_1DW;
730 
           elsif trn_rx_throttle = '1' then
731 
              RxCplDTrn_NextState <= ST_CplD_AFetch_THROTTLE;
732 
           else
733 
              RxCplDTrn_NextState <= ST_CplD_1ST_DATA;
734 
           end if;
735 
 
736 
        when ST_CplD_AFetch_Special =>
737 
                                               -- !!!!!!!!!!!!!!
738 
                                               -- Suppose 1DW CplD (sof-eof TLP) is not followed back-to-back
739 
                                               -- !!!!!!!!!!!!!!
740 
           RxCplDTrn_NextState <= ST_CplD_AFetch_Special_Tail;
741 
 
742 
 
743 
        when ST_CplD_AFetch_Special_Tail =>
744 
          if trn_rx_throttle='0' then
745 
            case CplD_Type is
746 
              when C_TLP_TYPE_IS_CPLD =>
747 
                RxCplDTrn_NextState <= ST_CplD_HEAD2;
748 
              when C_TLP_TYPE_IS_CPL =>
749 
                RxCplDTrn_NextState <= ST_Cpl_HEAD2;
750 
              when C_TLP_TYPE_IS_CPLDLK =>
751 
                RxCplDTrn_NextState <= ST_CplD_HEAD2;
752 
              when C_TLP_TYPE_IS_CPLLK =>
753 
                RxCplDTrn_NextState <= ST_Cpl_HEAD2;
754 
              when OTHERS =>
755 
                RxCplDTrn_NextState <= ST_CplD_IDLE;
756 
            end case;  -- CplD_Type
757 
          else
758 
            RxCplDTrn_NextState <= ST_CplD_IDLE;
759 
          end if;
760 
 
761 
 
762 
        when ST_CplD_AFetch_THROTTLE =>
763 
           if trn_reof_n_i='0' then
764 
              RxCplDTrn_NextState <= ST_CplD_ONLY_1DW;
765 
           elsif trn_rx_throttle = '1' then
766 
              RxCplDTrn_NextState <= ST_CplD_AFetch_THROTTLE;
767 
           else
768 
              RxCplDTrn_NextState <= ST_CplD_1ST_DATA;
769 
           end if;
770 
 
771 
 
772 
        when ST_CplD_ONLY_1DW =>
773 
          if trn_rx_throttle='0' then
774 
            case CplD_Type is
775 
              when C_TLP_TYPE_IS_CPLD =>
776 
                RxCplDTrn_NextState <= ST_CplD_HEAD2;
777 
              when C_TLP_TYPE_IS_CPL =>
778 
                RxCplDTrn_NextState <= ST_Cpl_HEAD2;
779 
              when C_TLP_TYPE_IS_CPLDLK =>
780 
                RxCplDTrn_NextState <= ST_CplD_HEAD2;
781 
              when C_TLP_TYPE_IS_CPLLK =>
782 
                RxCplDTrn_NextState <= ST_Cpl_HEAD2;
783 
              when OTHERS =>
784 
                RxCplDTrn_NextState <= ST_CplD_IDLE;
785 
            end case;  -- CplD_Type
786 
          else
787 
            RxCplDTrn_NextState <= ST_CplD_IDLE;
788 
          end if;
789 
 
790 
 
791 
        when ST_CplD_1ST_DATA =>
792 
           if trn_reof_n_i='0' then
793 
              RxCplDTrn_NextState <= ST_CplD_LAST_DATA;
794 
           elsif trn_rx_throttle = '1' then
795 
              RxCplDTrn_NextState <= ST_CplD_1ST_DATA_THROTTLE;
796 
           else
797 
              RxCplDTrn_NextState <= ST_CplD_DATA;
798 
           end if;
799 
 
800 
        when ST_CplD_1ST_DATA_THROTTLE =>
801 
           if trn_reof_n_i='0' then
802 
              RxCplDTrn_NextState <= ST_CplD_LAST_DATA;
803 
           elsif trn_rx_throttle = '1' then
804 
              RxCplDTrn_NextState <= ST_CplD_1ST_DATA_THROTTLE;
805 
           else
806 
              RxCplDTrn_NextState <= ST_CplD_DATA;
807 
           end if;
808 
 
809 
 
810 
        when ST_CplD_DATA =>
811 
           if trn_reof_n_i='0' then
812 
              RxCplDTrn_NextState <= ST_CplD_LAST_DATA;
813 
           elsif  trn_rx_throttle = '1' then
814 
              RxCplDTrn_NextState <= ST_CplD_DATA_THROTTLE;
815 
           else
816 
              RxCplDTrn_NextState <= ST_CplD_DATA;
817 
           end if;
818 
 
819 
 
820 
        when ST_CplD_DATA_THROTTLE =>
821 
           if trn_reof_n_i='0' then
822 
              RxCplDTrn_NextState <= ST_CplD_LAST_DATA;
823 
           elsif trn_rx_throttle = '1' then
824 
              RxCplDTrn_NextState <= ST_CplD_DATA_THROTTLE;
825 
           else
826 
              RxCplDTrn_NextState <= ST_CplD_DATA;
827 
           end if;
828 
 
829 
 
830 
        when ST_CplD_LAST_DATA =>                 -- Same as IDLE, to support
831 
                                                  --  back-to-back transactions
832 
          if trn_rx_throttle='0' then
833 
            case CplD_Type is
834 
              when C_TLP_TYPE_IS_CPLD =>
835 
                RxCplDTrn_NextState <= ST_CplD_HEAD2;
836 
              when C_TLP_TYPE_IS_CPL =>
837 
                RxCplDTrn_NextState <= ST_Cpl_HEAD2;
838 
              when C_TLP_TYPE_IS_CPLDLK =>
839 
                RxCplDTrn_NextState <= ST_CplD_HEAD2;
840 
              when C_TLP_TYPE_IS_CPLLK =>
841 
                RxCplDTrn_NextState <= ST_Cpl_HEAD2;
842 
              when OTHERS =>
843 
                RxCplDTrn_NextState <= ST_CplD_IDLE;
844 
            end case;  -- CplD_Type
845 
          else
846 
            RxCplDTrn_NextState <= ST_CplD_IDLE;
847 
          end if;
848 
 
849 
 
850 
        when OTHERS =>
851 
           RxCplDTrn_NextState <= ST_CplD_RESET;
852 
 
853 
     end case;
854 
 
855 
   end process;
856 
 
857 
 
858 
-- -------------------------------------------------
859 
-- Synchronous Registered: Tag_Map_Clear_i
860 
--
861 
   RxTrn_Tag_Map_Clear:
862 
   process ( trn_clk, Local_Reset_i)
863 
   begin
864 
      if Local_Reset_i = '1' then
865 
         Tag_Map_Clear_i     <= (OTHERS=>'0');
866 
 
867 
      elsif trn_clk'event and trn_clk = '1' then
868 
 
869 
         FOR j IN 0 TO C_TAG_MAP_WIDTH-1 LOOP
870 
 
871 
             -- CplD_Tag(C_TAG_WIDTH-2) used as token of BAR
872 
             if CplD_Tag(C_TAG_WIDTH-1)='0'
873 
                and CplD_Tag(C_TAG_WIDTH-2-1 downto 0)=CONV_STD_LOGIC_VECTOR(j, C_TAG_WIDTH-2)
874 
                and CplD_is_the_Last='1' then
875 
                Tag_Map_Clear_i(j) <=  '1';
876 
             else
877 
                Tag_Map_Clear_i(j) <=  '0';
878 
             end if;
879 
 
880 
         END LOOP;
881 
 
882 
      end if;
883 
   end process;
884 
 
885 
 
886 
 
887 
-- -------------------------------------------------
888 
-- Synchronous Registered: CplD_Length
889 
--
890 
   RxTrn_CplD_Length:
891 
   process ( trn_clk, Local_Reset_i)
892 
   begin
893 
      if Local_Reset_i = '1' then
894 
         CplD_Length     <= (OTHERS => '0');
895 
         CplD_is_1DW     <= '0';
896 
         Small_CplD      <= '0';
897 
         Small_CplD_r1   <= '0';
898 
 
899 
      elsif trn_clk'event and trn_clk = '1' then
900 
 
901 
         Small_CplD_r1   <= Small_CplD;
902 
 
903 
         if trn_rsof_n_i='0' then
904 
            CplD_Length     <= Tlp_has_4KB & trn_rd_i(C_TLP_LENG_BIT_TOP downto C_TLP_LENG_BIT_BOT);
905 
            CplD_is_1DW     <= Tlp_has_1DW;
906 
            if trn_rd_i(C_TLP_LENG_BIT_TOP downto C_TLP_LENG_BIT_BOT+2)=C_ALL_ZEROS(C_TLP_LENG_BIT_TOP downto C_TLP_LENG_BIT_BOT+2)
907 
               and trn_rd_i(C_TLP_LENG_BIT_BOT+1 downto C_TLP_LENG_BIT_BOT)/="00"
908 
               and trn_rd_i(C_TLP_TYPE_BIT_TOP downto C_TLP_TYPE_BIT_TOP-1)="01"   -- Cpl/D
909 
               then
910 
               Small_CplD      <= '1';
911 
            else
912 
               Small_CplD      <= '0';
913 
            end if;
914 
         else
915 
            CplD_Length     <= CplD_Length;
916 
            CplD_is_1DW     <= CplD_is_1DW;
917 
            Small_CplD      <= Small_CplD;
918 
         end if;
919 
 
920 
      end if;
921 
   end process;
922 
 
923 
 
924 
 
925 
 
926 
-- -------------------------------------------------
927 
-- Synchronous outputs: Addr_Inc
928 
--
929 
   RxFSM_Output_Addr_Inc:
930 
   process ( trn_clk, Local_Reset_i)
931 
   begin
932 
      if Local_Reset_i = '1' then
933 
         Addr_Inc  <= '1';
934 
 
935 
      elsif trn_clk'event and trn_clk = '1' then
936 
 
937 
         case RxCplDTrn_State_r1 is
938 
 
939 
            when ST_CplD_RESET =>
940 
               Addr_Inc  <= '1';
941 
 
942 
            when  ST_CplD_1ST_DATA =>
943 
               Addr_Inc  <= tRAM_DoutA_r1(CBIT_AINC_IN_TAGRAM);
944 
 
945 
            when ST_CplD_ONLY_1DW =>
946 
               Addr_Inc  <= tRAM_DoutA_r1(CBIT_AINC_IN_TAGRAM);
947 
 
948 
            when OTHERS =>
949 
               Addr_Inc  <= Addr_Inc;
950 
 
951 
         end case;
952 
      end if;
953 
   end process;
954 
 
955 
 
956 
-------------------------------------------------
957 
-- Calculation at trn_rsof_n
958 
--
959 
   Syn_Dex_wrAddress:
960 
   process ( trn_clk, Local_Reset_i)
961 
   begin
962 
      if Local_Reset_i = '1' then
963 
         Dex_CplD_Illegal        <= '0';
964 
         Reg_WrAddr_if_last_us   <= (OTHERS=>'0');   -- C_REGS_BASE_ADDR;
965 
         Reg_WrAddr_if_last_ds   <= (OTHERS=>'0');   -- C_REGS_BASE_ADDR;
966 
 
967 
      elsif trn_clk'event and trn_clk = '1' then
968 
 
969 
         if trn_rsof_n_i = '0' then
970 
            Reg_WrAddr_if_last_us(C_EP_AWIDTH-2-1 downto 2) <= CONV_STD_LOGIC_VECTOR(CINT_ADDR_DMA_US_CTRL, C_EP_AWIDTH-2-2) - trn_rd_i(C_NEXT_BD_LENG_MSB+32 downto 32);
971 
            Reg_WrAddr_if_last_ds(C_EP_AWIDTH-2-1 downto 2) <= CONV_STD_LOGIC_VECTOR(CINT_ADDR_DMA_DS_CTRL, C_EP_AWIDTH-2-2) - trn_rd_i(C_NEXT_BD_LENG_MSB+32 downto 32);
972 
--            Reg_WrAddr_if_last_us(C_EP_AWIDTH-2-1 downto 2) <= CONV_STD_LOGIC_VECTOR(CINT_ADDR_DMA_US_STA, C_EP_AWIDTH-2-2) - trn_rd_i(C_NEXT_BD_LENG_MSB+32 downto 32);
973 
--            Reg_WrAddr_if_last_ds(C_EP_AWIDTH-2-1 downto 2) <= CONV_STD_LOGIC_VECTOR(CINT_ADDR_DMA_DS_STA, C_EP_AWIDTH-2-2) - trn_rd_i(C_NEXT_BD_LENG_MSB+32 downto 32);
974 
         else
975 
            Reg_WrAddr_if_last_us   <= Reg_WrAddr_if_last_us;
976 
            Reg_WrAddr_if_last_ds   <= Reg_WrAddr_if_last_ds;
977 
         end if;
978 
 
979 
      end if;
980 
 
981 
   end process;
982 
 
983 
 
984 
-- ---------------------------------------------
985 
-- Reg Synchronous: RegAddr_?s_Dex
986 
--
987 
   RxFSM_Reg_RegAddr_xs_Dex:
988 
   process ( trn_clk, Local_Reset_i)
989 
   begin
990 
      if Local_Reset_i = '1' then
991 
         RegAddr_us_Dex   <= (Others=>'1');
992 
         RegAddr_ds_Dex   <= (Others=>'1');
993 
 
994 
      elsif trn_clk'event and trn_clk = '1' then
995 
 
996 
         if CplD_Tag(C_TAG_WIDTH-1 downto C_TAG_WIDTH-C_TAG_DECODE_BITS)/=C_TAG0_DMA_USB(C_TAG_WIDTH-1 downto C_TAG_WIDTH-C_TAG_DECODE_BITS) then
997 
            RegAddr_us_Dex   <= (Others=>'1');
998 
         elsif  CplD_is_the_Last = '1' then   -- us last/2nd dex
999 
            RegAddr_us_Dex   <= Reg_WrAddr_if_last_us;
1000 
         else                                 -- us 1st/unique dex
1001 
            RegAddr_us_Dex   <= -- C_REGS_BASE_ADDR(C_DECODE_BIT_TOP downto C_DECODE_BIT_BOT) &  ,(C_DECODE_BIT_BOT-2)
1002 
--                                CONV_STD_LOGIC_VECTOR(CINT_ADDR_DMA_US_PAH, C_DECODE_BIT_BOT) & "00";
1003 
                                CONV_STD_LOGIC_VECTOR(CINT_ADDR_DMA_US_PAH-1, C_DECODE_BIT_BOT) & "00";
1004 
         end if;
1005 
 
1006 
 
1007 
         if CplD_Tag(C_TAG_WIDTH-1 downto C_TAG_WIDTH-C_TAG_DECODE_BITS)/=C_TAG0_DMA_DSB(C_TAG_WIDTH-1 downto C_TAG_WIDTH-C_TAG_DECODE_BITS) then
1008 
            RegAddr_ds_Dex   <= (Others=>'1');
1009 
         elsif  CplD_is_the_Last = '1' then   -- ds last/2nd dex
1010 
            RegAddr_ds_Dex   <= Reg_WrAddr_if_last_ds;
1011 
         else                                 -- ds 1st/unique dex
1012 
            RegAddr_ds_Dex   <= -- C_REGS_BASE_ADDR(C_DECODE_BIT_TOP downto C_DECODE_BIT_BOT) &  ,(C_DECODE_BIT_BOT-2)
1013 
--                                CONV_STD_LOGIC_VECTOR(CINT_ADDR_DMA_DS_PAH, C_DECODE_BIT_BOT) & "00";
1014 
                                CONV_STD_LOGIC_VECTOR(CINT_ADDR_DMA_DS_PAH-1, C_DECODE_BIT_BOT) & "00";
1015 
         end if;
1016 
 
1017 
 
1018 
      end if;
1019 
   end process;
1020 
 
1021 
 
1022 
 
1023 
-- ---------------------------------------------
1024 
-- Reg Synchronous Delay: CplD_Tag_on_Dex
1025 
--
1026 
   RxFSM_Delay_CplD_Tag_on_Dex:
1027 
   process ( trn_clk, Local_Reset_i)
1028 
   begin
1029 
      if Local_Reset_i = '1' then
1030 
         CplD_Tag_on_Dex   <= '0';
1031 
 
1032 
      elsif trn_clk'event and trn_clk = '1' then
1033 
 
1034 
         if    CplD_Tag(C_TAG_WIDTH-1 downto C_TAG_WIDTH-C_TAG_DECODE_BITS)=C_TAG0_DMA_USB(C_TAG_WIDTH-1 downto C_TAG_WIDTH-C_TAG_DECODE_BITS) then
1035 
            CplD_Tag_on_Dex   <= '1';
1036 
         elsif CplD_Tag(C_TAG_WIDTH-1 downto C_TAG_WIDTH-C_TAG_DECODE_BITS)=C_TAG0_DMA_DSB(C_TAG_WIDTH-1 downto C_TAG_WIDTH-C_TAG_DECODE_BITS) then
1037 
            CplD_Tag_on_Dex   <= '1';
1038 
         else
1039 
            CplD_Tag_on_Dex   <= '0';
1040 
         end if;
1041 
 
1042 
      end if;
1043 
   end process;
1044 
 
1045 
 
1046 
-------------------------------------------------------
1047 
-- Synchronous outputs: DMA_Registers
1048 
--
1049 
   RxFSM_Output_DMA_Registers:
1050 
   process ( trn_clk, Local_Reset_i)
1051 
   begin
1052 
      if Local_Reset_i = '1' then
1053 
         Regs_WrEn_i     <= '0';
1054 
         Regs_WrMask_i   <= (OTHERS=>'0');
1055 
         Regs_WrDin_i    <= (OTHERS => '0');
1056 
 
1057 
      elsif trn_clk'event and trn_clk = '1' then
1058 
 
1059 
         case RxCplDTrn_State is
1060 
 
1061 
            when  ST_CplD_AFetch =>
1062 
               if CplD_Tag_on_Dex='1' then
1063 
                  Regs_WrEn_i     <= '1';
1064 
                  Regs_WrMask_i   <= "10";
1065 
                  Regs_WrDin_i    <= trn_rd_Little_r1;
1066 
               else
1067 
                  Regs_WrEn_i     <= '0';
1068 
                  Regs_WrMask_i   <= (OTHERS=>'0');
1069 
                  Regs_WrDin_i    <= (Others=>'0');
1070 
               end if;
1071 
 
1072 
            when  ST_CplD_AFetch_Special =>
1073 
               if CplD_Tag_on_Dex='1' then
1074 
                  Regs_WrEn_i     <= '1';
1075 
                  Regs_WrMask_i   <= "10";
1076 
                  Regs_WrDin_i    <= trn_rd_Little_r1;
1077 
               else
1078 
                  Regs_WrEn_i     <= '0';
1079 
                  Regs_WrMask_i   <= (OTHERS=>'0');
1080 
                  Regs_WrDin_i    <= (Others=>'0');
1081 
               end if;
1082 
 
1083 
            when  ST_CplD_1ST_DATA =>
1084 
               if CplD_Tag_on_Dex='1' then
1085 
                  Regs_WrEn_i     <= '1';
1086 
                  Regs_WrMask_i   <= (OTHERS=>'0');
1087 
                  Regs_WrDin_i    <= trn_rd_Little_r1;
1088 
               else
1089 
                  Regs_WrEn_i     <= '0';
1090 
                  Regs_WrMask_i   <= (OTHERS=>'0');
1091 
                  Regs_WrDin_i    <= (Others=>'0');
1092 
               end if;
1093 
 
1094 
            when ST_CplD_ONLY_1DW =>
1095 
               if CplD_Tag_on_Dex='1' then
1096 
                  Regs_WrEn_i     <= '1';
1097 
                  Regs_WrMask_i   <= (OTHERS=>'0');
1098 
                  Regs_WrDin_i    <= trn_rd_Little_r1;
1099 
               else
1100 
                  Regs_WrEn_i     <= '0';
1101 
                  Regs_WrMask_i   <= (OTHERS=>'0');
1102 
                  Regs_WrDin_i    <= (Others=>'0');
1103 
               end if;
1104 
 
1105 
            when ST_CplD_DATA =>
1106 
               if CplD_Tag_on_Dex='1' then
1107 
                  Regs_WrEn_i     <= '1';
1108 
                  Regs_WrMask_i   <= '0' & (trn_rrem_n_r1(3) or trn_rrem_n_r1(0));
1109 
                  Regs_WrDin_i    <= trn_rd_Little_r1;
1110 
               else
1111 
                  Regs_WrEn_i     <= '0';
1112 
                  Regs_WrMask_i   <= (OTHERS=>'0');
1113 
                  Regs_WrDin_i    <= (Others=>'0');
1114 
               end if;
1115 
 
1116 
            when ST_CplD_LAST_DATA =>
1117 
               if CplD_Tag_on_Dex='1' then
1118 
                  Regs_WrEn_i     <= '1';
1119 
                  Regs_WrMask_i   <= '0' & (trn_rrem_n_r1(3) or trn_rrem_n_r1(0));
1120 
                  Regs_WrDin_i    <= trn_rd_Little_r1;
1121 
               else
1122 
                  Regs_WrEn_i     <= '0';
1123 
                  Regs_WrMask_i   <= (OTHERS=>'0');
1124 
                  Regs_WrDin_i    <= (Others=>'0');
1125 
               end if;
1126 
 
1127 
            when OTHERS =>
1128 
               Regs_WrEn_i     <= '0';
1129 
               Regs_WrMask_i   <= (OTHERS=>'0');
1130 
               Regs_WrDin_i    <= (Others=>'0');
1131 
 
1132 
         end case;
1133 
 
1134 
      end if;
1135 
   end process;
1136 
 
1137 
 
1138 
-------------------------------------------------------
1139 
-- Synchronous outputs: DMA_Registers write Address
1140 
--
1141 
   RxFSM_Output_DMA_Registers_WrAddr:
1142 
   process ( trn_clk, Local_Reset_i)
1143 
   begin
1144 
      if Local_Reset_i = '1' then
1145 
         Regs_WrAddr_i   <= (OTHERS => '1');
1146 
 
1147 
      elsif trn_clk'event and trn_clk = '1' then
1148 
 
1149 
         case RxCplDTrn_State is
1150 
 
1151 
            when ST_CplD_IDLE =>
1152 
               Regs_WrAddr_i   <= (OTHERS => '1');
1153 
 
1154 
            when  ST_CplD_AFetch =>
1155 
               Regs_WrAddr_i   <= RegAddr_us_Dex and RegAddr_ds_Dex;
1156 
 
1157 
            when  ST_CplD_AFetch_Special =>
1158 
               Regs_WrAddr_i   <= RegAddr_us_Dex and RegAddr_ds_Dex;
1159 
 
1160 
            when  ST_CplD_1ST_DATA =>
1161 
               Regs_WrAddr_i(C_DECODE_BIT_BOT-1 downto 0)
1162 
                               <= Regs_WrAddr_i(C_DECODE_BIT_BOT-1 downto 0) + CONV_STD_LOGIC_VECTOR(8, C_DECODE_BIT_BOT);
1163 
 
1164 
            when ST_CplD_ONLY_1DW =>
1165 
               Regs_WrAddr_i(C_DECODE_BIT_BOT-1 downto 0)
1166 
                               <= Regs_WrAddr_i(C_DECODE_BIT_BOT-1 downto 0) + CONV_STD_LOGIC_VECTOR(8, C_DECODE_BIT_BOT);
1167 
 
1168 
            when ST_CplD_DATA =>
1169 
               Regs_WrAddr_i(C_DECODE_BIT_BOT-1 downto 0)
1170 
                               <= Regs_WrAddr_i(C_DECODE_BIT_BOT-1 downto 0) + CONV_STD_LOGIC_VECTOR(8, C_DECODE_BIT_BOT);
1171 
 
1172 
            when ST_CplD_LAST_DATA =>
1173 
               Regs_WrAddr_i(C_DECODE_BIT_BOT-1 downto 0)
1174 
                               <= Regs_WrAddr_i(C_DECODE_BIT_BOT-1 downto 0) + CONV_STD_LOGIC_VECTOR(8, C_DECODE_BIT_BOT);
1175 
 
1176 
            when OTHERS =>
1177 
               Regs_WrAddr_i   <= Regs_WrAddr_i;
1178 
 
1179 
         end case;
1180 
 
1181 
      end if;
1182 
   end process;
1183 
 
1184 
 
1185 
 
1186 
-----------------------------------------------------
1187 
-- Synchronous Register:
1188 
--                      dsDMA_dex_Tag_i
1189 
--                      usDMA_dex_Tag_i
1190 
--
1191 
   FSM_Reg_DMA_dex_Tags:
1192 
   process ( trn_clk, Local_Reset_i)
1193 
   begin
1194 
      if Local_Reset_i = '1' then
1195 
         usDMA_dex_Tag_i     <= C_TAG0_DMA_USB;
1196 
         dsDMA_dex_Tag_i     <= C_TAG0_DMA_DSB;
1197 
 
1198 
      elsif trn_clk'event and trn_clk = '1' then
1199 
 
1200 
         case RxCplDTrn_State is
1201 
 
1202 
           when ST_CplD_AFetch =>
1203 
 
1204 
              if  trn_rd_r1(C_CPLD_TAG_BIT_TOP downto C_CPLD_TAG_BIT_BOT)=usDMA_dex_Tag_i and CplD_is_the_Last = '1' then
1205 
                usDMA_dex_Tag_i(C_TAG_WIDTH-C_TAG_DECODE_BITS-1 downto 0)   <= usDMA_dex_Tag_i(C_TAG_WIDTH-C_TAG_DECODE_BITS-1 downto 0) + X"1";
1206 
              else
1207 
                usDMA_dex_Tag_i   <= usDMA_dex_Tag_i;
1208 
              end if;
1209 
 
1210 
              if trn_rd_r1(C_CPLD_TAG_BIT_TOP downto C_CPLD_TAG_BIT_BOT)=dsDMA_dex_Tag_i and CplD_is_the_Last = '1' then
1211 
                dsDMA_dex_Tag_i(C_TAG_WIDTH-C_TAG_DECODE_BITS-1 downto 0)   <= dsDMA_dex_Tag_i(C_TAG_WIDTH-C_TAG_DECODE_BITS-1 downto 0) + X"1";
1212 
              else
1213 
                dsDMA_dex_Tag_i   <= dsDMA_dex_Tag_i;
1214 
              end if;
1215 
 
1216 
           when ST_CplD_AFetch_Special =>
1217 
 
1218 
              if  trn_rd_r1(C_CPLD_TAG_BIT_TOP downto C_CPLD_TAG_BIT_BOT)=usDMA_dex_Tag_i and CplD_is_the_Last = '1' then
1219 
                usDMA_dex_Tag_i(C_TAG_WIDTH-C_TAG_DECODE_BITS-1 downto 0)   <= usDMA_dex_Tag_i(C_TAG_WIDTH-C_TAG_DECODE_BITS-1 downto 0) + X"1";
1220 
              else
1221 
                usDMA_dex_Tag_i   <= usDMA_dex_Tag_i;
1222 
              end if;
1223 
 
1224 
              if trn_rd_r1(C_CPLD_TAG_BIT_TOP downto C_CPLD_TAG_BIT_BOT)=dsDMA_dex_Tag_i and CplD_is_the_Last = '1' then
1225 
                dsDMA_dex_Tag_i(C_TAG_WIDTH-C_TAG_DECODE_BITS-1 downto 0)   <= dsDMA_dex_Tag_i(C_TAG_WIDTH-C_TAG_DECODE_BITS-1 downto 0) + X"1";
1226 
              else
1227 
                dsDMA_dex_Tag_i   <= dsDMA_dex_Tag_i;
1228 
              end if;
1229 
 
1230 
           when Others =>
1231 
              usDMA_dex_Tag_i   <= usDMA_dex_Tag_i;
1232 
              dsDMA_dex_Tag_i   <= dsDMA_dex_Tag_i;
1233 
 
1234 
         end case;
1235 
 
1236 
      end if;
1237 
   end process;
1238 
 
1239 
 
1240 
-- -------------------------------------------------------------
1241 
--   RAM holding downstream Tags of packet MRd requests
1242 
-- -------------------------------------------------------------
1243 
 
1244 
   tRAM_addra    <= CplD_Tag(C_TAGRAM_AWIDTH-1 downto 0);
1245 
   tRAM_weB_i(0) <= tRAM_weB;
1246 
 
1247 
   dspTag_BRAM:
1248 
   FF_TagRam64x36
1249 
     port map(
1250 
              clk       =>  trn_clk    ,
1251 
 
1252 
              wea       =>  tRAM_wea(0)   ,
1253 
              addra     =>  tRAM_addra ,
1254 
              dina      =>  tRAM_dina  ,
1255 
              douta     =>  tRAM_doutA ,
1256 
 
1257 
              web       =>  tRAM_weB_i(0) ,
1258 
              addrb     =>  tRAM_addrB ,
1259 
              dinb      =>  tRAM_dinB  ,
1260 
              doutb     =>  open
1261 
             );
1262 
 
1263 
 
1264 
--   dspTag_BRAM:
1265 
--   v5tagram64x36
1266 
--     port map(
1267 
--              clka      =>  trn_clk    ,
1268 
--              addra     =>  tRAM_addra ,
1269 
--              wea       =>  tRAM_wea   ,
1270 
--              dina      =>  tRAM_dina  ,
1271 
--              douta     =>  tRAM_doutA ,
1272 
--              clkb      =>  trn_clk    ,
1273 
--              addrb     =>  tRAM_addrB ,
1274 
--              web       =>  tRAM_weB_i ,
1275 
--              dinb      =>  tRAM_dinB  ,
1276 
--              doutb     =>  open
1277 
--             );
1278 
 
1279 
 
1280 
-- -----------------------------------------------------------------------------------
1281 
-- Synchronous delay: CplD_is_the_Last
1282 
--
1283 
   Syn_Delay_CplD_is_the_Last:
1284 
   process ( trn_clk )
1285 
   begin
1286 
      if trn_clk'event and trn_clk = '1' then
1287 
         CplD_is_the_Last_r1  <= CplD_is_the_Last;
1288 
      end if;
1289 
   end process;
1290 
 
1291 
-- -----------------------------------------------------------------------------------
1292 
-- Synchronous output: Updates_tRAM
1293 
--                     Update happens only at data TLP
1294 
--                     The last CplD of one MRd does not trigger tRAM update,
1295 
--                         to enable back-to-back transactions.
1296 
--
1297 
   RxFSM_Output_Updates_tRAM:
1298 
   process ( trn_clk, Local_Reset_i)
1299 
   begin
1300 
      if Local_Reset_i = '1' then
1301 
         Updates_tRAM <= '0';
1302 
 
1303 
      elsif trn_clk'event and trn_clk = '1' then
1304 
 
1305 
            Updates_tRAM   <=  CplD_State_is_AFetch
1306 
                           and DSP_Tag_on_RAM_r1
1307 
--                           and not trn_rx_throttle    -- trn_rsrc_rdy_n_r1
1308 
                           and not CplD_is_the_Last_r1
1309 
                           ;
1310 
 
1311 
      end if;
1312 
   end process;
1313 
 
1314 
 
1315 
-- -----------------------------------------------------------------------------------
1316 
-- Synchronous output: Update_was_too_late
1317 
--                     For 1DW CplD the update might be too late for the
1318 
--                     next CplD with the same TAG
1319 
--
1320 
   RxFSM_Output_Update_was_too_late:
1321 
   process ( trn_clk, Local_Reset_i)
1322 
   begin
1323 
      if Local_Reset_i = '1' then
1324 
         Update_was_too_late     <= '0';
1325 
         hazard_tag              <= (OTHERS=>'1');
1326 
         tag_matches_hazard      <= '0';
1327 
         hazard_update           <= '0';
1328 
         hazard_update_r1        <= '0';
1329 
         hazard_update_r2        <= '0';
1330 
         hazard_update_r3        <= '0';
1331 
      elsif trn_clk'event and trn_clk = '1' then
1332 
 
1333 
         if Small_CplD_r1='1' and CplD_State_is_after_AFetch='1' then
1334 
           hazard_update          <= '1';
1335 
           hazard_tag             <= CplD_Tag;
1336 
         else
1337 
           hazard_update          <= '0';
1338 
           hazard_tag             <= hazard_tag;
1339 
         end if;
1340 
 
1341 
         if CplD_Tag=hazard_tag then
1342 
            tag_matches_hazard    <= '1';
1343 
         else
1344 
            tag_matches_hazard    <= '0';
1345 
         end if;
1346 
 
1347 
         hazard_update_r1       <= hazard_update;
1348 
         hazard_update_r2       <= hazard_update_r1;
1349 
         hazard_update_r3       <= hazard_update_r2;
1350 
 
1351 
--         Update_was_too_late    <= hazard_update_r1 or hazard_update_r2 or hazard_update_r3;
1352 
         Update_was_too_late    <= hazard_update or hazard_update_r1 or hazard_update_r2 or hazard_update_r3;
1353 
      end if;
1354 
   end process;
1355 
 
1356 
 
1357 
-- ---------------------------------------------
1358 
-- Delay Synchronous Delay: Updates_tRAM
1359 
--
1360 
   RxFSM_Delay_Updates_tRAM:
1361 
   process ( trn_clk )
1362 
   begin
1363 
       if trn_clk'event and trn_clk = '1' then
1364 
         Updates_tRAM_r1     <= Updates_tRAM;
1365 
      end if;
1366 
   end process;
1367 
 
1368 
 
1369 
-- ---------------------------------------------
1370 
-- Synchronous Delay: tRAM_DoutA_r2
1371 
--
1372 
   Delay_tRAM_DoutA:
1373 
   process ( trn_clk )
1374 
   begin
1375 
      if trn_clk'event and trn_clk = '1' then
1376 
 
1377 
----         if CplD_State_is_AFetch='1' then    -- [ avoid confilict in simulation, can be removed ]
1378 
--            if TLB_Hit='1'
1379 
--               and TLB_Valid='1'               -- [ only for simulation. can be removed for imp.]
1380 
--               then
1381 
--               tRAM_DoutA_r1 <= TLB_Content;
1382 
--            else
1383 
--               tRAM_DoutA_r1 <= tRAM_doutA;
1384 
--            end if;
1385 
----         else
1386 
----            tRAM_DoutA_r1 <= tRAM_DoutA_r1;
1387 
----         end if;
1388 
 
1389 
         if Update_was_too_late='1' and tag_matches_hazard='1' then
1390 
           tRAM_DoutA_r1 <= hazard_content;
1391 
         else
1392 
           tRAM_DoutA_r1 <= tRAM_doutA;
1393 
         end if;
1394 
--         tRAM_DoutA_r1 <= tRAM_doutA;
1395 
         tRAM_DoutA_r2 <= tRAM_DoutA_r1;
1396 
 
1397 
      end if;
1398 
   end process;
1399 
 
1400 
 
1401 
-- ---------------------------------------------
1402 
-- Synchronous Output: hazard_content
1403 
--
1404 
   Syn_Reg_hazard_content:
1405 
   process ( trn_clk, Local_Reset_i)
1406 
   begin
1407 
      if Local_Reset_i = '1' then
1408 
         hazard_content  <= (OTHERS =>'1');
1409 
      elsif trn_clk'event and trn_clk = '1' then
1410 
         if tRAM_wea(0)='1' then
1411 
            hazard_content  <= tRAM_dina;
1412 
         else
1413 
            hazard_content  <= hazard_content;
1414 
         end if;
1415 
      end if;
1416 
   end process;
1417 
 
1418 
 
1419 
-- ---------------------------------------------
1420 
-- Synchronous Calculation: tRAM_dina_aInc
1421 
--
1422 
   Syn_Calc_tRAM_dina_aInc:
1423 
   process ( trn_clk, Local_Reset_i)
1424 
   begin
1425 
      if Local_Reset_i = '1' then
1426 
         tRAM_dina_aInc  <= (CBIT_AINC_IN_TAGRAM=>'1',
1427 
                             OTHERS =>'0'
1428 
                            );
1429 
      elsif trn_clk'event and trn_clk = '1' then
1430 
         tRAM_dina_aInc(C_TAGBAR_BIT_TOP downto C_TAGBAR_BIT_BOT)
1431 
                         <= tRAM_DoutA_r1(C_TAGBAR_BIT_TOP downto C_TAGBAR_BIT_BOT);
1432 
         tRAM_dina_aInc(C_TAGBAR_BIT_BOT-1 downto 0)                   --C_EP_AWIDTH  !!!!!
1433 
                         <= tRAM_DoutA_r1(C_TAGBAR_BIT_BOT-1 downto 0) --C_EP_AWIDTH  !!!!!
1434 
                          + CplD_Leng_in_Bytes_r1(C_TLP_FLD_WIDTH_OF_LENG+2 downto  0) ;
1435 
      end if;
1436 
   end process;
1437 
 
1438 
 
1439 
   tRAM_wea(0)  <= Updates_tRAM_r1;
1440 
   tRAM_dina    <= tRAM_dina_aInc;
1441 
--   tRAM_dina    <=   ('1' & tRAM_dina_aInc(C_TAGRAM_DWIDTH-1-1 downto 0))
1442 
--                     when Addr_Inc='1'
1443 
--                     else ('0' & tRAM_DoutA_r2(C_TAGRAM_DWIDTH-1-1 downto 0));
1444 
 
1445 
 
1446 
-- ---------------------------------------------
1447 
-- Synchronous Calculation: tRAM_DoutA_latch
1448 
--
1449 
   Syn_tRAM_DoutA_latch:
1450 
   process ( trn_clk, Local_Reset_i)
1451 
   begin
1452 
      if Local_Reset_i = '1' then
1453 
         tRAM_DoutA_latch  <= (CBIT_AINC_IN_TAGRAM=>'1',OTHERS =>'0');
1454 
      elsif trn_clk'event and trn_clk = '1' then
1455 
         if CplD_State_is_AFetch_r1='0' then
1456 
           tRAM_DoutA_latch <= tRAM_DoutA_latch;
1457 
         elsif Update_was_too_late='1' then
1458 
           tRAM_DoutA_latch <= tRAM_DoutA_r1;
1459 
         else
1460 
           tRAM_DoutA_latch <= tRAM_DoutA;
1461 
         end if;
1462 
      end if;
1463 
   end process;
1464 
 
1465 
-- ---------------------------------------------
1466 
-- Synchronous Output: TLB  (not used)
1467 
--
1468 
   Syn_Reg_TLB_Operation:
1469 
   process ( trn_clk, Local_Reset_i)
1470 
   begin
1471 
      if Local_Reset_i = '1' then
1472 
         TLB_Addr     <= (OTHERS =>'1');
1473 
         TLB_Content  <= (OTHERS =>'0');
1474 
         TLB_cnt      <= (OTHERS =>'0');
1475 
         TLB_Valid    <= '0';
1476 
         TLB_Hit      <= '0';
1477 
      elsif trn_clk'event and trn_clk = '1' then
1478 
 
1479 
         if Updates_tRAM_r1='0' then
1480 
            TLB_Content  <= TLB_Content;
1481 
            TLB_Addr     <= TLB_Addr;
1482 
            if TLB_cnt=C_ALL_ZEROS(3 downto 0) then
1483 
               TLB_cnt      <= TLB_cnt;
1484 
               TLB_Valid    <= '0';
1485 
            else
1486 
               TLB_cnt      <= TLB_cnt - '1';
1487 
               TLB_Valid    <= '1';
1488 
            end if;
1489 
         else
1490 
            TLB_Addr     <= tRAM_addra;
1491 
            TLB_cnt      <= C_TLB_VALID_CNT;
1492 
            TLB_Valid    <= '0';
1493 
            if Addr_Inc='1' then
1494 
               TLB_Content  <= '1' & tRAM_dina_aInc(C_TAGRAM_DWIDTH-1-1 downto 0);
1495 
            else
1496 
               TLB_Content  <= '0' & tRAM_DoutA_r2(C_TAGRAM_DWIDTH-1-1 downto 0);
1497 
            end if;
1498 
         end if;
1499 
 
1500 
         if TLB_Addr=tRAM_addra then
1501 
            TLB_Hit      <= '1';
1502 
         else
1503 
            TLB_Hit      <= '0';
1504 
         end if;
1505 
 
1506 
      end if;
1507 
   end process;
1508 
 
1509 
 
1510 
-- -------------------------------------------------
1511 
-- Synchronous outputs: DDR_Space_Hit
1512 
--
1513 
   RxFSM_Output_DDR_Space_Hit:
1514 
   process ( trn_clk, Local_Reset_i)
1515 
   begin
1516 
      if Local_Reset_i = '1' then
1517 
         DDR_Space_Hit  <= '0';
1518 
         DDR_wr_sof_i   <= '0';
1519 
         DDR_wr_eof_i   <= '0';
1520 
         DDR_wr_v_i     <= '0';
1521 
         DDR_wr_FA_i    <= '0';
1522 
         DDR_wr_Shift_i <= '0';
1523 
         DDR_wr_Mask_i  <= (OTHERS=>'0');
1524 
         DDR_wr_din_i   <= (OTHERS=>'0');
1525 
 
1526 
      elsif trn_clk'event and trn_clk = '1' then
1527 
 
1528 
         case RxCplDTrn_State_r1 is
1529 
 
1530 
            when ST_CplD_RESET =>
1531 
               DDR_Space_Hit  <= '0';
1532 
               DDR_wr_sof_i   <= '0';
1533 
               DDR_wr_eof_i   <= '0';
1534 
               DDR_wr_v_i     <= '0';
1535 
               DDR_wr_FA_i    <= '0';
1536 
               DDR_wr_Shift_i <= '0';
1537 
               DDR_wr_Mask_i  <= (OTHERS=>'0');
1538 
               DDR_wr_din_i   <= (OTHERS=>'0');
1539 
 
1540 
 
1541 
            when  ST_CplD_AFetch =>
1542 
               if trn_reof_n_r4='0' then
1543 
                  DDR_Space_Hit  <= DSP_Tag_on_RAM_r1;
1544 
                  DDR_wr_sof_i   <= '0';
1545 
                  DDR_wr_eof_i   <= DSP_Tag_on_RAM_r4p;
1546 
                  DDR_wr_v_i     <= DSP_Tag_on_RAM_r4p; -- DSP_Tag_on_RAM;  -- and not (trn_rx_throttle_r4 and trn_reof_n_r4);
1547 
                  DDR_wr_FA_i    <= '0';
1548 
                  DDR_wr_Shift_i <= '0';
1549 
                  DDR_wr_din_i   <= trn_rd_Little_r4;
1550 
                  DDR_wr_Mask_i  <= '0' & (trn_rrem_n_r4(3) or trn_rrem_n_r4(0));
1551 
               elsif DSP_Tag_on_RAM_r1 ='1' then
1552 
                                                DDR_Space_Hit  <= '1';
1553 
                  DDR_wr_sof_i   <= '0';
1554 
                  DDR_wr_eof_i   <= '0';
1555 
                  DDR_wr_v_i     <= '0'; -- not trn_rx_throttle_r1;
1556 
                  DDR_wr_FA_i    <= '0';
1557 
                  DDR_wr_Shift_i <= '0';
1558 
                  DDR_wr_Mask_i  <= (OTHERS=>'0');
1559 
                  DDR_wr_din_i   <= (OTHERS=>'0');
1560 
               else
1561 
                  DDR_Space_Hit  <= '0';
1562 
                  DDR_wr_sof_i   <= '0';
1563 
                  DDR_wr_eof_i   <= '0';
1564 
                  DDR_wr_v_i     <= '0';
1565 
                  DDR_wr_FA_i    <= '0';
1566 
                  DDR_wr_Shift_i <= '0';
1567 
                  DDR_wr_Mask_i  <= (OTHERS=>'0');
1568 
                  DDR_wr_din_i   <= (OTHERS=>'0');
1569 
               end if;
1570 
 
1571 
            when  ST_CplD_AFetch_Special =>
1572 
               if DSP_Tag_on_RAM_r1 ='1' then
1573 
                                                DDR_Space_Hit  <= '1';
1574 
--                  DDR_wr_sof_i   <= '0';
1575 
--                  DDR_wr_eof_i   <= '0';
1576 
--                  DDR_wr_v_i     <= '0'; -- not trn_rx_throttle_r1;
1577 
--                  DDR_wr_FA_i    <= '0';
1578 
--                  DDR_wr_Shift_i <= '0';
1579 
--                  DDR_wr_Mask_i  <= (OTHERS=>'0');
1580 
--                  DDR_wr_din_i   <= (OTHERS=>'0');
1581 
                                        else
1582 
                                                DDR_Space_Hit  <= '0';
1583 
--                  DDR_wr_sof_i   <= '0';
1584 
--                  DDR_wr_eof_i   <= '0';
1585 
--                  DDR_wr_v_i     <= '0';
1586 
--                  DDR_wr_FA_i    <= '0';
1587 
--                  DDR_wr_Shift_i <= '0';
1588 
--                  DDR_wr_Mask_i  <= (OTHERS=>'0');
1589 
--                  DDR_wr_din_i   <= (OTHERS=>'0');
1590 
                                        end if;
1591 
               DDR_wr_sof_i   <= '0';
1592 
               DDR_wr_eof_i   <= not trn_reof_n_r4 and DDR_Space_Hit;
1593 
               DDR_wr_v_i     <= (not (trn_rx_throttle_r4 and trn_reof_n_r4)) and DDR_Space_Hit;
1594 
               DDR_wr_FA_i    <= '0';
1595 
               DDR_wr_Shift_i <= '0';
1596 
               DDR_wr_din_i   <= trn_rd_Little_r4;
1597 
               DDR_wr_Mask_i  <= '0' & (trn_rrem_n_r4(3) or trn_rrem_n_r4(0));
1598 
 
1599 
 
1600 
            when  ST_CplD_AFetch_Special_Tail =>
1601 
               DDR_Space_Hit  <= DDR_Space_Hit;
1602 
               DDR_wr_sof_i   <= DDR_Space_Hit;  -- '1';
1603 
               DDR_wr_eof_i   <= '0';
1604 
               DDR_wr_v_i     <= DDR_Space_Hit;  -- '1'; -- not trn_rx_throttle_r1;
1605 
               DDR_wr_FA_i    <= '0';
1606 
               DDR_wr_Mask_i  <= (OTHERS=>'0');
1607 
               if Update_was_too_late='1' and tag_matches_hazard='1' then
1608 
                 DDR_wr_Shift_i <= not hazard_content(2);
1609 
                 DDR_wr_din_i   <= CplD_Leng_in_Bytes_r1(32-1 downto 0) & hazard_content(32-1 downto 0);
1610 
               else
1611 
                 DDR_wr_Shift_i <= not tRAM_DoutA_r1(2);
1612 
                 DDR_wr_din_i   <= CplD_Leng_in_Bytes_r1(32-1 downto 0) & tRAM_DoutA_r1(32-1 downto 0);
1613 
               end if;
1614 
 
1615 
 
1616 
            when  ST_CplD_AFetch_THROTTLE =>
1617 
               DDR_Space_Hit  <= DDR_Space_Hit;
1618 
               DDR_wr_sof_i   <= '0';
1619 
               DDR_wr_eof_i   <= '0';
1620 
               DDR_wr_v_i     <= '0';
1621 
               DDR_wr_FA_i    <= '0';
1622 
               DDR_wr_Shift_i <= '0';
1623 
               DDR_wr_Mask_i  <= (OTHERS=>'0');
1624 
               DDR_wr_din_i   <= DDR_wr_din_i;
1625 
 
1626 
 
1627 
            when  ST_CplD_1ST_DATA =>
1628 
               DDR_Space_Hit  <= DDR_Space_Hit;
1629 
               DDR_wr_sof_i   <= DDR_Space_Hit;  -- '1';
1630 
               DDR_wr_eof_i   <= '0';
1631 
               DDR_wr_v_i     <= DDR_Space_Hit;  -- '1'; -- not trn_rx_throttle_r1;
1632 
               DDR_wr_FA_i    <= '0';
1633 
               DDR_wr_Mask_i  <= (OTHERS=>'0');
1634 
               if Update_was_too_late='1' and tag_matches_hazard='1' then
1635 
                 DDR_wr_Shift_i <= not hazard_content(2);
1636 
                 DDR_wr_din_i   <= CplD_Leng_in_Bytes_r1(32-1 downto 0) & hazard_content(32-1 downto 0);
1637 
               elsif CplD_State_is_AFetch_r1 = '0' then
1638 
                 DDR_wr_Shift_i <= not tRAM_DoutA_latch(2);
1639 
                 DDR_wr_din_i   <= CplD_Leng_in_Bytes_r1(32-1 downto 0) & tRAM_DoutA_latch(32-1 downto 0);
1640 
               else
1641 
                 DDR_wr_Shift_i <= not tRAM_DoutA_r1(2);
1642 
                 DDR_wr_din_i   <= CplD_Leng_in_Bytes_r1(32-1 downto 0) & tRAM_DoutA_r1(32-1 downto 0);
1643 
               end if;
1644 
 
1645 
 
1646 
            when ST_CplD_ONLY_1DW =>
1647 
               DDR_Space_Hit  <= DDR_Space_Hit;
1648 
               DDR_wr_sof_i   <= DDR_Space_Hit;  -- '1';
1649 
               DDR_wr_eof_i   <= '0';
1650 
               DDR_wr_v_i     <= DDR_Space_Hit;  -- '1'; -- not trn_rx_throttle_r1;
1651 
               DDR_wr_FA_i    <= '0';
1652 
               DDR_wr_Mask_i  <= (OTHERS=>'0');
1653 
               if Update_was_too_late='1' and tag_matches_hazard='1' then
1654 
                 DDR_wr_Shift_i <= not hazard_content(2);
1655 
                 DDR_wr_din_i   <= CplD_Leng_in_Bytes_r1(32-1 downto 0) & hazard_content(32-1 downto 0);
1656 
               elsif CplD_State_is_AFetch_r1 = '0' then
1657 
                 DDR_wr_Shift_i <= not tRAM_DoutA_latch(2);
1658 
                 DDR_wr_din_i   <= CplD_Leng_in_Bytes_r1(32-1 downto 0) & tRAM_DoutA_latch(32-1 downto 0);
1659 
               else
1660 
                 DDR_wr_Shift_i <= not tRAM_DoutA_r1(2);
1661 
                 DDR_wr_din_i   <= CplD_Leng_in_Bytes_r1(32-1 downto 0) & tRAM_DoutA_r1(32-1 downto 0);
1662 
               end if;
1663 
 
1664 
 
1665 
            when OTHERS =>
1666 
               if trn_reof_n_r4='0' then
1667 
                  DDR_Space_Hit  <= '0';
1668 
               else
1669 
                  DDR_Space_Hit  <= DDR_Space_Hit;
1670 
               end if;
1671 
 
1672 
               DDR_wr_sof_i   <= '0';
1673 
               DDR_wr_eof_i   <= not trn_reof_n_r4 and DDR_Space_Hit;
1674 
               DDR_wr_v_i     <= (DDR_wr_sof_i or not (trn_rx_throttle_r4 and trn_reof_n_r4)) and DDR_Space_Hit;
1675 
               DDR_wr_FA_i    <= '0';
1676 
               DDR_wr_Shift_i <= '0';
1677 
               DDR_wr_din_i   <= trn_rd_Little_r4;
1678 
               if DDR_wr_sof_i='1' then
1679 
                  DDR_wr_Mask_i  <= "10";
1680 
               else
1681 
                  DDR_wr_Mask_i  <= '0' & (trn_rrem_n_r4(3) or trn_rrem_n_r4(0));
1682 
               end if;
1683 
 
1684 
         end case;
1685 
 
1686 
      end if;
1687 
   end process;
1688 
 
1689 
 
1690 
 
1691 
   concat_rd  <= trn_rd_r1(32-1 downto 0) & trn_rd_i(64-1 downto 32);
1692 
 
1693 
-- -------------------------------------------------
1694 
-- Synchronous outputs: eb_FIFO_Write
1695 
--
1696 
   RxFSM_Output_FIFO_Space_Hit:
1697 
   process ( trn_clk, Local_Reset_i)
1698 
   begin
1699 
      if Local_Reset_i = '1' then
1700 
         eb_FIFO_we_i   <= '0';
1701 
         eb_FIFO_wsof_i <= '0';
1702 
         eb_FIFO_weof_i <= '0';
1703 
         eb_FIFO_sof_marker <= '0';
1704 
         eb_FIFO_din_i  <= (OTHERS=>'0');
1705 
         EB_Write_State <= ST_EBWR_IDLE;
1706 
 
1707 
      elsif trn_clk'event and trn_clk = '1' then
1708 
 
1709 
         case EB_Write_State is
1710 
 
1711 
            when ST_EBWR_IDLE =>
1712 
               eb_FIFO_we_i    <= '0';
1713 
               eb_FIFO_wsof_i  <= '0';
1714 
               eb_FIFO_weof_i  <= '0';
1715 
               eb_FIFO_sof_marker  <= '0';
1716 
               eb_FIFO_din_i   <= (OTHERS=>'0');
1717 
               if trn_rx_throttle='0'
1718 
                  and CplD_Type=C_TLP_TYPE_IS_CPLD
1719 
                  and trn_rd_i(0)='0'              -- Odd-DW CplD is illegal
1720 
                  then
1721 
                  EB_Write_State  <= ST_EBWR_TAG;
1722 
               else
1723 
                  EB_Write_State  <= ST_EBWR_IDLE;
1724 
               end if;
1725 
 
1726 
            when  ST_EBWR_TAG =>
1727 
               eb_FIFO_we_i    <= '0';
1728 
               eb_FIFO_wsof_i  <= '0';
1729 
               eb_FIFO_weof_i  <= '0';
1730 
               eb_FIFO_din_i   <= (OTHERS=>'0');
1731 
               if trn_rsof_n_i='0' then
1732 
                  eb_FIFO_sof_marker  <= '0';
1733 
                  EB_Write_State  <= ST_EBWR_TAG;
1734 
               elsif trn_rx_throttle='0' and DSP_Tag_on_FIFO='1' then
1735 
                  eb_FIFO_sof_marker  <= '1';
1736 
                  EB_Write_State  <= ST_EBWR_DATA;
1737 
               else
1738 
                  eb_FIFO_sof_marker  <= '0';
1739 
                  EB_Write_State  <= ST_EBWR_IDLE;
1740 
               end if;
1741 
 
1742 
            when  ST_EBWR_DATA =>
1743 
               eb_FIFO_we_i    <= not trn_rx_throttle;
1744 
               eb_FIFO_wsof_i  <= eb_FIFO_sof_marker and not trn_rx_throttle;
1745 
               eb_FIFO_sof_marker  <= eb_FIFO_sof_marker and trn_rx_throttle;
1746 
               eb_FIFO_din_i   <= Endian_Invert_64(concat_rd);
1747 
               if trn_rx_throttle='0' and trn_reof_n_i='0' then
1748 
                  eb_FIFO_weof_i  <= '1';
1749 
                  EB_Write_State  <= ST_EBWR_IDLE;
1750 
               else
1751 
                  eb_FIFO_weof_i  <= '0';
1752 
                  EB_Write_State  <= ST_EBWR_DATA;
1753 
               end if;
1754 
 
1755 
 
1756 
            when OTHERS =>
1757 
               eb_FIFO_we_i    <= '0';
1758 
               eb_FIFO_wsof_i  <= '0';
1759 
               eb_FIFO_weof_i  <= '0';
1760 
               eb_FIFO_sof_marker  <= '0';
1761 
               eb_FIFO_din_i   <= (OTHERS=>'0');
1762 
               EB_Write_State  <= ST_EBWR_IDLE;
1763 
 
1764 
         end case;
1765 
 
1766 
      end if;
1767 
   end process;
1768 
 
1769 
 
1770 
end architecture Behavioral;

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