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[/] [pcie_sg_dma/] [branches/] [Virtex6/] [ML605_ISE12.3/] [pcie_sg_dma/] [Virtex6/] [ML605/] [tlpControl.vhd] - Blame information for rev 11

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Line No. Rev Author Line
1 11 barabba 
----------------------------------------------------------------------------------
2 
-- Company:
3 
-- Engineer:
4 
--
5 
-- Create Date:    11:09:49 10/18/2006
6 
-- Design Name:
7 
-- Module Name:    tlpControl - Behavioral
8 
-- Project Name:
9 
-- Target Devices:
10 
-- Tool versions:
11 
-- Description:
12 
--
13 
-- Dependencies:
14 
--
15 
-- Revision 1.20 - Memory space repartitioned.   13.07.2007
16 
--
17 
-- Revision 1.10 - x4 timing constraints met.   02.02.2007
18 
--
19 
-- Revision 1.06 - Timing improved.     17.01.2007
20 
--
21 
-- Revision 1.04 - FIFO added.     20.12.2006
22 
--
23 
-- Revision 1.02 - second release. 14.12.2006
24 
--
25 
-- Revision 1.00 - first release.  18.10.2006
26 
--
27 
-- Additional Comments:
28 
--
29 
----------------------------------------------------------------------------------
30 
 
31 
library IEEE;
32 
use IEEE.STD_LOGIC_1164.ALL;
33 
use IEEE.STD_LOGIC_ARITH.ALL;
34 
use IEEE.STD_LOGIC_UNSIGNED.ALL;
35 
 
36 
library work;
37 
use work.abb64Package.all;
38 
--use work.busmacro_xc4v_pkg.all;
39 
 
40 
-- Uncomment the following library declaration if instantiating
41 
-- any Xilinx primitives in this code.
42 
--library UNISIM;
43 
--use UNISIM.VComponents.all;
44 
 
45 
entity tlpControl is
46 
    port (
47 
 
48 
      --  Test pin, emulating DDR data flow discontinuity
49 
      mbuf_UserFull            : IN   std_logic;
50 
      trn_Blinker              : OUT  std_logic;
51 
 
52 
      -- DCB protocol interface
53 
      protocol_link_act        : IN  std_logic_vector(2-1 downto 0);
54 
      protocol_rst             : OUT std_logic;
55 
 
56 
      -- Interrupter triggers
57 
      DAQ_irq                  : IN  std_logic;
58 
      CTL_irq                  : IN  std_logic;
59 
      DLM_irq                  : IN  std_logic;
60 
 
61 
      -- Fabric side: CTL Rx
62 
      ctl_rv                   : OUT std_logic;
63 
      ctl_rd                   : OUT std_logic_vector(C_DBUS_WIDTH/2-1 downto 0);
64 
 
65 
      -- Fabric side: CTL Tx
66 
      ctl_ttake                : OUT std_logic;
67 
      ctl_tv                   : IN  std_logic;
68 
      ctl_td                   : IN  std_logic_vector(C_DBUS_WIDTH/2-1 downto 0);
69 
      ctl_tstop                : OUT std_logic;
70 
 
71 
      ctl_reset                : OUT std_logic;
72 
      ctl_status               : IN  std_logic_vector(C_DBUS_WIDTH/2-1 downto 0);
73 
 
74 
      -- Fabric side: DLM Rx
75 
      dlm_tv                   : OUT std_logic;
76 
      dlm_td                   : OUT std_logic_vector(C_DBUS_WIDTH/2-1 downto 0);
77 
 
78 
      -- Fabric side: DLM Tx
79 
      dlm_rv                   : IN  std_logic;
80 
      dlm_rd                   : IN  std_logic_vector(C_DBUS_WIDTH/2-1 downto 0);
81 
 
82 
      -- Event Buffer FIFO interface
83 
      eb_FIFO_we               : OUT std_logic;
84 
      eb_FIFO_wsof             : OUT std_logic;
85 
      eb_FIFO_weof             : OUT std_logic;
86 
      eb_FIFO_din              : OUT std_logic_vector(C_DBUS_WIDTH-1 downto 0);
87 
      eb_FIFO_re               : OUT std_logic;
88 
      eb_FIFO_empty            : IN  std_logic;
89 
      eb_FIFO_qout             : IN  std_logic_vector(C_DBUS_WIDTH-1 downto 0);
90 
      eb_FIFO_ow               : IN  std_logic;
91 
 
92 
      eb_FIFO_data_count       : IN  std_logic_vector(C_FIFO_DC_WIDTH downto 0);
93 
 
94 
      pio_reading_status       : OUT std_logic;
95 
      eb_FIFO_Status           : IN  std_logic_vector(C_DBUS_WIDTH-1 downto 0);
96 
      eb_FIFO_Rst              : OUT std_logic;
97 
 
98 
      Link_Buf_full            : IN  std_logic;
99 
 
100 
      -- Debugging signals
101 
      DMA_us_Done              : OUT std_logic;
102 
      DMA_us_Busy              : OUT std_logic;
103 
      DMA_us_Busy_LED          : OUT std_logic;
104 
      DMA_ds_Done              : OUT std_logic;
105 
      DMA_ds_Busy              : OUT std_logic;
106 
      DMA_ds_Busy_LED          : OUT std_logic;
107 
 
108 
      -- DDR control interface
109 
      DDR_Ready                : IN    std_logic;
110 
 
111 
      DDR_wr_sof               : OUT   std_logic;
112 
      DDR_wr_eof               : OUT   std_logic;
113 
      DDR_wr_v                 : OUT   std_logic;
114 
      DDR_wr_FA                : OUT   std_logic;
115 
      DDR_wr_Shift             : OUT   std_logic;
116 
      DDR_wr_Mask              : OUT   std_logic_vector(2-1 downto 0);
117 
      DDR_wr_din               : OUT   std_logic_vector(C_DBUS_WIDTH-1 downto 0);
118 
      DDR_wr_full              : IN    std_logic;
119 
 
120 
      DDR_rdc_sof              : OUT   std_logic;
121 
      DDR_rdc_eof              : OUT   std_logic;
122 
      DDR_rdc_v                : OUT   std_logic;
123 
      DDR_rdc_FA               : OUT   std_logic;
124 
      DDR_rdc_Shift            : OUT   std_logic;
125 
      DDR_rdc_din              : OUT   std_logic_vector(C_DBUS_WIDTH-1 downto 0);
126 
      DDR_rdc_full             : IN    std_logic;
127 
 
128 
--      DDR_rdD_sof              : IN    std_logic;
129 
--      DDR_rdD_eof              : IN    std_logic;
130 
--      DDR_rdDout_V             : IN    std_logic;
131 
--      DDR_rdDout               : IN    std_logic_vector(C_DBUS_WIDTH-1 downto 0);
132 
 
133 
      -- DDR payload FIFO Read Port
134 
      DDR_FIFO_RdEn            : OUT std_logic;
135 
      DDR_FIFO_Empty           : IN  std_logic;
136 
      DDR_FIFO_RdQout          : IN  std_logic_vector(C_DBUS_WIDTH-1 downto 0);
137 
 
138 
      -- Data generator table write
139 
      tab_we                   : OUT std_logic_vector(2-1 downto 0);
140 
      tab_wa                   : OUT std_logic_vector(12-1 downto 0);
141 
      tab_wd                   : OUT std_logic_vector(C_DBUS_WIDTH-1 downto 0);
142 
 
143 
      DG_is_Running            : IN  std_logic;
144 
      DG_Reset                 : OUT std_logic;
145 
      DG_Mask                  : OUT std_logic;
146 
 
147 
      -- Common interface
148 
      trn_clk                  : IN  std_logic;
149 
      trn_reset_n              : IN  std_logic;
150 
      trn_lnk_up_n             : IN  std_logic;
151 
 
152 
      -- Transaction receive interface
153 
      trn_rsof_n               : IN  std_logic;
154 
      trn_reof_n               : IN  std_logic;
155 
      trn_rd                   : IN  std_logic_vector(C_DBUS_WIDTH-1 downto 0);
156 
      trn_rrem_n               : IN  std_logic_vector(C_DBUS_WIDTH/8-1 downto 0);
157 
      trn_rerrfwd_n            : IN  std_logic;
158 
      trn_rsrc_rdy_n           : IN  std_logic;
159 
      trn_rdst_rdy_n           : OUT std_logic;
160 
      trn_rnp_ok_n             : OUT std_logic;
161 
      trn_rsrc_dsc_n           : IN  std_logic;
162 
      trn_rbar_hit_n           : IN  std_logic_vector(C_BAR_NUMBER-1 downto 0);
163 
--    trn_rfc_ph_av              : IN  std_logic_vector(7 downto 0);
164 
--    trn_rfc_pd_av              : IN  std_logic_vector(11 downto 0);
165 
--    trn_rfc_nph_av             : IN  std_logic_vector(7 downto 0);
166 
--    trn_rfc_npd_av             : IN  std_logic_vector(11 downto 0);
167 
--    trn_rfc_cplh_av            : IN  std_logic_vector(7 downto 0);
168 
--    trn_rfc_cpld_av            : IN  std_logic_vector(11 downto 0);
169 
 
170 
      -- Transaction transmit interface
171 
      trn_tsof_n              : OUT std_logic;
172 
      trn_teof_n              : OUT std_logic;
173 
      trn_td                  : OUT std_logic_vector(C_DBUS_WIDTH-1 downto 0);
174 
      trn_trem_n              : OUT std_logic_vector(C_DBUS_WIDTH/8-1 downto 0);
175 
      trn_terrfwd_n           : OUT std_logic;
176 
      trn_tsrc_rdy_n          : OUT std_logic;
177 
      trn_tdst_rdy_n          : IN  std_logic;
178 
      trn_tsrc_dsc_n          : OUT std_logic;
179 
      trn_tdst_dsc_n          : IN  std_logic;
180 
      trn_tbuf_av             : IN  std_logic_vector(C_TBUF_AWIDTH-1 downto 0);
181 
 
182 
      Format_Shower           : OUT   std_logic;
183 
 
184 
      -- Interrupt Interface
185 
                cfg_interrupt_n         : OUT std_logic;
186 
                cfg_interrupt_rdy_n     : IN  std_logic;
187 
                cfg_interrupt_mmenable  : IN  std_logic_VECTOR(2 downto 0);
188 
                cfg_interrupt_msienable : IN  std_logic;
189 
                cfg_interrupt_di        : OUT std_logic_VECTOR(7 downto 0);
190 
                cfg_interrupt_do        : IN  std_logic_VECTOR(7 downto 0);
191 
                cfg_interrupt_assert_n  : OUT std_logic;
192 
 
193 
      -- Local signals
194 
      pcie_link_width         : IN  std_logic_vector(CINT_BIT_LWIDTH_IN_GSR_TOP-CINT_BIT_LWIDTH_IN_GSR_BOT downto 0);
195 
      cfg_dcommand            : IN  std_logic_vector(16-1 downto 0);
196 
      localID                 : IN  std_logic_vector(C_ID_WIDTH-1 downto 0)
197 
         );
198 
 
199 
end entity tlpControl;
200 
 
201 
 
202 
 
203 
architecture Behavioral of tlpControl is
204 
 
205 
  signal trn_lnk_up_i       : std_logic;
206 
 
207 
---- Rx transaction control
208 
  component rx_Transact
209 
    port (
210 
      -- Common ports
211 
      trn_clk            : IN  std_logic;
212 
      trn_reset_n        : IN  std_logic;
213 
      trn_lnk_up_n       : IN  std_logic;
214 
 
215 
      -- Transaction receive interface
216 
      trn_rsof_n         : IN  std_logic;
217 
      trn_reof_n         : IN  std_logic;
218 
      trn_rd             : IN  std_logic_vector(C_DBUS_WIDTH-1 downto 0);
219 
      trn_rrem_n         : IN  std_logic_vector(C_DBUS_WIDTH/8-1 downto 0);
220 
      trn_rerrfwd_n      : IN  std_logic;
221 
      trn_rsrc_rdy_n     : IN  std_logic;
222 
      trn_rdst_rdy_n     : OUT std_logic;
223 
      trn_rnp_ok_n       : OUT std_logic;
224 
      trn_rsrc_dsc_n     : IN  std_logic;
225 
      trn_rbar_hit_n     : IN  std_logic_vector(C_BAR_NUMBER-1 downto 0);
226 
 
227 
--      trn_rfc_ph_av      : IN  std_logic_vector(7 downto 0);
228 
--      trn_rfc_pd_av      : IN  std_logic_vector(11 downto 0);
229 
--      trn_rfc_nph_av     : IN  std_logic_vector(7 downto 0);
230 
--      trn_rfc_npd_av     : IN  std_logic_vector(11 downto 0);
231 
--      trn_rfc_cplh_av    : IN  std_logic_vector(7 downto 0);
232 
--      trn_rfc_cpld_av    : IN  std_logic_vector(11 downto 0);
233 
 
234 
 
235 
      -- MRd Channel
236 
      pioCplD_Req        : OUT std_logic;
237 
      pioCplD_RE         : IN  std_logic;
238 
      pioCplD_Qout       : OUT std_logic_vector(C_CHANNEL_BUF_WIDTH-1 downto 0);
239 
      pio_FC_stop        : IN  std_logic;
240 
 
241 
 
242 
      -- MRd-downstream packet Channel
243 
      dsMRd_Req          : OUT std_logic;
244 
      dsMRd_RE           : IN  std_logic;
245 
      dsMRd_Qout         : OUT std_logic_vector(C_CHANNEL_BUF_WIDTH-1 downto 0);
246 
 
247 
 
248 
      -- Upstream MWr/MRd Channel
249 
      usTlp_Req          : OUT std_logic;
250 
      usTlp_RE           : IN  std_logic;
251 
      usTlp_Qout         : OUT std_logic_vector(C_CHANNEL_BUF_WIDTH-1 downto 0);
252 
      us_FC_stop         : IN  std_logic;
253 
      us_Last_sof        : IN  std_logic;
254 
      us_Last_eof        : IN  std_logic;
255 
 
256 
      -- Irpt Channel
257 
      Irpt_Req           : OUT std_logic;
258 
      Irpt_RE            : IN  std_logic;
259 
      Irpt_Qout          : OUT std_logic_vector(C_CHANNEL_BUF_WIDTH-1 downto 0);
260 
 
261 
 
262 
      -- Interrupt Interface
263 
                cfg_interrupt_n         : OUT std_logic;
264 
                cfg_interrupt_rdy_n     : IN  std_logic;
265 
                cfg_interrupt_mmenable  : IN  std_logic_VECTOR(2 downto 0);
266 
                cfg_interrupt_msienable : IN  std_logic;
267 
                cfg_interrupt_di        : OUT std_logic_VECTOR(7 downto 0);
268 
                cfg_interrupt_do        : IN  std_logic_VECTOR(7 downto 0);
269 
                cfg_interrupt_assert_n  : OUT std_logic;
270 
 
271 
 
272 
      -- Event Buffer write port
273 
      eb_FIFO_we              : OUT std_logic;
274 
      eb_FIFO_wsof            : OUT std_logic;
275 
      eb_FIFO_weof            : OUT std_logic;
276 
      eb_FIFO_din             : OUT std_logic_vector(C_DBUS_WIDTH-1 downto 0);
277 
 
278 
      eb_FIFO_data_count      : IN  std_logic_vector(C_FIFO_DC_WIDTH downto 0);
279 
      eb_FIFO_Empty           : IN  std_logic;
280 
      eb_FIFO_Reading         : IN  std_logic;
281 
      pio_reading_status      : OUT std_logic;
282 
 
283 
      -- Registers Write Port
284 
      Regs_WrEn0         : OUT std_logic;
285 
      Regs_WrMask0       : OUT std_logic_vector(2-1 downto 0);
286 
      Regs_WrAddr0       : OUT std_logic_vector(C_EP_AWIDTH-1 downto 0);
287 
      Regs_WrDin0        : OUT std_logic_vector(C_DBUS_WIDTH-1 downto 0);
288 
 
289 
      Regs_WrEn1         : OUT std_logic;
290 
      Regs_WrMask1       : OUT std_logic_vector(2-1 downto 0);
291 
      Regs_WrAddr1       : OUT std_logic_vector(C_EP_AWIDTH-1 downto 0);
292 
      Regs_WrDin1        : OUT std_logic_vector(C_DBUS_WIDTH-1 downto 0);
293 
 
294 
      -- Downstream DMA transferred bytes count up
295 
      ds_DMA_Bytes_Add   : OUT std_logic;
296 
      ds_DMA_Bytes       : OUT std_logic_vector(C_TLP_FLD_WIDTH_OF_LENG+2 downto 0);
297 
 
298 
      -- --------------------------
299 
      -- Registers
300 
      DMA_ds_PA          : IN  std_logic_vector(C_DBUS_WIDTH-1 downto 0);
301 
      DMA_ds_HA          : IN  std_logic_vector(C_DBUS_WIDTH-1 downto 0);
302 
      DMA_ds_BDA         : IN  std_logic_vector(C_DBUS_WIDTH-1 downto 0);
303 
      DMA_ds_Length      : IN  std_logic_vector(C_DBUS_WIDTH-1 downto 0);
304 
      DMA_ds_Control     : IN  std_logic_vector(C_DBUS_WIDTH-1 downto 0);
305 
      dsDMA_BDA_eq_Null  : IN  std_logic;
306 
      DMA_ds_Status      : OUT std_logic_vector(C_DBUS_WIDTH-1 downto 0);
307 
      DMA_ds_Done        : OUT std_logic;
308 
      DMA_ds_Busy        : OUT std_logic;
309 
      DMA_ds_Tout        : OUT std_logic;
310 
 
311 
      -- Calculation in advance, for better timing
312 
      dsHA_is_64b        : IN  std_logic;
313 
      dsBDA_is_64b       : IN  std_logic;
314 
 
315 
      -- Calculation in advance, for better timing
316 
      dsLeng_Hi19b_True  : IN  std_logic;
317 
      dsLeng_Lo7b_True   : IN  std_logic;
318 
 
319 
 
320 
      dsDMA_Start        : IN  std_logic;
321 
      dsDMA_Stop         : IN  std_logic;
322 
      dsDMA_Start2       : IN  std_logic;
323 
      dsDMA_Stop2        : IN  std_logic;
324 
      dsDMA_Channel_Rst  : IN  std_logic;
325 
      dsDMA_Cmd_Ack      : OUT std_logic;
326 
 
327 
      DMA_us_PA          : IN  std_logic_vector(C_DBUS_WIDTH-1 downto 0);
328 
      DMA_us_HA          : IN  std_logic_vector(C_DBUS_WIDTH-1 downto 0);
329 
      DMA_us_BDA         : IN  std_logic_vector(C_DBUS_WIDTH-1 downto 0);
330 
      DMA_us_Length      : IN  std_logic_vector(C_DBUS_WIDTH-1 downto 0);
331 
      DMA_us_Control     : IN  std_logic_vector(C_DBUS_WIDTH-1 downto 0);
332 
      usDMA_BDA_eq_Null  : IN  std_logic;
333 
      us_MWr_Param_Vec   : IN  std_logic_vector(6-1   downto 0);
334 
      DMA_us_Status      : OUT std_logic_vector(C_DBUS_WIDTH-1 downto 0);
335 
      DMA_us_Done        : OUT std_logic;
336 
      DMA_us_Busy        : OUT std_logic;
337 
      DMA_us_Tout        : OUT std_logic;
338 
 
339 
      -- Calculation in advance, for better timing
340 
      usHA_is_64b        : IN  std_logic;
341 
      usBDA_is_64b       : IN  std_logic;
342 
 
343 
      -- Calculation in advance, for better timing
344 
      usLeng_Hi19b_True  : IN  std_logic;
345 
      usLeng_Lo7b_True   : IN  std_logic;
346 
 
347 
 
348 
      usDMA_Start        : IN  std_logic;
349 
      usDMA_Stop         : IN  std_logic;
350 
      usDMA_Start2       : IN  std_logic;
351 
      usDMA_Stop2        : IN  std_logic;
352 
      usDMA_Channel_Rst  : IN  std_logic;
353 
      usDMA_Cmd_Ack      : OUT std_logic;
354 
 
355 
      MRd_Channel_Rst    : IN  std_logic;
356 
 
357 
      Sys_IRQ            : IN  std_logic_vector(C_DBUS_WIDTH-1 downto 0);
358 
 
359 
 
360 
      -- DDR write port
361 
      DDR_wr_sof_A       : OUT   std_logic;
362 
      DDR_wr_eof_A       : OUT   std_logic;
363 
      DDR_wr_v_A         : OUT   std_logic;
364 
      DDR_wr_FA_A        : OUT   std_logic;
365 
      DDR_wr_Shift_A     : OUT   std_logic;
366 
      DDR_wr_Mask_A      : OUT   std_logic_vector(2-1 downto 0);
367 
      DDR_wr_din_A       : OUT   std_logic_vector(C_DBUS_WIDTH-1 downto 0);
368 
 
369 
      DDR_wr_sof_B       : OUT   std_logic;
370 
      DDR_wr_eof_B       : OUT   std_logic;
371 
      DDR_wr_v_B         : OUT   std_logic;
372 
      DDR_wr_FA_B        : OUT   std_logic;
373 
      DDR_wr_Shift_B     : OUT   std_logic;
374 
      DDR_wr_Mask_B      : OUT   std_logic_vector(2-1 downto 0);
375 
      DDR_wr_din_B       : OUT   std_logic_vector(C_DBUS_WIDTH-1 downto 0);
376 
 
377 
      DDR_wr_full        : IN    std_logic;
378 
 
379 
      Link_Buf_full      : IN  std_logic;
380 
 
381 
      -- Data generator table write
382 
      tab_we             : OUT std_logic_vector(2-1 downto 0);
383 
      tab_wa             : OUT std_logic_vector(12-1 downto 0);
384 
      tab_wd             : OUT std_logic_vector(C_DBUS_WIDTH-1 downto 0);
385 
 
386 
      -- Interrupt generator signals
387 
      IG_Reset           : IN  std_logic;
388 
      IG_Host_Clear      : IN  std_logic;
389 
      IG_Latency         : IN  std_logic_vector(C_DBUS_WIDTH-1   downto 0);
390 
      IG_Num_Assert      : OUT std_logic_vector(C_DBUS_WIDTH-1   downto 0);
391 
      IG_Num_Deassert    : OUT std_logic_vector(C_DBUS_WIDTH-1   downto 0);
392 
      IG_Asserting       : OUT std_logic;
393 
 
394 
 
395 
      -- Additional
396 
      cfg_dcommand       : IN  std_logic_vector(16-1 downto 0);
397 
      localID            : IN  std_logic_vector(C_ID_WIDTH-1 downto 0)
398 
    );
399 
  end component rx_Transact;
400 
 
401 
  -- Downstream DMA transferred bytes count up
402 
  signal ds_DMA_Bytes_Add   : std_logic;
403 
  signal ds_DMA_Bytes       : std_logic_vector(C_TLP_FLD_WIDTH_OF_LENG+2 downto 0);
404 
 
405 
 
406 
---- Tx transaction control
407 
  component tx_Transact
408 
    port (
409 
      -- Common ports
410 
      trn_clk            : IN  std_logic;
411 
      trn_reset_n        : IN  std_logic;
412 
      trn_lnk_up_n       : IN  std_logic;
413 
 
414 
      -- Transaction
415 
      trn_tsof_n         : OUT std_logic;
416 
      trn_teof_n         : OUT std_logic;
417 
      trn_td             : OUT std_logic_vector(C_DBUS_WIDTH-1 downto 0);
418 
      trn_trem_n         : OUT std_logic_vector(C_DBUS_WIDTH/8-1 downto 0);
419 
      trn_terrfwd_n      : OUT std_logic;
420 
      trn_tsrc_rdy_n     : OUT std_logic;
421 
      trn_tdst_rdy_n     : IN  std_logic;
422 
      trn_tsrc_dsc_n     : OUT std_logic;
423 
      trn_tdst_dsc_n     : IN  std_logic;
424 
      trn_tbuf_av        : IN  std_logic_vector(C_TBUF_AWIDTH-1 downto 0);
425 
 
426 
      -- Upstream DMA transferred bytes count up
427 
      us_DMA_Bytes_Add   : OUT std_logic;
428 
      us_DMA_Bytes       : OUT std_logic_vector(C_TLP_FLD_WIDTH_OF_LENG+2 downto 0);
429 
 
430 
      -- MRd Channel
431 
      pioCplD_Req        : IN  std_logic;
432 
      pioCplD_RE         : OUT std_logic;
433 
      pioCplD_Qout       : IN  std_logic_vector(C_CHANNEL_BUF_WIDTH-1 downto 0);
434 
      pio_FC_stop        : OUT std_logic;
435 
 
436 
 
437 
      -- MRd-downstream packet Channel
438 
      dsMRd_Req          : IN  std_logic;
439 
      dsMRd_RE           : OUT std_logic;
440 
      dsMRd_Qout         : IN  std_logic_vector(C_CHANNEL_BUF_WIDTH-1 downto 0);
441 
 
442 
 
443 
      -- Upstream MWr Channel
444 
      usTlp_Req          : IN  std_logic;
445 
      usTlp_RE           : OUT std_logic;
446 
      usTlp_Qout         : IN  std_logic_vector(C_CHANNEL_BUF_WIDTH-1 downto 0);
447 
      us_FC_stop         : OUT std_logic;
448 
      us_Last_sof        : OUT std_logic;
449 
      us_Last_eof        : OUT std_logic;
450 
 
451 
 
452 
      -- Irpt Channel
453 
      Irpt_Req           : IN  std_logic;
454 
      Irpt_RE            : OUT std_logic;
455 
      Irpt_Qout          : IN  std_logic_vector(C_CHANNEL_BUF_WIDTH-1 downto 0);
456 
 
457 
 
458 
      -- Event Buffer FIFO read port
459 
      eb_FIFO_re         : OUT std_logic;
460 
      eb_FIFO_empty      : IN  std_logic;
461 
      eb_FIFO_qout       : IN  std_logic_vector(C_DBUS_WIDTH-1 downto 0);
462 
 
463 
      -- With Rx port
464 
      Regs_RdAddr        : OUT std_logic_vector(C_EP_AWIDTH-1 downto 0);
465 
      Regs_RdQout        : IN  std_logic_vector(C_DBUS_WIDTH-1 downto 0);
466 
 
467 
      -- Message routing method
468 
      Msg_Routing        : IN  std_logic_vector(C_GCR_MSG_ROUT_BIT_TOP-C_GCR_MSG_ROUT_BIT_BOT downto 0);
469 
 
470 
 
471 
      --  DDR read port
472 
      DDR_rdc_sof        : OUT   std_logic;
473 
      DDR_rdc_eof        : OUT   std_logic;
474 
      DDR_rdc_v          : OUT   std_logic;
475 
      DDR_rdc_FA         : OUT   std_logic;
476 
      DDR_rdc_Shift      : OUT   std_logic;
477 
      DDR_rdc_din        : OUT   std_logic_vector(C_DBUS_WIDTH-1 downto 0);
478 
      DDR_rdc_full       : IN    std_logic;
479 
 
480 
--      DDR_rdD_sof        : IN    std_logic;
481 
--      DDR_rdD_eof        : IN    std_logic;
482 
--      DDR_rdDout_V       : IN    std_logic;
483 
--      DDR_rdDout         : IN    std_logic_vector(C_DBUS_WIDTH-1 downto 0);
484 
 
485 
      -- DDR payload FIFO Read Port
486 
      DDR_FIFO_RdEn      : OUT std_logic;
487 
      DDR_FIFO_Empty     : IN  std_logic;
488 
      DDR_FIFO_RdQout    : IN  std_logic_vector(C_DBUS_WIDTH-1 downto 0);
489 
 
490 
      -- Additional
491 
      Tx_TimeOut         : OUT std_logic;
492 
      Tx_eb_TimeOut      : OUT std_logic;
493 
      Format_Shower      : OUT   std_logic;
494 
      Tx_Reset           : IN  std_logic;
495 
      mbuf_UserFull      : IN  std_logic;
496 
      localID            : IN  std_logic_vector(C_ID_WIDTH-1 downto 0)
497 
    );
498 
  end component tx_Transact;
499 
 
500 
 
501 
  -- Upstream DMA transferred bytes count up
502 
  signal   us_DMA_Bytes_Add   : std_logic;
503 
  signal   us_DMA_Bytes       : std_logic_vector(C_TLP_FLD_WIDTH_OF_LENG+2 downto 0);
504 
 
505 
  -- ------------------------------------------------
506 
  -- United memory space consisting of registers.
507 
  --
508 
  component Regs_Group
509 
    port (
510 
 
511 
      -- DCB protocol interface
512 
                protocol_link_act        : IN  std_logic_vector(2-1 downto 0);
513 
                protocol_rst             : OUT std_logic;
514 
 
515 
      -- Fabric side: CTL Rx
516 
      ctl_rv                   : OUT std_logic;
517 
      ctl_rd                   : OUT std_logic_vector(C_DBUS_WIDTH/2-1 downto 0);
518 
 
519 
      -- Fabric side: CTL Tx
520 
      ctl_ttake                : OUT std_logic;
521 
      ctl_tv                   : IN  std_logic;
522 
      ctl_td                   : IN  std_logic_vector(C_DBUS_WIDTH/2-1 downto 0);
523 
      ctl_tstop                : OUT std_logic;
524 
 
525 
      ctl_reset                : OUT std_logic;
526 
      ctl_status               : IN  std_logic_vector(C_DBUS_WIDTH/2-1 downto 0);
527 
 
528 
      -- Fabric side: DLM Rx
529 
      dlm_tv                   : OUT std_logic;
530 
      dlm_td                   : OUT std_logic_vector(C_DBUS_WIDTH/2-1 downto 0);
531 
 
532 
      -- Fabric side: DLM Tx
533 
      dlm_rv                   : IN  std_logic;
534 
      dlm_rd                   : IN  std_logic_vector(C_DBUS_WIDTH/2-1 downto 0);
535 
 
536 
      -- Event Buffer status
537 
      eb_FIFO_Status           : IN  std_logic_vector(C_DBUS_WIDTH-1 downto 0);
538 
      eb_FIFO_Rst              : OUT std_logic;
539 
 
540 
      -- Register Write
541 
      Regs_WrEnA               : IN  std_logic;
542 
      Regs_WrMaskA             : IN  std_logic_vector(2-1 downto 0);
543 
      Regs_WrAddrA             : IN  std_logic_vector(C_EP_AWIDTH-1   downto 0);
544 
      Regs_WrDinA              : IN  std_logic_vector(C_DBUS_WIDTH-1   downto 0);
545 
 
546 
      Regs_WrEnB               : IN  std_logic;
547 
      Regs_WrMaskB             : IN  std_logic_vector(2-1 downto 0);
548 
      Regs_WrAddrB             : IN  std_logic_vector(C_EP_AWIDTH-1   downto 0);
549 
      Regs_WrDinB              : IN  std_logic_vector(C_DBUS_WIDTH-1   downto 0);
550 
 
551 
      Regs_RdAddr              : IN  std_logic_vector(C_EP_AWIDTH-1   downto 0);
552 
      Regs_RdQout              : OUT std_logic_vector(C_DBUS_WIDTH-1   downto 0);
553 
 
554 
      -- Downstream DMA transferred bytes count up
555 
      ds_DMA_Bytes_Add         : IN  std_logic;
556 
      ds_DMA_Bytes             : IN  std_logic_vector(C_TLP_FLD_WIDTH_OF_LENG+2 downto 0);
557 
 
558 
      -- Register Values
559 
      DMA_ds_PA                : OUT std_logic_vector(C_DBUS_WIDTH-1 downto 0);
560 
      DMA_ds_HA                : OUT std_logic_vector(C_DBUS_WIDTH-1 downto 0);
561 
      DMA_ds_BDA               : OUT std_logic_vector(C_DBUS_WIDTH-1 downto 0);
562 
      DMA_ds_Length            : OUT std_logic_vector(C_DBUS_WIDTH-1 downto 0);
563 
      DMA_ds_Control           : OUT std_logic_vector(C_DBUS_WIDTH-1 downto 0);
564 
      dsDMA_BDA_eq_Null        : OUT std_logic;
565 
      DMA_ds_Status            : IN  std_logic_vector(C_DBUS_WIDTH-1 downto 0);
566 
      DMA_ds_Done              : IN  std_logic;
567 
--      DMA_ds_Busy              : IN  std_logic;
568 
      DMA_ds_Tout              : IN  std_logic;
569 
 
570 
      -- Calculation in advance, for better timing
571 
      dsHA_is_64b              : OUT std_logic;
572 
      dsBDA_is_64b             : OUT std_logic;
573 
 
574 
      -- Calculation in advance, for better timing
575 
      dsLeng_Hi19b_True        : OUT std_logic;
576 
      dsLeng_Lo7b_True         : OUT std_logic;
577 
 
578 
 
579 
      dsDMA_Start              : OUT std_logic;
580 
      dsDMA_Stop               : OUT std_logic;
581 
      dsDMA_Start2             : OUT std_logic;
582 
      dsDMA_Stop2              : OUT std_logic;
583 
      dsDMA_Channel_Rst        : OUT std_logic;
584 
      dsDMA_Cmd_Ack            : IN  std_logic;
585 
 
586 
      -- Upstream DMA transferred bytes count up
587 
      us_DMA_Bytes_Add         : IN  std_logic;
588 
      us_DMA_Bytes             : IN  std_logic_vector(C_TLP_FLD_WIDTH_OF_LENG+2 downto 0);
589 
 
590 
      DMA_us_PA                : OUT std_logic_vector(C_DBUS_WIDTH-1 downto 0);
591 
      DMA_us_HA                : OUT std_logic_vector(C_DBUS_WIDTH-1 downto 0);
592 
      DMA_us_BDA               : OUT std_logic_vector(C_DBUS_WIDTH-1 downto 0);
593 
      DMA_us_Length            : OUT std_logic_vector(C_DBUS_WIDTH-1 downto 0);
594 
      DMA_us_Control           : OUT std_logic_vector(C_DBUS_WIDTH-1 downto 0);
595 
      usDMA_BDA_eq_Null        : OUT std_logic;
596 
      us_MWr_Param_Vec         : OUT std_logic_vector(6-1   downto 0);
597 
      DMA_us_Status            : IN  std_logic_vector(C_DBUS_WIDTH-1 downto 0);
598 
      DMA_us_Done              : IN  std_logic;
599 
--      DMA_us_Busy              : IN  std_logic;
600 
      DMA_us_Tout              : IN  std_logic;
601 
 
602 
      -- Calculation in advance, for better timing
603 
      usHA_is_64b              : OUT std_logic;
604 
      usBDA_is_64b             : OUT std_logic;
605 
 
606 
      -- Calculation in advance, for better timing
607 
      usLeng_Hi19b_True        : OUT std_logic;
608 
      usLeng_Lo7b_True         : OUT std_logic;
609 
 
610 
 
611 
      usDMA_Start              : OUT std_logic;
612 
      usDMA_Stop               : OUT std_logic;
613 
      usDMA_Start2             : OUT std_logic;
614 
      usDMA_Stop2              : OUT std_logic;
615 
      usDMA_Channel_Rst        : OUT std_logic;
616 
      usDMA_Cmd_Ack            : IN  std_logic;
617 
 
618 
      -- Reset signals
619 
      MRd_Channel_Rst          : OUT std_logic;
620 
      Tx_Reset                 : OUT std_logic;
621 
 
622 
      -- to Interrupt module
623 
      Sys_IRQ                  : OUT std_logic_vector(C_DBUS_WIDTH-1 downto 0);
624 
      DAQ_irq                  : IN  std_logic;
625 
      CTL_irq                  : IN  std_logic;
626 
      DLM_irq                  : IN  std_logic;
627 
 
628 
      -- System error and info
629 
      eb_FIFO_ow               : IN  std_logic;
630 
      Tx_TimeOut               : IN  std_logic;
631 
      Tx_eb_TimeOut            : IN  std_logic;
632 
      Msg_Routing              : OUT std_logic_vector(C_GCR_MSG_ROUT_BIT_TOP-C_GCR_MSG_ROUT_BIT_BOT downto 0);
633 
      pcie_link_width          : IN  std_logic_vector(CINT_BIT_LWIDTH_IN_GSR_TOP-CINT_BIT_LWIDTH_IN_GSR_BOT downto 0);
634 
      cfg_dcommand             : IN  std_logic_vector(16-1 downto 0);
635 
 
636 
      -- Interrupt Generation Signals
637 
      IG_Reset                 : OUT std_logic;
638 
      IG_Host_Clear            : OUT std_logic;
639 
      IG_Latency               : OUT std_logic_vector(C_DBUS_WIDTH-1   downto 0);
640 
      IG_Num_Assert            : IN  std_logic_vector(C_DBUS_WIDTH-1   downto 0);
641 
      IG_Num_Deassert          : IN  std_logic_vector(C_DBUS_WIDTH-1   downto 0);
642 
      IG_Asserting             : IN  std_logic;
643 
 
644 
      -- Data generator control
645 
      DG_is_Running            : IN  std_logic;
646 
      DG_Reset                 : OUT std_logic;
647 
      DG_Mask                  : OUT std_logic;
648 
 
649 
      -- Common interface
650 
      trn_clk                  : IN  std_logic;
651 
      trn_lnk_up_n             : IN  std_logic;
652 
      trn_reset_n              : IN  std_logic
653 
    );
654 
  end component Regs_Group;
655 
 
656 
 
657 
  -- DDR write port
658 
  signal  DDR_wr_sof_A         : std_logic;
659 
  signal  DDR_wr_eof_A         : std_logic;
660 
  signal  DDR_wr_v_A           : std_logic;
661 
  signal  DDR_wr_FA_A          : std_logic;
662 
  signal  DDR_wr_Shift_A       : std_logic;
663 
  signal  DDR_wr_Mask_A        : std_logic_vector(2-1 downto 0);
664 
  signal  DDR_wr_din_A         : std_logic_vector(C_DBUS_WIDTH-1 downto 0);
665 
 
666 
  signal  DDR_wr_sof_B         : std_logic;
667 
  signal  DDR_wr_eof_B         : std_logic;
668 
  signal  DDR_wr_v_B           : std_logic;
669 
  signal  DDR_wr_FA_B          : std_logic;
670 
  signal  DDR_wr_Shift_B       : std_logic;
671 
  signal  DDR_wr_Mask_B        : std_logic_vector(2-1 downto 0);
672 
  signal  DDR_wr_din_B         : std_logic_vector(C_DBUS_WIDTH-1 downto 0);
673 
 
674 
  signal  DDR_wr_sof_i         : std_logic;
675 
  signal  DDR_wr_eof_i         : std_logic;
676 
  signal  DDR_wr_v_i           : std_logic;
677 
  signal  DDR_wr_FA_i          : std_logic;
678 
  signal  DDR_wr_Shift_i       : std_logic;
679 
  signal  DDR_wr_Mask_i        : std_logic_vector(2-1 downto 0);
680 
  signal  DDR_wr_din_i         : std_logic_vector(C_DBUS_WIDTH-1 downto 0)
681 
                               := (OTHERS=>'0');
682 
 
683 
  signal  DDR_wr_sof_A_r1      : std_logic;
684 
  signal  DDR_wr_eof_A_r1      : std_logic;
685 
  signal  DDR_wr_v_A_r1        : std_logic;
686 
  signal  DDR_wr_FA_A_r1       : std_logic;
687 
  signal  DDR_wr_Shift_A_r1    : std_logic;
688 
  signal  DDR_wr_Mask_A_r1     : std_logic_vector(2-1 downto 0);
689 
  signal  DDR_wr_din_A_r1      : std_logic_vector(C_DBUS_WIDTH-1 downto 0);
690 
 
691 
  signal  DDR_wr_sof_A_r2      : std_logic;
692 
  signal  DDR_wr_eof_A_r2      : std_logic;
693 
  signal  DDR_wr_v_A_r2        : std_logic;
694 
  signal  DDR_wr_FA_A_r2       : std_logic;
695 
  signal  DDR_wr_Shift_A_r2    : std_logic;
696 
  signal  DDR_wr_Mask_A_r2     : std_logic_vector(2-1 downto 0);
697 
  signal  DDR_wr_din_A_r2      : std_logic_vector(C_DBUS_WIDTH-1 downto 0);
698 
 
699 
  signal  DDR_wr_sof_A_r3      : std_logic;
700 
  signal  DDR_wr_eof_A_r3      : std_logic;
701 
  signal  DDR_wr_v_A_r3        : std_logic;
702 
  signal  DDR_wr_FA_A_r3       : std_logic;
703 
  signal  DDR_wr_Shift_A_r3    : std_logic;
704 
  signal  DDR_wr_Mask_A_r3     : std_logic_vector(2-1 downto 0);
705 
  signal  DDR_wr_din_A_r3      : std_logic_vector(C_DBUS_WIDTH-1 downto 0);
706 
 
707 
  -- eb FIFO read enable
708 
  signal  eb_FIFO_RdEn_i       : std_logic;
709 
 
710 
  -- Flow control signals
711 
  signal  pio_FC_stop          : std_logic;
712 
  signal  us_FC_stop           : std_logic;
713 
  signal  us_Last_sof          : std_logic;
714 
  signal  us_Last_eof          : std_logic;
715 
 
716 
 
717 
  -- Signals between Tx_Transact and Rx_Transact
718 
  signal  pioCplD_Req          : std_logic;
719 
  signal  pioCplD_RE           : std_logic;
720 
  signal  pioCplD_Qout         : std_logic_vector(C_CHANNEL_BUF_WIDTH-1 downto 0);
721 
 
722 
  -- MRd-downstream packet Channel
723 
  signal  dsMRd_Req            : std_logic;
724 
  signal  dsMRd_RE             : std_logic;
725 
  signal  dsMRd_Qout           : std_logic_vector(C_CHANNEL_BUF_WIDTH-1 downto 0);
726 
 
727 
  -- Upstream MWr Channel
728 
  signal  usTlp_Req            : std_logic;
729 
  signal  usTlp_RE             : std_logic;
730 
  signal  usTlp_Qout           : std_logic_vector(C_CHANNEL_BUF_WIDTH-1 downto 0);
731 
 
732 
  -- Irpt Channel
733 
  signal  Irpt_Req             : std_logic;
734 
  signal  Irpt_RE              : std_logic;
735 
  signal  Irpt_Qout            : std_logic_vector(C_CHANNEL_BUF_WIDTH-1 downto 0);
736 
 
737 
 
738 
  -- Registers Write Port
739 
  signal  Regs_WrEnA           : std_logic;
740 
  signal  Regs_WrMaskA         : std_logic_vector(2-1 downto 0);
741 
  signal  Regs_WrAddrA         : std_logic_vector(C_EP_AWIDTH-1 downto 0);
742 
  signal  Regs_WrDinA          : std_logic_vector(C_DBUS_WIDTH-1 downto 0);
743 
 
744 
  signal  Regs_WrEnB           : std_logic;
745 
  signal  Regs_WrMaskB         : std_logic_vector(2-1 downto 0);
746 
  signal  Regs_WrAddrB         : std_logic_vector(C_EP_AWIDTH-1 downto 0);
747 
  signal  Regs_WrDinB          : std_logic_vector(C_DBUS_WIDTH-1 downto 0);
748 
 
749 
 
750 
  -- Dex parameters to downstream DMA
751 
  signal  DMA_ds_PA            : std_logic_vector(C_DBUS_WIDTH-1 downto 0);
752 
  signal  DMA_ds_HA            : std_logic_vector(C_DBUS_WIDTH-1 downto 0);
753 
  signal  DMA_ds_BDA           : std_logic_vector(C_DBUS_WIDTH-1 downto 0);
754 
  signal  DMA_ds_Length        : std_logic_vector(C_DBUS_WIDTH-1 downto 0);
755 
  signal  DMA_ds_Control       : std_logic_vector(C_DBUS_WIDTH-1 downto 0);
756 
  signal  dsDMA_BDA_eq_Null    : std_logic;
757 
  signal  DMA_ds_Status        : std_logic_vector(C_DBUS_WIDTH-1 downto 0);
758 
  signal  DMA_ds_Done_i        : std_logic;
759 
  signal  DMA_ds_Busy_i        : std_logic;
760 
  signal  DMA_ds_Busy_led_i    : std_logic;
761 
  signal  cnt_ds_Busy          : std_logic_vector(20-1   downto 0);
762 
  signal  DMA_ds_Tout          : std_logic;
763 
 
764 
  -- Calculation in advance, for better timing
765 
  signal  dsHA_is_64b          : std_logic;
766 
  signal  dsBDA_is_64b         : std_logic;
767 
  -- Calculation in advance, for better timing
768 
  signal  dsLeng_Hi19b_True    : std_logic;
769 
  signal  dsLeng_Lo7b_True     : std_logic;
770 
 
771 
  -- Downstream Control Signals
772 
  signal  dsDMA_Start          : std_logic;
773 
  signal  dsDMA_Stop           : std_logic;
774 
  signal  dsDMA_Start2         : std_logic;
775 
  signal  dsDMA_Stop2          : std_logic;
776 
  signal  dsDMA_Cmd_Ack        : std_logic;
777 
  signal  dsDMA_Channel_Rst    : std_logic;
778 
 
779 
  -- Dex parameters to upstream DMA
780 
  signal  DMA_us_PA            : std_logic_vector(C_DBUS_WIDTH-1 downto 0);
781 
  signal  DMA_us_HA            : std_logic_vector(C_DBUS_WIDTH-1 downto 0);
782 
  signal  DMA_us_BDA           : std_logic_vector(C_DBUS_WIDTH-1 downto 0);
783 
  signal  DMA_us_Length        : std_logic_vector(C_DBUS_WIDTH-1 downto 0);
784 
  signal  DMA_us_Control       : std_logic_vector(C_DBUS_WIDTH-1 downto 0);
785 
  signal  usDMA_BDA_eq_Null    : std_logic;
786 
  signal  us_MWr_Param_Vec     : std_logic_vector(6-1   downto 0);
787 
  signal  DMA_us_Status        : std_logic_vector(C_DBUS_WIDTH-1 downto 0);
788 
  signal  DMA_us_Done_i        : std_logic;
789 
  signal  DMA_us_Busy_i        : std_logic;
790 
  signal  DMA_us_Busy_led_i    : std_logic;
791 
  signal  cnt_us_Busy          : std_logic_vector(20-1   downto 0);
792 
  signal  DMA_us_Tout          : std_logic;
793 
 
794 
  -- Calculation in advance, for better timing
795 
  signal  usHA_is_64b          : std_logic;
796 
  signal  usBDA_is_64b         : std_logic;
797 
  -- Calculation in advance, for better timing
798 
  signal  usLeng_Hi19b_True    : std_logic;
799 
  signal  usLeng_Lo7b_True     : std_logic;
800 
 
801 
  -- Upstream Control Signals
802 
  signal  usDMA_Start          : std_logic;
803 
  signal  usDMA_Stop           : std_logic;
804 
  signal  usDMA_Start2         : std_logic;
805 
  signal  usDMA_Stop2          : std_logic;
806 
  signal  usDMA_Cmd_Ack        : std_logic;
807 
  signal  usDMA_Channel_Rst    : std_logic;
808 
 
809 
 
810 
  --      MRd Channel Reset
811 
  signal  MRd_Channel_Rst      : std_logic;
812 
 
813 
  --      Tx module Reset
814 
  signal  Tx_Reset             : std_logic;
815 
 
816 
  --      Tx time out
817 
  signal  Tx_TimeOut           : std_logic;
818 
  signal  Tx_eb_TimeOut        : std_logic;
819 
 
820 
  -- Registers read port
821 
  signal  Regs_RdAddr          : std_logic_vector(C_EP_AWIDTH-1 downto 0);
822 
  signal  Regs_RdQout          : std_logic_vector(C_DBUS_WIDTH-1 downto 0);
823 
 
824 
  -- Register to Interrupt module
825 
  signal  Sys_IRQ              : std_logic_vector(C_DBUS_WIDTH-1 downto 0);
826 
 
827 
  -- Message routing method
828 
  signal  Msg_Routing          : std_logic_vector(C_GCR_MSG_ROUT_BIT_TOP-C_GCR_MSG_ROUT_BIT_BOT downto 0);
829 
 
830 
  -- Interrupt Generation Signals
831 
  signal  IG_Reset             : std_logic;
832 
  signal  IG_Host_Clear        : std_logic;
833 
  signal  IG_Latency           : std_logic_vector(C_DBUS_WIDTH-1   downto 0);
834 
  signal  IG_Num_Assert        : std_logic_vector(C_DBUS_WIDTH-1   downto 0);
835 
  signal  IG_Num_Deassert      : std_logic_vector(C_DBUS_WIDTH-1   downto 0);
836 
  signal  IG_Asserting         : std_logic;
837 
 
838 
  -- Test blinker
839 
  signal  trn_Blinker_cnt      : std_logic_vector(31 downto 0) := (OTHERS=>'0');
840 
 
841 
begin
842 
 
843 
 
844 
   DDR_wr_v            <=  DDR_wr_v_i      ;
845 
   DDR_wr_sof          <=  DDR_wr_sof_i    ;
846 
   DDR_wr_eof          <=  DDR_wr_eof_i    ;
847 
   DDR_wr_FA           <=  DDR_wr_FA_i     ;
848 
   DDR_wr_Shift        <=  DDR_wr_Shift_i  ;
849 
   DDR_wr_Mask         <=  DDR_wr_Mask_i   ;
850 
   DDR_wr_din          <=  DDR_wr_din_i    ;
851 
 
852 
   trn_Blinker         <=  trn_Blinker_cnt(26)   ;
853 
 
854 
   DMA_us_Busy         <=  DMA_us_Busy_i   ;
855 
   DMA_us_Busy_LED     <=  DMA_us_Busy_led_i   ;
856 
   DMA_ds_Busy         <=  DMA_ds_Busy_i   ;
857 
   DMA_ds_Busy_LED     <=  DMA_ds_Busy_led_i   ;
858 
 
859 
   eb_FIFO_re          <=  eb_FIFO_RdEn_i  ;
860 
 
861 
   DMA_ds_Done         <=  DMA_ds_Done_i   ;
862 
   DMA_us_Done         <=  DMA_us_Done_i   ;
863 
 
864 
   trn_lnk_up_i        <=  not trn_lnk_up_n;
865 
 
866 
   -- -------------------------------------------------------
867 
   -- Delay DDR write port A for 2 cycles
868 
   --
869 
   SynDelay_DDR_write_PIO:
870 
   process ( trn_clk )
871 
   begin
872 
      if trn_clk'event and trn_clk = '1' then
873 
        DDR_wr_v_A_r1     <=  DDR_wr_v_A;
874 
        DDR_wr_sof_A_r1   <=  DDR_wr_sof_A;
875 
        DDR_wr_eof_A_r1   <=  DDR_wr_eof_A;
876 
        DDR_wr_FA_A_r1    <=  DDR_wr_FA_A;
877 
        DDR_wr_Shift_A_r1 <=  DDR_wr_Shift_A;
878 
        DDR_wr_Mask_A_r1  <=  DDR_wr_Mask_A;
879 
        DDR_wr_din_A_r1   <=  DDR_wr_din_A;
880 
 
881 
        DDR_wr_v_A_r2     <=  DDR_wr_v_A_r1;
882 
        DDR_wr_sof_A_r2   <=  DDR_wr_sof_A_r1;
883 
        DDR_wr_eof_A_r2   <=  DDR_wr_eof_A_r1;
884 
        DDR_wr_FA_A_r2    <=  DDR_wr_FA_A_r1;
885 
        DDR_wr_Shift_A_r2 <=  DDR_wr_Shift_A_r1;
886 
        DDR_wr_Mask_A_r2  <=  DDR_wr_Mask_A_r1;
887 
        DDR_wr_din_A_r2   <=  DDR_wr_din_A_r1;
888 
 
889 
        DDR_wr_v_A_r3     <=  DDR_wr_v_A_r2;
890 
        DDR_wr_sof_A_r3   <=  DDR_wr_sof_A_r2;
891 
        DDR_wr_eof_A_r3   <=  DDR_wr_eof_A_r2;
892 
        DDR_wr_FA_A_r3    <=  DDR_wr_FA_A_r2;
893 
        DDR_wr_Shift_A_r3 <=  DDR_wr_Shift_A_r2;
894 
        DDR_wr_Mask_A_r3  <=  DDR_wr_Mask_A_r2;
895 
        DDR_wr_din_A_r3   <=  DDR_wr_din_A_r2;
896 
      end if;
897 
   end process;
898 
 
899 
 
900 
   -- -------------------------------------------------------
901 
   -- DDR writes: DDR Writes
902 
   --
903 
   SynProc_DDR_write:
904 
   process ( trn_clk )
905 
   begin
906 
      if trn_clk'event and trn_clk = '1' then
907 
        DDR_wr_v_i     <=  DDR_wr_v_A_r3 or DDR_wr_v_B;
908 
        if DDR_wr_v_A_r3 = '1' then
909 
          DDR_wr_sof_i   <=  DDR_wr_sof_A_r3;
910 
          DDR_wr_eof_i   <=  DDR_wr_eof_A_r3;
911 
          DDR_wr_FA_i    <=  DDR_wr_FA_A_r3;
912 
          DDR_wr_Shift_i <=  DDR_wr_Shift_A_r3;
913 
          DDR_wr_Mask_i  <=  DDR_wr_Mask_A_r3;
914 
          DDR_wr_din_i   <=  DDR_wr_din_A_r3;
915 
        elsif DDR_wr_v_B = '1' then
916 
          DDR_wr_sof_i   <=  DDR_wr_sof_B;
917 
          DDR_wr_eof_i   <=  DDR_wr_eof_B;
918 
          DDR_wr_FA_i    <=  DDR_wr_FA_B ;
919 
          DDR_wr_Shift_i <=  DDR_wr_Shift_B ;
920 
          DDR_wr_Mask_i  <=  DDR_wr_Mask_B;
921 
          DDR_wr_din_i   <=  DDR_wr_din_B;
922 
        else
923 
          DDR_wr_sof_i   <=  DDR_wr_sof_i;
924 
          DDR_wr_eof_i   <=  DDR_wr_eof_i;
925 
          DDR_wr_FA_i    <=  DDR_wr_FA_i ;
926 
          DDR_wr_Shift_i <=  DDR_wr_Shift_i ;
927 
          DDR_wr_Mask_i  <=  DDR_wr_Mask_i;
928 
          DDR_wr_din_i   <=  DDR_wr_din_i;
929 
        end if;
930 
      end if;
931 
   end process;
932 
 
933 
   -- -------------------------------------------------------
934 
   -- trn blink
935 
   --
936 
   SynProc_trn_blinker:
937 
   process ( trn_clk )
938 
   begin
939 
      if trn_clk'event and trn_clk = '1' then
940 
        trn_Blinker_cnt     <=  trn_Blinker_cnt + '1';
941 
      end if;
942 
   end process;
943 
 
944 
   -- -------------------------------------------------------
945 
   -- DMA upstream Busy display
946 
   --
947 
   SynProc_DMA_us_Busy_LED:
948 
   process ( trn_clk, DMA_us_Busy_i)
949 
   begin
950 
      if DMA_us_Busy_i='1' then
951 
        DMA_us_Busy_led_i <=  '1';
952 
        cnt_us_Busy       <=  (OTHERS=>'0');
953 
      elsif trn_clk'event and trn_clk = '1' then
954 
        if cnt_us_Busy=X"80000" then
955 
          DMA_us_Busy_led_i <=  '0';
956 
          cnt_us_Busy       <=  cnt_us_Busy;
957 
        else
958 
          DMA_us_Busy_led_i <=  DMA_us_Busy_led_i;
959 
          cnt_us_Busy       <=  cnt_us_Busy + '1';
960 
        end if;
961 
      end if;
962 
   end process;
963 
 
964 
   -- -------------------------------------------------------
965 
   -- DMA downstream Busy display
966 
   --
967 
   SynProc_DMA_ds_Busy_LED:
968 
   process ( trn_clk, DMA_ds_Busy_i)
969 
   begin
970 
      if DMA_ds_Busy_i='1' then
971 
        DMA_ds_Busy_led_i <=  '1';
972 
        cnt_ds_Busy       <=  (OTHERS=>'0');
973 
      elsif trn_clk'event and trn_clk = '1' then
974 
        if cnt_ds_Busy=X"FFFFF" then
975 
          DMA_ds_Busy_led_i <=  '0';
976 
          cnt_ds_Busy       <=  cnt_ds_Busy;
977 
        else
978 
          DMA_ds_Busy_led_i <=  DMA_ds_Busy_led_i;
979 
          cnt_ds_Busy       <=  cnt_ds_Busy + '1';
980 
        end if;
981 
      end if;
982 
   end process;
983 
 
984 
--    DDR_wr_v     <=  DDR_wr_v_A or DDR_wr_v_B;
985 
--    DDR_wr_sof   <=  DDR_wr_sof_A  when DDR_wr_v_A='1'  else  DDR_wr_sof_B;
986 
--    DDR_wr_eof   <=  DDR_wr_eof_A  when DDR_wr_v_A='1'  else  DDR_wr_eof_B;
987 
--    DDR_wr_FA    <=  DDR_wr_FA_A   when DDR_wr_v_A='1'  else  DDR_wr_FA_B;
988 
--    DDR_wr_din   <=  DDR_wr_din_A  when DDR_wr_v_A='1'  else  DDR_wr_din_B;
989 
 
990 
 
991 
    -- Rx TLP interface
992 
    rx_Itf:
993 
    rx_Transact
994 
    port map(
995 
      -- Common ports
996 
      trn_clk            => trn_clk,             -- IN  std_logic,
997 
      trn_reset_n        => trn_lnk_up_i     , -- trn_reset_n,         -- IN  std_logic,
998 
      trn_lnk_up_n       => trn_lnk_up_n,        -- IN  std_logic,
999 
 
1000 
      -- Transaction receive interface
1001 
      trn_rsof_n         => trn_rsof_n,          -- IN  std_logic,
1002 
      trn_reof_n         => trn_reof_n,          -- IN  std_logic,
1003 
      trn_rd             => trn_rd,              -- IN  std_logic_vector(31 downto 0),
1004 
      trn_rrem_n         => trn_rrem_n,          -- IN  STD_LOGIC_VECTOR (  7 downto 0 );
1005 
      trn_rerrfwd_n      => trn_rerrfwd_n,       -- IN  std_logic,
1006 
      trn_rsrc_rdy_n     => trn_rsrc_rdy_n,      -- IN  std_logic,
1007 
      trn_rdst_rdy_n     => trn_rdst_rdy_n,      -- OUT std_logic,
1008 
      trn_rnp_ok_n       => trn_rnp_ok_n,        -- OUT std_logic,
1009 
      trn_rsrc_dsc_n     => trn_rsrc_dsc_n,      -- IN std_logic,
1010 
      trn_rbar_hit_n     => trn_rbar_hit_n,      -- IN  std_logic_vector(6 downto 0),
1011 
--    trn_rfc_ph_av        => trn_rfc_ph_av,       -- IN  std_logic_vector(7 downto 0),
1012 
--    trn_rfc_pd_av        => trn_rfc_pd_av,       -- IN  std_logic_vector(11 downto 0),
1013 
--    trn_rfc_nph_av       => trn_rfc_nph_av,      -- IN  std_logic_vector(7 downto 0),
1014 
--    trn_rfc_npd_av       => trn_rfc_npd_av,      -- IN  std_logic_vector(11 downto 0),
1015 
--    trn_rfc_cplh_av      => trn_rfc_cplh_av,     -- IN  std_logic_vector(7 downto 0),
1016 
--    trn_rfc_cpld_av      => trn_rfc_cpld_av,     -- IN  std_logic_vector(11 downto 0),
1017 
 
1018 
 
1019 
      -- MRd Channel
1020 
      pioCplD_Req        => pioCplD_Req,         -- OUT std_logic;
1021 
      pioCplD_RE         => pioCplD_RE,          -- IN  std_logic;
1022 
      pioCplD_Qout       => pioCplD_Qout,        -- OUT std_logic_vector(96 downto 0);
1023 
      pio_FC_stop        => pio_FC_stop,         -- IN  std_logic;
1024 
 
1025 
      -- downstream MRd Channel
1026 
      dsMRd_Req          => dsMRd_Req,           -- OUT std_logic;
1027 
      dsMRd_RE           => dsMRd_RE,            -- IN  std_logic;
1028 
      dsMRd_Qout         => dsMRd_Qout,          -- OUT std_logic_vector(96 downto 0);
1029 
 
1030 
      -- Upstream MWr/MRd Channel
1031 
      usTlp_Req          => usTlp_Req,           -- OUT std_logic;
1032 
      usTlp_RE           => usTlp_RE,            -- IN  std_logic;
1033 
      usTlp_Qout         => usTlp_Qout,          -- OUT std_logic_vector(96 downto 0);
1034 
      us_FC_stop         => us_FC_stop,          -- IN  std_logic;
1035 
      us_Last_sof        => us_Last_sof,         -- IN  std_logic;
1036 
      us_Last_eof        => us_Last_eof,         -- IN  std_logic;
1037 
 
1038 
      -- Irpt Channel
1039 
      Irpt_Req           => Irpt_Req,            -- OUT std_logic;
1040 
      Irpt_RE            => Irpt_RE,             -- IN  std_logic;
1041 
      Irpt_Qout          => Irpt_Qout,           -- OUT std_logic_vector(96 downto 0);
1042 
 
1043 
 
1044 
      -- Interrupt Interface
1045 
                cfg_interrupt_n         => cfg_interrupt_n         ,  -- OUT std_logic;
1046 
                cfg_interrupt_rdy_n     => cfg_interrupt_rdy_n     ,  -- IN std_logic;
1047 
                cfg_interrupt_mmenable  => cfg_interrupt_mmenable  ,  -- IN std_logic_VECTOR(2 downto 0);
1048 
                cfg_interrupt_msienable => cfg_interrupt_msienable ,  -- IN std_logic;
1049 
                cfg_interrupt_di        => cfg_interrupt_di        ,  -- OUT std_logic_VECTOR(7 downto 0);
1050 
                cfg_interrupt_do        => cfg_interrupt_do        ,  -- IN std_logic_VECTOR(7 downto 0);
1051 
                cfg_interrupt_assert_n  => cfg_interrupt_assert_n  ,  -- OUT std_logic;
1052 
 
1053 
 
1054 
      -- Event Buffer write port
1055 
      eb_FIFO_we          =>  eb_FIFO_we    ,       -- OUT std_logic;
1056 
      eb_FIFO_wsof        =>  eb_FIFO_wsof  ,       -- OUT std_logic;
1057 
      eb_FIFO_weof        =>  eb_FIFO_weof  ,       -- OUT std_logic;
1058 
      eb_FIFO_din         =>  eb_FIFO_din   ,       -- OUT std_logic_vector(C_DBUS_WIDTH-1 downto 0);
1059 
 
1060 
      eb_FIFO_data_count  =>  eb_FIFO_data_count,   -- IN  std_logic_vector(C_FIFO_DC_WIDTH downto 0);
1061 
      eb_FIFO_Empty       =>  eb_FIFO_Empty     ,   -- IN  std_logic;
1062 
      eb_FIFO_Reading     =>  eb_FIFO_RdEn_i    ,   -- IN  std_logic;
1063 
      pio_reading_status  =>  pio_reading_status    ,   -- OUT std_logic;
1064 
 
1065 
      -- Register Write
1066 
      Regs_WrEn0          =>  Regs_WrEnA    ,       -- OUT std_logic;
1067 
      Regs_WrMask0        =>  Regs_WrMaskA  ,       -- OUT std_logic_vector(2-1   downto 0);
1068 
      Regs_WrAddr0        =>  Regs_WrAddrA  ,       -- OUT std_logic_vector(16-1   downto 0);
1069 
      Regs_WrDin0         =>  Regs_WrDinA   ,       -- OUT std_logic_vector(32-1   downto 0);
1070 
 
1071 
      Regs_WrEn1          =>  Regs_WrEnB    ,       -- OUT std_logic;
1072 
      Regs_WrMask1        =>  Regs_WrMaskB  ,       -- OUT std_logic_vector(2-1   downto 0);
1073 
      Regs_WrAddr1        =>  Regs_WrAddrB  ,       -- OUT std_logic_vector(16-1   downto 0);
1074 
      Regs_WrDin1         =>  Regs_WrDinB   ,       -- OUT std_logic_vector(32-1   downto 0);
1075 
 
1076 
      -- Downstream DMA transferred bytes count up
1077 
      ds_DMA_Bytes_Add    =>  ds_DMA_Bytes_Add     ,  -- OUT std_logic;
1078 
      ds_DMA_Bytes        =>  ds_DMA_Bytes         ,  -- OUT std_logic_vector(C_TLP_FLD_WIDTH_OF_LENG+2 downto 0);
1079 
 
1080 
      -- Registers
1081 
                DMA_ds_PA           =>  DMA_ds_PA            ,  -- IN  std_logic_vector(63 downto 0);
1082 
                DMA_ds_HA           =>  DMA_ds_HA            ,  -- IN  std_logic_vector(63 downto 0);
1083 
                DMA_ds_BDA          =>  DMA_ds_BDA           ,  -- IN  std_logic_vector(63 downto 0);
1084 
                DMA_ds_Length       =>  DMA_ds_Length        ,  -- IN  std_logic_vector(31 downto 0);
1085 
                DMA_ds_Control      =>  DMA_ds_Control       ,  -- IN  std_logic_vector(31 downto 0);
1086 
      dsDMA_BDA_eq_Null   =>  dsDMA_BDA_eq_Null    ,  -- IN  std_logic;
1087 
                DMA_ds_Status       =>  DMA_ds_Status        ,  -- OUT std_logic_vector(31 downto 0);
1088 
      DMA_ds_Done         =>  DMA_ds_Done_i        ,  -- OUT std_logic;
1089 
      DMA_ds_Busy         =>  DMA_ds_Busy_i        ,  -- OUT std_logic;
1090 
      DMA_ds_Tout         =>  DMA_ds_Tout          ,  -- OUT std_logic;
1091 
 
1092 
      dsHA_is_64b         =>  dsHA_is_64b          ,  -- IN  std_logic;
1093 
      dsBDA_is_64b        =>  dsBDA_is_64b         ,  -- IN  std_logic;
1094 
 
1095 
      dsLeng_Hi19b_True   =>  dsLeng_Hi19b_True    ,  -- IN  std_logic;
1096 
      dsLeng_Lo7b_True    =>  dsLeng_Lo7b_True     ,  -- IN  std_logic;
1097 
 
1098 
                dsDMA_Start         =>  dsDMA_Start          ,  -- IN  std_logic;
1099 
                dsDMA_Stop          =>  dsDMA_Stop           ,  -- IN  std_logic;
1100 
                dsDMA_Start2        =>  dsDMA_Start2         ,  -- IN  std_logic;
1101 
                dsDMA_Stop2         =>  dsDMA_Stop2          ,  -- IN  std_logic;
1102 
                dsDMA_Channel_Rst   =>  dsDMA_Channel_Rst    ,  -- IN  std_logic;
1103 
      dsDMA_Cmd_Ack       =>  dsDMA_Cmd_Ack        ,  -- OUT std_logic;
1104 
 
1105 
                DMA_us_PA           =>  DMA_us_PA            ,  -- IN  std_logic_vector(63 downto 0);
1106 
                DMA_us_HA           =>  DMA_us_HA            ,  -- IN  std_logic_vector(63 downto 0);
1107 
                DMA_us_BDA          =>  DMA_us_BDA           ,  -- IN  std_logic_vector(63 downto 0);
1108 
                DMA_us_Length       =>  DMA_us_Length        ,  -- IN  std_logic_vector(31 downto 0);
1109 
                DMA_us_Control      =>  DMA_us_Control       ,  -- IN  std_logic_vector(31 downto 0);
1110 
      usDMA_BDA_eq_Null   =>  usDMA_BDA_eq_Null    ,  -- IN  std_logic;
1111 
      us_MWr_Param_Vec    =>  us_MWr_Param_Vec     ,  -- IN  std_logic_vector(6-1   downto 0);
1112 
                DMA_us_Status       =>  DMA_us_Status        ,  -- OUT std_logic_vector(31 downto 0);
1113 
      DMA_us_Done         =>  DMA_us_Done_i        ,  -- OUT std_logic;
1114 
      DMA_us_Busy         =>  DMA_us_Busy_i        ,  -- OUT std_logic;
1115 
      DMA_us_Tout         =>  DMA_us_Tout          ,  -- OUT std_logic;
1116 
 
1117 
      usHA_is_64b         =>  usHA_is_64b          ,  -- IN  std_logic;
1118 
      usBDA_is_64b        =>  usBDA_is_64b         ,  -- IN  std_logic;
1119 
 
1120 
      usLeng_Hi19b_True   =>  usLeng_Hi19b_True    ,  -- IN  std_logic;
1121 
      usLeng_Lo7b_True    =>  usLeng_Lo7b_True     ,  -- IN  std_logic;
1122 
 
1123 
 
1124 
                usDMA_Start         =>  usDMA_Start          ,  -- IN  std_logic;
1125 
                usDMA_Stop          =>  usDMA_Stop           ,  -- IN  std_logic;
1126 
                usDMA_Start2        =>  usDMA_Start2         ,  -- IN  std_logic;
1127 
                usDMA_Stop2         =>  usDMA_Stop2          ,  -- IN  std_logic;
1128 
                usDMA_Channel_Rst   =>  usDMA_Channel_Rst    ,  -- IN  std_logic;
1129 
      usDMA_Cmd_Ack       =>  usDMA_Cmd_Ack        ,  -- OUT std_logic;
1130 
 
1131 
 
1132 
      -- Reset signals
1133 
                MRd_Channel_Rst     =>  MRd_Channel_Rst      ,  -- IN  std_logic;
1134 
 
1135 
      -- to Interrupt module
1136 
      Sys_IRQ             =>  Sys_IRQ              ,  -- IN  std_logic_vector(31 downto 0);
1137 
 
1138 
      IG_Reset            =>  IG_Reset             ,
1139 
      IG_Host_Clear       =>  IG_Host_Clear        ,
1140 
      IG_Latency          =>  IG_Latency           ,
1141 
      IG_Num_Assert       =>  IG_Num_Assert        ,
1142 
      IG_Num_Deassert     =>  IG_Num_Deassert      ,
1143 
      IG_Asserting        =>  IG_Asserting         ,
1144 
 
1145 
 
1146 
      -- DDR write port
1147 
      DDR_wr_sof_A        =>  DDR_wr_sof_A    , -- OUT   std_logic;
1148 
      DDR_wr_eof_A        =>  DDR_wr_eof_A    , -- OUT   std_logic;
1149 
      DDR_wr_v_A          =>  DDR_wr_v_A      , -- OUT   std_logic;
1150 
      DDR_wr_FA_A         =>  DDR_wr_FA_A     , -- OUT   std_logic;
1151 
      DDR_wr_Shift_A      =>  DDR_wr_Shift_A  , -- OUT   std_logic;
1152 
      DDR_wr_Mask_A       =>  DDR_wr_Mask_A   , -- OUT   std_logic_vector(2-1 downto 0);
1153 
      DDR_wr_din_A        =>  DDR_wr_din_A    , -- OUT   std_logic_vector(C_DBUS_WIDTH-1 downto 0);
1154 
 
1155 
      DDR_wr_sof_B        =>  DDR_wr_sof_B    , -- OUT   std_logic;
1156 
      DDR_wr_eof_B        =>  DDR_wr_eof_B    , -- OUT   std_logic;
1157 
      DDR_wr_v_B          =>  DDR_wr_v_B      , -- OUT   std_logic;
1158 
      DDR_wr_FA_B         =>  DDR_wr_FA_B     , -- OUT   std_logic;
1159 
      DDR_wr_Shift_B      =>  DDR_wr_Shift_B  , -- OUT   std_logic;
1160 
      DDR_wr_Mask_B       =>  DDR_wr_Mask_B   , -- OUT   std_logic_vector(2-1 downto 0);
1161 
      DDR_wr_din_B        =>  DDR_wr_din_B    , -- OUT   std_logic_vector(C_DBUS_WIDTH-1 downto 0);
1162 
 
1163 
      DDR_wr_full         =>  DDR_wr_full     , -- IN    std_logic;
1164 
 
1165 
 
1166 
      Link_Buf_full       =>  Link_Buf_full   , -- IN    std_logic;
1167 
 
1168 
 
1169 
      -- Data generator table write
1170 
      tab_we              =>  tab_we          , -- OUT std_logic_vector(2-1 downto 0);
1171 
      tab_wa              =>  tab_wa          , -- OUT std_logic_vector(12-1 downto 0);
1172 
      tab_wd              =>  tab_wd          , -- OUT std_logic_vector(C_DBUS_WIDTH-1 downto 0);
1173 
 
1174 
      -- Additional
1175 
      cfg_dcommand        =>  cfg_dcommand         ,  -- IN  std_logic_vector(15 downto 0)
1176 
      localID             =>  localID                 -- IN  std_logic_vector(15 downto 0)
1177 
    );
1178 
 
1179 
 
1180 
 
1181 
    -- Tx TLP interface
1182 
    tx_Itf:
1183 
    tx_Transact
1184 
    port map(
1185 
      -- Common ports
1186 
      trn_clk             => trn_clk,             -- IN  std_logic,
1187 
      trn_reset_n         => trn_lnk_up_i     , -- trn_reset_n,         -- IN  std_logic,
1188 
      trn_lnk_up_n        => trn_lnk_up_n,        -- IN  std_logic,
1189 
 
1190 
      -- Transaction
1191 
      trn_tsof_n          => trn_tsof_n,          -- OUT std_logic,
1192 
      trn_teof_n          => trn_teof_n,          -- OUT std_logic,
1193 
      trn_td              => trn_td,              -- OUT std_logic_vector(31 downto 0),
1194 
      trn_trem_n          => trn_trem_n,          -- OUT STD_LOGIC_VECTOR (  7 downto 0 );
1195 
      trn_terrfwd_n       => trn_terrfwd_n,       -- OUT std_logic,
1196 
      trn_tsrc_rdy_n      => trn_tsrc_rdy_n,      -- OUT std_logic,
1197 
      trn_tdst_rdy_n      => trn_tdst_rdy_n,      -- IN  std_logic,
1198 
      trn_tsrc_dsc_n      => trn_tsrc_dsc_n,      -- OUT std_logic,
1199 
      trn_tdst_dsc_n      => trn_tdst_dsc_n,      -- IN  std_logic,
1200 
      trn_tbuf_av         => trn_tbuf_av,         -- IN  std_logic_vector(6 downto 0),
1201 
 
1202 
      -- Upstream DMA transferred bytes count up
1203 
      us_DMA_Bytes_Add    => us_DMA_Bytes_Add,    -- OUT std_logic;
1204 
      us_DMA_Bytes        => us_DMA_Bytes,        -- OUT std_logic_vector(C_TLP_FLD_WIDTH_OF_LENG+2 downto 0);
1205 
 
1206 
      -- MRd Channel
1207 
      pioCplD_Req         => pioCplD_Req,         -- IN  std_logic;
1208 
      pioCplD_RE          => pioCplD_RE,          -- OUT std_logic;
1209 
      pioCplD_Qout        => pioCplD_Qout,        -- IN  std_logic_vector(96 downto 0);
1210 
      pio_FC_stop         => pio_FC_stop,         -- OUT std_logic;
1211 
 
1212 
      -- downstream MRd Channel
1213 
      dsMRd_Req           => dsMRd_Req,           -- IN  std_logic;
1214 
      dsMRd_RE            => dsMRd_RE,            -- OUT std_logic;
1215 
      dsMRd_Qout          => dsMRd_Qout,          -- IN  std_logic_vector(96 downto 0);
1216 
 
1217 
      -- Upstream MWr/MRd Channel
1218 
      usTlp_Req           => usTlp_Req,           -- IN  std_logic;
1219 
      usTlp_RE            => usTlp_RE,            -- OUT std_logic;
1220 
      usTlp_Qout          => usTlp_Qout,          -- IN  std_logic_vector(96 downto 0);
1221 
      us_FC_stop          => us_FC_stop,          -- OUT std_logic;
1222 
      us_Last_sof         => us_Last_sof,         -- OUT std_logic;
1223 
      us_Last_eof         => us_Last_eof,         -- OUT std_logic;
1224 
 
1225 
      -- Irpt Channel
1226 
      Irpt_Req            => Irpt_Req,            -- IN  std_logic;
1227 
      Irpt_RE             => Irpt_RE,             -- OUT std_logic;
1228 
      Irpt_Qout           => Irpt_Qout,           -- IN  std_logic_vector(96 downto 0);
1229 
 
1230 
 
1231 
      -- Event Buffer FIFO read port
1232 
      eb_FIFO_re          => eb_FIFO_RdEn_i,      -- OUT std_logic;
1233 
      eb_FIFO_empty       => eb_FIFO_empty ,      -- IN  std_logic;
1234 
      eb_FIFO_qout        => eb_FIFO_qout  ,      -- IN  std_logic_vector(C_DBUS_WIDTH-1 downto 0);
1235 
 
1236 
      -- Registers read
1237 
      Regs_RdAddr         => Regs_RdAddr,         -- OUT std_logic_vector(15 downto 0);
1238 
      Regs_RdQout         => Regs_RdQout,         -- IN  std_logic_vector(31 downto 0);
1239 
 
1240 
      -- Message routing method
1241 
      Msg_Routing         => Msg_Routing,
1242 
 
1243 
      --  DDR read port
1244 
      DDR_rdc_sof         =>  DDR_rdc_sof       ,  -- OUT   std_logic;
1245 
      DDR_rdc_eof         =>  DDR_rdc_eof       ,  -- OUT   std_logic;
1246 
      DDR_rdc_v           =>  DDR_rdc_v         ,  -- OUT   std_logic;
1247 
      DDR_rdc_FA          =>  DDR_rdc_FA        ,  -- OUT   std_logic;
1248 
      DDR_rdc_Shift       =>  DDR_rdc_Shift     ,  -- OUT   std_logic;
1249 
      DDR_rdc_din         =>  DDR_rdc_din       ,  -- OUT   std_logic_vector(C_DBUS_WIDTH-1 downto 0);
1250 
      DDR_rdc_full        =>  DDR_rdc_full      ,  -- IN    std_logic;
1251 
 
1252 
      -- DDR payload FIFO Read Port
1253 
      DDR_FIFO_RdEn       =>  DDR_FIFO_RdEn     ,  -- OUT std_logic;
1254 
      DDR_FIFO_Empty      =>  DDR_FIFO_Empty    ,  -- IN  std_logic;
1255 
      DDR_FIFO_RdQout     =>  DDR_FIFO_RdQout   ,  -- IN  std_logic_vector(C_DBUS_WIDTH-1 downto 0);
1256 
--      DDR_rdD_sof         =>  DDR_rdD_sof       ,  -- IN    std_logic;
1257 
--      DDR_rdD_eof         =>  DDR_rdD_eof       ,  -- IN    std_logic;
1258 
--      DDR_rdDout_V        =>  DDR_rdDout_V      ,  -- IN    std_logic;
1259 
--      DDR_rdDout          =>  DDR_rdDout        ,  -- IN    std_logic_vector(C_DBUS_WIDTH-1 downto 0);
1260 
 
1261 
 
1262 
      -- Additional
1263 
      Tx_TimeOut          => Tx_TimeOut,          -- OUT std_logic;
1264 
      Tx_eb_TimeOut       => Tx_eb_TimeOut,       -- OUT std_logic;
1265 
      Format_Shower       => Format_Shower,       -- OUT std_logic;
1266 
      Tx_Reset            => Tx_Reset,            -- IN  std_logic;
1267 
      mbuf_UserFull       => mbuf_UserFull,       -- IN  std_logic;
1268 
      localID             => localID              -- IN  std_logic_vector(15 downto 0)
1269 
    );
1270 
 
1271 
 
1272 
 
1273 
  -- ------------------------------------------------
1274 
  --   Unified memory space
1275 
  -- ------------------------------------------------
1276 
   Memory_Space:
1277 
   Regs_Group
1278 
   PORT MAP(
1279 
 
1280 
      -- DCB protocol interface
1281 
      protocol_link_act   =>  protocol_link_act    ,  -- IN  std_logic_vector(2-1 downto 0);
1282 
      protocol_rst        =>  protocol_rst         ,  -- OUT std_logic;
1283 
 
1284 
      -- Fabric side: CTL Rx
1285 
      ctl_rv              =>  ctl_rv               ,  -- OUT std_logic;
1286 
      ctl_rd              =>  ctl_rd               ,  -- OUT std_logic_vector(C_DBUS_WIDTH/2-1 downto 0);
1287 
 
1288 
      -- Fabric side: CTL Tx
1289 
      ctl_ttake           =>  ctl_ttake            ,  -- OUT std_logic;
1290 
      ctl_tv              =>  ctl_tv               ,  -- IN  std_logic;
1291 
      ctl_td              =>  ctl_td               ,  -- IN  std_logic_vector(C_DBUS_WIDTH/2-1 downto 0);
1292 
      ctl_tstop           =>  ctl_tstop            ,  -- OUT std_logic;
1293 
 
1294 
      ctl_reset           =>  ctl_reset            ,  -- OUT std_logic;
1295 
      ctl_status          =>  ctl_status           ,  -- IN  std_logic_vector(C_DBUS_WIDTH/2-1 downto 0);
1296 
 
1297 
      -- Fabric side: DLM Rx
1298 
      dlm_tv              =>  dlm_tv               ,  -- OUT std_logic;
1299 
      dlm_td              =>  dlm_td               ,  -- OUT std_logic_vector(C_DBUS_WIDTH/2-1 downto 0);
1300 
 
1301 
      -- Fabric side: DLM Tx
1302 
      dlm_rv              =>  dlm_rv               ,  -- IN  std_logic;
1303 
      dlm_rd              =>  dlm_rd               ,  -- IN  std_logic_vector(C_DBUS_WIDTH/2-1 downto 0);
1304 
 
1305 
      -- Event Buffer status + reset
1306 
      eb_FIFO_Status      =>  eb_FIFO_Status  ,      -- IN  std_logic_vector(C_DBUS_WIDTH-1 downto 0);
1307 
      eb_FIFO_Rst         =>  eb_FIFO_Rst     ,      -- OUT std_logic;
1308 
 
1309 
      -- Registers
1310 
      Regs_WrEnA          =>  Regs_WrEnA      ,      -- IN  std_logic;
1311 
      Regs_WrMaskA        =>  Regs_WrMaskA    ,      -- IN  std_logic_vector(2-1   downto 0);
1312 
      Regs_WrAddrA        =>  Regs_WrAddrA    ,      -- IN  std_logic_vector(16-1   downto 0);
1313 
      Regs_WrDinA         =>  Regs_WrDinA     ,      -- IN  std_logic_vector(32-1   downto 0);
1314 
 
1315 
      Regs_WrEnB          =>  Regs_WrEnB      ,      -- IN  std_logic;
1316 
      Regs_WrMaskB        =>  Regs_WrMaskB    ,      -- IN  std_logic_vector(2-1   downto 0);
1317 
      Regs_WrAddrB        =>  Regs_WrAddrB    ,      -- IN  std_logic_vector(16-1   downto 0);
1318 
      Regs_WrDinB         =>  Regs_WrDinB     ,      -- IN  std_logic_vector(32-1   downto 0);
1319 
 
1320 
 
1321 
      Regs_RdAddr         =>  Regs_RdAddr     ,      -- IN  std_logic_vector(15 downto 0);
1322 
      Regs_RdQout         =>  Regs_RdQout     ,      -- OUT std_logic_vector(31 downto 0);
1323 
 
1324 
      -- Downstream DMA transferred bytes count up
1325 
      ds_DMA_Bytes_Add    =>  ds_DMA_Bytes_Add     , -- IN  std_logic;
1326 
      ds_DMA_Bytes        =>  ds_DMA_Bytes         , -- IN  std_logic_vector(C_TLP_FLD_WIDTH_OF_LENG+2 downto 0);
1327 
 
1328 
      -- Register values
1329 
      DMA_ds_PA           =>  DMA_ds_PA            ,  -- OUT std_logic_vector(63 downto 0);
1330 
      DMA_ds_HA           =>  DMA_ds_HA            ,  -- OUT std_logic_vector(63 downto 0);
1331 
      DMA_ds_BDA          =>  DMA_ds_BDA           ,  -- OUT std_logic_vector(63 downto 0);
1332 
      DMA_ds_Length       =>  DMA_ds_Length        ,  -- OUT std_logic_vector(31 downto 0);
1333 
      DMA_ds_Control      =>  DMA_ds_Control       ,  -- OUT std_logic_vector(31 downto 0);
1334 
      dsDMA_BDA_eq_Null   =>  dsDMA_BDA_eq_Null    ,  -- OUT std_logic;
1335 
      DMA_ds_Status       =>  DMA_ds_Status        ,  -- IN  std_logic_vector(31 downto 0);
1336 
      DMA_ds_Done         =>  DMA_ds_Done_i        ,  -- IN  std_logic;
1337 
      DMA_ds_Tout         =>  DMA_ds_Tout          ,  -- IN  std_logic;
1338 
 
1339 
      dsHA_is_64b         =>  dsHA_is_64b          ,  -- OUT std_logic;
1340 
      dsBDA_is_64b        =>  dsBDA_is_64b         ,  -- OUT std_logic;
1341 
 
1342 
      dsLeng_Hi19b_True   =>  dsLeng_Hi19b_True    ,  -- OUT std_logic;
1343 
      dsLeng_Lo7b_True    =>  dsLeng_Lo7b_True     ,  -- OUT std_logic;
1344 
 
1345 
      dsDMA_Start         =>  dsDMA_Start          ,  -- OUT std_logic;
1346 
      dsDMA_Stop          =>  dsDMA_Stop           ,  -- OUT std_logic;
1347 
      dsDMA_Start2        =>  dsDMA_Start2         ,  -- OUT std_logic;
1348 
      dsDMA_Stop2         =>  dsDMA_Stop2          ,  -- OUT std_logic;
1349 
      dsDMA_Channel_Rst   =>  dsDMA_Channel_Rst    ,  -- OUT std_logic;
1350 
      dsDMA_Cmd_Ack       =>  dsDMA_Cmd_Ack        ,  -- IN  std_logic;
1351 
 
1352 
      -- Upstream DMA transferred bytes count up
1353 
      us_DMA_Bytes_Add    =>  us_DMA_Bytes_Add     ,  -- IN  std_logic;
1354 
      us_DMA_Bytes        =>  us_DMA_Bytes         ,  -- IN  std_logic_vector(C_TLP_FLD_WIDTH_OF_LENG+2 downto 0);
1355 
 
1356 
      DMA_us_PA           =>  DMA_us_PA            ,  -- OUT std_logic_vector(63 downto 0);
1357 
      DMA_us_HA           =>  DMA_us_HA            ,  -- OUT std_logic_vector(63 downto 0);
1358 
      DMA_us_BDA          =>  DMA_us_BDA           ,  -- OUT std_logic_vector(63 downto 0);
1359 
      DMA_us_Length       =>  DMA_us_Length        ,  -- OUT std_logic_vector(31 downto 0);
1360 
      DMA_us_Control      =>  DMA_us_Control       ,  -- OUT std_logic_vector(31 downto 0);
1361 
      usDMA_BDA_eq_Null   =>  usDMA_BDA_eq_Null    ,  -- OUT std_logic;
1362 
      us_MWr_Param_Vec    =>  us_MWr_Param_Vec     ,  -- OUT std_logic_vector(6-1   downto 0);
1363 
      DMA_us_Status       =>  DMA_us_Status        ,  -- IN  std_logic_vector(31 downto 0);
1364 
      DMA_us_Done         =>  DMA_us_Done_i        ,  -- IN  std_logic;
1365 
      DMA_us_Tout         =>  DMA_us_Tout          ,  -- IN  std_logic;
1366 
 
1367 
      usHA_is_64b         =>  usHA_is_64b          ,  -- OUT std_logic;
1368 
      usBDA_is_64b        =>  usBDA_is_64b         ,  -- OUT std_logic;
1369 
 
1370 
      usLeng_Hi19b_True   =>  usLeng_Hi19b_True    ,  -- OUT std_logic;
1371 
      usLeng_Lo7b_True    =>  usLeng_Lo7b_True     ,  -- OUT std_logic;
1372 
 
1373 
 
1374 
      usDMA_Start         =>  usDMA_Start          ,  -- OUT std_logic;
1375 
      usDMA_Stop          =>  usDMA_Stop           ,  -- OUT std_logic;
1376 
      usDMA_Start2        =>  usDMA_Start2         ,  -- OUT std_logic;
1377 
      usDMA_Stop2         =>  usDMA_Stop2          ,  -- OUT std_logic;
1378 
      usDMA_Channel_Rst   =>  usDMA_Channel_Rst    ,  -- OUT std_logic;
1379 
      usDMA_Cmd_Ack       =>  usDMA_Cmd_Ack        ,  -- IN  std_logic;
1380 
 
1381 
      -- Reset signals
1382 
      MRd_Channel_Rst     =>  MRd_Channel_Rst      ,  -- OUT std_logic;
1383 
      Tx_Reset            =>  Tx_Reset             ,  -- OUT std_logic;
1384 
 
1385 
      -- to Interrupt module
1386 
      Sys_IRQ             =>  Sys_IRQ              ,  -- OUT std_logic_vector(31 downto 0);
1387 
      DAQ_irq             =>  DAQ_irq              ,  -- IN  std_logic;
1388 
      CTL_irq             =>  CTL_irq              ,  -- IN  std_logic;
1389 
      DLM_irq             =>  DLM_irq              ,  -- IN  std_logic;
1390 
 
1391 
      -- System error and info
1392 
      eb_FIFO_ow          =>  eb_FIFO_ow           ,
1393 
      Tx_TimeOut          =>  Tx_TimeOut           ,
1394 
      Tx_eb_TimeOut       =>  Tx_eb_TimeOut        ,
1395 
      Msg_Routing         =>  Msg_Routing          ,
1396 
      pcie_link_width     =>  pcie_link_width      ,
1397 
      cfg_dcommand        =>  cfg_dcommand         ,
1398 
 
1399 
      -- Interrupt Generation Signals
1400 
      IG_Reset            =>  IG_Reset             ,
1401 
      IG_Host_Clear       =>  IG_Host_Clear        ,
1402 
      IG_Latency          =>  IG_Latency           ,
1403 
      IG_Num_Assert       =>  IG_Num_Assert        ,
1404 
      IG_Num_Deassert     =>  IG_Num_Deassert      ,
1405 
      IG_Asserting        =>  IG_Asserting         ,
1406 
 
1407 
      -- Data generator control
1408 
      DG_is_Running       =>  DG_is_Running        ,
1409 
      DG_Reset            =>  DG_Reset             ,
1410 
      DG_Mask             =>  DG_Mask              ,
1411 
 
1412 
      -- Common
1413 
      trn_clk             =>  trn_clk              ,  -- IN  std_logic;
1414 
      trn_lnk_up_n        =>  trn_lnk_up_n         ,  -- IN  std_logic,
1415 
      trn_reset_n         =>  trn_reset_n             -- IN  std_logic;
1416 
        );
1417 
 
1418 
 
1419 
end architecture Behavioral;

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