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[/] [pcie_sg_dma/] [branches/] [Virtex6/] [ML605_ISE12.3/] [pcie_sg_dma/] [Virtex6/] [ML605/] [tx_Transact.vhd] - Blame information for rev 11

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Line No. Rev Author Line
1 11 barabba 
----------------------------------------------------------------------------------
2 
-- Company:
3 
-- Engineer:
4 
--
5 
-- Design Name:
6 
-- Module Name:    tx_Transact - Behavioral
7 
-- Project Name:
8 
-- Target Devices:
9 
-- Tool versions:
10 
-- Description:
11 
--
12 
-- Dependencies:
13 
--
14 
-- Revision 1.30 - Memory buffer applied and structure regulated for DPR.   25.03.2008
15 
--
16 
-- Revision 1.20 - Literal assignments rewritten.   02.08.2007
17 
--
18 
-- Revision 1.10 - x4 timing constraints met.   02.02.2007
19 
--
20 
-- Revision 1.06 - BRAM output and FIFO output both registered.  01.02.2007
21 
--
22 
-- Revision 1.04 - Timing improved.     17.01.2007
23 
--
24 
-- Revision 1.02 - FIFO added.    20.12.2006
25 
--
26 
-- Revision 1.00 - first release. 14.12.2006
27 
--
28 
-- Additional Comments:
29 
--
30 
----------------------------------------------------------------------------------
31 
 
32 
library IEEE;
33 
use IEEE.STD_LOGIC_1164.ALL;
34 
use IEEE.STD_LOGIC_ARITH.ALL;
35 
use IEEE.STD_LOGIC_UNSIGNED.ALL;
36 
 
37 
library work;
38 
use work.abb64Package.all;
39 
 
40 
-- Uncomment the following library declaration if instantiating
41 
-- any Xilinx primitives in this code.
42 
--library UNISIM;
43 
--use UNISIM.VComponents.all;
44 
 
45 
entity tx_Transact is
46 
    port (
47 
      -- Common ports
48 
      trn_clk            : IN  std_logic;
49 
      trn_reset_n        : IN  std_logic;
50 
      trn_lnk_up_n       : IN  std_logic;
51 
 
52 
      -- Transaction
53 
      trn_tsof_n         : OUT std_logic;
54 
      trn_teof_n         : OUT std_logic;
55 
      trn_td             : OUT std_logic_vector(C_DBUS_WIDTH-1 downto 0);
56 
      trn_trem_n         : OUT std_logic_vector(C_DBUS_WIDTH/8-1 downto 0);
57 
      trn_terrfwd_n      : OUT std_logic;
58 
      trn_tsrc_rdy_n     : OUT std_logic;
59 
      trn_tdst_rdy_n     : IN  std_logic;
60 
      trn_tsrc_dsc_n     : OUT std_logic;
61 
      trn_tdst_dsc_n     : IN  std_logic;
62 
      trn_tbuf_av        : IN  std_logic_vector(C_TBUF_AWIDTH-1 downto 0);
63 
 
64 
      -- Upstream DMA transferred bytes count up
65 
      us_DMA_Bytes_Add   : OUT std_logic;
66 
      us_DMA_Bytes       : OUT std_logic_vector(C_TLP_FLD_WIDTH_OF_LENG+2 downto 0);
67 
 
68 
      -- Event Buffer FIFO read port
69 
      eb_FIFO_re         : OUT std_logic;
70 
      eb_FIFO_empty      : IN  std_logic;
71 
      eb_FIFO_qout       : IN  std_logic_vector(C_DBUS_WIDTH-1 downto 0);
72 
 
73 
      -- Read interface for Tx port
74 
      Regs_RdAddr        : OUT std_logic_vector(C_EP_AWIDTH-1   downto 0);
75 
      Regs_RdQout        : IN  std_logic_vector(C_DBUS_WIDTH-1   downto 0);
76 
 
77 
      -- Irpt Channel
78 
      Irpt_Req           : IN  std_logic;
79 
      Irpt_RE            : OUT std_logic;
80 
      Irpt_Qout          : IN  std_logic_vector(C_CHANNEL_BUF_WIDTH-1 downto 0);
81 
 
82 
      -- PIO MRd Channel
83 
      pioCplD_Req        : IN  std_logic;
84 
      pioCplD_RE         : OUT std_logic;
85 
      pioCplD_Qout       : IN  std_logic_vector(C_CHANNEL_BUF_WIDTH-1 downto 0);
86 
      pio_FC_stop        : OUT std_logic;
87 
 
88 
      -- downstream MRd Channel
89 
      dsMRd_Req          : IN  std_logic;
90 
      dsMRd_RE           : OUT std_logic;
91 
      dsMRd_Qout         : IN  std_logic_vector(C_CHANNEL_BUF_WIDTH-1 downto 0);
92 
 
93 
      -- upstream MWr/MRd Channel
94 
      usTlp_Req          : IN  std_logic;
95 
      usTlp_RE           : OUT std_logic;
96 
      usTlp_Qout         : IN  std_logic_vector(C_CHANNEL_BUF_WIDTH-1 downto 0);
97 
      us_FC_stop         : OUT std_logic;
98 
      us_Last_sof        : OUT std_logic;
99 
      us_Last_eof        : OUT std_logic;
100 
 
101 
      -- Message routing method
102 
      Msg_Routing        : IN  std_logic_vector(C_GCR_MSG_ROUT_BIT_TOP-C_GCR_MSG_ROUT_BIT_BOT downto 0);
103 
 
104 
      --  DDR read port
105 
      DDR_rdc_sof        : OUT   std_logic;
106 
      DDR_rdc_eof        : OUT   std_logic;
107 
      DDR_rdc_v          : OUT   std_logic;
108 
      DDR_rdc_FA         : OUT   std_logic;
109 
      DDR_rdc_Shift      : OUT   std_logic;
110 
      DDR_rdc_din        : OUT   std_logic_vector(C_DBUS_WIDTH-1 downto 0);
111 
      DDR_rdc_full       : IN    std_logic;
112 
 
113 
      -- DDR payload FIFO Read Port
114 
      DDR_FIFO_RdEn      : OUT std_logic;
115 
      DDR_FIFO_Empty     : IN  std_logic;
116 
      DDR_FIFO_RdQout    : IN  std_logic_vector(C_DBUS_WIDTH-1 downto 0);
117 
--      DDR_rdD_sof        : IN    std_logic;
118 
--      DDR_rdD_eof        : IN    std_logic;
119 
--      DDR_rdDout_V       : IN    std_logic;
120 
--      DDR_rdDout         : IN    std_logic_vector(C_DBUS_WIDTH-1 downto 0);
121 
 
122 
 
123 
      -- Additional
124 
      Tx_TimeOut         : OUT   std_logic;
125 
      Tx_eb_TimeOut      : OUT   std_logic;
126 
      Format_Shower      : OUT   std_logic;
127 
      mbuf_UserFull      : IN  std_logic;
128 
      Tx_Reset           : IN  std_logic;
129 
      localID            : IN  std_logic_vector(C_ID_WIDTH-1 downto 0)
130 
    );
131 
 
132 
end tx_Transact;
133 
 
134 
 
135 
architecture Behavioral of tx_Transact is
136 
 
137 
  type TxTrnStates is      ( St_TxIdle           -- Idle
138 
 
139 
                           , St_d_CmdReq         -- Issue the read command to MemReader
140 
                           , St_d_CmdAck         -- Wait for the read command ACK from MemReader
141 
                           , St_d_Header0        -- 1st Header for TLP with payload
142 
                           , St_d_Header2        -- 2nd Header for TLP with payload
143 
--                           , St_d_HeaderPlus     -- Extra Header for TLP4 with payload
144 
                           , St_d_1st_Data       -- Last Header for TLP3/4 with payload
145 
                           , St_d_Payload        -- Data for TLP with payload
146 
                           , St_d_Payload_used   -- Data flow from memory buffer discontinued
147 
                           , St_d_Tail           -- Last data for TLP with payload
148 
                           , St_d_Tail_chk       -- Last data extended for TLP with payload
149 
 
150 
                           , St_nd_Prepare       -- Prepare for 1st Header of TLP without payload
151 
--                           , St_nd_Header1       -- 1st Header for TLP without payload
152 
                           , St_nd_Header2       -- 2nd Header for TLP without payload
153 
--                           , St_nd_HeaderPlus    -- Extra Header for TLP4 without payload
154 
                           , St_nd_HeaderLast    -- Tail processing for the last dword of TLP w/o payload
155 
                           , St_nd_Arbitration   -- One extra cycle for arbitration
156 
                           );
157 
 
158 
  -- State variables
159 
  signal   TxTrn_State            : TxTrnStates;
160 
 
161 
  -- Signals with the arbitrator
162 
  signal   take_an_Arbitration    : std_logic;
163 
  signal   Req_Bundle             : std_logic_vector (C_CHANNEL_NUMBER-1 downto 0);
164 
  signal   Read_a_Buffer          : std_logic_vector (C_CHANNEL_NUMBER-1 downto 0);
165 
  signal   Ack_Indice             : std_logic_vector (C_CHANNEL_NUMBER-1 downto 0);
166 
 
167 
  signal   Tx_Indicator           : std_logic_vector (C_CHANNEL_NUMBER-1 downto 0);
168 
  signal   b1_Tx_Indicator        : std_logic_vector (C_CHANNEL_NUMBER-1 downto 0);
169 
  signal   vec_ChQout_Valid       : std_logic_vector (C_CHANNEL_NUMBER-1 downto 0);
170 
  signal   Tx_Busy                : std_logic;
171 
 
172 
  -- Channel buffer output token bits
173 
  signal   usTLP_is_MWr           : std_logic;
174 
  signal   TLP_is_CplD            : std_logic;
175 
 
176 
  -- Bit information, telling whether the outgoing TLP has payload
177 
  signal   ChBuf_has_Payload      : std_logic;
178 
  signal   ChBuf_No_Payload       : std_logic;
179 
 
180 
  -- Channel buffers output OR'ed and registered
181 
  signal   Trn_Qout_wire          :  std_logic_vector(C_CHANNEL_BUF_WIDTH-1 downto 0);
182 
  signal   Trn_Qout_reg           :  std_logic_vector(C_CHANNEL_BUF_WIDTH-1 downto 0);
183 
 
184 
  --  Addresses from different channel buffer
185 
  signal   mAddr_pioCplD          : std_logic_vector(C_PRAM_AWIDTH-1+2 downto 0);
186 
  signal   mAddr_usTlp            : std_logic_vector(C_PRAM_AWIDTH-1+2 downto 0);
187 
  signal   DDRAddr_usTlp          : std_logic_vector(C_DDR_IAWIDTH-1 downto 0);
188 
  signal   Regs_Addr_pioCplD      : std_logic_vector(C_EP_AWIDTH-1 downto 0);
189 
  signal   DDRAddr_pioCplD        : std_logic_vector(C_DDR_IAWIDTH-1 downto 0);
190 
  --  BAR number
191 
  signal   BAR_pioCplD            : std_logic_vector(C_ENCODE_BAR_NUMBER-1 downto 0);
192 
  signal   BAR_usTlp              : std_logic_vector(C_ENCODE_BAR_NUMBER-1 downto 0);
193 
  --  Misc. info.
194 
  signal   AInc_usTlp             : std_logic;
195 
  signal   pioCplD_is_0Leng       : std_logic;
196 
 
197 
  -- Delay for requests from Channel Buffers
198 
  signal   Irpt_Req_r1            : std_logic;
199 
  signal   pioCplD_Req_r1         : std_logic;
200 
  signal   dsMRd_Req_r1           : std_logic;
201 
  signal   usTlp_Req_r1           : std_logic;
202 
 
203 
  -- Registered channel buffer outputs
204 
  signal   Irpt_Qout_to_TLP       : std_logic_vector(C_CHANNEL_BUF_WIDTH-1 downto 0);
205 
  signal   pioCplD_Qout_to_TLP    : std_logic_vector(C_CHANNEL_BUF_WIDTH-1 downto 0);
206 
  signal   dsMRd_Qout_to_TLP      : std_logic_vector(C_CHANNEL_BUF_WIDTH-1 downto 0);
207 
  signal   usTlp_Qout_to_TLP      : std_logic_vector(C_CHANNEL_BUF_WIDTH-1 downto 0);
208 
 
209 
  signal   pioCplD_Req_Min_Leng   : std_logic;
210 
  signal   pioCplD_Req_2DW_Leng   : std_logic;
211 
  signal   usTlp_Req_Min_Leng     : std_logic;
212 
  signal   usTlp_Req_2DW_Leng     : std_logic;
213 
 
214 
  --  Channel buffer read enables
215 
  signal   Irpt_RE_i              : std_logic;
216 
  signal   pioCplD_RE_i           : std_logic;
217 
  signal   dsMRd_RE_i             : std_logic;
218 
  signal   usTlp_RE_i             : std_logic;
219 
 
220 
  -- Flow controls
221 
  signal   pio_FC_stop_i          : std_logic;
222 
  signal   us_FC_stop_i           : std_logic;
223 
 
224 
  -- Local reset for tx
225 
  signal   trn_tx_Reset_n         : std_logic;
226 
 
227 
  -- Alias for transaction interface signals
228 
  signal   trn_td_i               : std_logic_vector(C_DBUS_WIDTH-1 downto 0);
229 
  signal   trn_tsof_n_i           : std_logic;
230 
  signal   trn_trem_n_i           : std_logic_vector(C_DBUS_WIDTH/8-1 downto 0);
231 
  signal   trn_teof_n_i           : std_logic;
232 
  signal   Format_Shower_i        : std_logic;
233 
 
234 
  signal   trn_tsrc_rdy_n_i       : std_logic;
235 
  signal   trn_tsrc_dsc_n_i       : std_logic;
236 
  signal   trn_terrfwd_n_i        : std_logic;
237 
 
238 
  signal   trn_tdst_rdy_n_i       : std_logic;
239 
 
240 
  signal   trn_tdst_dsc_n_i       : std_logic;
241 
  signal   trn_tbuf_av_i          : std_logic_vector(C_TBUF_AWIDTH-1 downto 0);
242 
 
243 
  -- Upstream DMA transferred bytes count up
244 
  signal   us_DMA_Bytes_Add_i     : std_logic;
245 
  signal   us_DMA_Bytes_i         : std_logic_vector(C_TLP_FLD_WIDTH_OF_LENG+2 downto 0);
246 
 
247 
  ---------------------  Memory Reader  -----------------------------
248 
  ---
249 
  --- Memory reader is the interface to access all sorts of memories
250 
  ---   BRAM, FIFO, Registers, as well as possible DDR SDRAM
251 
  ---
252 
  -------------------------------------------------------------------
253 
  COMPONENT
254 
  tx_Mem_Reader
255 
  PORT(
256 
       DDR_rdc_sof           : OUT   std_logic;
257 
       DDR_rdc_eof           : OUT   std_logic;
258 
       DDR_rdc_v             : OUT   std_logic;
259 
       DDR_rdc_FA            : OUT   std_logic;
260 
       DDR_rdc_Shift         : OUT   std_logic;
261 
       DDR_rdc_din           : OUT   std_logic_vector(C_DBUS_WIDTH-1 downto 0);
262 
       DDR_rdc_full          : IN    std_logic;
263 
 
264 
--       DDR_rdD_sof           : IN    std_logic;
265 
--       DDR_rdD_eof           : IN    std_logic;
266 
--       DDR_rdDout_V          : IN    std_logic;
267 
--       DDR_rdDout            : IN    std_logic_vector(C_DBUS_WIDTH-1 downto 0);
268 
 
269 
       DDR_FIFO_RdEn         : OUT   std_logic;
270 
       DDR_FIFO_Empty        : IN    std_logic;
271 
       DDR_FIFO_RdQout       : IN    std_logic_vector(C_DBUS_WIDTH-1 downto 0);
272 
 
273 
       eb_FIFO_re            : OUT   std_logic;
274 
       eb_FIFO_empty         : IN    std_logic;
275 
       eb_FIFO_qout          : IN    std_logic_vector(C_DBUS_WIDTH-1 downto 0);
276 
 
277 
       Regs_RdAddr           : OUT   std_logic_vector(C_EP_AWIDTH-1 downto 0);
278 
       Regs_RdQout           : IN    std_logic_vector(C_DBUS_WIDTH-1 downto 0);
279 
 
280 
       RdNumber              : IN    std_logic_vector(C_TLP_FLD_WIDTH_OF_LENG-1 downto 0);
281 
       RdNumber_eq_One       : IN    std_logic;
282 
       RdNumber_eq_Two       : IN    std_logic;
283 
       StartAddr             : IN    std_logic_vector(C_DBUS_WIDTH-1 downto 0);
284 
       Shift_1st_QWord       : IN    std_logic;
285 
       FixedAddr             : IN    std_logic;
286 
       is_CplD               : IN    std_logic;
287 
       BAR_value             : IN    std_logic_vector(C_ENCODE_BAR_NUMBER-1 downto 0);
288 
       RdCmd_Req             : IN    std_logic;
289 
       RdCmd_Ack             : OUT   std_logic;
290 
 
291 
       mbuf_WE               : OUT   std_logic;
292 
       mbuf_Din              : OUT   std_logic_vector(C_DBUS_WIDTH*9/8-1 downto 0);
293 
       mbuf_Full             : IN    std_logic;
294 
       mbuf_aFull            : IN    std_logic;
295 
       mbuf_UserFull         : IN    std_logic;
296 
 
297 
       Tx_TimeOut            : OUT   std_logic;
298 
       Tx_eb_TimeOut         : OUT   std_logic;
299 
       mReader_Rst_n         : IN    std_logic;
300 
       trn_clk               : IN    std_logic
301 
      );
302 
  END COMPONENT;
303 
 
304 
  signal   RdNumber               : std_logic_vector(C_TLP_FLD_WIDTH_OF_LENG-1 downto 0);
305 
  signal   RdNumber_eq_One        : std_logic;
306 
  signal   RdNumber_eq_Two        : std_logic;
307 
  signal   StartAddr              : std_logic_vector(C_DBUS_WIDTH-1 downto 0);
308 
  signal   Shift_1st_QWord        : std_logic;
309 
  signal   FixedAddr              : std_logic;
310 
  signal   is_CplD                : std_logic;
311 
  signal   BAR_value              : std_logic_vector(C_ENCODE_BAR_NUMBER-1 downto 0);
312 
  signal   RdCmd_Req              : std_logic;
313 
  signal   RdCmd_Ack              : std_logic;
314 
 
315 
 
316 
  ---------------------  Memory Buffer  -----------------------------
317 
  ---
318 
  --- A unified memory buffer holding the payload for the next tx TLP
319 
  ---   34 bits wide, wherein 2 additional framing bits
320 
  ---   temporarily 64 data depth, possibly deepened.
321 
  ---
322 
  -------------------------------------------------------------------
323 
  component
324 
  v6_mBuf_128x72
325 
  port (
326 
        clk                  : IN     std_logic;
327 
        rst                  : IN     std_logic;
328 
        wr_en                : IN     std_logic;
329 
        din                  : IN     std_logic_VECTOR(C_DBUS_WIDTH*9/8-1 downto 0);
330 
        prog_full            : OUT    std_logic;
331 
        full                 : OUT    std_logic;
332 
        rd_en                : IN     std_logic;
333 
        dout                 : OUT    std_logic_VECTOR(C_DBUS_WIDTH*9/8-1 downto 0);
334 
        empty                : OUT    std_logic
335 
       );
336 
  end component;
337 
 
338 
  signal   mbuf_reset             : std_logic;
339 
  signal   mbuf_WE                : std_logic;
340 
  signal   mbuf_Din               : std_logic_VECTOR(C_DBUS_WIDTH*9/8-1 downto 0);
341 
  signal   mbuf_Full              : std_logic;
342 
  signal   mbuf_aFull             : std_logic;
343 
  signal   mbuf_RE                : std_logic;
344 
  signal   mbuf_Qout              : std_logic_VECTOR(C_DBUS_WIDTH*9/8-1 downto 0);
345 
  signal   mbuf_Empty             : std_logic;
346 
  -- Calculated infomation
347 
  signal   mbuf_RE_ok             : std_logic;
348 
  signal   mbuf_Qvalid            : std_logic;
349 
 
350 
  ---------------------  Output arbitration  ------------------------
351 
  ---
352 
  --- For sake of fairness, the priorities are cycled every time
353 
  ---   a service is done, after which the priority of the request
354 
  ---   just serviced is set to the lowest and other lower priorities
355 
  ---   increased and higher stay.
356 
  ---
357 
  -------------------------------------------------------------------
358 
  COMPONENT
359 
  Tx_Output_Arbitor
360 
  PORT(
361 
        rst_n                : IN    std_logic;
362 
        clk                  : IN    std_logic;
363 
        arbtake              : IN    std_logic;
364 
        Req                  : IN    std_logic_vector(C_ARBITRATE_WIDTH-1 downto 0);
365 
        bufread              : OUT   std_logic_vector(C_ARBITRATE_WIDTH-1 downto 0);
366 
        Ack                  : OUT   std_logic_vector(C_ARBITRATE_WIDTH-1 downto 0)
367 
      );
368 
  END COMPONENT;
369 
 
370 
 
371 
begin
372 
 
373 
   -- Connect outputs
374 
   trn_td                <= trn_td_i;
375 
   trn_tsof_n            <= trn_tsof_n_i;
376 
   trn_trem_n            <= trn_trem_n_i;
377 
   trn_teof_n            <= trn_teof_n_i;
378 
 
379 
   trn_tsrc_rdy_n        <= trn_tsrc_rdy_n_i;
380 
   trn_tsrc_dsc_n        <= trn_tsrc_dsc_n_i;
381 
   trn_terrfwd_n         <= trn_terrfwd_n_i;
382 
 
383 
   Format_Shower         <= Format_Shower_i;
384 
   us_Last_sof           <= usTLP_is_MWr and not trn_tsof_n_i;
385 
   us_Last_eof           <= usTLP_is_MWr and not trn_teof_n_i;
386 
 
387 
   -- Connect inputs
388 
   trn_tdst_rdy_n_i      <= trn_tdst_rdy_n;
389 
   trn_tdst_dsc_n_i      <= trn_tdst_dsc_n;
390 
   trn_tbuf_av_i         <= trn_tbuf_av;
391 
 
392 
 
393 
   -- Always deasserted
394 
   trn_tsrc_dsc_n_i      <= '1';
395 
   trn_terrfwd_n_i       <= '1';
396 
--   trn_trem_n_i          <= (OTHERS=>'0');
397 
 
398 
 
399 
   -- Upstream DMA transferred bytes counting up
400 
   us_DMA_Bytes_Add      <= us_DMA_Bytes_Add_i;
401 
   us_DMA_Bytes          <= us_DMA_Bytes_i    ;
402 
 
403 
 
404 
   -- Flow controls
405 
   pio_FC_stop           <= pio_FC_stop_i;
406 
   us_FC_stop            <= us_FC_stop_i;
407 
 
408 
---------------------------------------------------------------------------------
409 
-- Synchronous Calculation: us_FC_stop, pio_FC_stop
410 
--
411 
   Synch_Calc_FC_stop:
412 
   process ( trn_clk, Tx_Reset)
413 
   begin
414 
      if Tx_Reset = '1' then
415 
         us_FC_stop_i        <= '1';
416 
         pio_FC_stop_i       <= '1';
417 
      elsif trn_clk'event and trn_clk = '1' then
418 
        if trn_tbuf_av_i(C_TBUF_AWIDTH-1 downto 1) /=C_ALL_ZEROS(C_TBUF_AWIDTH-1 downto 1) then
419 
           us_FC_stop_i        <= '0';
420 
           pio_FC_stop_i       <= '0';
421 
        else
422 
           us_FC_stop_i        <= '1';
423 
           pio_FC_stop_i       <= '1';
424 
        end if;
425 
      end if;
426 
   end process;
427 
 
428 
 
429 
   -- Channel buffer read enable
430 
   Irpt_RE               <= Irpt_RE_i;
431 
   pioCplD_RE            <= pioCplD_RE_i;
432 
   dsMRd_RE              <= dsMRd_RE_i;
433 
   usTlp_RE              <= usTlp_RE_i;
434 
 
435 
 
436 
-- -----------------------------------
437 
--   Synchronized Local reset
438 
--
439 
   Syn_Local_Reset:
440 
   process ( trn_clk, trn_reset_n)
441 
   begin
442 
      if trn_reset_n = '0' then
443 
         trn_tx_Reset_n   <= '0';
444 
      elsif trn_clk'event and trn_clk = '1' then
445 
         trn_tx_Reset_n   <= trn_tdst_dsc_n_i and not Tx_Reset;
446 
      end if;
447 
   end process;
448 
 
449 
-- -----------------------------------
450 
--   Format detector
451 
--
452 
   Syn_Format_Shower:
453 
   process ( trn_clk, trn_reset_n)
454 
   begin
455 
      if trn_reset_n = '0' then
456 
         Format_Shower_i   <= '0';
457 
      elsif trn_clk'event and trn_clk = '1' then
458 
         if Format_Shower_i = '0' then
459 
           if trn_tsof_n_i='0' and trn_tsrc_rdy_n_i='0' and trn_tdst_rdy_n_i='0' then
460 
              Format_Shower_i   <= '1';
461 
           else
462 
              Format_Shower_i   <= '0';
463 
           end if;
464 
         else
465 
           if trn_teof_n_i='0' and trn_tsrc_rdy_n_i='0' and trn_tdst_rdy_n_i='0' then
466 
              Format_Shower_i   <= '0';
467 
           else
468 
              Format_Shower_i   <= '1';
469 
           end if;
470 
         end if;
471 
      end if;
472 
   end process;
473 
 
474 
------------------------------------------------------------
475 
---             Memory reader
476 
------------------------------------------------------------
477 
   ABB_Tx_MReader:
478 
   tx_Mem_Reader
479 
   PORT MAP(
480 
            DDR_rdc_sof     => DDR_rdc_sof     ,  --  OUT   std_logic;
481 
            DDR_rdc_eof     => DDR_rdc_eof     ,  --  OUT   std_logic;
482 
            DDR_rdc_v       => DDR_rdc_v       ,  --  OUT   std_logic;
483 
            DDR_rdc_FA      => DDR_rdc_FA      ,  --  OUT   std_logic;
484 
            DDR_rdc_Shift   => DDR_rdc_Shift   ,  --  OUT   std_logic;
485 
            DDR_rdc_din     => DDR_rdc_din     ,  --  OUT   std_logic_vector(C_DBUS_WIDTH-1 downto 0);
486 
            DDR_rdc_full    => DDR_rdc_full    ,  --  IN    std_logic;
487 
 
488 
--            DDR_rdD_sof     => DDR_rdD_sof     ,  --  IN    std_logic;
489 
--            DDR_rdD_eof     => DDR_rdD_eof     ,  --  IN    std_logic;
490 
--            DDR_rdDout_V    => DDR_rdDout_V    ,  --  IN    std_logic;
491 
--            DDR_rdDout      => DDR_rdDout      ,  --  IN    std_logic_vector(C_DBUS_WIDTH-1 downto 0);
492 
 
493 
            DDR_FIFO_RdEn   => DDR_FIFO_RdEn   ,  -- OUT std_logic;
494 
            DDR_FIFO_Empty  => DDR_FIFO_Empty  ,  -- IN  std_logic;
495 
            DDR_FIFO_RdQout => DDR_FIFO_RdQout ,  -- IN  std_logic_vector(C_DBUS_WIDTH-1 downto 0);
496 
 
497 
            eb_FIFO_re      => eb_FIFO_re      ,  -- OUT std_logic;
498 
            eb_FIFO_empty   => eb_FIFO_empty   ,  -- IN  std_logic;
499 
            eb_FIFO_qout    => eb_FIFO_qout    ,  -- IN  std_logic_vector(C_DBUS_WIDTH-1 downto 0);
500 
 
501 
            Regs_RdAddr     => Regs_RdAddr     ,  -- OUT std_logic_vector(C_EP_AWIDTH-1 downto 0);
502 
            Regs_RdQout     => Regs_RdQout     ,  -- IN  std_logic_vector(C_DBUS_WIDTH-1 downto 0);
503 
 
504 
            RdNumber        => RdNumber        ,  -- IN  std_logic_vector(C_DBUS_WIDTH-1 downto 0);
505 
            RdNumber_eq_One => RdNumber_eq_One ,  -- IN  std_logic;
506 
            RdNumber_eq_Two => RdNumber_eq_Two ,  -- IN  std_logic;
507 
            StartAddr       => StartAddr       ,  -- IN  std_logic_vector(C_DBUS_WIDTH-1 downto 0);
508 
            Shift_1st_QWord => Shift_1st_QWord ,  -- IN  std_logic;
509 
            FixedAddr       => '0',         -- FixedAddr       ,  -- IN  std_logic;
510 
            is_CplD         => is_CplD         ,  -- IN  std_logic;
511 
            BAR_value       => BAR_value       ,  -- IN  std_logic_vector(C_ENCODE_BAR_NUMBER-1 downto 0);
512 
            RdCmd_Req       => RdCmd_Req       ,  -- IN  std_logic;
513 
            RdCmd_Ack       => RdCmd_Ack       ,  -- OUT std_logic;
514 
 
515 
            mbuf_WE         => mbuf_WE         ,  -- OUT std_logic;
516 
            mbuf_Din        => mbuf_Din        ,  -- OUT std_logic_vector(C_DBUS_WIDTH-1 downto 0);
517 
            mbuf_Full       => mbuf_Full       ,  -- IN  std_logic;
518 
            mbuf_aFull      => mbuf_aFull      ,  -- IN  std_logic;
519 
            mbuf_UserFull   => mbuf_UserFull   ,  -- IN  std_logic;
520 
 
521 
            Tx_TimeOut      => Tx_TimeOut      ,  -- OUT std_logic;
522 
            Tx_eb_TimeOut   => Tx_eb_TimeOut   ,  -- OUT std_logic;
523 
            mReader_Rst_n   => trn_tx_Reset_n  ,  -- IN  std_logic;
524 
            trn_clk         => trn_clk            -- IN  std_logic
525 
           );
526 
 
527 
 
528 
------------------------------------------------------------
529 
---             Memory buffer
530 
------------------------------------------------------------
531 
   ABB_Tx_MBuffer:
532 
   v6_mBuf_128x72
533 
   PORT MAP(
534 
            wr_en         => mbuf_WE               , -- IN  std_logic;
535 
            din           => mbuf_Din              , -- IN  std_logic_VECTOR(C_DBUS_WIDTH+1 downto 0);
536 
            prog_full     => mbuf_aFull            , -- OUT std_logic;
537 
            full          => mbuf_Full             , -- OUT std_logic;
538 
            rd_en         => mbuf_RE               , -- IN  std_logic;
539 
            dout          => mbuf_Qout             , -- OUT std_logic_VECTOR(C_DBUS_WIDTH+1 downto 0);
540 
            empty         => mbuf_Empty            , -- OUT std_logic
541 
            rst           => mbuf_reset, --Tx_Reset              , -- IN  std_logic;
542 
            clk           => trn_clk                 -- IN  std_logic;
543 
           );
544 
 
545 
   mbuf_RE        <=  mbuf_RE_ok and (not trn_tdst_rdy_n_i or trn_tsrc_rdy_n_i);
546 
 
547 
---------------------------------------------------------------------------------
548 
-- Synchronous Delay: mbuf_Qout Valid
549 
--
550 
   Synchron_Delay_mbuf_Qvalid:
551 
   process ( trn_clk, Tx_Reset)
552 
   begin
553 
      if Tx_Reset = '1' then
554 
         mbuf_Qvalid        <= '0';
555 
      elsif trn_clk'event and trn_clk = '1' then
556 
        if     mbuf_Qvalid='0' and mbuf_RE='1' and mbuf_Empty='0' then  -- a valid data is going out
557 
           mbuf_Qvalid          <= '1';
558 
        elsif  mbuf_Qvalid='1' and mbuf_RE='1' and mbuf_Empty='1' then  -- an invalid data is going out
559 
           mbuf_Qvalid          <= '0';
560 
        else                                                        -- state stays
561 
           mbuf_Qvalid          <= mbuf_Qvalid;
562 
        end if;
563 
      end if;
564 
   end process;
565 
 
566 
 
567 
------------------------------------------------------------
568 
---             Output arbitration
569 
------------------------------------------------------------
570 
   O_Arbitration:
571 
   Tx_Output_Arbitor
572 
   PORT MAP(
573 
            rst_n         => trn_tx_Reset_n,
574 
            clk           => trn_clk,
575 
            arbtake       => take_an_Arbitration,
576 
            Req           => Req_Bundle,
577 
            bufread       => Read_a_Buffer,
578 
            Ack           => Ack_Indice
579 
           );
580 
 
581 
 
582 
-----------------------------------------------------
583 
-- Synchronous Delay: Channel Requests
584 
--
585 
   Synchron_Delay_ChRequests:
586 
   process ( trn_clk )
587 
   begin
588 
     if trn_clk'event and trn_clk = '1' then
589 
         Irpt_Req_r1      <= Irpt_Req;
590 
         pioCplD_Req_r1   <= pioCplD_Req;
591 
         dsMRd_Req_r1     <= dsMRd_Req;
592 
         usTlp_Req_r1     <= usTlp_Req;
593 
      end if;
594 
   end process;
595 
 
596 
 
597 
-----------------------------------------------------
598 
-- Synchronous Delay: Tx_Busy
599 
--
600 
   Synchron_Delay_Tx_Busy:
601 
   process ( trn_clk )
602 
   begin
603 
     if trn_clk'event and trn_clk = '1' then
604 
         Tx_Indicator     <= b1_Tx_Indicator;
605 
         Tx_Busy          <= (b1_Tx_Indicator(C_CHAN_INDEX_IRPT)   and vec_ChQout_Valid(C_CHAN_INDEX_IRPT)  )
606 
                          or (b1_Tx_Indicator(C_CHAN_INDEX_MRD)    and vec_ChQout_Valid(C_CHAN_INDEX_MRD)   )
607 
                          or (b1_Tx_Indicator(C_CHAN_INDEX_DMA_DS) and vec_ChQout_Valid(C_CHAN_INDEX_DMA_DS))
608 
                          or (b1_Tx_Indicator(C_CHAN_INDEX_DMA_US) and vec_ChQout_Valid(C_CHAN_INDEX_DMA_US))
609 
                          ;
610 
      end if;
611 
   end process;
612 
 
613 
 
614 
-- ---------------------------------------------
615 
-- Reg : Channel Buffer Qout has Payload
616 
--
617 
   Reg_ChBuf_with_Payload:
618 
   process ( trn_clk )
619 
   begin
620 
      if trn_clk'event and trn_clk = '1' then
621 
         ChBuf_has_Payload     <= (b1_Tx_Indicator(C_CHAN_INDEX_MRD)    and TLP_is_CplD  and vec_ChQout_Valid(C_CHAN_INDEX_MRD)   )
622 
                               or (b1_Tx_Indicator(C_CHAN_INDEX_DMA_US) and usTLP_is_MWr and vec_ChQout_Valid(C_CHAN_INDEX_DMA_US))
623 
                               ;
624 
      end if;
625 
   end process;
626 
 
627 
-- ---------------------------------------------
628 
-- Channel Buffer Qout has no Payload
629 
--   (! subordinate to ChBuf_has_Payload ! )
630 
--
631 
   ChBuf_No_Payload      <=   Tx_Busy;
632 
 
633 
 
634 
-- Arbitrator inputs
635 
   Req_Bundle(C_CHAN_INDEX_IRPT)         <= Irpt_Req_r1;
636 
   Req_Bundle(C_CHAN_INDEX_MRD)          <= pioCplD_Req_r1;
637 
   Req_Bundle(C_CHAN_INDEX_DMA_DS)       <= dsMRd_Req_r1;
638 
   Req_Bundle(C_CHAN_INDEX_DMA_US)       <= usTlp_Req_r1;
639 
 
640 
-- Arbitrator outputs
641 
   b1_Tx_Indicator(C_CHAN_INDEX_IRPT)    <= Ack_Indice(C_CHAN_INDEX_IRPT);
642 
   b1_Tx_Indicator(C_CHAN_INDEX_MRD)     <= Ack_Indice(C_CHAN_INDEX_MRD);
643 
   b1_Tx_Indicator(C_CHAN_INDEX_DMA_DS)  <= Ack_Indice(C_CHAN_INDEX_DMA_DS);
644 
   b1_Tx_Indicator(C_CHAN_INDEX_DMA_US)  <= Ack_Indice(C_CHAN_INDEX_DMA_US);
645 
 
646 
 
647 
-- Arbitrator reads channel buffers
648 
   Irpt_RE_i                             <= Read_a_Buffer(C_CHAN_INDEX_IRPT);
649 
   pioCplD_RE_i                          <= Read_a_Buffer(C_CHAN_INDEX_MRD);
650 
   dsMRd_RE_i                            <= Read_a_Buffer(C_CHAN_INDEX_DMA_DS);
651 
   usTlp_RE_i                            <= Read_a_Buffer(C_CHAN_INDEX_DMA_US);
652 
 
653 
 
654 
-- determine whether the upstream TLP is an MWr or an MRd.
655 
   usTLP_is_MWr          <= usTlp_Qout  (C_CHBUF_FMT_BIT_TOP);
656 
   TLP_is_CplD           <= pioCplD_Qout(C_CHBUF_FMT_BIT_TOP);
657 
 
658 
 
659 
-- check if the Channel buffer output is valid
660 
   vec_ChQout_Valid(C_CHAN_INDEX_IRPT)    <= Irpt_Qout   (C_CHBUF_QVALID_BIT);
661 
   vec_ChQout_Valid(C_CHAN_INDEX_MRD)     <= pioCplD_Qout(C_CHBUF_QVALID_BIT);
662 
   vec_ChQout_Valid(C_CHAN_INDEX_DMA_DS)  <= dsMRd_Qout  (C_CHBUF_QVALID_BIT);
663 
   vec_ChQout_Valid(C_CHAN_INDEX_DMA_US)  <= usTlp_Qout  (C_CHBUF_QVALID_BIT);
664 
 
665 
 
666 
-- -----------------------------------
667 
-- Delay : Channel_Buffer_Qout
668 
--         Bit-mapping is done
669 
--
670 
   Delay_Channel_Buffer_Qout:
671 
   process ( trn_clk, trn_tx_Reset_n)
672 
   begin
673 
      if trn_tx_Reset_n = '0' then
674 
         Irpt_Qout_to_TLP      <= (Others=>'0');
675 
         pioCplD_Qout_to_TLP   <= (Others=>'0');
676 
         dsMRd_Qout_to_TLP     <= (Others=>'0');
677 
         usTlp_Qout_to_TLP     <= (Others=>'0');
678 
 
679 
         pioCplD_Req_Min_Leng  <= '0';
680 
         pioCplD_Req_2DW_Leng  <= '0';
681 
         usTlp_Req_Min_Leng    <= '0';
682 
         usTlp_Req_2DW_Leng    <= '0';
683 
 
684 
         Regs_Addr_pioCplD     <= (Others=>'1');
685 
         mAddr_pioCplD         <= (Others=>'1');
686 
         mAddr_usTlp           <= (Others=>'1');
687 
         AInc_usTlp            <= '1';
688 
         BAR_pioCplD           <= (Others=>'1');
689 
         BAR_usTlp             <= (Others=>'1');
690 
         pioCplD_is_0Leng      <= '0';
691 
 
692 
      elsif trn_clk'event and trn_clk = '1' then
693 
 
694 
         if b1_Tx_Indicator(C_CHAN_INDEX_IRPT)='1' then
695 
            Irpt_Qout_to_TLP  <= (Others=>'0');   -- must be 1st argument
696 
            -- 1st header Hi
697 
            Irpt_Qout_to_TLP(C_TLP_FMT_BIT_TOP downto C_TLP_FMT_BIT_BOT)    <= Irpt_Qout(C_CHBUF_FMT_BIT_TOP downto C_CHBUF_FMT_BIT_BOT);
698 
--            Irpt_Qout_to_TLP(C_TLP_TYPE_BIT_TOP downto C_TLP_TYPE_BIT_BOT)  <= C_TYPE_OF_MSG; --Irpt_Qout(C_CHBUF_MSGTYPE_BIT_TOP downto C_CHBUF_MSGTYPE_BIT_BOT);
699 
            Irpt_Qout_to_TLP(C_TLP_TYPE_BIT_TOP downto C_TLP_TYPE_BIT_BOT)  <= C_TYPE_OF_MSG(C_TLP_TYPE_BIT_TOP
700 
                                                                               downto C_TLP_TYPE_BIT_BOT+1+C_GCR_MSG_ROUT_BIT_TOP-C_GCR_MSG_ROUT_BIT_BOT)
701 
                                                                             & Msg_Routing;
702 
            Irpt_Qout_to_TLP(C_TLP_TC_BIT_TOP   downto C_TLP_TC_BIT_BOT)    <= Irpt_Qout(C_CHBUF_TC_BIT_TOP downto C_CHBUF_TC_BIT_BOT);
703 
            Irpt_Qout_to_TLP(C_TLP_LENG_BIT_TOP downto C_TLP_LENG_BIT_BOT)  <= Irpt_Qout(C_CHBUF_LENG_BIT_TOP downto C_CHBUF_LENG_BIT_BOT);
704 
 
705 
            -- 1st header Lo
706 
            Irpt_Qout_to_TLP(C_TLP_REQID_BIT_TOP downto C_TLP_REQID_BIT_BOT)  <= localID;
707 
            Irpt_Qout_to_TLP(C_TLP_TAG_BIT_TOP   downto C_TLP_TAG_BIT_BOT)    <= Irpt_Qout(C_CHBUF_TAG_BIT_TOP downto C_CHBUF_TAG_BIT_BOT);
708 
            Irpt_Qout_to_TLP(C_MSG_CODE_BIT_TOP  downto C_MSG_CODE_BIT_BOT)   <= Irpt_Qout(C_CHBUF_MSG_CODE_BIT_TOP downto C_CHBUF_MSG_CODE_BIT_BOT);
709 
            -- 2nd headers all zero
710 
            -- ...
711 
 
712 
         else
713 
            Irpt_Qout_to_TLP     <= (Others=>'0');
714 
         end if;
715 
 
716 
 
717 
         if b1_Tx_Indicator(C_CHAN_INDEX_MRD)='1' then
718 
            pioCplD_Qout_to_TLP  <= (Others=>'0');   -- must be 1st argument
719 
            -- 1st header Hi
720 
            pioCplD_Qout_to_TLP(C_TLP_FMT_BIT_TOP  downto C_TLP_FMT_BIT_BOT)   <= pioCplD_Qout(C_CHBUF_FMT_BIT_TOP  downto C_CHBUF_FMT_BIT_BOT);
721 
            pioCplD_Qout_to_TLP(C_TLP_TYPE_BIT_TOP downto C_TLP_TYPE_BIT_BOT)  <= C_TYPE_COMPLETION; --pioCplD_Qout(C_CHBUF_TYPE_BIT_TOP downto C_CHBUF_TYPE_BIT_BOT);
722 
            pioCplD_Qout_to_TLP(C_TLP_TC_BIT_TOP   downto C_TLP_TC_BIT_BOT)    <= pioCplD_Qout(C_CHBUF_TC_BIT_TOP   downto C_CHBUF_TC_BIT_BOT);
723 
            pioCplD_Qout_to_TLP(C_TLP_ATTR_BIT_TOP downto C_TLP_ATTR_BIT_BOT)  <= pioCplD_Qout(C_CHBUF_ATTR_BIT_TOP downto C_CHBUF_ATTR_BIT_BOT);
724 
            pioCplD_Qout_to_TLP(C_TLP_LENG_BIT_TOP downto C_TLP_LENG_BIT_BOT)  <= pioCplD_Qout(C_CHBUF_LENG_BIT_TOP downto C_CHBUF_LENG_BIT_BOT);
725 
            -- 1st header Lo
726 
            pioCplD_Qout_to_TLP(C_CPLD_CPLT_ID_BIT_TOP downto C_CPLD_CPLT_ID_BIT_BOT)  <= localID;
727 
            pioCplD_Qout_to_TLP(C_CPLD_CS_BIT_TOP     downto C_CPLD_CS_BIT_BOT)        <= pioCplD_Qout(C_CHBUF_CPLD_CS_BIT_TOP downto C_CHBUF_CPLD_CS_BIT_BOT);
728 
            pioCplD_Qout_to_TLP(C_CPLD_BC_BIT_TOP     downto C_CPLD_BC_BIT_BOT)        <= pioCplD_Qout(C_CHBUF_CPLD_BC_BIT_TOP downto C_CHBUF_CPLD_BC_BIT_BOT);
729 
            -- 2nd header Hi
730 
            pioCplD_Qout_to_TLP(C_DBUS_WIDTH+C_CPLD_REQID_BIT_TOP downto C_DBUS_WIDTH+C_CPLD_REQID_BIT_BOT)  <= pioCplD_Qout(C_CHBUF_CPLD_REQID_BIT_TOP downto C_CHBUF_CPLD_REQID_BIT_BOT);
731 
            pioCplD_Qout_to_TLP(C_DBUS_WIDTH+C_CPLD_TAG_BIT_TOP   downto C_DBUS_WIDTH+C_CPLD_TAG_BIT_BOT)    <= pioCplD_Qout(C_CHBUF_CPLD_TAG_BIT_TOP   downto C_CHBUF_CPLD_TAG_BIT_BOT);
732 
            pioCplD_Qout_to_TLP(C_DBUS_WIDTH+C_CPLD_LA_BIT_TOP    downto C_DBUS_WIDTH+C_CPLD_LA_BIT_BOT)     <= pioCplD_Qout(C_CHBUF_CPLD_LA_BIT_TOP    downto C_CHBUF_CPLD_LA_BIT_BOT);
733 
            -- no 2nd header Lo
734 
 
735 
            if pioCplD_Qout(C_CHBUF_LENG_BIT_TOP downto C_CHBUF_LENG_BIT_BOT)
736 
               = CONV_STD_LOGIC_VECTOR(1, C_TLP_FLD_WIDTH_OF_LENG)
737 
               then
738 
               pioCplD_Req_Min_Leng  <= '1';
739 
            else
740 
               pioCplD_Req_Min_Leng  <= '0';
741 
            end if;
742 
            if pioCplD_Qout(C_CHBUF_LENG_BIT_TOP downto C_CHBUF_LENG_BIT_BOT)
743 
               = CONV_STD_LOGIC_VECTOR(2, C_TLP_FLD_WIDTH_OF_LENG)
744 
               then
745 
               pioCplD_Req_2DW_Leng  <= '1';
746 
            else
747 
               pioCplD_Req_2DW_Leng  <= '0';
748 
            end if;
749 
 
750 
            -- Misc
751 
            Regs_Addr_pioCplD    <= pioCplD_Qout(C_CHBUF_PA_BIT_TOP downto C_CHBUF_PA_BIT_BOT);
752 
            mAddr_pioCplD        <= pioCplD_Qout(C_CHBUF_MA_BIT_TOP downto C_CHBUF_MA_BIT_BOT);  -- !! C_CHBUF_MA_BIT_BOT);
753 
            DDRAddr_pioCplD      <= pioCplD_Qout(C_CHBUF_DDA_BIT_TOP downto C_CHBUF_DDA_BIT_BOT);
754 
            BAR_pioCplD          <= pioCplD_Qout(C_CHBUF_CPLD_BAR_BIT_TOP downto C_CHBUF_CPLD_BAR_BIT_BOT);
755 
            pioCplD_is_0Leng     <= pioCplD_Qout(C_CHBUF_0LENG_BIT);
756 
         else
757 
            pioCplD_Req_Min_Leng <= '0';
758 
            pioCplD_Req_2DW_Leng <= '0';
759 
            pioCplD_Qout_to_TLP  <= (Others=>'0');
760 
            Regs_Addr_pioCplD    <= (Others=>'1');
761 
            mAddr_pioCplD        <= (Others=>'1');
762 
            DDRAddr_pioCplD      <= (Others=>'1');
763 
            BAR_pioCplD          <= (Others=>'1');
764 
            pioCplD_is_0Leng     <= '0';
765 
         end if;
766 
 
767 
 
768 
         if b1_Tx_Indicator(C_CHAN_INDEX_DMA_US)='1' then
769 
            usTlp_Qout_to_TLP  <= (Others=>'0');   -- must be 1st argument
770 
            -- 1st header HI
771 
            usTlp_Qout_to_TLP(C_TLP_FMT_BIT_TOP  downto C_TLP_FMT_BIT_BOT)   <= usTlp_Qout(C_CHBUF_FMT_BIT_TOP  downto C_CHBUF_FMT_BIT_BOT);
772 
            usTlp_Qout_to_TLP(C_TLP_TYPE_BIT_TOP downto C_TLP_TYPE_BIT_BOT)  <= C_ALL_ZEROS(C_TLP_TYPE_BIT_TOP  downto C_TLP_TYPE_BIT_BOT);
773 
            usTlp_Qout_to_TLP(C_TLP_TC_BIT_TOP   downto C_TLP_TC_BIT_BOT)    <= usTlp_Qout(C_CHBUF_TC_BIT_TOP   downto C_CHBUF_TC_BIT_BOT);
774 
            usTlp_Qout_to_TLP(C_TLP_ATTR_BIT_TOP downto C_TLP_ATTR_BIT_BOT)  <= usTlp_Qout(C_CHBUF_ATTR_BIT_TOP downto C_CHBUF_ATTR_BIT_BOT);
775 
            usTlp_Qout_to_TLP(C_TLP_LENG_BIT_TOP downto C_TLP_LENG_BIT_BOT)  <= usTlp_Qout(C_CHBUF_LENG_BIT_TOP downto C_CHBUF_LENG_BIT_BOT);
776 
            -- 1st header LO
777 
            usTlp_Qout_to_TLP(C_TLP_REQID_BIT_TOP   downto C_TLP_REQID_BIT_BOT)    <= localID;
778 
            usTlp_Qout_to_TLP(C_TLP_TAG_BIT_TOP     downto C_TLP_TAG_BIT_BOT)      <= usTlp_Qout(C_CHBUF_TAG_BIT_TOP   downto C_CHBUF_TAG_BIT_BOT);
779 
            usTlp_Qout_to_TLP(C_TLP_LAST_BE_BIT_TOP downto C_TLP_LAST_BE_BIT_BOT)  <= C_ALL_ONES(C_TLP_LAST_BE_BIT_TOP downto C_TLP_LAST_BE_BIT_BOT);
780 
            usTlp_Qout_to_TLP(C_TLP_1ST_BE_BIT_TOP  downto C_TLP_1ST_BE_BIT_BOT)   <= C_ALL_ONES(C_TLP_1ST_BE_BIT_TOP  downto C_TLP_1ST_BE_BIT_BOT);
781 
            -- 2nd header HI (Address)
782 
--            usTlp_Qout_to_TLP(2*C_DBUS_WIDTH-1 downto C_DBUS_WIDTH)    <= usTlp_Qout(C_CHBUF_HA_BIT_TOP downto C_CHBUF_HA_BIT_BOT);
783 
            if usTlp_Qout(C_CHBUF_FMT_BIT_BOT)='1' then  -- 4DW MWr
784 
               usTlp_Qout_to_TLP(2*C_DBUS_WIDTH-1 downto C_DBUS_WIDTH+32)    <= usTlp_Qout(C_CHBUF_HA_BIT_TOP downto C_CHBUF_HA_BIT_BOT+32);
785 
            else
786 
               usTlp_Qout_to_TLP(2*C_DBUS_WIDTH-1 downto C_DBUS_WIDTH+32)    <= usTlp_Qout(C_CHBUF_HA_BIT_TOP-32 downto C_CHBUF_HA_BIT_BOT);
787 
            end if;
788 
            -- 2nd header LO (Address)
789 
            usTlp_Qout_to_TLP(2*C_DBUS_WIDTH-1-32 downto C_DBUS_WIDTH)    <= usTlp_Qout(C_CHBUF_HA_BIT_TOP-32 downto C_CHBUF_HA_BIT_BOT);
790 
 
791 
            --
792 
            if usTlp_Qout(C_CHBUF_LENG_BIT_TOP downto C_CHBUF_LENG_BIT_BOT)
793 
               = CONV_STD_LOGIC_VECTOR(1, C_TLP_FLD_WIDTH_OF_LENG)
794 
               then
795 
               usTlp_Req_Min_Leng  <= '1';
796 
            else
797 
               usTlp_Req_Min_Leng  <= '0';
798 
            end if;
799 
            if usTlp_Qout(C_CHBUF_LENG_BIT_TOP downto C_CHBUF_LENG_BIT_BOT)
800 
               = CONV_STD_LOGIC_VECTOR(2, C_TLP_FLD_WIDTH_OF_LENG)
801 
               then
802 
               usTlp_Req_2DW_Leng  <= '1';
803 
            else
804 
               usTlp_Req_2DW_Leng  <= '0';
805 
            end if;
806 
 
807 
            -- Misc
808 
            DDRAddr_usTlp        <= usTlp_Qout(C_CHBUF_DDA_BIT_TOP downto C_CHBUF_DDA_BIT_BOT);
809 
            mAddr_usTlp          <= usTlp_Qout(C_CHBUF_MA_BIT_TOP downto C_CHBUF_MA_BIT_BOT);  -- !! C_CHBUF_MA_BIT_BOT);
810 
            AInc_usTlp           <= usTlp_Qout(C_CHBUF_AINC_BIT);
811 
            BAR_usTlp            <= usTlp_Qout(C_CHBUF_DMA_BAR_BIT_TOP downto C_CHBUF_DMA_BAR_BIT_BOT);
812 
 
813 
         else
814 
            usTlp_Req_Min_Leng   <= '0';
815 
            usTlp_Req_2DW_Leng   <= '0';
816 
            usTlp_Qout_to_TLP    <= (Others=>'0');
817 
            DDRAddr_usTlp        <= (Others=>'1');
818 
            mAddr_usTlp          <= (Others=>'1');
819 
            AInc_usTlp           <= '1';
820 
            BAR_usTlp            <= (Others=>'1');
821 
         end if;
822 
 
823 
 
824 
         if b1_Tx_Indicator(C_CHAN_INDEX_DMA_DS)='1' then
825 
            dsMRd_Qout_to_TLP  <= (Others=>'0');   -- must be 1st argument
826 
            -- 1st header HI
827 
            dsMRd_Qout_to_TLP(C_TLP_FMT_BIT_TOP  downto C_TLP_FMT_BIT_BOT)   <= dsMRd_Qout(C_CHBUF_FMT_BIT_TOP  downto C_CHBUF_FMT_BIT_BOT);
828 
            dsMRd_Qout_to_TLP(C_TLP_TYPE_BIT_TOP downto C_TLP_TYPE_BIT_BOT)  <= C_ALL_ZEROS(C_TLP_TYPE_BIT_TOP  downto C_TLP_TYPE_BIT_BOT);
829 
            dsMRd_Qout_to_TLP(C_TLP_TC_BIT_TOP   downto C_TLP_TC_BIT_BOT)    <= dsMRd_Qout(C_CHBUF_TC_BIT_TOP   downto C_CHBUF_TC_BIT_BOT);
830 
            dsMRd_Qout_to_TLP(C_TLP_ATTR_BIT_TOP downto C_TLP_ATTR_BIT_BOT)  <= dsMRd_Qout(C_CHBUF_ATTR_BIT_TOP downto C_CHBUF_ATTR_BIT_BOT);
831 
            dsMRd_Qout_to_TLP(C_TLP_LENG_BIT_TOP downto C_TLP_LENG_BIT_BOT)  <= dsMRd_Qout(C_CHBUF_LENG_BIT_TOP downto C_CHBUF_LENG_BIT_BOT);
832 
            -- 1st header LO
833 
            dsMRd_Qout_to_TLP(C_TLP_REQID_BIT_TOP   downto C_TLP_REQID_BIT_BOT)    <= localID;
834 
            dsMRd_Qout_to_TLP(C_TLP_TAG_BIT_TOP     downto C_TLP_TAG_BIT_BOT)      <= dsMRd_Qout(C_CHBUF_TAG_BIT_TOP   downto C_CHBUF_TAG_BIT_BOT);
835 
            dsMRd_Qout_to_TLP(C_TLP_LAST_BE_BIT_TOP downto C_TLP_LAST_BE_BIT_BOT)  <= C_ALL_ONES(C_TLP_LAST_BE_BIT_TOP downto C_TLP_LAST_BE_BIT_BOT);
836 
            dsMRd_Qout_to_TLP(C_TLP_1ST_BE_BIT_TOP  downto C_TLP_1ST_BE_BIT_BOT)   <= C_ALL_ONES(C_TLP_1ST_BE_BIT_TOP  downto C_TLP_1ST_BE_BIT_BOT);
837 
            -- 2nd header (Address)
838 
            dsMRd_Qout_to_TLP(2*C_DBUS_WIDTH-1 downto C_DBUS_WIDTH)    <= dsMRd_Qout(C_CHBUF_HA_BIT_TOP downto C_CHBUF_HA_BIT_BOT);
839 
 
840 
         else
841 
            dsMRd_Qout_to_TLP    <= (Others=>'0');
842 
         end if;
843 
 
844 
      end if;
845 
   end process;
846 
 
847 
 
848 
-- OR-wired channel buffer outputs
849 
   Trn_Qout_wire        <= Irpt_Qout_to_TLP
850 
                        or pioCplD_Qout_to_TLP
851 
                        or dsMRd_Qout_to_TLP
852 
                        or usTlp_Qout_to_TLP
853 
                        ;
854 
 
855 
-- ---------------------------------------------------
856 
-- State Machine: Tx output control
857 
--
858 
   TxFSM_OutputControl:
859 
   process ( trn_clk, trn_tx_Reset_n)
860 
   begin
861 
      if trn_tx_Reset_n = '0' then
862 
         take_an_Arbitration  <= '0';
863 
         RdNumber             <= (Others=>'0');
864 
         RdNumber_eq_One      <= '0';
865 
         RdNumber_eq_Two      <= '0';
866 
         StartAddr            <= (Others=>'0');
867 
         Shift_1st_QWord      <= '0';
868 
--         FixedAddr            <= '0';
869 
         is_CplD              <= '0';
870 
         BAR_value            <= (Others=>'0');
871 
         RdCmd_Req            <= '0';
872 
         mbuf_reset           <= '1';
873 
         mbuf_RE_ok           <= '0';
874 
         trn_tsrc_rdy_n_i     <= '1';
875 
         trn_tsof_n_i         <= '1';
876 
         trn_teof_n_i         <= '1';
877 
         trn_td_i             <= (Others=>'0');
878 
         trn_trem_n_i         <= (Others=>'0');
879 
         TxTrn_State          <= St_TxIdle;
880 
         Trn_Qout_reg         <= (Others=>'0');
881 
 
882 
      elsif trn_clk'event and trn_clk = '1' then
883 
 
884 
         case TxTrn_State is
885 
 
886 
            when St_TxIdle    =>
887 
              trn_tsrc_rdy_n_i     <= '1';
888 
              trn_tsof_n_i         <= '1';
889 
              trn_teof_n_i         <= '1';
890 
              trn_td_i             <= (Others=>'0');
891 
              trn_trem_n_i         <= (Others=>'0');
892 
              mbuf_RE_ok           <= '0';
893 
              take_an_Arbitration  <= '0';
894 
              Trn_Qout_reg         <= Trn_Qout_wire;
895 
              RdNumber             <= Trn_Qout_wire (C_TLP_FLD_WIDTH_OF_LENG-1+32 downto 32);
896 
              RdNumber_eq_One      <= pioCplD_Req_Min_Leng or usTlp_Req_Min_Leng;
897 
              RdNumber_eq_Two      <= pioCplD_Req_2DW_Leng or usTlp_Req_2DW_Leng;
898 
--              FixedAddr            <= not AInc_usTlp;
899 
--              BAR_value            <= BAR_pioCplD and BAR_usTlp;
900 
              RdCmd_Req            <= ChBuf_has_Payload;
901 
              if pioCplD_is_0Leng='1' then
902 
                BAR_value            <=  '0' & CONV_STD_LOGIC_VECTOR(CINT_REGS_SPACE_BAR, C_ENCODE_BAR_NUMBER-1);
903 
                StartAddr            <=  C_ALL_ONES(C_DBUS_WIDTH-1 downto 0) ;
904 
                Shift_1st_QWord      <=  '1';
905 
                is_CplD              <=  '0';
906 
              elsif BAR_pioCplD=CONV_STD_LOGIC_VECTOR(CINT_DDR_SPACE_BAR, C_ENCODE_BAR_NUMBER) then
907 
                BAR_value            <=  '0' & BAR_pioCplD(C_ENCODE_BAR_NUMBER-2 downto 0);
908 
                StartAddr            <=  (C_ALL_ONES(C_DBUS_WIDTH-1 downto C_DDR_IAWIDTH) & DDRAddr_pioCplD);
909 
                Shift_1st_QWord      <=  '1';
910 
                is_CplD              <=  '1';
911 
              elsif BAR_pioCplD=CONV_STD_LOGIC_VECTOR(CINT_FIFO_SPACE_BAR, C_ENCODE_BAR_NUMBER) then
912 
                BAR_value            <=  '0' & BAR_pioCplD(C_ENCODE_BAR_NUMBER-2 downto 0);
913 
                StartAddr            <=  (C_ALL_ONES(C_DBUS_WIDTH-1 downto C_PRAM_AWIDTH+2) & mAddr_pioCplD);
914 
                Shift_1st_QWord      <=  '1';
915 
                is_CplD              <=  '1';
916 
--              elsif BAR_usTlp=CONV_STD_LOGIC_VECTOR(CINT_FIFO_SPACE_BAR, C_ENCODE_BAR_NUMBER) then
917 
--                BAR_value            <=  '0' & BAR_usTlp(C_ENCODE_BAR_NUMBER-2 downto 0);
918 
--                StartAddr            <=  C_ALL_ONES(C_DBUS_WIDTH-1 downto C_PRAM_AWIDTH+4) & mAddr_usTlp & "00";
919 
              elsif BAR_usTlp=CONV_STD_LOGIC_VECTOR(CINT_DDR_SPACE_BAR, C_ENCODE_BAR_NUMBER) then
920 
                BAR_value            <=  '0' & BAR_usTlp(C_ENCODE_BAR_NUMBER-2 downto 0);
921 
                StartAddr            <=  C_ALL_ONES(C_DBUS_WIDTH-1 downto C_DDR_IAWIDTH) & DDRAddr_usTlp;
922 
                Shift_1st_QWord      <=  not usTlp_Qout_to_TLP(C_TLP_FMT_BIT_BOT);
923 
                is_CplD              <=  '0';
924 
              elsif BAR_usTlp=CONV_STD_LOGIC_VECTOR(CINT_FIFO_SPACE_BAR, C_ENCODE_BAR_NUMBER) then
925 
                BAR_value            <=  '0' & BAR_usTlp(C_ENCODE_BAR_NUMBER-2 downto 0);
926 
                StartAddr            <=  C_ALL_ONES(C_DBUS_WIDTH-1 downto C_DDR_IAWIDTH) & DDRAddr_usTlp;
927 
                Shift_1st_QWord      <=  not usTlp_Qout_to_TLP(C_TLP_FMT_BIT_BOT);
928 
                is_CplD              <=  '0';
929 
              else
930 
                BAR_value            <=  '0' & BAR_pioCplD(C_ENCODE_BAR_NUMBER-2 downto 0);
931 
                StartAddr            <=  (C_ALL_ONES(C_DBUS_WIDTH-1 downto C_EP_AWIDTH) & Regs_Addr_pioCplD)
932 
--                                     and (C_ALL_ONES(C_DBUS_WIDTH-1 downto C_PRAM_AWIDTH+2) & mAddr_usTlp)
933 
                                     ;
934 
                Shift_1st_QWord      <=  '1';
935 
                is_CplD              <=  '0';
936 
              end if;
937 
 
938 
              if ChBuf_has_Payload = '1' then
939 
                TxTrn_State          <= St_d_CmdReq;
940 
                mbuf_reset           <= '0';
941 
              elsif ChBuf_No_Payload = '1' then
942 
                TxTrn_State          <= St_nd_Prepare;
943 
                mbuf_reset           <= '0';
944 
              else
945 
                TxTrn_State          <= St_TxIdle;
946 
                mbuf_reset           <= not mbuf_Empty;  -- '1';
947 
              end if;
948 
 
949 
 
950 
            --- --- --- --- --- --- --- --- --- --- --- --- ---
951 
            --- --- --- --- --- --- --- --- --- --- --- --- ---
952 
 
953 
            when St_nd_Prepare    =>
954 
              trn_teof_n_i         <= '1';
955 
              if trn_tdst_rdy_n_i = '0' then
956 
                TxTrn_State          <= St_nd_Header2;  -- St_nd_Header1
957 
                trn_tsrc_rdy_n_i     <= '0';
958 
                trn_tsof_n_i         <= '0';
959 
                trn_td_i             <= Trn_Qout_reg (C_DBUS_WIDTH-1 downto 0);
960 
              else
961 
                TxTrn_State          <= St_nd_Prepare;
962 
                trn_tsrc_rdy_n_i     <= '1';
963 
                trn_tsof_n_i         <= '1';
964 
                trn_td_i             <= (Others=>'0');
965 
              end if;
966 
 
967 
 
968 
            when St_nd_Header2    =>
969 
              trn_tsrc_rdy_n_i     <= '0';
970 
              if trn_tdst_rdy_n_i = '1' then
971 
                TxTrn_State          <= St_nd_Header2;
972 
                take_an_Arbitration  <= '0';
973 
                trn_tsof_n_i         <= trn_tsof_n_i;
974 
                trn_teof_n_i         <= '1';
975 
                trn_td_i             <= trn_td_i; -- Trn_Qout_reg (C_DBUS_WIDTH-1 downto 0);
976 
              else                                                    -- 3DW header
977 
                TxTrn_State          <= St_nd_HeaderLast;
978 
                take_an_Arbitration  <= '1';
979 
                trn_tsof_n_i         <= '1';
980 
                trn_teof_n_i         <= '0';
981 
                if Trn_Qout_reg (C_TLP_FMT_BIT_BOT) = '1' then       -- 4DW header
982 
                  trn_trem_n_i         <= X"00";
983 
                  trn_td_i             <= Trn_Qout_reg (C_DBUS_WIDTH*2-1 downto C_DBUS_WIDTH);
984 
                else
985 
                  trn_trem_n_i         <= X"0F";
986 
                  trn_td_i             <= Trn_Qout_reg (C_DBUS_WIDTH-1+32 downto C_DBUS_WIDTH) & X"00000000";
987 
                end if;
988 
              end if;
989 
 
990 
 
991 
            when St_nd_HeaderLast    =>
992 
              trn_tsof_n_i         <= '1';
993 
              take_an_Arbitration  <= '0';
994 
              if trn_tdst_rdy_n_i = '1' then
995 
                TxTrn_State          <= St_nd_HeaderLast;
996 
                trn_tsrc_rdy_n_i     <= '0';
997 
                trn_teof_n_i         <= '0';
998 
                trn_td_i             <= trn_td_i;
999 
                trn_trem_n_i         <= trn_trem_n_i;
1000 
              else
1001 
                TxTrn_State          <= St_nd_Arbitration;  -- St_TxIdle;
1002 
                trn_tsrc_rdy_n_i     <= '1';
1003 
                trn_teof_n_i         <= '1';
1004 
                trn_td_i             <= trn_td_i;
1005 
                trn_trem_n_i         <= trn_trem_n_i;
1006 
              end if;
1007 
 
1008 
            when St_nd_Arbitration    =>
1009 
              trn_tsof_n_i         <= '1';
1010 
              TxTrn_State          <= St_TxIdle;
1011 
              trn_tsrc_rdy_n_i     <= '1';
1012 
              trn_teof_n_i         <= '1';
1013 
              trn_td_i             <= trn_td_i;
1014 
              trn_trem_n_i         <= (OTHERS=>'0');
1015 
 
1016 
 
1017 
            --- --- --- --- --- --- --- --- --- --- --- --- ---
1018 
            --- --- --- --- --- --- --- --- --- --- --- --- ---
1019 
 
1020 
            when St_d_CmdReq    =>
1021 
              if RdCmd_Ack = '1' then
1022 
                RdCmd_Req            <= '0';
1023 
                TxTrn_State          <= St_d_CmdAck;
1024 
              else
1025 
                RdCmd_Req            <= '1';
1026 
                TxTrn_State          <= St_d_CmdReq;
1027 
              end if;
1028 
 
1029 
 
1030 
            when St_d_CmdAck    =>
1031 
              trn_teof_n_i         <= '1';
1032 
              if mbuf_Empty = '0' and trn_tdst_rdy_n_i = '0' then
1033 
                trn_tsrc_rdy_n_i     <= '1';
1034 
                trn_tsof_n_i         <= '1';
1035 
                trn_td_i             <= (Others=>'0');
1036 
                mbuf_RE_ok           <= '1';
1037 
                TxTrn_State          <= St_d_Header0;  -- St_d_Header1
1038 
              else
1039 
                trn_tsrc_rdy_n_i     <= '1';
1040 
                trn_tsof_n_i         <= '1';
1041 
                trn_td_i             <= (Others=>'0');
1042 
                mbuf_RE_ok           <= '0';
1043 
                TxTrn_State          <= St_d_CmdAck;
1044 
              end if;
1045 
 
1046 
 
1047 
            when St_d_Header0    =>
1048 
              if trn_tdst_rdy_n_i = '0' then
1049 
                take_an_Arbitration  <= '1';
1050 
                trn_tsrc_rdy_n_i     <= '0';
1051 
                trn_tsof_n_i         <= '0';
1052 
                trn_teof_n_i         <= '1';
1053 
                trn_td_i             <= Trn_Qout_reg (C_DBUS_WIDTH-1 downto 0);
1054 
                mbuf_RE_ok           <= not Trn_Qout_reg (C_TLP_FMT_BIT_BOT);      -- '1'; -- 4DW
1055 
                TxTrn_State          <= St_d_Header2;
1056 
              else
1057 
                take_an_Arbitration  <= '0';
1058 
                trn_tsrc_rdy_n_i     <= '1';
1059 
                trn_tsof_n_i         <= '1';
1060 
                trn_teof_n_i         <= '1';
1061 
                trn_td_i             <= trn_td_i;
1062 
                mbuf_RE_ok           <= '0';
1063 
                TxTrn_State          <= St_d_Header0;
1064 
              end if;
1065 
 
1066 
 
1067 
            when St_d_Header2    =>
1068 
              trn_tsrc_rdy_n_i     <= '0';
1069 
              trn_trem_n_i         <= (OTHERS=>'0');
1070 
              take_an_Arbitration  <= '0';
1071 
              if trn_tdst_rdy_n_i = '1' then
1072 
                TxTrn_State          <= St_d_Header2;
1073 
--                trn_td_i             <= Trn_Qout_reg (C_DBUS_WIDTH-1+32 downto 32);
1074 
                trn_td_i             <= Trn_Qout_reg (C_DBUS_WIDTH-1 downto 0);
1075 
                trn_tsof_n_i         <= '0';
1076 
                trn_teof_n_i         <= '1';
1077 
                mbuf_RE_ok           <= not Trn_Qout_reg (C_TLP_FMT_BIT_BOT);
1078 
              elsif Trn_Qout_reg (C_TLP_FMT_BIT_BOT) = '1' then   -- 4DW header
1079 
                TxTrn_State          <= St_d_1st_Data;  -- St_d_HeaderPlus;
1080 
--                trn_td_i             <= Trn_Qout_reg (C_DBUS_WIDTH-1+96 downto 96);
1081 
                trn_td_i             <= Trn_Qout_reg (C_DBUS_WIDTH*2-1 downto C_DBUS_WIDTH);
1082 
                trn_tsof_n_i         <= '1';
1083 
                trn_teof_n_i         <= '1';
1084 
                mbuf_RE_ok           <= '1';
1085 
              else                                                -- 3DW header
1086 
--                trn_td_i             <= Trn_Qout_reg (C_DBUS_WIDTH-1+64 downto 64);
1087 
                trn_td_i             <= Trn_Qout_reg (C_DBUS_WIDTH*2-1 downto C_DBUS_WIDTH+32)
1088 
                                      & mbuf_Qout(C_DBUS_WIDTH-1-32 downto 0);
1089 
                trn_tsof_n_i         <= '1';
1090 
                trn_teof_n_i         <= mbuf_Qout(C_DBUS_WIDTH);
1091 
                mbuf_RE_ok           <= not trn_tsrc_rdy_n_i and mbuf_Qout(C_DBUS_WIDTH);
1092 
                if mbuf_Qout(C_DBUS_WIDTH) = '0' then
1093 
                  TxTrn_State          <= St_d_Tail_chk;
1094 
                else
1095 
                  TxTrn_State          <= St_d_1st_Data;
1096 
                end if;
1097 
              end if;
1098 
 
1099 
 
1100 
 
1101 
            when St_d_1st_Data    =>
1102 
              mbuf_RE_ok           <= not trn_tsrc_rdy_n_i and mbuf_Qout(C_DBUS_WIDTH);
1103 
--              trn_tsof_n_i         <= '1';
1104 
              take_an_Arbitration  <= '0';
1105 
              if trn_tdst_rdy_n_i = '1' then
1106 
                TxTrn_State          <= St_d_1st_Data;
1107 
                trn_teof_n_i         <= '1';
1108 
                trn_td_i             <= trn_td_i;
1109 
                trn_tsrc_rdy_n_i     <= '0';
1110 
              elsif mbuf_Qout(C_DBUS_WIDTH) = '0' then
1111 
                TxTrn_State          <= St_d_Tail_chk;
1112 
                trn_teof_n_i         <= '0';
1113 
                trn_trem_n_i         <= X"0" & mbuf_Qout(70) & mbuf_Qout(70)
1114 
                                             & mbuf_Qout(70) & mbuf_Qout(70);
1115 
                trn_td_i             <= mbuf_Qout(C_DBUS_WIDTH-1 downto 0);
1116 
                trn_tsrc_rdy_n_i     <= not mbuf_Qvalid; -- '0';
1117 
              elsif mbuf_Qvalid = '0' then
1118 
                TxTrn_State          <= St_d_Payload_used;
1119 
                trn_teof_n_i         <= '1';
1120 
                trn_td_i             <= mbuf_Qout(C_DBUS_WIDTH-1 downto 0);
1121 
                trn_tsrc_rdy_n_i     <= '1';
1122 
              else
1123 
                TxTrn_State          <= St_d_Payload;
1124 
                trn_teof_n_i         <= '1';
1125 
                trn_td_i             <= mbuf_Qout(C_DBUS_WIDTH-1 downto 0);
1126 
                trn_tsrc_rdy_n_i     <= '0';
1127 
              end if;
1128 
 
1129 
 
1130 
            when St_d_Payload    =>
1131 
              mbuf_RE_ok           <= '1';
1132 
--              trn_tsof_n_i         <= '1';
1133 
              take_an_Arbitration  <= '0';
1134 
              if trn_tdst_rdy_n_i='1' then
1135 
                trn_td_i             <= trn_td_i;
1136 
                trn_teof_n_i         <= trn_teof_n_i;
1137 
                trn_trem_n_i         <= trn_trem_n_i;
1138 
                trn_tsrc_rdy_n_i     <= '0';
1139 
                if mbuf_Qout(C_DBUS_WIDTH) = '0' then
1140 
                  TxTrn_State          <= St_d_Tail;
1141 
                elsif mbuf_Qvalid='1' then
1142 
                  TxTrn_State          <= St_d_Payload;
1143 
                else
1144 
                  TxTrn_State          <= St_d_Payload_used;
1145 
                end if;
1146 
              else
1147 
                trn_td_i             <= mbuf_Qout(C_DBUS_WIDTH-1 downto 0);
1148 
                trn_teof_n_i         <= mbuf_Qout(C_DBUS_WIDTH);
1149 
                trn_tsrc_rdy_n_i     <= mbuf_Qout(C_DBUS_WIDTH) and not mbuf_Qvalid;
1150 
                if mbuf_Qout(C_DBUS_WIDTH) = '0' then
1151 
                  TxTrn_State          <= St_d_Tail_chk;
1152 
                  trn_trem_n_i         <= X"0" & mbuf_Qout(70) & mbuf_Qout(70)
1153 
                                               & mbuf_Qout(70) & mbuf_Qout(70);
1154 
                elsif mbuf_Qvalid='1' then
1155 
                  trn_trem_n_i         <= (OTHERS=>'0');
1156 
                  TxTrn_State          <= St_d_Payload;
1157 
                else
1158 
                  trn_trem_n_i         <= (OTHERS=>'0');
1159 
                  TxTrn_State          <= St_d_Payload_used;
1160 
                end if;
1161 
              end if;
1162 
 
1163 
 
1164 
            when St_d_Payload_used    =>
1165 
              mbuf_RE_ok           <= '1';
1166 
              take_an_Arbitration  <= '0';
1167 
--              trn_tsof_n_i         <= '1';
1168 
              if trn_tsrc_rdy_n_i='0' then
1169 
                trn_td_i             <= mbuf_Qout(C_DBUS_WIDTH-1 downto 0);
1170 
                trn_tsrc_rdy_n_i     <= not mbuf_Qvalid and not trn_tdst_rdy_n_i;
1171 
                if mbuf_Qout(C_DBUS_WIDTH) = '0' then
1172 
                  trn_teof_n_i         <= '0';
1173 
                  trn_trem_n_i         <= X"0" & mbuf_Qout(70) & mbuf_Qout(70)
1174 
                                               & mbuf_Qout(70) & mbuf_Qout(70);
1175 
                else
1176 
                  trn_teof_n_i         <= '1';
1177 
                  trn_trem_n_i         <= (OTHERS=>'0');
1178 
                end if;
1179 
                if mbuf_Qvalid='1' then
1180 
                  TxTrn_State          <= St_d_Payload;
1181 
                else
1182 
                  TxTrn_State          <= St_d_Payload_used;
1183 
                end if;
1184 
              elsif mbuf_Qvalid='1' then
1185 
                  trn_td_i             <= mbuf_Qout(C_DBUS_WIDTH-1 downto 0);
1186 
                  trn_tsrc_rdy_n_i     <= '0';
1187 
                  if mbuf_Qout(C_DBUS_WIDTH) = '0' then
1188 
                    trn_teof_n_i         <= '0';
1189 
                    trn_trem_n_i         <= X"0" & mbuf_Qout(70) & mbuf_Qout(70)
1190 
                                                 & mbuf_Qout(70) & mbuf_Qout(70);
1191 
                  else
1192 
                    trn_teof_n_i         <= '1';
1193 
                    trn_trem_n_i         <= (OTHERS=>'0');
1194 
                  end if;
1195 
                  if mbuf_Qout(C_DBUS_WIDTH) = '0' then
1196 
                    TxTrn_State          <= St_d_Tail_chk;
1197 
                  else
1198 
                    TxTrn_State          <= St_d_Payload;
1199 
                  end if;
1200 
              else
1201 
                  TxTrn_State          <= St_d_Payload_used;
1202 
                  trn_td_i             <= trn_td_i;
1203 
                  trn_teof_n_i         <= trn_teof_n_i;
1204 
                  trn_trem_n_i         <= trn_trem_n_i;
1205 
                  trn_tsrc_rdy_n_i     <= '1';
1206 
              end if;
1207 
 
1208 
 
1209 
            when St_d_Tail    =>
1210 
              take_an_Arbitration  <= '0';
1211 
              mbuf_RE_ok           <= '0';
1212 
--              trn_tsof_n_i         <= '1';
1213 
              trn_tsrc_rdy_n_i     <= '0';
1214 
              if trn_tdst_rdy_n_i = '1' then
1215 
                TxTrn_State          <= St_d_Tail;
1216 
                trn_teof_n_i         <= trn_teof_n_i;
1217 
                trn_trem_n_i         <= trn_trem_n_i;
1218 
                trn_td_i             <= trn_td_i;
1219 
              else
1220 
                TxTrn_State          <= St_d_Tail_chk;
1221 
                trn_teof_n_i         <= '0';
1222 
                trn_trem_n_i         <= X"0" & mbuf_Qout(70) & mbuf_Qout(70)
1223 
                                             & mbuf_Qout(70) & mbuf_Qout(70);
1224 
                trn_td_i             <= mbuf_Qout(C_DBUS_WIDTH-1 downto 0);
1225 
              end if;
1226 
 
1227 
 
1228 
            when St_d_Tail_chk    =>
1229 
              take_an_Arbitration  <= '0';
1230 
              mbuf_RE_ok           <= '0';
1231 
--              trn_tsof_n_i         <= '1';
1232 
              if trn_tdst_rdy_n_i = '1' then
1233 
                trn_tsrc_rdy_n_i     <= '0';
1234 
                trn_teof_n_i         <= '0';
1235 
                trn_trem_n_i         <= trn_trem_n_i;
1236 
                trn_td_i             <= trn_td_i;
1237 
                TxTrn_State          <= St_d_Tail_chk;
1238 
              else
1239 
                trn_tsrc_rdy_n_i     <= '1';
1240 
                trn_teof_n_i         <= '1';
1241 
                trn_td_i             <= (Others=>'0');
1242 
                trn_trem_n_i         <= (Others=>'0');
1243 
                TxTrn_State          <= St_TxIdle;
1244 
              end if;
1245 
 
1246 
 
1247 
            when Others    =>
1248 
               take_an_Arbitration  <= '0';
1249 
               RdNumber             <= (Others=>'0');
1250 
               RdNumber_eq_One      <= '0';
1251 
               RdNumber_eq_Two      <= '0';
1252 
               StartAddr            <= (Others=>'0');
1253 
--               FixedAddr            <= '0';
1254 
               BAR_value            <= (Others=>'0');
1255 
               RdCmd_Req            <= '0';
1256 
               mbuf_reset           <= '0';
1257 
               mbuf_RE_ok           <= '0';
1258 
               trn_tsrc_rdy_n_i     <= '1';
1259 
               trn_tsof_n_i         <= '1';
1260 
               trn_teof_n_i         <= '1';
1261 
               trn_td_i             <= (Others=>'0');
1262 
               trn_trem_n_i         <= (Others=>'0');
1263 
               TxTrn_State          <= St_TxIdle;
1264 
 
1265 
         end case;
1266 
 
1267 
      end if;
1268 
   end process;
1269 
 
1270 
 
1271 
---------------------------------------------------------------------------------
1272 
-- Synchronous Accumulation: us_DMA_Bytes
1273 
--
1274 
   Synch_Acc_us_DMA_Bytes:
1275 
   process ( trn_clk )
1276 
   begin
1277 
      if trn_clk'event and trn_clk = '1' then
1278 
        us_DMA_Bytes_i   <= '0' & trn_td_i(32+C_TLP_FLD_WIDTH_OF_LENG-1 downto 32) & "00";
1279 
        if trn_td_i(C_TLP_FMT_BIT_TOP) = '1'
1280 
           and trn_td_i(C_TLP_TYPE_BIT_TOP downto C_TLP_TYPE_BIT_BOT)
1281 
               = C_ALL_ZEROS(C_TLP_TYPE_BIT_TOP downto C_TLP_TYPE_BIT_BOT) then
1282 
           us_DMA_Bytes_Add_i  <=  not trn_tsof_n_i
1283 
                               and not trn_tsrc_rdy_n_i
1284 
                               and not trn_tdst_rdy_n_i
1285 
                               ;
1286 
        else
1287 
           us_DMA_Bytes_Add_i  <= '0';
1288 
        end if;
1289 
      end if;
1290 
   end process;
1291 
 
1292 
end architecture Behavioral;

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