1 |
11 |
barabba |
//-----------------------------------------------------------------------------
|
2 |
|
|
//
|
3 |
|
|
// (c) Copyright 2009 Xilinx, Inc. All rights reserved.
|
4 |
|
|
//
|
5 |
|
|
// This file contains confidential and proprietary information of Xilinx, Inc.
|
6 |
|
|
// and is protected under U.S. and international copyright and other
|
7 |
|
|
// intellectual property laws.
|
8 |
|
|
//
|
9 |
|
|
// DISCLAIMER
|
10 |
|
|
//
|
11 |
|
|
// This disclaimer is not a license and does not grant any rights to the
|
12 |
|
|
// materials distributed herewith. Except as otherwise provided in a valid
|
13 |
|
|
// license issued to you by Xilinx, and to the maximum extent permitted by
|
14 |
|
|
// applicable law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND WITH ALL
|
15 |
|
|
// FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES AND CONDITIONS, EXPRESS,
|
16 |
|
|
// IMPLIED, OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF
|
17 |
|
|
// MERCHANTABILITY, NON-INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE;
|
18 |
|
|
// and (2) Xilinx shall not be liable (whether in contract or tort, including
|
19 |
|
|
// negligence, or under any other theory of liability) for any loss or damage
|
20 |
|
|
// of any kind or nature related to, arising under or in connection with these
|
21 |
|
|
// materials, including for any direct, or any indirect, special, incidental,
|
22 |
|
|
// or consequential loss or damage (including loss of data, profits, goodwill,
|
23 |
|
|
// or any type of loss or damage suffered as a result of any action brought by
|
24 |
|
|
// a third party) even if such damage or loss was reasonably foreseeable or
|
25 |
|
|
// Xilinx had been advised of the possibility of the same.
|
26 |
|
|
//
|
27 |
|
|
// CRITICAL APPLICATIONS
|
28 |
|
|
//
|
29 |
|
|
// Xilinx products are not designed or intended to be fail-safe, or for use in
|
30 |
|
|
// any application requiring fail-safe performance, such as life-support or
|
31 |
|
|
// safety devices or systems, Class III medical devices, nuclear facilities,
|
32 |
|
|
// applications related to the deployment of airbags, or any other
|
33 |
|
|
// applications that could lead to death, personal injury, or severe property
|
34 |
|
|
// or environmental damage (individually and collectively, "Critical
|
35 |
|
|
// Applications"). Customer assumes the sole risk and liability of any use of
|
36 |
|
|
// Xilinx products in Critical Applications, subject only to applicable laws
|
37 |
|
|
// and regulations governing limitations on product liability.
|
38 |
|
|
//
|
39 |
|
|
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART OF THIS FILE
|
40 |
|
|
// AT ALL TIMES.
|
41 |
|
|
//
|
42 |
|
|
//-----------------------------------------------------------------------------
|
43 |
|
|
// Project : Virtex-6 Integrated Block for PCI Express
|
44 |
|
|
// File : gtx_wrapper_v6.v
|
45 |
|
|
//-- Description: GTX module for Virtex6 PCIe Block
|
46 |
|
|
//--
|
47 |
|
|
//--
|
48 |
|
|
//--
|
49 |
|
|
//--------------------------------------------------------------------------------
|
50 |
|
|
|
51 |
|
|
`timescale 1ns/1ns
|
52 |
|
|
|
53 |
|
|
module gtx_wrapper_v6 (
|
54 |
|
|
|
55 |
|
|
// TX
|
56 |
|
|
TX,
|
57 |
|
|
TX_,
|
58 |
|
|
TxData,
|
59 |
|
|
TxDataK,
|
60 |
|
|
TxElecIdle,
|
61 |
|
|
TxCompliance,
|
62 |
|
|
|
63 |
|
|
// RX
|
64 |
|
|
RX,
|
65 |
|
|
RX_,
|
66 |
|
|
RxData,
|
67 |
|
|
RxDataK,
|
68 |
|
|
RxPolarity,
|
69 |
|
|
RxValid,
|
70 |
|
|
RxElecIdle,
|
71 |
|
|
RxStatus,
|
72 |
|
|
|
73 |
|
|
// other
|
74 |
|
|
GTRefClkout,
|
75 |
|
|
RxPLLLkDet,
|
76 |
|
|
TxDetectRx,
|
77 |
|
|
PhyStatus,
|
78 |
|
|
TXPdownAsynch,
|
79 |
|
|
PowerDown,
|
80 |
|
|
Rate,
|
81 |
|
|
Reset_n,
|
82 |
|
|
GTReset_n,
|
83 |
|
|
PCLK,
|
84 |
|
|
REFCLK,
|
85 |
|
|
TxDeemph,
|
86 |
|
|
TxMargin,
|
87 |
|
|
TxSwing,
|
88 |
|
|
ChanIsAligned,
|
89 |
|
|
local_pcs_reset,
|
90 |
|
|
RxResetDone,
|
91 |
|
|
SyncDone
|
92 |
|
|
|
93 |
|
|
);
|
94 |
|
|
|
95 |
|
|
parameter NO_OF_LANES = 1;
|
96 |
|
|
parameter REF_CLK_FREQ = 0;
|
97 |
|
|
parameter PL_FAST_TRAIN = "FALSE";
|
98 |
|
|
|
99 |
|
|
localparam GTX_PLL_DIVSEL_FB = (REF_CLK_FREQ == 0) ? 5 :
|
100 |
|
|
(REF_CLK_FREQ == 1) ? 4 :
|
101 |
|
|
(REF_CLK_FREQ == 2) ? 2 : 0;
|
102 |
|
|
localparam SIMULATION = (PL_FAST_TRAIN == "TRUE") ? 1 : 0;
|
103 |
|
|
|
104 |
|
|
localparam RXPLL_CP_CFG = (REF_CLK_FREQ == 0) ? 8'h09 :
|
105 |
|
|
(REF_CLK_FREQ == 1) ? 8'h09 :
|
106 |
|
|
(REF_CLK_FREQ == 2) ? 8'h0D : 8'h09;
|
107 |
|
|
|
108 |
|
|
localparam TXPLL_CP_CFG = (REF_CLK_FREQ == 0) ? 8'h09 :
|
109 |
|
|
(REF_CLK_FREQ == 1) ? 8'h09 :
|
110 |
|
|
(REF_CLK_FREQ == 2) ? 8'h0D : 8'h09;
|
111 |
|
|
|
112 |
|
|
localparam RX_CLK25_DIVIDER = (REF_CLK_FREQ == 0) ? 4 :
|
113 |
|
|
(REF_CLK_FREQ == 1) ? 5 :
|
114 |
|
|
(REF_CLK_FREQ == 2) ? 10 : 10 ;
|
115 |
|
|
|
116 |
|
|
localparam TX_CLK25_DIVIDER = (REF_CLK_FREQ == 0) ? 4 :
|
117 |
|
|
(REF_CLK_FREQ == 1) ? 5 :
|
118 |
|
|
(REF_CLK_FREQ == 2) ? 10 : 10 ;
|
119 |
|
|
|
120 |
|
|
// TX
|
121 |
|
|
output [NO_OF_LANES-1:0] TX;
|
122 |
|
|
output [NO_OF_LANES-1:0] TX_;
|
123 |
|
|
input [(NO_OF_LANES*16)-1:0] TxData;
|
124 |
|
|
input [(NO_OF_LANES*2)-1:0] TxDataK;
|
125 |
|
|
input [NO_OF_LANES-1:0] TxElecIdle;
|
126 |
|
|
input [NO_OF_LANES-1:0] TxCompliance;
|
127 |
|
|
|
128 |
|
|
// RX
|
129 |
|
|
input [NO_OF_LANES-1:0] RX;
|
130 |
|
|
input [NO_OF_LANES-1:0] RX_;
|
131 |
|
|
output [(NO_OF_LANES*16)-1:0] RxData;
|
132 |
|
|
output [(NO_OF_LANES*2)-1:0] RxDataK;
|
133 |
|
|
input [NO_OF_LANES-1:0] RxPolarity;
|
134 |
|
|
output [NO_OF_LANES-1:0] RxValid;
|
135 |
|
|
output [NO_OF_LANES-1:0] RxElecIdle;
|
136 |
|
|
output [(NO_OF_LANES*3)-1:0] RxStatus;
|
137 |
|
|
|
138 |
|
|
// other
|
139 |
|
|
output [NO_OF_LANES-1:0] GTRefClkout;
|
140 |
|
|
output [NO_OF_LANES-1:0] RxPLLLkDet;
|
141 |
|
|
input TxDetectRx;
|
142 |
|
|
output [NO_OF_LANES-1:0] PhyStatus;
|
143 |
|
|
input PCLK;
|
144 |
|
|
output [NO_OF_LANES-1:0] ChanIsAligned;
|
145 |
|
|
input TXPdownAsynch;
|
146 |
|
|
|
147 |
|
|
input [(NO_OF_LANES*2)-1:0] PowerDown;
|
148 |
|
|
input Rate;
|
149 |
|
|
input Reset_n;
|
150 |
|
|
input GTReset_n;
|
151 |
|
|
input REFCLK;
|
152 |
|
|
input TxDeemph;
|
153 |
|
|
input TxMargin;
|
154 |
|
|
input TxSwing;
|
155 |
|
|
input local_pcs_reset;
|
156 |
|
|
output RxResetDone;
|
157 |
|
|
output SyncDone;
|
158 |
|
|
|
159 |
|
|
genvar i;
|
160 |
|
|
|
161 |
|
|
// dummy signals to avoid port mismatch with DUAL_GTX
|
162 |
|
|
wire [15:0] RxData_dummy;
|
163 |
|
|
wire [1:0] RxDataK_dummy;
|
164 |
|
|
wire [15:0] TxData_dummy;
|
165 |
|
|
wire [1:0] TxDataK_dummy;
|
166 |
|
|
|
167 |
|
|
// inputs
|
168 |
|
|
wire [(NO_OF_LANES*16)-1:0] GTX_TxData = TxData;
|
169 |
|
|
wire [(NO_OF_LANES*2)-1:0] GTX_TxDataK = TxDataK;
|
170 |
|
|
wire [(NO_OF_LANES)-1:0] GTX_TxElecIdle = TxElecIdle;
|
171 |
|
|
wire [(NO_OF_LANES-1):0] GTX_TxCompliance = TxCompliance;
|
172 |
|
|
wire [(NO_OF_LANES)-1:0] GTX_RXP = RX[(NO_OF_LANES)-1:0];
|
173 |
|
|
wire [(NO_OF_LANES)-1:0] GTX_RXN = RX_[(NO_OF_LANES)-1:0];
|
174 |
|
|
|
175 |
|
|
// outputs
|
176 |
|
|
wire [(NO_OF_LANES)-1:0] GTX_TXP;
|
177 |
|
|
wire [(NO_OF_LANES)-1:0] GTX_TXN;
|
178 |
|
|
wire [(NO_OF_LANES*16)-1:0] GTX_RxData;
|
179 |
|
|
wire [(NO_OF_LANES*2)-1:0] GTX_RxDataK;
|
180 |
|
|
wire [(NO_OF_LANES)-1:0] GTX_RxPolarity = RxPolarity ;
|
181 |
|
|
wire [(NO_OF_LANES)-1:0] GTX_RxValid;
|
182 |
|
|
wire [(NO_OF_LANES)-1:0] GTX_RxElecIdle;
|
183 |
|
|
wire [(NO_OF_LANES-1):0] GTX_RxResetDone;
|
184 |
|
|
wire [(NO_OF_LANES*3)-1:0] GTX_RxChbondLevel;
|
185 |
|
|
wire [(NO_OF_LANES*3)-1:0] GTX_RxStatus;
|
186 |
|
|
|
187 |
|
|
|
188 |
|
|
wire [3:0] RXCHBOND [NO_OF_LANES+1:0];
|
189 |
|
|
wire [3:0] TXBYPASS8B10B = 4'b0000;
|
190 |
|
|
wire RXDEC8B10BUSE = 1'b1;
|
191 |
|
|
wire [NO_OF_LANES-1:0] GTX_PhyStatus;
|
192 |
|
|
wire RESETDONE [NO_OF_LANES-1:0];
|
193 |
|
|
wire REFCLK;
|
194 |
|
|
wire GTXRESET = 1'b0;
|
195 |
|
|
|
196 |
|
|
wire [NO_OF_LANES-1:0] SYNC_DONE;
|
197 |
|
|
wire [NO_OF_LANES-1:0] OUT_DIV_RESET;
|
198 |
|
|
wire [NO_OF_LANES-1:0] PCS_RESET;
|
199 |
|
|
wire [NO_OF_LANES-1:0] TXENPMAPHASEALIGN;
|
200 |
|
|
wire [NO_OF_LANES-1:0] TXPMASETPHASE;
|
201 |
|
|
wire [NO_OF_LANES-1:0] TXRESETDONE;
|
202 |
|
|
wire [NO_OF_LANES-1:0] TXRATEDONE;
|
203 |
|
|
wire [NO_OF_LANES-1:0] PHYSTATUS;
|
204 |
|
|
wire [NO_OF_LANES-1:0] RXVALID;
|
205 |
|
|
wire [NO_OF_LANES-1:0] RATE_CLK_SEL;
|
206 |
|
|
|
207 |
|
|
|
208 |
|
|
reg [(NO_OF_LANES-1):0] GTX_RxResetDone_q;
|
209 |
|
|
reg [(NO_OF_LANES-1):0] TXRESETDONE_q;
|
210 |
|
|
|
211 |
|
|
wire [NO_OF_LANES-1:0] RxValid;
|
212 |
|
|
|
213 |
|
|
assign RxResetDone = &(GTX_RxResetDone_q[(NO_OF_LANES)-1:0]);
|
214 |
|
|
assign TX[(NO_OF_LANES)-1:0] = GTX_TXP[(NO_OF_LANES)-1:0];
|
215 |
|
|
assign TX_[(NO_OF_LANES)-1:0] = GTX_TXN[(NO_OF_LANES)-1:0];
|
216 |
|
|
assign RXCHBOND[0] = 4'b0000;
|
217 |
|
|
assign TxData_dummy = 16'b0;
|
218 |
|
|
assign TxDataK_dummy = 2'b0;
|
219 |
|
|
assign SyncDone = &(SYNC_DONE[(NO_OF_LANES)-1:0]);
|
220 |
|
|
|
221 |
|
|
// pipeline to improve timing
|
222 |
|
|
always @ (posedge PCLK) begin
|
223 |
|
|
|
224 |
|
|
GTX_RxResetDone_q[(NO_OF_LANES)-1:0] <= GTX_RxResetDone[(NO_OF_LANES)-1:0];
|
225 |
|
|
TXRESETDONE_q[(NO_OF_LANES)-1:0] <= TXRESETDONE[(NO_OF_LANES)-1:0];
|
226 |
|
|
|
227 |
|
|
end
|
228 |
|
|
|
229 |
|
|
generate
|
230 |
|
|
|
231 |
|
|
for (i=0; i < NO_OF_LANES; i=i+1) begin: GTXD
|
232 |
|
|
|
233 |
|
|
assign GTX_RxChbondLevel[(3*i)+2:(3*i)] = (NO_OF_LANES-(i+1));
|
234 |
|
|
|
235 |
|
|
|
236 |
|
|
GTX_RX_VALID_FILTER_V6 # (
|
237 |
|
|
.CLK_COR_MIN_LAT(28)
|
238 |
|
|
)
|
239 |
|
|
GTX_RX_VALID_FILTER (
|
240 |
|
|
|
241 |
|
|
.USER_RXCHARISK ( RxDataK[(2*i)+1:2*i] ), //O
|
242 |
|
|
.USER_RXDATA ( RxData[(16*i)+15:(16*i)+0] ), //O
|
243 |
|
|
.USER_RXVALID ( RxValid[i] ), //O
|
244 |
|
|
.USER_RXELECIDLE ( RxElecIdle[i] ), //O
|
245 |
|
|
.USER_RX_STATUS ( RxStatus[(3*i)+2:(3*i)] ), //O
|
246 |
|
|
.USER_RX_PHY_STATUS ( PhyStatus[i] ), //O
|
247 |
|
|
|
248 |
|
|
|
249 |
|
|
.GT_RXCHARISK ( GTX_RxDataK[(2*i)+1:2*i] ), //I
|
250 |
|
|
.GT_RXDATA ( GTX_RxData[(16*i)+15:(16*i)+0] ), //I
|
251 |
|
|
.GT_RXVALID ( GTX_RxValid[i] ), //I
|
252 |
|
|
.GT_RXELECIDLE ( GTX_RxElecIdle[i] ), //I
|
253 |
|
|
.GT_RX_STATUS ( GTX_RxStatus[(3*i)+2:(3*i)] ), //I
|
254 |
|
|
.GT_RX_PHY_STATUS ( PHYSTATUS[i] ),
|
255 |
|
|
|
256 |
|
|
.USER_CLK ( PCLK ), //I
|
257 |
|
|
.RESET ( !Reset_n ) //I
|
258 |
|
|
|
259 |
|
|
);
|
260 |
|
|
|
261 |
|
|
GTX_TX_SYNC_RATE_V6 # (
|
262 |
|
|
.C_SIMULATION(SIMULATION)
|
263 |
|
|
)
|
264 |
|
|
GTX_TX_SYNC (
|
265 |
|
|
|
266 |
|
|
.ENPMAPHASEALIGN ( TXENPMAPHASEALIGN[i] ), //O
|
267 |
|
|
.PMASETPHASE ( TXPMASETPHASE[i] ), //O
|
268 |
|
|
.SYNC_DONE ( SYNC_DONE[i] ), //O
|
269 |
|
|
.OUT_DIV_RESET ( OUT_DIV_RESET[i] ), //O
|
270 |
|
|
.PCS_RESET ( PCS_RESET[i] ), //O
|
271 |
|
|
.USER_PHYSTATUS ( PHYSTATUS[i] ), //O
|
272 |
|
|
.RATE_CLK_SEL ( RATE_CLK_SEL[i] ), //0
|
273 |
|
|
|
274 |
|
|
.USER_CLK ( PCLK ), //I
|
275 |
|
|
.RESET ( !Reset_n ), //I
|
276 |
|
|
.RATE ( Rate ), //I
|
277 |
|
|
.RATEDONE ( TXRATEDONE[i] ), //I
|
278 |
|
|
.GT_PHYSTATUS ( GTX_PhyStatus[i] ), //I
|
279 |
|
|
.RESETDONE ( TXRESETDONE_q[i] & GTX_RxResetDone_q[i] ), //I
|
280 |
|
|
|
281 |
|
|
.DEBUG_STATUS ( ), // O
|
282 |
|
|
.ENPMA_STATE_MASK ( 3'b000 ), // I
|
283 |
|
|
.OUTDIV_STATE_MASK( 3'b010 ) // I
|
284 |
|
|
|
285 |
|
|
);
|
286 |
|
|
|
287 |
|
|
GTXE1 # (
|
288 |
|
|
|
289 |
|
|
.TX_DRIVE_MODE("PIPE"),
|
290 |
|
|
.TX_CLK_SOURCE("RXPLL"),
|
291 |
|
|
.POWER_SAVE(10'b0000000100),
|
292 |
|
|
.CM_TRIM ( 2'b01 ),
|
293 |
|
|
.PMA_CDR_SCAN ( 27'h640404C ),
|
294 |
|
|
.PMA_CFG( 76'h0040000040000000003 ),
|
295 |
|
|
.RCV_TERM_GND ("TRUE"),
|
296 |
|
|
.RCV_TERM_VTTRX ("FALSE"),
|
297 |
|
|
.RX_DLYALIGN_EDGESET(5'b00010),
|
298 |
|
|
.RX_DLYALIGN_LPFINC(4'b0110),
|
299 |
|
|
.RX_DLYALIGN_OVRDSETTING(8'b10000000),
|
300 |
|
|
.TERMINATION_CTRL(5'b10101),
|
301 |
|
|
.TERMINATION_OVRD("TRUE"),
|
302 |
|
|
.TX_DLYALIGN_LPFINC(4'b0110),
|
303 |
|
|
.TX_DLYALIGN_OVRDSETTING(8'b10000000),
|
304 |
|
|
.TXPLL_CP_CFG( TXPLL_CP_CFG ),
|
305 |
|
|
.OOBDETECT_THRESHOLD( 3'b011 ),
|
306 |
|
|
.RXPLL_CP_CFG ( RXPLL_CP_CFG ),
|
307 |
|
|
//.TX_DETECT_RX_CFG( 14'h1832 ),
|
308 |
|
|
.TX_TDCC_CFG ( 2'b11 ),
|
309 |
|
|
.BIAS_CFG ( 17'h00014 ),
|
310 |
|
|
.AC_CAP_DIS ( "FALSE" ),
|
311 |
|
|
.DFE_CFG ( 8'b00011011 ),
|
312 |
|
|
.SIM_TX_ELEC_IDLE_LEVEL("1"),
|
313 |
|
|
.SIM_RECEIVER_DETECT_PASS("TRUE"),
|
314 |
|
|
.RX_EN_REALIGN_RESET_BUF("TRUE"),
|
315 |
|
|
.TX_IDLE_ASSERT_DELAY(3'b100), // TX-idle-set-to-idle (13 UI)
|
316 |
|
|
.TX_IDLE_DEASSERT_DELAY(3'b010), // TX-idle-to-diff (7 UI)
|
317 |
|
|
.CHAN_BOND_SEQ_2_CFG(5'b11111), // 5'b11111 for PCIE mode, 5'b00000 for other modes
|
318 |
|
|
.CHAN_BOND_KEEP_ALIGN("TRUE"),
|
319 |
|
|
.RX_IDLE_HI_CNT(4'b1000),
|
320 |
|
|
.RX_IDLE_LO_CNT(4'b0000),
|
321 |
|
|
.RX_EN_IDLE_RESET_BUF("TRUE"),
|
322 |
|
|
.TX_DATA_WIDTH(20),
|
323 |
|
|
.RX_DATA_WIDTH(20),
|
324 |
|
|
.ALIGN_COMMA_WORD(1),
|
325 |
|
|
.CHAN_BOND_1_MAX_SKEW(7),
|
326 |
|
|
.CHAN_BOND_2_MAX_SKEW(1),
|
327 |
|
|
.CHAN_BOND_SEQ_1_1(10'b0001000101), // D5.2 (end TS2)
|
328 |
|
|
.CHAN_BOND_SEQ_1_2(10'b0001000101), // D5.2 (end TS2)
|
329 |
|
|
.CHAN_BOND_SEQ_1_3(10'b0001000101), // D5.2 (end TS2)
|
330 |
|
|
.CHAN_BOND_SEQ_1_4(10'b0110111100), // K28.5 (COM)
|
331 |
|
|
.CHAN_BOND_SEQ_1_ENABLE(4'b1111), // order is 4321
|
332 |
|
|
.CHAN_BOND_SEQ_2_1(10'b0100111100), // K28.1 (FTS)
|
333 |
|
|
.CHAN_BOND_SEQ_2_2(10'b0100111100), // K28.1 (FTS)
|
334 |
|
|
.CHAN_BOND_SEQ_2_3(10'b0110111100), // K28.5 (COM)
|
335 |
|
|
.CHAN_BOND_SEQ_2_4(10'b0100111100), // K28.1 (FTS)
|
336 |
|
|
.CHAN_BOND_SEQ_2_ENABLE(4'b1111), // order is 4321
|
337 |
|
|
.CHAN_BOND_SEQ_2_USE("TRUE"),
|
338 |
|
|
.CHAN_BOND_SEQ_LEN(4), // 1..4
|
339 |
|
|
.RX_CLK25_DIVIDER(RX_CLK25_DIVIDER),
|
340 |
|
|
.TX_CLK25_DIVIDER(TX_CLK25_DIVIDER),
|
341 |
|
|
.CLK_COR_ADJ_LEN(1), // 1..4
|
342 |
|
|
.CLK_COR_DET_LEN(1), // 1..4
|
343 |
|
|
.CLK_COR_INSERT_IDLE_FLAG("FALSE"),
|
344 |
|
|
.CLK_COR_KEEP_IDLE("FALSE"),
|
345 |
|
|
.CLK_COR_MAX_LAT(30),
|
346 |
|
|
.CLK_COR_MIN_LAT(28),
|
347 |
|
|
.CLK_COR_PRECEDENCE("TRUE"),
|
348 |
|
|
.CLK_CORRECT_USE("TRUE"),
|
349 |
|
|
.CLK_COR_REPEAT_WAIT(0),
|
350 |
|
|
.CLK_COR_SEQ_1_1(10'b0100011100), // K28.0 (SKP)
|
351 |
|
|
.CLK_COR_SEQ_1_2(10'b0000000000),
|
352 |
|
|
.CLK_COR_SEQ_1_3(10'b0000000000),
|
353 |
|
|
.CLK_COR_SEQ_1_4(10'b0000000000),
|
354 |
|
|
.CLK_COR_SEQ_1_ENABLE(4'b1111),
|
355 |
|
|
.CLK_COR_SEQ_2_1(10'b0000000000),
|
356 |
|
|
.CLK_COR_SEQ_2_2(10'b0000000000),
|
357 |
|
|
.CLK_COR_SEQ_2_3(10'b0000000000),
|
358 |
|
|
.CLK_COR_SEQ_2_4(10'b0000000000),
|
359 |
|
|
.CLK_COR_SEQ_2_ENABLE(4'b1111),
|
360 |
|
|
.CLK_COR_SEQ_2_USE("FALSE"),
|
361 |
|
|
.COMMA_10B_ENABLE(10'b1111111111),
|
362 |
|
|
.COMMA_DOUBLE("FALSE"),
|
363 |
|
|
.DEC_MCOMMA_DETECT("TRUE"),
|
364 |
|
|
.DEC_PCOMMA_DETECT("TRUE"),
|
365 |
|
|
.DEC_VALID_COMMA_ONLY("TRUE"),
|
366 |
|
|
.MCOMMA_10B_VALUE(10'b1010000011),
|
367 |
|
|
.MCOMMA_DETECT("TRUE"),
|
368 |
|
|
.PCI_EXPRESS_MODE("TRUE"),
|
369 |
|
|
.PCOMMA_10B_VALUE(10'b0101111100),
|
370 |
|
|
.PCOMMA_DETECT("TRUE"),
|
371 |
|
|
.RXPLL_DIVSEL_FB(GTX_PLL_DIVSEL_FB), // 1..5, 8, 10
|
372 |
|
|
.TXPLL_DIVSEL_FB(GTX_PLL_DIVSEL_FB), // 1..5, 8, 10
|
373 |
|
|
.RXPLL_DIVSEL_REF(1), // 1..6, 8, 10, 12, 16, 20
|
374 |
|
|
.TXPLL_DIVSEL_REF(1), // 1..6, 8, 10, 12, 16, 20
|
375 |
|
|
.RXPLL_DIVSEL_OUT(2), // 1, 2, 4
|
376 |
|
|
.TXPLL_DIVSEL_OUT(2), // 1, 2, 4
|
377 |
|
|
.RXPLL_DIVSEL45_FB(5),
|
378 |
|
|
.TXPLL_DIVSEL45_FB(5),
|
379 |
|
|
.RX_BUFFER_USE("TRUE"),
|
380 |
|
|
.RX_DECODE_SEQ_MATCH("TRUE"),
|
381 |
|
|
.RX_LOS_INVALID_INCR(8), // power of 2: 1..128
|
382 |
|
|
.RX_LOSS_OF_SYNC_FSM("FALSE"),
|
383 |
|
|
.RX_LOS_THRESHOLD(128), // power of 2: 4..512
|
384 |
|
|
.RX_SLIDE_MODE("AUTO"), // 00=OFF 01=AUTO 10=PCS 11=PMA
|
385 |
|
|
.RX_XCLK_SEL ("RXREC"),
|
386 |
|
|
.TX_BUFFER_USE("FALSE"), // Must be set to FALSE for use by PCIE
|
387 |
|
|
.TX_XCLK_SEL ("TXUSR"), // Must be set to TXUSR for use by PCIE
|
388 |
|
|
.TXPLL_LKDET_CFG (3'b101),
|
389 |
|
|
.RX_EYE_SCANMODE (2'b00),
|
390 |
|
|
.RX_EYE_OFFSET (8'h4C),
|
391 |
|
|
.PMA_RX_CFG ( 25'h05ce048 ),
|
392 |
|
|
.TRANS_TIME_NON_P2(8'h19), // Reduced simulation time
|
393 |
|
|
.TRANS_TIME_FROM_P2(12'h03c), // Reduced simulation time
|
394 |
|
|
.TRANS_TIME_TO_P2(10'h064), // Reduced simulation time
|
395 |
|
|
.TRANS_TIME_RATE(8'hD7), // Reduced simulation time
|
396 |
|
|
.SHOW_REALIGN_COMMA("FALSE"),
|
397 |
|
|
.TX_PMADATA_OPT(1'b0), // Lockup latch between PCS and PMA
|
398 |
|
|
.PMA_TX_CFG( 20'h00082 ) // Aligns posedge of USRCLK
|
399 |
|
|
|
400 |
|
|
)
|
401 |
|
|
GTX (
|
402 |
|
|
|
403 |
|
|
.COMFINISH (),
|
404 |
|
|
.COMINITDET (),
|
405 |
|
|
.COMSASDET (),
|
406 |
|
|
.COMWAKEDET (),
|
407 |
|
|
.DADDR (),
|
408 |
|
|
.DCLK (),
|
409 |
|
|
.DEN (),
|
410 |
|
|
.DFECLKDLYADJ (),
|
411 |
|
|
.DFECLKDLYADJMON (),
|
412 |
|
|
.DFEDLYOVRD ( 1'b1 ),
|
413 |
|
|
.DFEEYEDACMON (),
|
414 |
|
|
.DFESENSCAL (),
|
415 |
|
|
.DFETAP1 (),
|
416 |
|
|
.DFETAP1MONITOR (),
|
417 |
|
|
.DFETAP2 (),
|
418 |
|
|
.DFETAP2MONITOR (),
|
419 |
|
|
.DFETAP3 (),
|
420 |
|
|
.DFETAP3MONITOR (),
|
421 |
|
|
.DFETAP4 (),
|
422 |
|
|
.DFETAP4MONITOR (),
|
423 |
|
|
.DFETAPOVRD ( 1'b1 ),
|
424 |
|
|
.DI (),
|
425 |
|
|
.DRDY (),
|
426 |
|
|
.DRPDO (),
|
427 |
|
|
.DWE (),
|
428 |
|
|
.GATERXELECIDLE ( 1'b0 ),
|
429 |
|
|
.GREFCLKRX (),
|
430 |
|
|
.GREFCLKTX (),
|
431 |
|
|
.GTXRXRESET ( ~GTReset_n ),
|
432 |
|
|
.GTXTEST ( {11'b10000000000,OUT_DIV_RESET[i],1'b0} ),
|
433 |
|
|
.GTXTXRESET ( ~GTReset_n ),
|
434 |
|
|
.LOOPBACK ( 3'b000 ),
|
435 |
|
|
.MGTREFCLKFAB (),
|
436 |
|
|
.MGTREFCLKRX ( {1'b0,REFCLK} ),
|
437 |
|
|
.MGTREFCLKTX ( {1'b0,REFCLK} ),
|
438 |
|
|
.NORTHREFCLKRX (),
|
439 |
|
|
.NORTHREFCLKTX (),
|
440 |
|
|
.PHYSTATUS ( GTX_PhyStatus[i] ),
|
441 |
|
|
.PLLRXRESET ( 1'b0 ),
|
442 |
|
|
.PLLTXRESET ( 1'b0 ),
|
443 |
|
|
.PRBSCNTRESET ( 1'b0 ),
|
444 |
|
|
.RXBUFRESET ( 1'b0 ),
|
445 |
|
|
.RXBUFSTATUS (),
|
446 |
|
|
.RXBYTEISALIGNED (),
|
447 |
|
|
.RXBYTEREALIGN (),
|
448 |
|
|
.RXCDRRESET ( 1'b0 ),
|
449 |
|
|
.RXCHANBONDSEQ (),
|
450 |
|
|
.RXCHANISALIGNED ( ChanIsAligned[i] ),
|
451 |
|
|
.RXCHANREALIGN (),
|
452 |
|
|
.RXCHARISCOMMA (),
|
453 |
|
|
.RXCHARISK ( {RxDataK_dummy[1:0], GTX_RxDataK[(2*i)+1:2*i]} ),
|
454 |
|
|
.RXCHBONDI ( RXCHBOND[i] ),
|
455 |
|
|
.RXCHBONDLEVEL ( GTX_RxChbondLevel[(3*i)+2:(3*i)] ),
|
456 |
|
|
.RXCHBONDMASTER ( (i == 0) ),
|
457 |
|
|
.RXCHBONDO ( RXCHBOND[i+1] ),
|
458 |
|
|
.RXCHBONDSLAVE ( (i > 0) ),
|
459 |
|
|
.RXCLKCORCNT (),
|
460 |
|
|
.RXCOMMADET (),
|
461 |
|
|
.RXCOMMADETUSE ( 1'b1 ),
|
462 |
|
|
.RXDATA ( {RxData_dummy[15:0],GTX_RxData[(16*i)+15:(16*i)+0]} ),
|
463 |
|
|
.RXDATAVALID (),
|
464 |
|
|
.RXDEC8B10BUSE ( RXDEC8B10BUSE ),
|
465 |
|
|
.RXDISPERR (),
|
466 |
|
|
.RXDLYALIGNDISABLE ( 1'b1),
|
467 |
|
|
.RXELECIDLE ( GTX_RxElecIdle[i] ),
|
468 |
|
|
.RXENCHANSYNC ( 1'b1 ),
|
469 |
|
|
.RXENMCOMMAALIGN ( 1'b1 ),
|
470 |
|
|
.RXENPCOMMAALIGN ( 1'b1 ),
|
471 |
|
|
.RXENPMAPHASEALIGN ( 1'b0 ),
|
472 |
|
|
.RXENPRBSTST ( 3'b0 ),
|
473 |
|
|
.RXENSAMPLEALIGN ( 1'b0 ),
|
474 |
|
|
.RXEQMIX ( 10'b0110000110 ),
|
475 |
|
|
.RXGEARBOXSLIP ( 1'b0 ),
|
476 |
|
|
.RXHEADER (),
|
477 |
|
|
.RXHEADERVALID (),
|
478 |
|
|
.RXLOSSOFSYNC (),
|
479 |
|
|
.RXN ( GTX_RXN[i] ),
|
480 |
|
|
.RXNOTINTABLE (),
|
481 |
|
|
.RXOVERSAMPLEERR (),
|
482 |
|
|
.RXP ( GTX_RXP[i] ),
|
483 |
|
|
.RXPLLLKDET ( RxPLLLkDet[i] ),
|
484 |
|
|
.RXPLLLKDETEN ( 1'b1 ),
|
485 |
|
|
.RXPLLPOWERDOWN ( 1'b0 ),
|
486 |
|
|
.RXPLLREFSELDY ( 3'b000 ),
|
487 |
|
|
.RXPMASETPHASE ( 1'b0 ),
|
488 |
|
|
.RXPOLARITY ( GTX_RxPolarity[i] ),
|
489 |
|
|
.RXPOWERDOWN ( PowerDown[(2*i)+1:(2*i)] ),
|
490 |
|
|
.RXPRBSERR (),
|
491 |
|
|
.RXRATE ( {1'b1, Rate} ),
|
492 |
|
|
.RXRATEDONE ( ),
|
493 |
|
|
.RXRECCLK ( RXRECCLK ),
|
494 |
|
|
.RXRECCLKPCS ( ),
|
495 |
|
|
.RXRESET ( ~GTReset_n | local_pcs_reset | PCS_RESET[i] ),
|
496 |
|
|
.RXRESETDONE ( GTX_RxResetDone[i] ),
|
497 |
|
|
.RXRUNDISP (),
|
498 |
|
|
.RXSLIDE ( 1'b0 ),
|
499 |
|
|
.RXSTARTOFSEQ (),
|
500 |
|
|
.RXSTATUS ( GTX_RxStatus[(3*i)+2:(3*i)] ),
|
501 |
|
|
.RXUSRCLK ( PCLK ),
|
502 |
|
|
.RXUSRCLK2 ( PCLK ),
|
503 |
|
|
.RXVALID (GTX_RxValid[i]),
|
504 |
|
|
.SOUTHREFCLKRX (),
|
505 |
|
|
.SOUTHREFCLKTX (),
|
506 |
|
|
.TSTCLK0 ( 1'b0 ),
|
507 |
|
|
.TSTCLK1 ( 1'b0 ),
|
508 |
|
|
.TSTIN ( {20{1'b1}} ),
|
509 |
|
|
.TSTOUT (),
|
510 |
|
|
.TXBUFDIFFCTRL ( 3'b111 ),
|
511 |
|
|
.TXBUFSTATUS (),
|
512 |
|
|
.TXBYPASS8B10B ( TXBYPASS8B10B[3:0] ),
|
513 |
|
|
.TXCHARDISPMODE ( {3'b000, GTX_TxCompliance[i]} ),
|
514 |
|
|
.TXCHARDISPVAL ( 4'b0000 ),
|
515 |
|
|
.TXCHARISK ( {TxDataK_dummy[1:0], GTX_TxDataK[(2*i)+1:2*i]} ),
|
516 |
|
|
.TXCOMINIT ( 1'b0 ),
|
517 |
|
|
.TXCOMSAS ( 1'b0 ),
|
518 |
|
|
.TXCOMWAKE ( 1'b0 ),
|
519 |
|
|
.TXDATA ( {TxData_dummy[15:0], GTX_TxData[(16*i)+15:(16*i)+0]} ),
|
520 |
|
|
.TXDEEMPH ( TxDeemph ),
|
521 |
|
|
.TXDETECTRX ( TxDetectRx ),
|
522 |
|
|
.TXDIFFCTRL ( 4'b1111 ),
|
523 |
|
|
.TXDLYALIGNDISABLE ( 1'b1 ),
|
524 |
|
|
.TXELECIDLE ( GTX_TxElecIdle[i] ),
|
525 |
|
|
.TXENC8B10BUSE ( 1'b1 ),
|
526 |
|
|
.TXENPMAPHASEALIGN ( TXENPMAPHASEALIGN[i] ),
|
527 |
|
|
.TXENPRBSTST (),
|
528 |
|
|
.TXGEARBOXREADY (),
|
529 |
|
|
.TXHEADER (),
|
530 |
|
|
.TXINHIBIT ( 1'b0 ),
|
531 |
|
|
.TXKERR (),
|
532 |
|
|
.TXMARGIN ( {TxMargin, 2'b00} ),
|
533 |
|
|
.TXN ( GTX_TXN[i] ),
|
534 |
|
|
.TXOUTCLK (),
|
535 |
|
|
.TXOUTCLKPCS (),
|
536 |
|
|
.TXP ( GTX_TXP[i] ),
|
537 |
|
|
.TXPDOWNASYNCH ( TXPdownAsynch ),
|
538 |
|
|
.TXPLLLKDET ( ),
|
539 |
|
|
.TXPLLLKDETEN ( 1'b0 ),
|
540 |
|
|
.TXPLLPOWERDOWN ( 1'b0 ),
|
541 |
|
|
.TXPLLREFSELDY ( 3'b000 ),
|
542 |
|
|
.TXPMASETPHASE ( TXPMASETPHASE[i] ),
|
543 |
|
|
.TXPOLARITY ( 1'b0 ),
|
544 |
|
|
.TXPOSTEMPHASIS (),
|
545 |
|
|
.TXPOWERDOWN ( PowerDown[(2*i)+1:(2*i)] ),
|
546 |
|
|
.TXPRBSFORCEERR (),
|
547 |
|
|
.TXPREEMPHASIS (),
|
548 |
|
|
.TXRATE ( {1'b1, Rate} ),
|
549 |
|
|
.TXRESET ( ~GTReset_n | local_pcs_reset | PCS_RESET[i] ),
|
550 |
|
|
.TXRESETDONE ( TXRESETDONE[i] ),
|
551 |
|
|
.TXRUNDISP (),
|
552 |
|
|
.TXSEQUENCE (),
|
553 |
|
|
.TXSTARTSEQ (),
|
554 |
|
|
.TXSWING ( TxSwing ),
|
555 |
|
|
.TXUSRCLK ( PCLK ),
|
556 |
|
|
.TXUSRCLK2 ( PCLK ),
|
557 |
|
|
.USRCODEERR (),
|
558 |
|
|
.IGNORESIGDET (),
|
559 |
|
|
.PERFCLKRX (),
|
560 |
|
|
.PERFCLKTX (),
|
561 |
|
|
.RXDLYALIGNMONITOR (),
|
562 |
|
|
.RXDLYALIGNOVERRIDE ( 1'b0 ),
|
563 |
|
|
.RXDLYALIGNRESET (),
|
564 |
|
|
.RXDLYALIGNSWPPRECURB ( 1'b1 ),
|
565 |
|
|
.RXDLYALIGNUPDSW ( 1'b0 ),
|
566 |
|
|
.TXDLYALIGNMONITOR (),
|
567 |
|
|
.TXDLYALIGNOVERRIDE ( 1'b0 ),
|
568 |
|
|
.TXDLYALIGNRESET (),
|
569 |
|
|
.TXDLYALIGNUPDSW ( 1'b1 ),
|
570 |
|
|
.TXRATEDONE ( TXRATEDONE[i] )
|
571 |
|
|
|
572 |
|
|
|
573 |
|
|
);
|
574 |
|
|
end
|
575 |
|
|
|
576 |
|
|
endgenerate
|
577 |
|
|
|
578 |
|
|
|
579 |
|
|
endmodule
|