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//-----------------------------------------------------------------------------
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//
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// (c) Copyright 2009 Xilinx, Inc. All rights reserved.
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//
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// This file contains confidential and proprietary information of Xilinx, Inc.
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// and is protected under U.S. and international copyright and other
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// intellectual property laws.
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//
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// DISCLAIMER
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//
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// This disclaimer is not a license and does not grant any rights to the
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// materials distributed herewith. Except as otherwise provided in a valid
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// license issued to you by Xilinx, and to the maximum extent permitted by
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// applicable law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND WITH ALL
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// FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES AND CONDITIONS, EXPRESS,
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// IMPLIED, OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF
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// MERCHANTABILITY, NON-INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE;
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// and (2) Xilinx shall not be liable (whether in contract or tort, including
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// negligence, or under any other theory of liability) for any loss or damage
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// of any kind or nature related to, arising under or in connection with these
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// materials, including for any direct, or any indirect, special, incidental,
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// or consequential loss or damage (including loss of data, profits, goodwill,
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// or any type of loss or damage suffered as a result of any action brought by
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// a third party) even if such damage or loss was reasonably foreseeable or
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// Xilinx had been advised of the possibility of the same.
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//
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// CRITICAL APPLICATIONS
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//
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// Xilinx products are not designed or intended to be fail-safe, or for use in
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// any application requiring fail-safe performance, such as life-support or
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// safety devices or systems, Class III medical devices, nuclear facilities,
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// applications related to the deployment of airbags, or any other
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// applications that could lead to death, personal injury, or severe property
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// or environmental damage (individually and collectively, "Critical
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// Applications"). Customer assumes the sole risk and liability of any use of
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// Xilinx products in Critical Applications, subject only to applicable laws
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// and regulations governing limitations on product liability.
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//
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// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART OF THIS FILE
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// AT ALL TIMES.
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//
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//-----------------------------------------------------------------------------
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// Project : Virtex-6 Integrated Block for PCI Express
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// File : pcie_pipe_v6.v
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//-- Description: PIPE module for Virtex6 PCIe Block
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//--
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//--
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//--
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//--------------------------------------------------------------------------------
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`timescale 1ns/1ns
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module pcie_pipe_v6 #
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(
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parameter NO_OF_LANES = 8,
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parameter LINK_CAP_MAX_LINK_SPEED = 4'h1,
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parameter PIPE_PIPELINE_STAGES = 0 // 0 - 0 stages, 1 - 1 stage, 2 - 2 stages
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)
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(
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// Pipe Per-Link Signals
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input wire pipe_tx_rcvr_det_i ,
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input wire pipe_tx_reset_i ,
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input wire pipe_tx_rate_i ,
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input wire pipe_tx_deemph_i ,
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input wire [2:0] pipe_tx_margin_i ,
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input wire pipe_tx_swing_i ,
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output wire pipe_tx_rcvr_det_o ,
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output wire pipe_tx_reset_o ,
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output wire pipe_tx_rate_o ,
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output wire pipe_tx_deemph_o ,
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output wire [2:0] pipe_tx_margin_o ,
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output wire pipe_tx_swing_o ,
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// Pipe Per-Lane Signals - Lane 0
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output wire [ 1:0] pipe_rx0_char_is_k_o ,
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output wire [15:0] pipe_rx0_data_o ,
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output wire pipe_rx0_valid_o ,
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output wire pipe_rx0_chanisaligned_o ,
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output wire [ 2:0] pipe_rx0_status_o ,
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output wire pipe_rx0_phy_status_o ,
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output wire pipe_rx0_elec_idle_o ,
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input wire pipe_rx0_polarity_i ,
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input wire pipe_tx0_compliance_i ,
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input wire [ 1:0] pipe_tx0_char_is_k_i ,
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input wire [15:0] pipe_tx0_data_i ,
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input wire pipe_tx0_elec_idle_i ,
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input wire [ 1:0] pipe_tx0_powerdown_i ,
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input wire [ 1:0] pipe_rx0_char_is_k_i ,
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input wire [15:0] pipe_rx0_data_i ,
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input wire pipe_rx0_valid_i ,
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input wire pipe_rx0_chanisaligned_i ,
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input wire [ 2:0] pipe_rx0_status_i ,
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input wire pipe_rx0_phy_status_i ,
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input wire pipe_rx0_elec_idle_i ,
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output wire pipe_rx0_polarity_o ,
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output wire pipe_tx0_compliance_o ,
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output wire [ 1:0] pipe_tx0_char_is_k_o ,
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output wire [15:0] pipe_tx0_data_o ,
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output wire pipe_tx0_elec_idle_o ,
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output wire [ 1:0] pipe_tx0_powerdown_o ,
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// Pipe Per-Lane Signals - Lane 1
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output wire [ 1:0] pipe_rx1_char_is_k_o ,
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output wire [15:0] pipe_rx1_data_o ,
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output wire pipe_rx1_valid_o ,
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output wire pipe_rx1_chanisaligned_o ,
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output wire [ 2:0] pipe_rx1_status_o ,
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output wire pipe_rx1_phy_status_o ,
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output wire pipe_rx1_elec_idle_o ,
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input wire pipe_rx1_polarity_i ,
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input wire pipe_tx1_compliance_i ,
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input wire [ 1:0] pipe_tx1_char_is_k_i ,
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input wire [15:0] pipe_tx1_data_i ,
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input wire pipe_tx1_elec_idle_i ,
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input wire [ 1:0] pipe_tx1_powerdown_i ,
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input wire [ 1:0] pipe_rx1_char_is_k_i ,
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input wire [15:0] pipe_rx1_data_i ,
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input wire pipe_rx1_valid_i ,
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input wire pipe_rx1_chanisaligned_i ,
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input wire [ 2:0] pipe_rx1_status_i ,
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input wire pipe_rx1_phy_status_i ,
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input wire pipe_rx1_elec_idle_i ,
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output wire pipe_rx1_polarity_o ,
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output wire pipe_tx1_compliance_o ,
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output wire [ 1:0] pipe_tx1_char_is_k_o ,
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output wire [15:0] pipe_tx1_data_o ,
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output wire pipe_tx1_elec_idle_o ,
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output wire [ 1:0] pipe_tx1_powerdown_o ,
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// Pipe Per-Lane Signals - Lane 2
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output wire [ 1:0] pipe_rx2_char_is_k_o ,
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output wire [15:0] pipe_rx2_data_o ,
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output wire pipe_rx2_valid_o ,
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output wire pipe_rx2_chanisaligned_o ,
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output wire [ 2:0] pipe_rx2_status_o ,
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output wire pipe_rx2_phy_status_o ,
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output wire pipe_rx2_elec_idle_o ,
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input wire pipe_rx2_polarity_i ,
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input wire pipe_tx2_compliance_i ,
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input wire [ 1:0] pipe_tx2_char_is_k_i ,
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input wire [15:0] pipe_tx2_data_i ,
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input wire pipe_tx2_elec_idle_i ,
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input wire [ 1:0] pipe_tx2_powerdown_i ,
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input wire [ 1:0] pipe_rx2_char_is_k_i ,
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input wire [15:0] pipe_rx2_data_i ,
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input wire pipe_rx2_valid_i ,
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input wire pipe_rx2_chanisaligned_i ,
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input wire [ 2:0] pipe_rx2_status_i ,
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input wire pipe_rx2_phy_status_i ,
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input wire pipe_rx2_elec_idle_i ,
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output wire pipe_rx2_polarity_o ,
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output wire pipe_tx2_compliance_o ,
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output wire [ 1:0] pipe_tx2_char_is_k_o ,
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output wire [15:0] pipe_tx2_data_o ,
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output wire pipe_tx2_elec_idle_o ,
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output wire [ 1:0] pipe_tx2_powerdown_o ,
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// Pipe Per-Lane Signals - Lane 3
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output wire [ 1:0] pipe_rx3_char_is_k_o ,
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output wire [15:0] pipe_rx3_data_o ,
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output wire pipe_rx3_valid_o ,
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output wire pipe_rx3_chanisaligned_o ,
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output wire [ 2:0] pipe_rx3_status_o ,
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output wire pipe_rx3_phy_status_o ,
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output wire pipe_rx3_elec_idle_o ,
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input wire pipe_rx3_polarity_i ,
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input wire pipe_tx3_compliance_i ,
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input wire [ 1:0] pipe_tx3_char_is_k_i ,
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input wire [15:0] pipe_tx3_data_i ,
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input wire pipe_tx3_elec_idle_i ,
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input wire [ 1:0] pipe_tx3_powerdown_i ,
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input wire [ 1:0] pipe_rx3_char_is_k_i ,
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input wire [15:0] pipe_rx3_data_i ,
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input wire pipe_rx3_valid_i ,
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input wire pipe_rx3_chanisaligned_i ,
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input wire [ 2:0] pipe_rx3_status_i ,
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input wire pipe_rx3_phy_status_i ,
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input wire pipe_rx3_elec_idle_i ,
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output wire pipe_rx3_polarity_o ,
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output wire pipe_tx3_compliance_o ,
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output wire [ 1:0] pipe_tx3_char_is_k_o ,
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output wire [15:0] pipe_tx3_data_o ,
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output wire pipe_tx3_elec_idle_o ,
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output wire [ 1:0] pipe_tx3_powerdown_o ,
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// Pipe Per-Lane Signals - Lane 4
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output wire [ 1:0] pipe_rx4_char_is_k_o ,
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output wire [15:0] pipe_rx4_data_o ,
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output wire pipe_rx4_valid_o ,
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output wire pipe_rx4_chanisaligned_o ,
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output wire [ 2:0] pipe_rx4_status_o ,
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output wire pipe_rx4_phy_status_o ,
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output wire pipe_rx4_elec_idle_o ,
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input wire pipe_rx4_polarity_i ,
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input wire pipe_tx4_compliance_i ,
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input wire [ 1:0] pipe_tx4_char_is_k_i ,
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input wire [15:0] pipe_tx4_data_i ,
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input wire pipe_tx4_elec_idle_i ,
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input wire [ 1:0] pipe_tx4_powerdown_i ,
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input wire [ 1:0] pipe_rx4_char_is_k_i ,
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input wire [15:0] pipe_rx4_data_i ,
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input wire pipe_rx4_valid_i ,
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input wire pipe_rx4_chanisaligned_i ,
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input wire [ 2:0] pipe_rx4_status_i ,
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input wire pipe_rx4_phy_status_i ,
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input wire pipe_rx4_elec_idle_i ,
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output wire pipe_rx4_polarity_o ,
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output wire pipe_tx4_compliance_o ,
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output wire [ 1:0] pipe_tx4_char_is_k_o ,
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output wire [15:0] pipe_tx4_data_o ,
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output wire pipe_tx4_elec_idle_o ,
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output wire [ 1:0] pipe_tx4_powerdown_o ,
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// Pipe Per-Lane Signals - Lane 5
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output wire [ 1:0] pipe_rx5_char_is_k_o ,
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output wire [15:0] pipe_rx5_data_o ,
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223 |
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output wire pipe_rx5_valid_o ,
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224 |
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output wire pipe_rx5_chanisaligned_o ,
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225 |
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output wire [ 2:0] pipe_rx5_status_o ,
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226 |
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output wire pipe_rx5_phy_status_o ,
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227 |
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output wire pipe_rx5_elec_idle_o ,
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228 |
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input wire pipe_rx5_polarity_i ,
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229 |
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input wire pipe_tx5_compliance_i ,
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230 |
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input wire [ 1:0] pipe_tx5_char_is_k_i ,
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231 |
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input wire [15:0] pipe_tx5_data_i ,
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232 |
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input wire pipe_tx5_elec_idle_i ,
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233 |
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input wire [ 1:0] pipe_tx5_powerdown_i ,
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234 |
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235 |
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input wire [ 1:0] pipe_rx5_char_is_k_i ,
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236 |
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input wire [15:0] pipe_rx5_data_i ,
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237 |
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input wire pipe_rx5_valid_i ,
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238 |
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input wire pipe_rx5_chanisaligned_i ,
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239 |
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input wire [ 2:0] pipe_rx5_status_i ,
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240 |
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input wire pipe_rx5_phy_status_i ,
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241 |
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input wire pipe_rx5_elec_idle_i ,
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242 |
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output wire pipe_rx5_polarity_o ,
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243 |
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output wire pipe_tx5_compliance_o ,
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output wire [ 1:0] pipe_tx5_char_is_k_o ,
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output wire [15:0] pipe_tx5_data_o ,
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246 |
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output wire pipe_tx5_elec_idle_o ,
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247 |
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output wire [ 1:0] pipe_tx5_powerdown_o ,
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248 |
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249 |
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// Pipe Per-Lane Signals - Lane 6
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output wire [ 1:0] pipe_rx6_char_is_k_o ,
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251 |
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output wire [15:0] pipe_rx6_data_o ,
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252 |
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output wire pipe_rx6_valid_o ,
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253 |
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output wire pipe_rx6_chanisaligned_o ,
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254 |
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output wire [ 2:0] pipe_rx6_status_o ,
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255 |
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output wire pipe_rx6_phy_status_o ,
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256 |
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output wire pipe_rx6_elec_idle_o ,
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257 |
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input wire pipe_rx6_polarity_i ,
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258 |
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input wire pipe_tx6_compliance_i ,
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259 |
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input wire [ 1:0] pipe_tx6_char_is_k_i ,
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260 |
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input wire [15:0] pipe_tx6_data_i ,
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261 |
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input wire pipe_tx6_elec_idle_i ,
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262 |
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input wire [ 1:0] pipe_tx6_powerdown_i ,
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263 |
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264 |
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input wire [ 1:0] pipe_rx6_char_is_k_i ,
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265 |
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input wire [15:0] pipe_rx6_data_i ,
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266 |
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input wire pipe_rx6_valid_i ,
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267 |
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input wire pipe_rx6_chanisaligned_i ,
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268 |
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input wire [ 2:0] pipe_rx6_status_i ,
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269 |
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input wire pipe_rx6_phy_status_i ,
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270 |
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input wire pipe_rx6_elec_idle_i ,
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271 |
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output wire pipe_rx6_polarity_o ,
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272 |
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output wire pipe_tx6_compliance_o ,
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273 |
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output wire [ 1:0] pipe_tx6_char_is_k_o ,
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274 |
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output wire [15:0] pipe_tx6_data_o ,
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275 |
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output wire pipe_tx6_elec_idle_o ,
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276 |
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output wire [ 1:0] pipe_tx6_powerdown_o ,
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277 |
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278 |
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// Pipe Per-Lane Signals - Lane 7
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279 |
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output wire [ 1:0] pipe_rx7_char_is_k_o ,
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280 |
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output wire [15:0] pipe_rx7_data_o ,
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281 |
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output wire pipe_rx7_valid_o ,
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282 |
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output wire pipe_rx7_chanisaligned_o ,
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283 |
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output wire [ 2:0] pipe_rx7_status_o ,
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284 |
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output wire pipe_rx7_phy_status_o ,
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285 |
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output wire pipe_rx7_elec_idle_o ,
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286 |
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input wire pipe_rx7_polarity_i ,
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287 |
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input wire pipe_tx7_compliance_i ,
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288 |
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input wire [ 1:0] pipe_tx7_char_is_k_i ,
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289 |
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input wire [15:0] pipe_tx7_data_i ,
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290 |
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input wire pipe_tx7_elec_idle_i ,
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291 |
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input wire [ 1:0] pipe_tx7_powerdown_i ,
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292 |
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293 |
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input wire [ 1:0] pipe_rx7_char_is_k_i ,
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294 |
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input wire [15:0] pipe_rx7_data_i ,
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295 |
|
|
input wire pipe_rx7_valid_i ,
|
296 |
|
|
input wire pipe_rx7_chanisaligned_i ,
|
297 |
|
|
input wire [ 2:0] pipe_rx7_status_i ,
|
298 |
|
|
input wire pipe_rx7_phy_status_i ,
|
299 |
|
|
input wire pipe_rx7_elec_idle_i ,
|
300 |
|
|
output wire pipe_rx7_polarity_o ,
|
301 |
|
|
output wire pipe_tx7_compliance_o ,
|
302 |
|
|
output wire [ 1:0] pipe_tx7_char_is_k_o ,
|
303 |
|
|
output wire [15:0] pipe_tx7_data_o ,
|
304 |
|
|
output wire pipe_tx7_elec_idle_o ,
|
305 |
|
|
output wire [ 1:0] pipe_tx7_powerdown_o ,
|
306 |
|
|
|
307 |
|
|
// Non PIPE signals
|
308 |
|
|
input wire [ 5:0] pl_ltssm_state ,
|
309 |
|
|
input wire pipe_clk ,
|
310 |
|
|
input wire rst_n
|
311 |
|
|
);
|
312 |
|
|
|
313 |
|
|
//******************************************************************//
|
314 |
|
|
// Reality check. //
|
315 |
|
|
//******************************************************************//
|
316 |
|
|
|
317 |
|
|
parameter Tc2o = 1; // clock to out delay model
|
318 |
|
|
|
319 |
|
|
|
320 |
|
|
wire [ 1:0] pipe_rx0_char_is_k_q ;
|
321 |
|
|
wire [15:0] pipe_rx0_data_q ;
|
322 |
|
|
wire [ 1:0] pipe_rx1_char_is_k_q ;
|
323 |
|
|
wire [15:0] pipe_rx1_data_q ;
|
324 |
|
|
wire [ 1:0] pipe_rx2_char_is_k_q ;
|
325 |
|
|
wire [15:0] pipe_rx2_data_q ;
|
326 |
|
|
wire [ 1:0] pipe_rx3_char_is_k_q ;
|
327 |
|
|
wire [15:0] pipe_rx3_data_q ;
|
328 |
|
|
wire [ 1:0] pipe_rx4_char_is_k_q ;
|
329 |
|
|
wire [15:0] pipe_rx4_data_q ;
|
330 |
|
|
wire [ 1:0] pipe_rx5_char_is_k_q ;
|
331 |
|
|
wire [15:0] pipe_rx5_data_q ;
|
332 |
|
|
wire [ 1:0] pipe_rx6_char_is_k_q ;
|
333 |
|
|
wire [15:0] pipe_rx6_data_q ;
|
334 |
|
|
wire [ 1:0] pipe_rx7_char_is_k_q ;
|
335 |
|
|
wire [15:0] pipe_rx7_data_q ;
|
336 |
|
|
|
337 |
|
|
//synthesis translate_off
|
338 |
|
|
// initial begin
|
339 |
|
|
// $display("[%t] %m NO_OF_LANES %0d PIPE_PIPELINE_STAGES %0d", $time, NO_OF_LANES, PIPE_PIPELINE_STAGES);
|
340 |
|
|
// end
|
341 |
|
|
//synthesis translate_on
|
342 |
|
|
|
343 |
|
|
generate
|
344 |
|
|
|
345 |
|
|
pcie_pipe_misc_v6 # (
|
346 |
|
|
|
347 |
|
|
.PIPE_PIPELINE_STAGES(PIPE_PIPELINE_STAGES)
|
348 |
|
|
|
349 |
|
|
)
|
350 |
|
|
pipe_misc_i (
|
351 |
|
|
|
352 |
|
|
.pipe_tx_rcvr_det_i(pipe_tx_rcvr_det_i),
|
353 |
|
|
.pipe_tx_reset_i(pipe_tx_reset_i),
|
354 |
|
|
.pipe_tx_rate_i(pipe_tx_rate_i),
|
355 |
|
|
.pipe_tx_deemph_i(pipe_tx_deemph_i),
|
356 |
|
|
.pipe_tx_margin_i(pipe_tx_margin_i),
|
357 |
|
|
.pipe_tx_swing_i(pipe_tx_swing_i),
|
358 |
|
|
|
359 |
|
|
.pipe_tx_rcvr_det_o(pipe_tx_rcvr_det_o),
|
360 |
|
|
.pipe_tx_reset_o(pipe_tx_reset_o),
|
361 |
|
|
.pipe_tx_rate_o(pipe_tx_rate_o),
|
362 |
|
|
.pipe_tx_deemph_o(pipe_tx_deemph_o),
|
363 |
|
|
.pipe_tx_margin_o(pipe_tx_margin_o),
|
364 |
|
|
.pipe_tx_swing_o(pipe_tx_swing_o) ,
|
365 |
|
|
|
366 |
|
|
.pipe_clk(pipe_clk),
|
367 |
|
|
.rst_n(rst_n)
|
368 |
|
|
);
|
369 |
|
|
|
370 |
|
|
|
371 |
|
|
pcie_pipe_lane_v6 # (
|
372 |
|
|
|
373 |
|
|
.PIPE_PIPELINE_STAGES(PIPE_PIPELINE_STAGES)
|
374 |
|
|
|
375 |
|
|
)
|
376 |
|
|
pipe_lane_0_i (
|
377 |
|
|
|
378 |
|
|
.pipe_rx_char_is_k_o(pipe_rx0_char_is_k_q),
|
379 |
|
|
.pipe_rx_data_o(pipe_rx0_data_q),
|
380 |
|
|
.pipe_rx_valid_o(pipe_rx0_valid_o),
|
381 |
|
|
.pipe_rx_chanisaligned_o(pipe_rx0_chanisaligned_o),
|
382 |
|
|
.pipe_rx_status_o(pipe_rx0_status_o),
|
383 |
|
|
.pipe_rx_phy_status_o(pipe_rx0_phy_status_o),
|
384 |
|
|
.pipe_rx_elec_idle_o(pipe_rx0_elec_idle_o),
|
385 |
|
|
.pipe_rx_polarity_i(pipe_rx0_polarity_i),
|
386 |
|
|
.pipe_tx_compliance_i(pipe_tx0_compliance_i),
|
387 |
|
|
.pipe_tx_char_is_k_i(pipe_tx0_char_is_k_i),
|
388 |
|
|
.pipe_tx_data_i(pipe_tx0_data_i),
|
389 |
|
|
.pipe_tx_elec_idle_i(pipe_tx0_elec_idle_i),
|
390 |
|
|
.pipe_tx_powerdown_i(pipe_tx0_powerdown_i),
|
391 |
|
|
|
392 |
|
|
.pipe_rx_char_is_k_i(pipe_rx0_char_is_k_i),
|
393 |
|
|
.pipe_rx_data_i(pipe_rx0_data_i),
|
394 |
|
|
.pipe_rx_valid_i(pipe_rx0_valid_i),
|
395 |
|
|
.pipe_rx_chanisaligned_i(pipe_rx0_chanisaligned_i),
|
396 |
|
|
.pipe_rx_status_i(pipe_rx0_status_i),
|
397 |
|
|
.pipe_rx_phy_status_i(pipe_rx0_phy_status_i),
|
398 |
|
|
.pipe_rx_elec_idle_i(pipe_rx0_elec_idle_i),
|
399 |
|
|
.pipe_rx_polarity_o(pipe_rx0_polarity_o),
|
400 |
|
|
.pipe_tx_compliance_o(pipe_tx0_compliance_o),
|
401 |
|
|
.pipe_tx_char_is_k_o(pipe_tx0_char_is_k_o),
|
402 |
|
|
.pipe_tx_data_o(pipe_tx0_data_o),
|
403 |
|
|
.pipe_tx_elec_idle_o(pipe_tx0_elec_idle_o),
|
404 |
|
|
.pipe_tx_powerdown_o(pipe_tx0_powerdown_o),
|
405 |
|
|
|
406 |
|
|
.pipe_clk(pipe_clk),
|
407 |
|
|
.rst_n(rst_n)
|
408 |
|
|
|
409 |
|
|
);
|
410 |
|
|
|
411 |
|
|
if (NO_OF_LANES >= 2) begin
|
412 |
|
|
|
413 |
|
|
pcie_pipe_lane_v6 # (
|
414 |
|
|
|
415 |
|
|
.PIPE_PIPELINE_STAGES(PIPE_PIPELINE_STAGES)
|
416 |
|
|
|
417 |
|
|
)
|
418 |
|
|
pipe_lane_1_i (
|
419 |
|
|
|
420 |
|
|
.pipe_rx_char_is_k_o(pipe_rx1_char_is_k_q),
|
421 |
|
|
.pipe_rx_data_o(pipe_rx1_data_q),
|
422 |
|
|
.pipe_rx_valid_o(pipe_rx1_valid_o),
|
423 |
|
|
.pipe_rx_chanisaligned_o(pipe_rx1_chanisaligned_o),
|
424 |
|
|
.pipe_rx_status_o(pipe_rx1_status_o),
|
425 |
|
|
.pipe_rx_phy_status_o(pipe_rx1_phy_status_o),
|
426 |
|
|
.pipe_rx_elec_idle_o(pipe_rx1_elec_idle_o),
|
427 |
|
|
.pipe_rx_polarity_i(pipe_rx1_polarity_i),
|
428 |
|
|
.pipe_tx_compliance_i(pipe_tx1_compliance_i),
|
429 |
|
|
.pipe_tx_char_is_k_i(pipe_tx1_char_is_k_i),
|
430 |
|
|
.pipe_tx_data_i(pipe_tx1_data_i),
|
431 |
|
|
.pipe_tx_elec_idle_i(pipe_tx1_elec_idle_i),
|
432 |
|
|
.pipe_tx_powerdown_i(pipe_tx1_powerdown_i),
|
433 |
|
|
|
434 |
|
|
.pipe_rx_char_is_k_i(pipe_rx1_char_is_k_i),
|
435 |
|
|
.pipe_rx_data_i(pipe_rx1_data_i),
|
436 |
|
|
.pipe_rx_valid_i(pipe_rx1_valid_i),
|
437 |
|
|
.pipe_rx_chanisaligned_i(pipe_rx1_chanisaligned_i),
|
438 |
|
|
.pipe_rx_status_i(pipe_rx1_status_i),
|
439 |
|
|
.pipe_rx_phy_status_i(pipe_rx1_phy_status_i),
|
440 |
|
|
.pipe_rx_elec_idle_i(pipe_rx1_elec_idle_i),
|
441 |
|
|
.pipe_rx_polarity_o(pipe_rx1_polarity_o),
|
442 |
|
|
.pipe_tx_compliance_o(pipe_tx1_compliance_o),
|
443 |
|
|
.pipe_tx_char_is_k_o(pipe_tx1_char_is_k_o),
|
444 |
|
|
.pipe_tx_data_o(pipe_tx1_data_o),
|
445 |
|
|
.pipe_tx_elec_idle_o(pipe_tx1_elec_idle_o),
|
446 |
|
|
.pipe_tx_powerdown_o(pipe_tx1_powerdown_o),
|
447 |
|
|
|
448 |
|
|
.pipe_clk(pipe_clk),
|
449 |
|
|
.rst_n(rst_n)
|
450 |
|
|
|
451 |
|
|
);
|
452 |
|
|
|
453 |
|
|
end
|
454 |
|
|
else begin
|
455 |
|
|
//<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<
|
456 |
|
|
// start remove before release
|
457 |
|
|
`ifndef PIPE_RX_ERR_INJ
|
458 |
|
|
// end remove before release
|
459 |
|
|
//<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<
|
460 |
|
|
assign pipe_rx1_char_is_k_o = 2'b00;
|
461 |
|
|
assign pipe_rx1_data_o = 16'h0000;
|
462 |
|
|
assign pipe_rx1_valid_o = 1'b0;
|
463 |
|
|
assign pipe_rx1_chanisaligned_o = 1'b0;
|
464 |
|
|
assign pipe_rx1_status_o = 3'b000;
|
465 |
|
|
assign pipe_rx1_phy_status_o = 1'b0;
|
466 |
|
|
assign pipe_rx1_elec_idle_o = 1'b1;
|
467 |
|
|
assign pipe_rx1_polarity_o = 1'b0;
|
468 |
|
|
assign pipe_tx1_compliance_o = 1'b0;
|
469 |
|
|
assign pipe_tx1_char_is_k_o = 2'b00;
|
470 |
|
|
assign pipe_tx1_data_o = 16'h0000;
|
471 |
|
|
assign pipe_tx1_elec_idle_o = 1'b1;
|
472 |
|
|
assign pipe_tx1_powerdown_o = 2'b00;
|
473 |
|
|
//<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<
|
474 |
|
|
// start remove before release
|
475 |
|
|
`endif // PIPE_RX_ERR_INJ
|
476 |
|
|
// end remove before release
|
477 |
|
|
//<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<
|
478 |
|
|
end
|
479 |
|
|
|
480 |
|
|
if (NO_OF_LANES >= 4) begin
|
481 |
|
|
|
482 |
|
|
pcie_pipe_lane_v6 # (
|
483 |
|
|
|
484 |
|
|
.PIPE_PIPELINE_STAGES(PIPE_PIPELINE_STAGES)
|
485 |
|
|
)
|
486 |
|
|
pipe_lane_2_i (
|
487 |
|
|
|
488 |
|
|
.pipe_rx_char_is_k_o(pipe_rx2_char_is_k_q),
|
489 |
|
|
.pipe_rx_data_o(pipe_rx2_data_q),
|
490 |
|
|
.pipe_rx_valid_o(pipe_rx2_valid_o),
|
491 |
|
|
.pipe_rx_chanisaligned_o(pipe_rx2_chanisaligned_o),
|
492 |
|
|
.pipe_rx_status_o(pipe_rx2_status_o),
|
493 |
|
|
.pipe_rx_phy_status_o(pipe_rx2_phy_status_o),
|
494 |
|
|
.pipe_rx_elec_idle_o(pipe_rx2_elec_idle_o),
|
495 |
|
|
.pipe_rx_polarity_i(pipe_rx2_polarity_i),
|
496 |
|
|
.pipe_tx_compliance_i(pipe_tx2_compliance_i),
|
497 |
|
|
.pipe_tx_char_is_k_i(pipe_tx2_char_is_k_i),
|
498 |
|
|
.pipe_tx_data_i(pipe_tx2_data_i),
|
499 |
|
|
.pipe_tx_elec_idle_i(pipe_tx2_elec_idle_i),
|
500 |
|
|
.pipe_tx_powerdown_i(pipe_tx2_powerdown_i),
|
501 |
|
|
|
502 |
|
|
.pipe_rx_char_is_k_i(pipe_rx2_char_is_k_i),
|
503 |
|
|
.pipe_rx_data_i(pipe_rx2_data_i),
|
504 |
|
|
.pipe_rx_valid_i(pipe_rx2_valid_i),
|
505 |
|
|
.pipe_rx_chanisaligned_i(pipe_rx2_chanisaligned_i),
|
506 |
|
|
.pipe_rx_status_i(pipe_rx2_status_i),
|
507 |
|
|
.pipe_rx_phy_status_i(pipe_rx2_phy_status_i),
|
508 |
|
|
.pipe_rx_elec_idle_i(pipe_rx2_elec_idle_i),
|
509 |
|
|
.pipe_rx_polarity_o(pipe_rx2_polarity_o),
|
510 |
|
|
.pipe_tx_compliance_o(pipe_tx2_compliance_o),
|
511 |
|
|
.pipe_tx_char_is_k_o(pipe_tx2_char_is_k_o),
|
512 |
|
|
.pipe_tx_data_o(pipe_tx2_data_o),
|
513 |
|
|
.pipe_tx_elec_idle_o(pipe_tx2_elec_idle_o),
|
514 |
|
|
.pipe_tx_powerdown_o(pipe_tx2_powerdown_o),
|
515 |
|
|
|
516 |
|
|
.pipe_clk(pipe_clk),
|
517 |
|
|
.rst_n(rst_n)
|
518 |
|
|
|
519 |
|
|
);
|
520 |
|
|
|
521 |
|
|
pcie_pipe_lane_v6 # (
|
522 |
|
|
|
523 |
|
|
.PIPE_PIPELINE_STAGES(PIPE_PIPELINE_STAGES)
|
524 |
|
|
|
525 |
|
|
)
|
526 |
|
|
pipe_lane_3_i (
|
527 |
|
|
|
528 |
|
|
.pipe_rx_char_is_k_o(pipe_rx3_char_is_k_q),
|
529 |
|
|
.pipe_rx_data_o(pipe_rx3_data_q),
|
530 |
|
|
.pipe_rx_valid_o(pipe_rx3_valid_o),
|
531 |
|
|
.pipe_rx_chanisaligned_o(pipe_rx3_chanisaligned_o),
|
532 |
|
|
.pipe_rx_status_o(pipe_rx3_status_o),
|
533 |
|
|
.pipe_rx_phy_status_o(pipe_rx3_phy_status_o),
|
534 |
|
|
.pipe_rx_elec_idle_o(pipe_rx3_elec_idle_o),
|
535 |
|
|
.pipe_rx_polarity_i(pipe_rx3_polarity_i),
|
536 |
|
|
.pipe_tx_compliance_i(pipe_tx3_compliance_i),
|
537 |
|
|
.pipe_tx_char_is_k_i(pipe_tx3_char_is_k_i),
|
538 |
|
|
.pipe_tx_data_i(pipe_tx3_data_i),
|
539 |
|
|
.pipe_tx_elec_idle_i(pipe_tx3_elec_idle_i),
|
540 |
|
|
.pipe_tx_powerdown_i(pipe_tx3_powerdown_i),
|
541 |
|
|
|
542 |
|
|
.pipe_rx_char_is_k_i(pipe_rx3_char_is_k_i),
|
543 |
|
|
.pipe_rx_data_i(pipe_rx3_data_i),
|
544 |
|
|
.pipe_rx_valid_i(pipe_rx3_valid_i),
|
545 |
|
|
.pipe_rx_chanisaligned_i(pipe_rx3_chanisaligned_i),
|
546 |
|
|
.pipe_rx_status_i(pipe_rx3_status_i),
|
547 |
|
|
.pipe_rx_phy_status_i(pipe_rx3_phy_status_i),
|
548 |
|
|
.pipe_rx_elec_idle_i(pipe_rx3_elec_idle_i),
|
549 |
|
|
.pipe_rx_polarity_o(pipe_rx3_polarity_o),
|
550 |
|
|
.pipe_tx_compliance_o(pipe_tx3_compliance_o),
|
551 |
|
|
.pipe_tx_char_is_k_o(pipe_tx3_char_is_k_o),
|
552 |
|
|
.pipe_tx_data_o(pipe_tx3_data_o),
|
553 |
|
|
.pipe_tx_elec_idle_o(pipe_tx3_elec_idle_o),
|
554 |
|
|
.pipe_tx_powerdown_o(pipe_tx3_powerdown_o),
|
555 |
|
|
|
556 |
|
|
.pipe_clk(pipe_clk),
|
557 |
|
|
.rst_n(rst_n)
|
558 |
|
|
|
559 |
|
|
);
|
560 |
|
|
|
561 |
|
|
end
|
562 |
|
|
else begin
|
563 |
|
|
//<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<
|
564 |
|
|
// start remove before release
|
565 |
|
|
`ifndef PIPE_RX_ERR_INJ
|
566 |
|
|
// end remove before release
|
567 |
|
|
//<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<
|
568 |
|
|
assign pipe_rx2_char_is_k_o = 2'b00;
|
569 |
|
|
assign pipe_rx2_data_o = 16'h0000;
|
570 |
|
|
assign pipe_rx2_valid_o = 1'b0;
|
571 |
|
|
assign pipe_rx2_chanisaligned_o = 1'b0;
|
572 |
|
|
assign pipe_rx2_status_o = 3'b000;
|
573 |
|
|
assign pipe_rx2_phy_status_o = 1'b0;
|
574 |
|
|
assign pipe_rx2_elec_idle_o = 1'b1;
|
575 |
|
|
assign pipe_rx2_polarity_o = 1'b0;
|
576 |
|
|
assign pipe_tx2_compliance_o = 1'b0;
|
577 |
|
|
assign pipe_tx2_char_is_k_o = 2'b00;
|
578 |
|
|
assign pipe_tx2_data_o = 16'h0000;
|
579 |
|
|
assign pipe_tx2_elec_idle_o = 1'b1;
|
580 |
|
|
assign pipe_tx2_powerdown_o = 2'b00;
|
581 |
|
|
|
582 |
|
|
assign pipe_rx3_char_is_k_o = 2'b00;
|
583 |
|
|
assign pipe_rx3_data_o = 16'h0000;
|
584 |
|
|
assign pipe_rx3_valid_o = 1'b0;
|
585 |
|
|
assign pipe_rx3_chanisaligned_o = 1'b0;
|
586 |
|
|
assign pipe_rx3_status_o = 3'b000;
|
587 |
|
|
assign pipe_rx3_phy_status_o = 1'b0;
|
588 |
|
|
assign pipe_rx3_elec_idle_o = 1'b1;
|
589 |
|
|
assign pipe_rx3_polarity_o = 1'b0;
|
590 |
|
|
assign pipe_tx3_compliance_o = 1'b0;
|
591 |
|
|
assign pipe_tx3_char_is_k_o = 2'b00;
|
592 |
|
|
assign pipe_tx3_data_o = 16'h0000;
|
593 |
|
|
assign pipe_tx3_elec_idle_o = 1'b1;
|
594 |
|
|
assign pipe_tx3_powerdown_o = 2'b00;
|
595 |
|
|
//<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<
|
596 |
|
|
// start remove before release
|
597 |
|
|
`endif // PIPE_RX_ERR_INJ
|
598 |
|
|
// end remove before release
|
599 |
|
|
//<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<
|
600 |
|
|
end
|
601 |
|
|
|
602 |
|
|
if (NO_OF_LANES >= 8) begin
|
603 |
|
|
|
604 |
|
|
pcie_pipe_lane_v6 # (
|
605 |
|
|
|
606 |
|
|
.PIPE_PIPELINE_STAGES(PIPE_PIPELINE_STAGES)
|
607 |
|
|
|
608 |
|
|
)
|
609 |
|
|
pipe_lane_4_i (
|
610 |
|
|
|
611 |
|
|
.pipe_rx_char_is_k_o(pipe_rx4_char_is_k_q),
|
612 |
|
|
.pipe_rx_data_o(pipe_rx4_data_q),
|
613 |
|
|
.pipe_rx_valid_o(pipe_rx4_valid_o),
|
614 |
|
|
.pipe_rx_chanisaligned_o(pipe_rx4_chanisaligned_o),
|
615 |
|
|
.pipe_rx_status_o(pipe_rx4_status_o),
|
616 |
|
|
.pipe_rx_phy_status_o(pipe_rx4_phy_status_o),
|
617 |
|
|
.pipe_rx_elec_idle_o(pipe_rx4_elec_idle_o),
|
618 |
|
|
.pipe_rx_polarity_i(pipe_rx4_polarity_i),
|
619 |
|
|
.pipe_tx_compliance_i(pipe_tx4_compliance_i),
|
620 |
|
|
.pipe_tx_char_is_k_i(pipe_tx4_char_is_k_i),
|
621 |
|
|
.pipe_tx_data_i(pipe_tx4_data_i),
|
622 |
|
|
.pipe_tx_elec_idle_i(pipe_tx4_elec_idle_i),
|
623 |
|
|
.pipe_tx_powerdown_i(pipe_tx4_powerdown_i),
|
624 |
|
|
|
625 |
|
|
.pipe_rx_char_is_k_i(pipe_rx4_char_is_k_i),
|
626 |
|
|
.pipe_rx_data_i(pipe_rx4_data_i),
|
627 |
|
|
.pipe_rx_valid_i(pipe_rx4_valid_i),
|
628 |
|
|
.pipe_rx_chanisaligned_i(pipe_rx4_chanisaligned_i),
|
629 |
|
|
.pipe_rx_status_i(pipe_rx4_status_i),
|
630 |
|
|
.pipe_rx_phy_status_i(pipe_rx4_phy_status_i),
|
631 |
|
|
.pipe_rx_elec_idle_i(pipe_rx4_elec_idle_i),
|
632 |
|
|
.pipe_rx_polarity_o(pipe_rx4_polarity_o),
|
633 |
|
|
.pipe_tx_compliance_o(pipe_tx4_compliance_o),
|
634 |
|
|
.pipe_tx_char_is_k_o(pipe_tx4_char_is_k_o),
|
635 |
|
|
.pipe_tx_data_o(pipe_tx4_data_o),
|
636 |
|
|
.pipe_tx_elec_idle_o(pipe_tx4_elec_idle_o),
|
637 |
|
|
.pipe_tx_powerdown_o(pipe_tx4_powerdown_o),
|
638 |
|
|
|
639 |
|
|
.pipe_clk(pipe_clk),
|
640 |
|
|
.rst_n(rst_n)
|
641 |
|
|
|
642 |
|
|
);
|
643 |
|
|
|
644 |
|
|
pcie_pipe_lane_v6 # (
|
645 |
|
|
|
646 |
|
|
.PIPE_PIPELINE_STAGES(PIPE_PIPELINE_STAGES)
|
647 |
|
|
|
648 |
|
|
)
|
649 |
|
|
pipe_lane_5_i (
|
650 |
|
|
|
651 |
|
|
.pipe_rx_char_is_k_o(pipe_rx5_char_is_k_q),
|
652 |
|
|
.pipe_rx_data_o(pipe_rx5_data_q),
|
653 |
|
|
.pipe_rx_valid_o(pipe_rx5_valid_o),
|
654 |
|
|
.pipe_rx_chanisaligned_o(pipe_rx5_chanisaligned_o),
|
655 |
|
|
.pipe_rx_status_o(pipe_rx5_status_o),
|
656 |
|
|
.pipe_rx_phy_status_o(pipe_rx5_phy_status_o),
|
657 |
|
|
.pipe_rx_elec_idle_o(pipe_rx5_elec_idle_o),
|
658 |
|
|
.pipe_rx_polarity_i(pipe_rx5_polarity_i),
|
659 |
|
|
.pipe_tx_compliance_i(pipe_tx5_compliance_i),
|
660 |
|
|
.pipe_tx_char_is_k_i(pipe_tx5_char_is_k_i),
|
661 |
|
|
.pipe_tx_data_i(pipe_tx5_data_i),
|
662 |
|
|
.pipe_tx_elec_idle_i(pipe_tx5_elec_idle_i),
|
663 |
|
|
.pipe_tx_powerdown_i(pipe_tx5_powerdown_i),
|
664 |
|
|
|
665 |
|
|
.pipe_rx_char_is_k_i(pipe_rx5_char_is_k_i),
|
666 |
|
|
.pipe_rx_data_i(pipe_rx5_data_i),
|
667 |
|
|
.pipe_rx_valid_i(pipe_rx5_valid_i),
|
668 |
|
|
.pipe_rx_chanisaligned_i(pipe_rx5_chanisaligned_i),
|
669 |
|
|
.pipe_rx_status_i(pipe_rx5_status_i),
|
670 |
|
|
.pipe_rx_phy_status_i(pipe_rx4_phy_status_i),
|
671 |
|
|
.pipe_rx_elec_idle_i(pipe_rx4_elec_idle_i),
|
672 |
|
|
.pipe_rx_polarity_o(pipe_rx5_polarity_o),
|
673 |
|
|
.pipe_tx_compliance_o(pipe_tx5_compliance_o),
|
674 |
|
|
.pipe_tx_char_is_k_o(pipe_tx5_char_is_k_o),
|
675 |
|
|
.pipe_tx_data_o(pipe_tx5_data_o),
|
676 |
|
|
.pipe_tx_elec_idle_o(pipe_tx5_elec_idle_o),
|
677 |
|
|
.pipe_tx_powerdown_o(pipe_tx5_powerdown_o),
|
678 |
|
|
|
679 |
|
|
.pipe_clk(pipe_clk),
|
680 |
|
|
.rst_n(rst_n)
|
681 |
|
|
|
682 |
|
|
);
|
683 |
|
|
|
684 |
|
|
pcie_pipe_lane_v6 # (
|
685 |
|
|
|
686 |
|
|
.PIPE_PIPELINE_STAGES(PIPE_PIPELINE_STAGES)
|
687 |
|
|
|
688 |
|
|
)
|
689 |
|
|
pipe_lane_6_i (
|
690 |
|
|
|
691 |
|
|
.pipe_rx_char_is_k_o(pipe_rx6_char_is_k_q),
|
692 |
|
|
.pipe_rx_data_o(pipe_rx6_data_q),
|
693 |
|
|
.pipe_rx_valid_o(pipe_rx6_valid_o),
|
694 |
|
|
.pipe_rx_chanisaligned_o(pipe_rx6_chanisaligned_o),
|
695 |
|
|
.pipe_rx_status_o(pipe_rx6_status_o),
|
696 |
|
|
.pipe_rx_phy_status_o(pipe_rx6_phy_status_o),
|
697 |
|
|
.pipe_rx_elec_idle_o(pipe_rx6_elec_idle_o),
|
698 |
|
|
.pipe_rx_polarity_i(pipe_rx6_polarity_i),
|
699 |
|
|
.pipe_tx_compliance_i(pipe_tx6_compliance_i),
|
700 |
|
|
.pipe_tx_char_is_k_i(pipe_tx6_char_is_k_i),
|
701 |
|
|
.pipe_tx_data_i(pipe_tx6_data_i),
|
702 |
|
|
.pipe_tx_elec_idle_i(pipe_tx6_elec_idle_i),
|
703 |
|
|
.pipe_tx_powerdown_i(pipe_tx6_powerdown_i),
|
704 |
|
|
|
705 |
|
|
.pipe_rx_char_is_k_i(pipe_rx6_char_is_k_i),
|
706 |
|
|
.pipe_rx_data_i(pipe_rx6_data_i),
|
707 |
|
|
.pipe_rx_valid_i(pipe_rx6_valid_i),
|
708 |
|
|
.pipe_rx_chanisaligned_i(pipe_rx6_chanisaligned_i),
|
709 |
|
|
.pipe_rx_status_i(pipe_rx6_status_i),
|
710 |
|
|
.pipe_rx_phy_status_i(pipe_rx4_phy_status_i),
|
711 |
|
|
.pipe_rx_elec_idle_i(pipe_rx6_elec_idle_i),
|
712 |
|
|
.pipe_rx_polarity_o(pipe_rx6_polarity_o),
|
713 |
|
|
.pipe_tx_compliance_o(pipe_tx6_compliance_o),
|
714 |
|
|
.pipe_tx_char_is_k_o(pipe_tx6_char_is_k_o),
|
715 |
|
|
.pipe_tx_data_o(pipe_tx6_data_o),
|
716 |
|
|
.pipe_tx_elec_idle_o(pipe_tx6_elec_idle_o),
|
717 |
|
|
.pipe_tx_powerdown_o(pipe_tx6_powerdown_o),
|
718 |
|
|
|
719 |
|
|
.pipe_clk(pipe_clk),
|
720 |
|
|
.rst_n(rst_n)
|
721 |
|
|
|
722 |
|
|
);
|
723 |
|
|
|
724 |
|
|
pcie_pipe_lane_v6 # (
|
725 |
|
|
|
726 |
|
|
.PIPE_PIPELINE_STAGES(PIPE_PIPELINE_STAGES)
|
727 |
|
|
|
728 |
|
|
)
|
729 |
|
|
pipe_lane_7_i (
|
730 |
|
|
|
731 |
|
|
.pipe_rx_char_is_k_o(pipe_rx7_char_is_k_q),
|
732 |
|
|
.pipe_rx_data_o(pipe_rx7_data_q),
|
733 |
|
|
.pipe_rx_valid_o(pipe_rx7_valid_o),
|
734 |
|
|
.pipe_rx_chanisaligned_o(pipe_rx7_chanisaligned_o),
|
735 |
|
|
.pipe_rx_status_o(pipe_rx7_status_o),
|
736 |
|
|
.pipe_rx_phy_status_o(pipe_rx7_phy_status_o),
|
737 |
|
|
.pipe_rx_elec_idle_o(pipe_rx7_elec_idle_o),
|
738 |
|
|
.pipe_rx_polarity_i(pipe_rx7_polarity_i),
|
739 |
|
|
.pipe_tx_compliance_i(pipe_tx7_compliance_i),
|
740 |
|
|
.pipe_tx_char_is_k_i(pipe_tx7_char_is_k_i),
|
741 |
|
|
.pipe_tx_data_i(pipe_tx7_data_i),
|
742 |
|
|
.pipe_tx_elec_idle_i(pipe_tx7_elec_idle_i),
|
743 |
|
|
.pipe_tx_powerdown_i(pipe_tx7_powerdown_i),
|
744 |
|
|
|
745 |
|
|
.pipe_rx_char_is_k_i(pipe_rx7_char_is_k_i),
|
746 |
|
|
.pipe_rx_data_i(pipe_rx7_data_i),
|
747 |
|
|
.pipe_rx_valid_i(pipe_rx7_valid_i),
|
748 |
|
|
.pipe_rx_chanisaligned_i(pipe_rx7_chanisaligned_i),
|
749 |
|
|
.pipe_rx_status_i(pipe_rx7_status_i),
|
750 |
|
|
.pipe_rx_phy_status_i(pipe_rx4_phy_status_i),
|
751 |
|
|
.pipe_rx_elec_idle_i(pipe_rx7_elec_idle_i),
|
752 |
|
|
.pipe_rx_polarity_o(pipe_rx7_polarity_o),
|
753 |
|
|
.pipe_tx_compliance_o(pipe_tx7_compliance_o),
|
754 |
|
|
.pipe_tx_char_is_k_o(pipe_tx7_char_is_k_o),
|
755 |
|
|
.pipe_tx_data_o(pipe_tx7_data_o),
|
756 |
|
|
.pipe_tx_elec_idle_o(pipe_tx7_elec_idle_o),
|
757 |
|
|
.pipe_tx_powerdown_o(pipe_tx7_powerdown_o),
|
758 |
|
|
|
759 |
|
|
.pipe_clk(pipe_clk),
|
760 |
|
|
.rst_n(rst_n)
|
761 |
|
|
|
762 |
|
|
);
|
763 |
|
|
|
764 |
|
|
end
|
765 |
|
|
else begin
|
766 |
|
|
//<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<
|
767 |
|
|
// start remove before release
|
768 |
|
|
`ifndef PIPE_RX_ERR_INJ
|
769 |
|
|
// end remove before release
|
770 |
|
|
//<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<
|
771 |
|
|
assign pipe_rx4_char_is_k_o = 2'b00;
|
772 |
|
|
assign pipe_rx4_data_o = 16'h0000;
|
773 |
|
|
assign pipe_rx4_valid_o = 1'b0;
|
774 |
|
|
assign pipe_rx4_chanisaligned_o = 1'b0;
|
775 |
|
|
assign pipe_rx4_status_o = 3'b000;
|
776 |
|
|
assign pipe_rx4_phy_status_o = 1'b0;
|
777 |
|
|
assign pipe_rx4_elec_idle_o = 1'b1;
|
778 |
|
|
assign pipe_rx4_polarity_o = 1'b0;
|
779 |
|
|
assign pipe_tx4_compliance_o = 1'b0;
|
780 |
|
|
assign pipe_tx4_char_is_k_o = 2'b00;
|
781 |
|
|
assign pipe_tx4_data_o = 16'h0000;
|
782 |
|
|
assign pipe_tx4_elec_idle_o = 1'b1;
|
783 |
|
|
assign pipe_tx4_powerdown_o = 2'b00;
|
784 |
|
|
|
785 |
|
|
assign pipe_rx5_char_is_k_o = 2'b00;
|
786 |
|
|
assign pipe_rx5_data_o = 16'h0000;
|
787 |
|
|
assign pipe_rx5_valid_o = 1'b0;
|
788 |
|
|
assign pipe_rx5_chanisaligned_o = 1'b0;
|
789 |
|
|
assign pipe_rx5_status_o = 3'b000;
|
790 |
|
|
assign pipe_rx5_phy_status_o = 1'b0;
|
791 |
|
|
assign pipe_rx5_elec_idle_o = 1'b1;
|
792 |
|
|
assign pipe_rx5_polarity_o = 1'b0;
|
793 |
|
|
assign pipe_tx5_compliance_o = 1'b0;
|
794 |
|
|
assign pipe_tx5_char_is_k_o = 2'b00;
|
795 |
|
|
assign pipe_tx5_data_o = 16'h0000;
|
796 |
|
|
assign pipe_tx5_elec_idle_o = 1'b1;
|
797 |
|
|
assign pipe_tx5_powerdown_o = 2'b00;
|
798 |
|
|
|
799 |
|
|
assign pipe_rx6_char_is_k_o = 2'b00;
|
800 |
|
|
assign pipe_rx6_data_o = 16'h0000;
|
801 |
|
|
assign pipe_rx6_valid_o = 1'b0;
|
802 |
|
|
assign pipe_rx6_chanisaligned_o = 1'b0;
|
803 |
|
|
assign pipe_rx6_status_o = 3'b000;
|
804 |
|
|
assign pipe_rx6_phy_status_o = 1'b0;
|
805 |
|
|
assign pipe_rx6_elec_idle_o = 1'b1;
|
806 |
|
|
assign pipe_rx6_polarity_o = 1'b0;
|
807 |
|
|
assign pipe_tx6_compliance_o = 1'b0;
|
808 |
|
|
assign pipe_tx6_char_is_k_o = 2'b00;
|
809 |
|
|
assign pipe_tx6_data_o = 16'h0000;
|
810 |
|
|
assign pipe_tx6_elec_idle_o = 1'b1;
|
811 |
|
|
assign pipe_tx6_powerdown_o = 2'b00;
|
812 |
|
|
|
813 |
|
|
assign pipe_rx7_char_is_k_o = 2'b00;
|
814 |
|
|
assign pipe_rx7_data_o = 16'h0000;
|
815 |
|
|
assign pipe_rx7_valid_o = 1'b0;
|
816 |
|
|
assign pipe_rx7_chanisaligned_o = 1'b0;
|
817 |
|
|
assign pipe_rx7_status_o = 3'b000;
|
818 |
|
|
assign pipe_rx7_phy_status_o = 1'b0;
|
819 |
|
|
assign pipe_rx7_elec_idle_o = 1'b1;
|
820 |
|
|
assign pipe_rx7_polarity_o = 1'b0;
|
821 |
|
|
assign pipe_tx7_compliance_o = 1'b0;
|
822 |
|
|
assign pipe_tx7_char_is_k_o = 2'b00;
|
823 |
|
|
assign pipe_tx7_data_o = 16'h0000;
|
824 |
|
|
assign pipe_tx7_elec_idle_o = 1'b1;
|
825 |
|
|
assign pipe_tx7_powerdown_o = 2'b00;
|
826 |
|
|
//<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<
|
827 |
|
|
// start remove before release
|
828 |
|
|
`endif // PIPE_RX_ERR_INJ
|
829 |
|
|
// end remove before release
|
830 |
|
|
//<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<
|
831 |
|
|
end
|
832 |
|
|
|
833 |
|
|
endgenerate
|
834 |
|
|
|
835 |
|
|
//<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<
|
836 |
|
|
// start remove before release
|
837 |
|
|
`ifdef PIPE_RX_ERR_INJ
|
838 |
|
|
|
839 |
|
|
generate
|
840 |
|
|
|
841 |
|
|
if (LINK_CAP_MAX_LINK_SPEED == 4'h2) begin
|
842 |
|
|
|
843 |
|
|
reg [5:0] pl_ltssm_state_q;
|
844 |
|
|
|
845 |
|
|
always @(posedge pipe_clk) begin
|
846 |
|
|
|
847 |
|
|
if (rst_n)
|
848 |
|
|
pl_ltssm_state_q <= 0;
|
849 |
|
|
else
|
850 |
|
|
pl_ltssm_state_q <= pl_ltssm_state;
|
851 |
|
|
|
852 |
|
|
end
|
853 |
|
|
|
854 |
|
|
wire plm_in_l0 = (pl_ltssm_state_q == 6'h16);
|
855 |
|
|
|
856 |
|
|
|
857 |
|
|
pcie_pipe_err_inject # (
|
858 |
|
|
.NO_OF_LANES(NO_OF_LANES)
|
859 |
|
|
)
|
860 |
|
|
rx_err_inj(
|
861 |
|
|
|
862 |
|
|
.enable(plm_in_l0),
|
863 |
|
|
.pipe_clk(pipe_clk),
|
864 |
|
|
.pipe_rst(!rst_n),
|
865 |
|
|
|
866 |
|
|
.o_ln0_cisk(pipe_rx0_char_is_k_o),
|
867 |
|
|
.o_ln0_data(pipe_rx0_data_o),
|
868 |
|
|
.i_ln0_cisk(pipe_rx0_char_is_k_q),
|
869 |
|
|
.i_ln0_data(pipe_rx0_data_q),
|
870 |
|
|
.o_ln1_cisk(pipe_rx1_char_is_k_o),
|
871 |
|
|
.o_ln1_data(pipe_rx1_data_o),
|
872 |
|
|
.i_ln1_cisk((NO_OF_LANES >= 2 ) ? pipe_rx1_char_is_k_q : 2'b0),
|
873 |
|
|
.i_ln1_data((NO_OF_LANES >= 2 ) ? pipe_rx1_data_q : 16'h0),
|
874 |
|
|
.o_ln2_cisk(pipe_rx2_char_is_k_o),
|
875 |
|
|
.o_ln2_data(pipe_rx2_data_o),
|
876 |
|
|
.i_ln2_cisk((NO_OF_LANES >= 4 ) ? pipe_rx2_char_is_k_q : 2'b0),
|
877 |
|
|
.i_ln2_data((NO_OF_LANES >= 4 ) ? pipe_rx2_data_q : 16'h0),
|
878 |
|
|
.o_ln3_cisk(pipe_rx3_char_is_k_o),
|
879 |
|
|
.o_ln3_data(pipe_rx3_data_o),
|
880 |
|
|
.i_ln3_cisk((NO_OF_LANES >= 4 ) ? pipe_rx3_char_is_k_q : 2'b0),
|
881 |
|
|
.i_ln3_data((NO_OF_LANES >= 4 ) ? pipe_rx3_data_q : 16'h0),
|
882 |
|
|
.o_ln4_cisk(pipe_rx4_char_is_k_o),
|
883 |
|
|
.o_ln4_data(pipe_rx4_data_o),
|
884 |
|
|
.i_ln4_cisk((NO_OF_LANES >= 8 ) ? pipe_rx4_char_is_k_q : 2'b0),
|
885 |
|
|
.i_ln4_data((NO_OF_LANES >= 8 ) ? pipe_rx4_data_q : 16'h0),
|
886 |
|
|
.o_ln5_cisk(pipe_rx5_char_is_k_o),
|
887 |
|
|
.o_ln5_data(pipe_rx5_data_o),
|
888 |
|
|
.i_ln5_cisk((NO_OF_LANES >= 8 ) ? pipe_rx5_char_is_k_q : 2'b0),
|
889 |
|
|
.i_ln5_data((NO_OF_LANES >= 8 ) ? pipe_rx5_data_q : 16'h0),
|
890 |
|
|
.o_ln6_cisk(pipe_rx6_char_is_k_o),
|
891 |
|
|
.o_ln6_data(pipe_rx6_data_o),
|
892 |
|
|
.i_ln6_cisk((NO_OF_LANES >= 8 ) ? pipe_rx6_char_is_k_q : 2'b0),
|
893 |
|
|
.i_ln6_data((NO_OF_LANES >= 8 ) ? pipe_rx6_data_q : 16'h0),
|
894 |
|
|
.o_ln7_cisk(pipe_rx7_char_is_k_o),
|
895 |
|
|
.o_ln7_data(pipe_rx7_data_o),
|
896 |
|
|
.i_ln7_cisk((NO_OF_LANES >= 8 ) ? pipe_rx7_char_is_k_q : 2'b0),
|
897 |
|
|
.i_ln7_data((NO_OF_LANES >= 8 ) ? pipe_rx7_data_q : 16'h0)
|
898 |
|
|
);
|
899 |
|
|
|
900 |
|
|
end else begin
|
901 |
|
|
|
902 |
|
|
assign pipe_rx0_char_is_k_o = pipe_rx0_char_is_k_q;
|
903 |
|
|
assign pipe_rx0_data_o = pipe_rx0_data_q;
|
904 |
|
|
assign pipe_rx1_char_is_k_o = pipe_rx1_char_is_k_q;
|
905 |
|
|
assign pipe_rx1_data_o = pipe_rx1_data_q;
|
906 |
|
|
assign pipe_rx2_char_is_k_o = pipe_rx2_char_is_k_q;
|
907 |
|
|
assign pipe_rx2_data_o = pipe_rx2_data_q;
|
908 |
|
|
assign pipe_rx3_char_is_k_o = pipe_rx3_char_is_k_q;
|
909 |
|
|
assign pipe_rx3_data_o = pipe_rx3_data_q;
|
910 |
|
|
assign pipe_rx4_char_is_k_o = pipe_rx4_char_is_k_q;
|
911 |
|
|
assign pipe_rx4_data_o = pipe_rx4_data_q;
|
912 |
|
|
assign pipe_rx5_char_is_k_o = pipe_rx5_char_is_k_q;
|
913 |
|
|
assign pipe_rx5_data_o = pipe_rx5_data_q;
|
914 |
|
|
assign pipe_rx6_char_is_k_o = pipe_rx6_char_is_k_q;
|
915 |
|
|
assign pipe_rx6_data_o = pipe_rx6_data_q;
|
916 |
|
|
assign pipe_rx7_char_is_k_o = pipe_rx7_char_is_k_q;
|
917 |
|
|
assign pipe_rx7_data_o = pipe_rx7_data_q;
|
918 |
|
|
|
919 |
|
|
end
|
920 |
|
|
|
921 |
|
|
endgenerate
|
922 |
|
|
|
923 |
|
|
|
924 |
|
|
`endif // PIPE_RX_ERR_INJ
|
925 |
|
|
// end remove before release
|
926 |
|
|
//<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<
|
927 |
|
|
|
928 |
|
|
//<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<
|
929 |
|
|
// start remove before release
|
930 |
|
|
`ifndef PIPE_RX_ERR_INJ
|
931 |
|
|
// end remove before release
|
932 |
|
|
//<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<
|
933 |
|
|
|
934 |
|
|
assign pipe_rx0_char_is_k_o = pipe_rx0_char_is_k_q;
|
935 |
|
|
assign pipe_rx0_data_o = pipe_rx0_data_q;
|
936 |
|
|
assign pipe_rx1_char_is_k_o = pipe_rx1_char_is_k_q;
|
937 |
|
|
assign pipe_rx1_data_o = pipe_rx1_data_q;
|
938 |
|
|
assign pipe_rx2_char_is_k_o = pipe_rx2_char_is_k_q;
|
939 |
|
|
assign pipe_rx2_data_o = pipe_rx2_data_q;
|
940 |
|
|
assign pipe_rx3_char_is_k_o = pipe_rx3_char_is_k_q;
|
941 |
|
|
assign pipe_rx3_data_o = pipe_rx3_data_q;
|
942 |
|
|
assign pipe_rx4_char_is_k_o = pipe_rx4_char_is_k_q;
|
943 |
|
|
assign pipe_rx4_data_o = pipe_rx4_data_q;
|
944 |
|
|
assign pipe_rx5_char_is_k_o = pipe_rx5_char_is_k_q;
|
945 |
|
|
assign pipe_rx5_data_o = pipe_rx5_data_q;
|
946 |
|
|
assign pipe_rx6_char_is_k_o = pipe_rx6_char_is_k_q;
|
947 |
|
|
assign pipe_rx6_data_o = pipe_rx6_data_q;
|
948 |
|
|
assign pipe_rx7_char_is_k_o = pipe_rx7_char_is_k_q;
|
949 |
|
|
assign pipe_rx7_data_o = pipe_rx7_data_q;
|
950 |
|
|
|
951 |
|
|
//<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<
|
952 |
|
|
// start remove before release
|
953 |
|
|
`endif // PIPE_RX_ERR_INJ
|
954 |
|
|
// end remove before release
|
955 |
|
|
//<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<
|
956 |
|
|
|
957 |
|
|
endmodule
|