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[/] [pcie_sg_dma/] [branches/] [Virtex6/] [ML605_ISE12.3/] [v6eb_pcie.vhd_Original] - Blame information for rev 11

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1 11 barabba 
----------------------------------------------------------------------------------
2 
-- Company:
3 
-- Engineer:
4 
--
5 
-- Create Date:    09:12:51 01 Feb 2010
6 
-- Design Name:
7 
-- Module Name:    v6pcieDMA - Behavioral
8 
-- Project Name:
9 
-- Target Devices:
10 
-- Tool versions:
11 
-- Description:
12 
--
13 
-- Dependencies:
14 
--
15 
-- Revision:
16 
--
17 
-- Revision 1.00 - File Released
18 
--
19 
-- Additional Comments:
20 
--
21 
----------------------------------------------------------------------------------
22 
library IEEE;
23 
use IEEE.STD_LOGIC_1164.ALL;
24 
use IEEE.STD_LOGIC_ARITH.ALL;
25 
use IEEE.STD_LOGIC_UNSIGNED.ALL;
26 
 
27 
library work;
28 
use work.abb64Package.all;
29 
 
30 
---- Uncomment the following library declaration if instantiating
31 
---- any Xilinx primitives in this code.
32 
library UNISIM;
33 
use UNISIM.VComponents.all;
34 
 
35 
entity v6pcieDMA is
36 
    generic (
37 
          constant pcieLanes            : integer     := C_NUM_PCIE_LANES
38 
          );
39 
    Port (
40 
 
41 
          -- Optical links
42 
          TILE0_REFCLK_PAD_N_IN         : IN  std_logic;
43 
          TILE0_REFCLK_PAD_P_IN         : IN  std_logic;
44 
 
45 
          RXN_IN                        : IN  std_logic;
46 
          RXP_IN                        : IN  std_logic;
47 
          TXN_OUT                       : OUT std_logic;
48 
          TXP_OUT                       : OUT std_logic;
49 
 
50 
          SFP_LOS                       : IN  std_logic;
51 
 
52 
 
53 
                         user_clk                                                        : IN std_logic;
54 
 
55 
          -- DDR interface
56 
 
57 
--          ddr2_sys_clk                  : IN    std_logic;
58 
--v6          Button_Rst                    : IN    std_logic;
59 
 
60 
          -- dummy pin input  !!!! not really exists
61 
--v6          dummy_pin_in                  : IN    std_logic_vector(3-1 downto 0);
62 
 
63 
          -- DPR blinker
64 
          LEDs_IO_pin                   : OUT   std_logic_vector(7 downto 0);
65 
 
66 
 
67 
--v6          refclkout                 : OUT   std_logic;
68 
 
69 
          -- PCIe transceivers
70 
          pci_exp_rxp                   : IN    std_logic_vector(pcieLanes - 1 downto 0);
71 
          pci_exp_rxn                   : IN    std_logic_vector(pcieLanes - 1 downto 0);
72 
          pci_exp_txp                   : OUT   std_logic_vector(pcieLanes - 1 downto 0);
73 
          pci_exp_txn                   : OUT   std_logic_vector(pcieLanes - 1 downto 0);
74 
 
75 
          -- Necessity signals
76 
          sys_clk_p                     : IN    std_logic;
77 
          sys_clk_n                     : IN    std_logic;
78 
          sys_reset_n                   : IN    std_logic
79 
          );
80 
 
81 
end entity v6pcieDMA;
82 
 
83 
 
84 
architecture Behavioral of v6pcieDMA is
85 
 
86 
component pcie_userlogic_01_cw
87 
  port (
88 
    ce: in std_logic := '1';
89 
    clk: in std_logic; -- clock period = 5.0 ns (200.0 Mhz)
90 
    rst_i: in std_logic;
91 
    rst_o: out std_logic;
92 
    rst_o_pls: out std_logic
93 
  );
94 
end component;
95 
 
96 
--   signal dlm_rec0              : std_logic_vector(3 downto 0);
97 
--   signal dlm_rec_valid0        : std_logic;
98 
--
99 
--   signal dlm_rec1              : std_logic_vector(3 downto 0);
100 
--   signal dlm_rec_valid1        : std_logic;
101 
 
102 
 
103 
 
104 
------------- COMPONENT Declaration: v6_pcie_v1_3 x4 ------
105 
 component v6_pcie_v1_3
106 
   generic (
107 
         PL_FAST_TRAIN  : boolean
108 
         );
109 
   port (
110 
    ---------------------------------------------------------
111 
    -- 1. PCI Express (pci_exp) Interface
112 
    ---------------------------------------------------------
113 
 
114 
    -- Tx
115 
    pci_exp_txn                    : out STD_LOGIC_VECTOR ( pcieLanes - 1 downto 0 );
116 
    pci_exp_txp                    : out STD_LOGIC_VECTOR ( pcieLanes - 1 downto 0 );
117 
 
118 
    -- Rx
119 
    pci_exp_rxn                    : in  STD_LOGIC_VECTOR ( pcieLanes - 1 downto 0 );
120 
    pci_exp_rxp                    : in  STD_LOGIC_VECTOR ( pcieLanes - 1 downto 0 );
121 
 
122 
    ---------------------------------------------------------
123 
    -- 2. Transaction (TRN) Interface
124 
    ---------------------------------------------------------
125 
 
126 
    -- Common
127 
    trn_clk                        : out STD_LOGIC;
128 
    trn_reset_n                    : out STD_LOGIC;
129 
    trn_lnk_up_n                   : out STD_LOGIC;
130 
 
131 
    -- Tx
132 
    trn_tbuf_av                    : out STD_LOGIC_vector (6-1 downto 0);
133 
    trn_tcfg_req_n                 : out STD_LOGIC;
134 
    trn_terr_drop_n                : out STD_LOGIC;
135 
    trn_tdst_rdy_n                 : out STD_LOGIC;
136 
    trn_td                         : in  STD_LOGIC_vector (64-1 downto 0);
137 
    trn_trem_n                     : in  STD_LOGIC;
138 
    trn_tsof_n                     : in  STD_LOGIC;
139 
    trn_teof_n                     : in  STD_LOGIC;
140 
    trn_tsrc_rdy_n                 : in  STD_LOGIC;
141 
    trn_tsrc_dsc_n                 : in  STD_LOGIC;
142 
    trn_terrfwd_n                  : in  STD_LOGIC;
143 
    trn_tcfg_gnt_n                 : in  STD_LOGIC;
144 
    trn_tstr_n                     : in  STD_LOGIC;
145 
 
146 
    -- Rx
147 
    trn_rd                         : out STD_LOGIC_vector (64-1 downto 0);
148 
    trn_rrem_n                     : out STD_LOGIC;
149 
    trn_rsof_n                     : out STD_LOGIC;
150 
    trn_reof_n                     : out STD_LOGIC;
151 
    trn_rsrc_rdy_n                 : out STD_LOGIC;
152 
    trn_rsrc_dsc_n                 : out STD_LOGIC;
153 
    trn_rerrfwd_n                  : out STD_LOGIC;
154 
    trn_rbar_hit_n                 : out STD_LOGIC_vector (7-1 downto 0);
155 
    trn_rdst_rdy_n                 : in  STD_LOGIC;
156 
    trn_rnp_ok_n                   : in  STD_LOGIC;
157 
 
158 
    -- Flow Control
159 
    trn_fc_cpld                    : out STD_LOGIC_vector (12-1 downto 0);
160 
    trn_fc_cplh                    : out STD_LOGIC_vector (8-1 downto 0);
161 
    trn_fc_npd                     : out STD_LOGIC_vector (12-1 downto 0);
162 
    trn_fc_nph                     : out STD_LOGIC_vector (8-1 downto 0);
163 
    trn_fc_pd                      : out STD_LOGIC_vector (12-1 downto 0);
164 
    trn_fc_ph                      : out STD_LOGIC_vector (8-1 downto 0);
165 
    trn_fc_sel                     : in  STD_LOGIC_vector (3-1 downto 0);
166 
 
167 
 
168 
    ---------------------------------------------------------
169 
    -- 3. Configuration (CFG) Interface
170 
    ---------------------------------------------------------
171 
 
172 
    cfg_do                         : out STD_LOGIC_vector (32-1 downto 0);
173 
    cfg_rd_wr_done_n               : out STD_LOGIC;
174 
    cfg_di                         : in  STD_LOGIC_vector (32-1 downto 0);
175 
    cfg_byte_en_n                  : in  STD_LOGIC_vector (4-1 downto 0);
176 
    cfg_dwaddr                     : in  STD_LOGIC_vector (10-1 downto 0);
177 
    cfg_wr_en_n                    : in  STD_LOGIC;
178 
    cfg_rd_en_n                    : in  STD_LOGIC;
179 
 
180 
    cfg_err_cor_n                  : in  STD_LOGIC;
181 
    cfg_err_ur_n                   : in  STD_LOGIC;
182 
    cfg_err_ecrc_n                 : in  STD_LOGIC;
183 
    cfg_err_cpl_timeout_n          : in  STD_LOGIC;
184 
    cfg_err_cpl_abort_n            : in  STD_LOGIC;
185 
    cfg_err_cpl_unexpect_n         : in  STD_LOGIC;
186 
    cfg_err_posted_n               : in  STD_LOGIC;
187 
    cfg_err_locked_n               : in  STD_LOGIC;
188 
    cfg_err_tlp_cpl_header         : in  STD_LOGIC_vector (48-1 downto 0);
189 
    cfg_err_cpl_rdy_n              : out STD_LOGIC;
190 
    cfg_interrupt_n                : in  STD_LOGIC;
191 
    cfg_interrupt_rdy_n            : out STD_LOGIC;
192 
    cfg_interrupt_assert_n         : in  STD_LOGIC;
193 
    cfg_interrupt_di               : in  STD_LOGIC_vector (8-1 downto 0);
194 
    cfg_interrupt_do               : out STD_LOGIC_vector (8-1 downto 0);
195 
    cfg_interrupt_mmenable         : out STD_LOGIC_vector (3-1 downto 0);
196 
    cfg_interrupt_msienable        : out STD_LOGIC;
197 
    cfg_interrupt_msixenable       : out STD_LOGIC;
198 
    cfg_interrupt_msixfm           : out STD_LOGIC;
199 
    cfg_turnoff_ok_n               : in  STD_LOGIC;
200 
    cfg_to_turnoff_n               : out STD_LOGIC;
201 
    cfg_trn_pending_n              : in  STD_LOGIC;
202 
    cfg_pm_wake_n                  : in  STD_LOGIC;
203 
    cfg_bus_number                 : out STD_LOGIC_vector (8-1 downto 0);
204 
    cfg_device_number              : out STD_LOGIC_vector (5-1 downto 0);
205 
    cfg_function_number            : out STD_LOGIC_vector (3-1 downto 0);
206 
    cfg_status                     : out STD_LOGIC_vector (16-1 downto 0);
207 
    cfg_command                    : out STD_LOGIC_vector (16-1 downto 0);
208 
    cfg_dstatus                    : out STD_LOGIC_vector (16-1 downto 0);
209 
    cfg_dcommand                   : out STD_LOGIC_vector (16-1 downto 0);
210 
    cfg_lstatus                    : out STD_LOGIC_vector (16-1 downto 0);
211 
    cfg_lcommand                   : out STD_LOGIC_vector (16-1 downto 0);
212 
    cfg_dcommand2                  : out STD_LOGIC_vector (16-1 downto 0);
213 
    cfg_pcie_link_state_n          : out STD_LOGIC_vector (3-1 downto 0);
214 
    cfg_dsn                        : in  STD_LOGIC_vector (64-1 downto 0);
215 
    cfg_pmcsr_pme_en               : out STD_LOGIC;
216 
    cfg_pmcsr_pme_status           : out STD_LOGIC;
217 
    cfg_pmcsr_powerstate           : out STD_LOGIC_vector (2-1 downto 0);
218 
    lnk_clk_en                     : out STD_LOGIC;
219 
 
220 
 
221 
    ---------------------------------------------------------
222 
    -- 4. Physical Layer Control and Status (PL) Interface
223 
    ---------------------------------------------------------
224 
 
225 
    pl_initial_link_width          : out STD_LOGIC_vector (3-1 downto 0);
226 
    pl_lane_reversal_mode          : out STD_LOGIC_vector (2-1 downto 0);
227 
    pl_link_gen2_capable           : out STD_LOGIC;
228 
    pl_link_partner_gen2_supported : out STD_LOGIC;
229 
    pl_link_upcfg_capable          : out STD_LOGIC;
230 
    pl_ltssm_state                 : out STD_LOGIC_vector (6-1 downto 0);
231 
    pl_received_hot_rst            : out STD_LOGIC;
232 
    pl_sel_link_rate               : out STD_LOGIC;
233 
    pl_sel_link_width              : out STD_LOGIC_vector (2-1 downto 0);
234 
    pl_directed_link_auton         : in  STD_LOGIC;
235 
    pl_directed_link_change        : in  STD_LOGIC_vector (2-1 downto 0);
236 
    pl_directed_link_speed         : in  STD_LOGIC;
237 
    pl_directed_link_width         : in  STD_LOGIC_vector (2-1 downto 0);
238 
    pl_upstream_prefer_deemph      : in  STD_LOGIC;
239 
 
240 
 
241 
    ---------------------------------------------------------
242 
    -- 5. System  (SYS) Interface
243 
    ---------------------------------------------------------
244 
 
245 
    sys_clk                        : in  STD_LOGIC;
246 
    sys_reset_n                    : in  STD_LOGIC
247 
  );
248 
 end component;
249 
 
250 
 
251 
 
252 
------------- COMPONENT Declaration: v6_pcie_v1_3 x8 ------
253 
 component v6_pcie_v1_3x8
254 
   generic (
255 
         PL_FAST_TRAIN  : boolean
256 
         );
257 
   port (
258 
    ---------------------------------------------------------
259 
    -- 1. PCI Express (pci_exp) Interface
260 
    ---------------------------------------------------------
261 
 
262 
    -- Tx
263 
    pci_exp_txn                    : out STD_LOGIC_VECTOR ( pcieLanes - 1 downto 0 );
264 
    pci_exp_txp                    : out STD_LOGIC_VECTOR ( pcieLanes - 1 downto 0 );
265 
 
266 
    -- Rx
267 
    pci_exp_rxn                    : in  STD_LOGIC_VECTOR ( pcieLanes - 1 downto 0 );
268 
    pci_exp_rxp                    : in  STD_LOGIC_VECTOR ( pcieLanes - 1 downto 0 );
269 
 
270 
    ---------------------------------------------------------
271 
    -- 2. Transaction (TRN) Interface
272 
    ---------------------------------------------------------
273 
 
274 
    -- Common
275 
    trn_clk                        : out STD_LOGIC;
276 
    trn_reset_n                    : out STD_LOGIC;
277 
    trn_lnk_up_n                   : out STD_LOGIC;
278 
 
279 
    -- Tx
280 
    trn_tbuf_av                    : out STD_LOGIC_vector (6-1 downto 0);
281 
    trn_tcfg_req_n                 : out STD_LOGIC;
282 
    trn_terr_drop_n                : out STD_LOGIC;
283 
    trn_tdst_rdy_n                 : out STD_LOGIC;
284 
    trn_td                         : in  STD_LOGIC_vector (64-1 downto 0);
285 
    trn_trem_n                     : in  STD_LOGIC;
286 
    trn_tsof_n                     : in  STD_LOGIC;
287 
    trn_teof_n                     : in  STD_LOGIC;
288 
    trn_tsrc_rdy_n                 : in  STD_LOGIC;
289 
    trn_tsrc_dsc_n                 : in  STD_LOGIC;
290 
    trn_terrfwd_n                  : in  STD_LOGIC;
291 
    trn_tcfg_gnt_n                 : in  STD_LOGIC;
292 
    trn_tstr_n                     : in  STD_LOGIC;
293 
 
294 
    -- Rx
295 
    trn_rd                         : out STD_LOGIC_vector (64-1 downto 0);
296 
    trn_rrem_n                     : out STD_LOGIC;
297 
    trn_rsof_n                     : out STD_LOGIC;
298 
    trn_reof_n                     : out STD_LOGIC;
299 
    trn_rsrc_rdy_n                 : out STD_LOGIC;
300 
    trn_rsrc_dsc_n                 : out STD_LOGIC;
301 
    trn_rerrfwd_n                  : out STD_LOGIC;
302 
    trn_rbar_hit_n                 : out STD_LOGIC_vector (7-1 downto 0);
303 
    trn_rdst_rdy_n                 : in  STD_LOGIC;
304 
    trn_rnp_ok_n                   : in  STD_LOGIC;
305 
 
306 
    -- Flow Control
307 
    trn_fc_cpld                    : out STD_LOGIC_vector (12-1 downto 0);
308 
    trn_fc_cplh                    : out STD_LOGIC_vector (8-1 downto 0);
309 
    trn_fc_npd                     : out STD_LOGIC_vector (12-1 downto 0);
310 
    trn_fc_nph                     : out STD_LOGIC_vector (8-1 downto 0);
311 
    trn_fc_pd                      : out STD_LOGIC_vector (12-1 downto 0);
312 
    trn_fc_ph                      : out STD_LOGIC_vector (8-1 downto 0);
313 
    trn_fc_sel                     : in  STD_LOGIC_vector (3-1 downto 0);
314 
 
315 
 
316 
    ---------------------------------------------------------
317 
    -- 3. Configuration (CFG) Interface
318 
    ---------------------------------------------------------
319 
 
320 
    cfg_do                         : out STD_LOGIC_vector (32-1 downto 0);
321 
    cfg_rd_wr_done_n               : out STD_LOGIC;
322 
    cfg_di                         : in  STD_LOGIC_vector (32-1 downto 0);
323 
    cfg_byte_en_n                  : in  STD_LOGIC_vector (4-1 downto 0);
324 
    cfg_dwaddr                     : in  STD_LOGIC_vector (10-1 downto 0);
325 
    cfg_wr_en_n                    : in  STD_LOGIC;
326 
    cfg_rd_en_n                    : in  STD_LOGIC;
327 
 
328 
    cfg_err_cor_n                  : in  STD_LOGIC;
329 
    cfg_err_ur_n                   : in  STD_LOGIC;
330 
    cfg_err_ecrc_n                 : in  STD_LOGIC;
331 
    cfg_err_cpl_timeout_n          : in  STD_LOGIC;
332 
    cfg_err_cpl_abort_n            : in  STD_LOGIC;
333 
    cfg_err_cpl_unexpect_n         : in  STD_LOGIC;
334 
    cfg_err_posted_n               : in  STD_LOGIC;
335 
    cfg_err_locked_n               : in  STD_LOGIC;
336 
    cfg_err_tlp_cpl_header         : in  STD_LOGIC_vector (48-1 downto 0);
337 
    cfg_err_cpl_rdy_n              : out STD_LOGIC;
338 
    cfg_interrupt_n                : in  STD_LOGIC;
339 
    cfg_interrupt_rdy_n            : out STD_LOGIC;
340 
    cfg_interrupt_assert_n         : in  STD_LOGIC;
341 
    cfg_interrupt_di               : in  STD_LOGIC_vector (8-1 downto 0);
342 
    cfg_interrupt_do               : out STD_LOGIC_vector (8-1 downto 0);
343 
    cfg_interrupt_mmenable         : out STD_LOGIC_vector (3-1 downto 0);
344 
    cfg_interrupt_msienable        : out STD_LOGIC;
345 
    cfg_interrupt_msixenable       : out STD_LOGIC;
346 
    cfg_interrupt_msixfm           : out STD_LOGIC;
347 
    cfg_turnoff_ok_n               : in  STD_LOGIC;
348 
    cfg_to_turnoff_n               : out STD_LOGIC;
349 
    cfg_trn_pending_n              : in  STD_LOGIC;
350 
    cfg_pm_wake_n                  : in  STD_LOGIC;
351 
    cfg_bus_number                 : out STD_LOGIC_vector (8-1 downto 0);
352 
    cfg_device_number              : out STD_LOGIC_vector (5-1 downto 0);
353 
    cfg_function_number            : out STD_LOGIC_vector (3-1 downto 0);
354 
    cfg_status                     : out STD_LOGIC_vector (16-1 downto 0);
355 
    cfg_command                    : out STD_LOGIC_vector (16-1 downto 0);
356 
    cfg_dstatus                    : out STD_LOGIC_vector (16-1 downto 0);
357 
    cfg_dcommand                   : out STD_LOGIC_vector (16-1 downto 0);
358 
    cfg_lstatus                    : out STD_LOGIC_vector (16-1 downto 0);
359 
    cfg_lcommand                   : out STD_LOGIC_vector (16-1 downto 0);
360 
    cfg_dcommand2                  : out STD_LOGIC_vector (16-1 downto 0);
361 
    cfg_pcie_link_state_n          : out STD_LOGIC_vector (3-1 downto 0);
362 
    cfg_dsn                        : in  STD_LOGIC_vector (64-1 downto 0);
363 
    cfg_pmcsr_pme_en               : out STD_LOGIC;
364 
    cfg_pmcsr_pme_status           : out STD_LOGIC;
365 
    cfg_pmcsr_powerstate           : out STD_LOGIC_vector (2-1 downto 0);
366 
    lnk_clk_en                     : out STD_LOGIC;
367 
 
368 
 
369 
    ---------------------------------------------------------
370 
    -- 4. Physical Layer Control and Status (PL) Interface
371 
    ---------------------------------------------------------
372 
 
373 
    pl_initial_link_width          : out STD_LOGIC_vector (3-1 downto 0);
374 
    pl_lane_reversal_mode          : out STD_LOGIC_vector (2-1 downto 0);
375 
    pl_link_gen2_capable           : out STD_LOGIC;
376 
    pl_link_partner_gen2_supported : out STD_LOGIC;
377 
    pl_link_upcfg_capable          : out STD_LOGIC;
378 
    pl_ltssm_state                 : out STD_LOGIC_vector (6-1 downto 0);
379 
    pl_received_hot_rst            : out STD_LOGIC;
380 
    pl_sel_link_rate               : out STD_LOGIC;
381 
    pl_sel_link_width              : out STD_LOGIC_vector (2-1 downto 0);
382 
    pl_directed_link_auton         : in  STD_LOGIC;
383 
    pl_directed_link_change        : in  STD_LOGIC_vector (2-1 downto 0);
384 
    pl_directed_link_speed         : in  STD_LOGIC;
385 
    pl_directed_link_width         : in  STD_LOGIC_vector (2-1 downto 0);
386 
    pl_upstream_prefer_deemph      : in  STD_LOGIC;
387 
 
388 
 
389 
    ---------------------------------------------------------
390 
    -- 5. System  (SYS) Interface
391 
    ---------------------------------------------------------
392 
 
393 
    sys_clk                        : in  STD_LOGIC;
394 
    sys_reset_n                    : in  STD_LOGIC
395 
  );
396 
 end component;
397 
 
398 
 
399 
--
400 
--   signal ddr2_sys_clk_i               : std_logic;
401 
--   signal idelay_value_counter         : std_logic_vector(6-1 downto 0);
402 
--   signal idelay_calibrate_successful  : std_logic;
403 
   signal fifo_reset_done              : std_logic;
404 
--   signal failure_read                 : std_logic;
405 
   signal pio_reading_status           : std_logic;
406 
 
407 
 
408 
-- -----------------------------------------------------------------------
409 
--  DDR SDRAM control module
410 
--   1 or 2 DDR RAM modules are used
411 
--
412 
   COMPONENT bram_DDRs_Control
413 
   GENERIC (
414 
             C_ASYNFIFO_WIDTH  :  integer ;
415 
             P_SIMULATION      :  boolean
416 
            );
417 
   PORT (
418 
 
419 
 
420 
      -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
421 
      DDR_wr_sof               : IN    std_logic;
422 
      DDR_wr_eof               : IN    std_logic;
423 
      DDR_wr_v                 : IN    std_logic;
424 
      DDR_wr_FA                : IN    std_logic;
425 
      DDR_wr_Shift             : IN    std_logic;
426 
      DDR_wr_Mask              : IN    std_logic_vector(2-1 downto 0);
427 
      DDR_wr_din               : IN    std_logic_vector(C_DBUS_WIDTH-1 downto 0);
428 
      DDR_wr_full              : OUT   std_logic;
429 
 
430 
      DDR_rdc_sof              : IN    std_logic;
431 
      DDR_rdc_eof              : IN    std_logic;
432 
      DDR_rdc_v                : IN    std_logic;
433 
      DDR_rdc_FA               : IN    std_logic;
434 
      DDR_rdc_Shift            : IN    std_logic;
435 
      DDR_rdc_din              : IN    std_logic_vector(C_DBUS_WIDTH-1 downto 0);
436 
      DDR_rdc_full             : OUT   std_logic;
437 
 
438 
      -- DDR payload FIFO Read Port
439 
      DDR_FIFO_RdEn            : IN    std_logic;
440 
      DDR_FIFO_Empty           : OUT   std_logic;
441 
      DDR_FIFO_RdQout          : OUT   std_logic_vector(C_DBUS_WIDTH-1 downto 0);
442 
--      DDR_rdD_sof              : OUT   std_logic;
443 
--      DDR_rdD_eof              : OUT   std_logic;
444 
--      DDR_rdDout_V             : OUT   std_logic;
445 
--      DDR_rdDout               : OUT   std_logic_vector(C_DBUS_WIDTH-1 downto 0);
446 
 
447 
      -- Common interface
448 
      DDR_Ready                : OUT   std_logic;
449 
      DDR_Blinker              : OUT   std_logic;
450 
      mem_clk                  : IN    std_logic;
451 
      trn_clk                  : IN    std_logic;
452 
      trn_reset_n              : IN    std_logic
453 
    );
454 
   END COMPONENT;
455 
 
456 
   signal    DDR_wr_sof               :  std_logic;
457 
   signal    DDR_wr_eof               :  std_logic;
458 
   signal    DDR_wr_v                 :  std_logic;
459 
   signal    DDR_wr_FA                :  std_logic;
460 
   signal    DDR_wr_Shift             :  std_logic;
461 
   signal    DDR_wr_Mask              :  std_logic_vector(2-1 downto 0);
462 
   signal    DDR_wr_din               :  std_logic_vector(C_DBUS_WIDTH-1 downto 0);
463 
   signal    DDR_wr_full              :  std_logic;
464 
 
465 
   signal    DDR_rdc_sof              :  std_logic;
466 
   signal    DDR_rdc_eof              :  std_logic;
467 
   signal    DDR_rdc_v                :  std_logic;
468 
   signal    DDR_rdc_FA               :  std_logic;
469 
   signal    DDR_rdc_Shift            :  std_logic;
470 
   signal    DDR_rdc_din              :  std_logic_vector(C_DBUS_WIDTH-1 downto 0);
471 
   signal    DDR_rdc_full             :  std_logic;
472 
 
473 
   signal    DDR_FIFO_RdEn            :  std_logic;
474 
   signal    DDR_FIFO_Empty           :  std_logic;
475 
   signal    DDR_FIFO_RdQout          :  std_logic_vector(C_DBUS_WIDTH-1 downto 0);
476 
 
477 
--   signal    DDR_rdD_sof              :  std_logic;
478 
--   signal    DDR_rdD_eof              :  std_logic;
479 
--   signal    DDR_rdDout_V             :  std_logic;
480 
--   signal    DDR_rdDout               :  std_logic_vector(C_DBUS_WIDTH-1 downto 0);
481 
 
482 
   signal    DDR_Ready                :  std_logic;
483 
   signal    DDR_Blinker              :  std_logic;
484 
 
485 
--   signal    mem_clk                  :  std_logic;
486 
 
487 
   -- -----------------------------------------------------------------------
488 
   -- FIFO module
489 
   --      16K x 8B
490 
   component eb_wrapper
491 
     port (
492 
           wr_clk      : IN  std_logic;
493 
           wr_en       : IN  std_logic;
494 
           din         : IN  std_logic_VECTOR(72-1 downto 0);
495 
           pfull       : OUT std_logic;
496 
           full        : OUT std_logic;
497 
 
498 
           rd_clk      : IN  std_logic;
499 
           rd_en       : IN  std_logic;
500 
           dout        : OUT std_logic_VECTOR(72-1 downto 0);
501 
           pempty      : OUT std_logic;
502 
           empty       : OUT std_logic;
503 
 
504 
           data_count  : OUT std_logic_VECTOR(C_EMU_FIFO_DC_WIDTH-1 downto 0);
505 
           rst         : IN  std_logic
506 
           );
507 
   end component;
508 
 
509 
   signal  eb_wclk            :  std_logic;
510 
   signal  eb_we              :  std_logic;
511 
   signal  eb_wsof            :  std_logic;
512 
   signal  eb_weof            :  std_logic;
513 
   signal  eb_din             :  std_logic_VECTOR(72-1 downto 0);
514 
   signal  eb_pfull           :  std_logic;
515 
   signal  eb_full            :  std_logic;
516 
   signal  eb_rclk            :  std_logic;
517 
   signal  eb_re              :  std_logic;
518 
   signal  eb_dout            :  std_logic_VECTOR(72-1 downto 0);
519 
   signal  eb_pempty          :  std_logic;
520 
   signal  eb_empty           :  std_logic;
521 
   signal  eb_rst             :  std_logic;
522 
   signal  eb_FIFO_Status     :  std_logic_VECTOR(C_DBUS_WIDTH-1 downto 0);
523 
   signal  eb_data_count      :  std_logic_vector(C_FIFO_DC_WIDTH downto 0);
524 
   signal  pio_read_status    :  std_logic;
525 
   signal  eb_FIFO_ow         :  std_logic;
526 
 
527 
   signal  eb_we_up           :  std_logic;
528 
   signal  eb_din_up          :  std_logic_VECTOR(72-1 downto 0);
529 
 
530 
 
531 
   signal  tab_sel            : STD_LOGIC;
532 
   signal  tab_we             : STD_LOGIC_VECTOR (2-1 downto 0);
533 
   signal  tab_wa             : STD_LOGIC_VECTOR (12-1 downto 0);
534 
   signal  tab_wd             : STD_LOGIC_VECTOR (C_DBUS_WIDTH-1 downto 0);
535 
 
536 
   signal  dg_running         : STD_LOGIC;
537 
   signal  dg_mask            : STD_LOGIC;
538 
   signal  dg_rst             : STD_LOGIC;
539 
 
540 
   -- debug signal
541 
   signal  dg_debug_led       : STD_LOGIC;
542 
 
543 
   -- Protocol Interface module
544 
   COMPONENT protocol_IF
545 
   PORT (
546 
           -- DAQ Tx
547 
           data2send_start          : OUT   std_logic;
548 
           data2send_end            : OUT   std_logic;
549 
           data2send                : OUT   std_logic_vector(64-1 downto 0);
550 
           crc_error_send           : OUT   std_logic;
551 
           data2send_stop           : IN    std_logic;
552 
 
553 
           -- DAQ Rx
554 
           data_rec_start           : IN    std_logic;
555 
           data_rec_end             : IN    std_logic;
556 
           data_rec                 : IN    std_logic_vector(64-1 downto 0);
557 
           crc_error_rec            : IN    std_logic;
558 
           data_rec_stop            : OUT   std_logic;
559 
 
560 
           -- CTL Tx
561 
           ctrl2send_start          : OUT   std_logic;
562 
           ctrl2send_end            : OUT   std_logic;
563 
           ctrl2send                : OUT   std_logic_vector(16-1 downto 0);
564 
           ctrl2send_stop           : IN    std_logic;
565 
 
566 
           -- CTL Rx
567 
           ctrl_rec_start           : IN    std_logic;
568 
           ctrl_rec_end             : IN    std_logic;
569 
           ctrl_rec                 : IN    std_logic_vector(16-1 downto 0);
570 
           ctrl_rec_stop            : OUT   std_logic;
571 
 
572 
           -- DLM Tx
573 
           dlm2send_va              : OUT   std_logic;
574 
           dlm2send_type            : OUT   std_logic_vector(4-1 downto 0);
575 
 
576 
           -- DLM Rx
577 
           dlm_rec_va               : IN    std_logic;
578 
           dlm_rec_type             : IN    std_logic_vector(4-1 downto 0);
579 
 
580 
           -- Common signals
581 
           link_tx_clk              : IN    std_logic;
582 
           link_rx_clk              : IN    std_logic;
583 
           link_active              : IN    std_logic_vector(2-1 downto 0);
584 
           protocol_clk             : OUT   std_logic;
585 
           protocol_res_n           : OUT   std_logic;
586 
 
587 
           -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
588 
 
589 
           -- Fabric side: DAQ Rx
590 
           daq_rv                   : IN    std_logic;
591 
           daq_rsof                 : IN    std_logic;
592 
           daq_reof                 : IN    std_logic;
593 
           daq_rd                   : IN    std_logic_vector(C_DBUS_WIDTH-1 downto 0);
594 
           daq_rstop                : OUT   std_logic;
595 
 
596 
           -- Fabric side: DAQ Tx
597 
           daq_tv                   : OUT   std_logic;
598 
           daq_tsof                 : OUT   std_logic;
599 
           daq_teof                 : OUT   std_logic;
600 
           daq_td                   : OUT   std_logic_vector(C_DBUS_WIDTH-1 downto 0);
601 
           daq_tstop                : IN    std_logic;
602 
 
603 
           -- Fabric side: DLM Rx
604 
           dlm_rv                   : IN    std_logic;
605 
           dlm_rd                   : IN    std_logic_vector(C_DBUS_WIDTH/2-1 downto 0);
606 
 
607 
           -- Fabric side: DLM Tx
608 
           dlm_tv                   : OUT   std_logic;
609 
           dlm_td                   : OUT   std_logic_vector(C_DBUS_WIDTH/2-1 downto 0);
610 
 
611 
           -- Fabric side: CTL Rx
612 
           ctl_rv                   : IN    std_logic;
613 
           ctl_rd                   : IN    std_logic_vector(C_DBUS_WIDTH/2-1 downto 0);
614 
           ctl_rstop                : OUT   std_logic;
615 
 
616 
           -- Fabric side: CTL Tx
617 
           ctl_ttake                : IN    std_logic;
618 
           ctl_tv                   : OUT   std_logic;
619 
           ctl_td                   : OUT   std_logic_vector(C_DBUS_WIDTH/2-1 downto 0);
620 
           ctl_tstop                : IN    std_logic;
621 
 
622 
           ctl_reset                : IN    std_logic;
623 
           ctl_status               : OUT   std_logic_vector(C_DBUS_WIDTH/2-1 downto 0);
624 
 
625 
           -- Interrupter triggers
626 
           DAQ_irq                  : OUT   std_logic;
627 
           CTL_irq                  : OUT   std_logic;
628 
           DLM_irq                  : OUT   std_logic;
629 
 
630 
           -- Data generator table write port
631 
           tab_sel                  : IN    STD_LOGIC;
632 
           tab_we                   : IN    STD_LOGIC_VECTOR (2-1 downto 0);
633 
           tab_wa                   : IN    STD_LOGIC_VECTOR (12-1 downto 0);
634 
           tab_wd                   : IN    STD_LOGIC_VECTOR (64-1 downto 0);
635 
 
636 
           -- DG control/status signal
637 
           dg_running               : OUT   STD_LOGIC;
638 
           dg_mask                  : IN    STD_LOGIC;
639 
           dg_rst                   : IN    STD_LOGIC;
640 
 
641 
           -- DG debug signal
642 
           daq_start_led            : OUT   STD_LOGIC;
643 
 
644 
           -- Fabric side: Common signals
645 
           trn_clk                  : IN    std_logic;
646 
           protocol_link_act        : OUT   std_logic_vector(2-1 downto 0);
647 
           protocol_rst             : IN    std_logic
648 
    );
649 
   END COMPONENT;
650 
 
651 
   -- DAQ Tx
652 
   signal  data2send_start          : std_logic;
653 
   signal  data2send_end            : std_logic;
654 
   signal  data2send                : std_logic_vector(64-1 downto 0);
655 
   signal  crc_error_send           : std_logic;
656 
   signal  data2send_stop           : std_logic
657 
                                    := '0';
658 
 
659 
   -- DAQ Rx
660 
   signal  data_rec_start           : std_logic;
661 
   signal  data_rec_end             : std_logic;
662 
   signal  data_rec                 : std_logic_vector(64-1 downto 0);
663 
   signal  crc_error_rec            : std_logic;
664 
   signal  data_rec_stop            : std_logic;
665 
 
666 
   -- CTL Tx
667 
   signal  ctrl2send_start          : std_logic;
668 
   signal  ctrl2send_end            : std_logic;
669 
   signal  ctrl2send                : std_logic_vector(16-1 downto 0);
670 
   signal  ctrl2send_stop           : std_logic;
671 
 
672 
   -- CTL Rx
673 
   signal  ctrl_rec_start           : std_logic;
674 
   signal  ctrl_rec_end             : std_logic;
675 
   signal  ctrl_rec                 : std_logic_vector(16-1 downto 0);
676 
   signal  ctrl_rec_stop            : std_logic;
677 
 
678 
   -- DLM Tx
679 
   signal  dlm2send_va              : std_logic;
680 
   signal  dlm2send_type            : std_logic_vector(4-1 downto 0);
681 
 
682 
   -- DLM Rx
683 
   signal  dlm_rec_va               : std_logic;
684 
   signal  dlm_rec_type             : std_logic_vector(4-1 downto 0);
685 
 
686 
 
687 
   -- Common signals
688 
   signal  link_rx_clk              : std_logic;
689 
   signal  link_tx_clk              : std_logic;
690 
   signal  link_active              : std_logic_vector(2-1 downto 0);
691 
   signal  protocol_clk             : std_logic;
692 
   signal  protocol_res_n           : std_logic;
693 
 
694 
 
695 
   -- Fabric side: DAQ Rx
696 
   signal  daq_rv                   : std_logic;
697 
   signal  daq_rsof                 : std_logic;
698 
   signal  daq_reof                 : std_logic;
699 
   signal  daq_rd                   : std_logic_vector(C_DBUS_WIDTH-1 downto 0);
700 
   signal  daq_rstop                : std_logic;
701 
 
702 
   -- Fabric side: DAQ Tx
703 
   signal  daq_tv                   : std_logic;
704 
   signal  daq_tsof                 : std_logic;
705 
   signal  daq_teof                 : std_logic;
706 
   signal  daq_td                   : std_logic_vector(C_DBUS_WIDTH-1 downto 0);
707 
   signal  daq_tstop                : std_logic;
708 
 
709 
   -- Fabric side: DLM Rx
710 
   signal  dlm_rv                   : std_logic;
711 
   signal  dlm_rd                   : std_logic_vector(C_DBUS_WIDTH/2-1 downto 0);
712 
 
713 
   -- Fabric side: DLM Tx
714 
   signal  dlm_tv                   : std_logic;
715 
   signal  dlm_td                   : std_logic_vector(C_DBUS_WIDTH/2-1 downto 0);
716 
 
717 
   -- Fabric side: CTL Rx
718 
   signal  ctl_rv                   : std_logic;
719 
   signal  ctl_rd                   : std_logic_vector(C_DBUS_WIDTH/2-1 downto 0);
720 
   signal  ctl_rstop                : std_logic;
721 
 
722 
   -- Fabric side: CTL Tx
723 
   signal  ctl_ttake                : std_logic;
724 
   signal  ctl_tv                   : std_logic;
725 
   signal  ctl_td                   : std_logic_vector(C_DBUS_WIDTH/2-1 downto 0);
726 
   signal  ctl_tstop                : std_logic;
727 
 
728 
   signal  ctl_reset                : std_logic;
729 
   signal  ctl_status               : std_logic_vector(C_DBUS_WIDTH/2-1 downto 0);
730 
 
731 
   -- Interrupter triggers
732 
   signal  DAQ_irq                  : std_logic;
733 
   signal  CTL_irq                  : std_logic;
734 
   signal  DLM_irq                  : std_logic;
735 
 
736 
   -- Fabric side: Common signals
737 
   signal  protocol_link_act        : std_logic_vector(2-1 downto 0);
738 
   signal  protocol_rst             : std_logic;
739 
 
740 
 
741 
   -- Pseudo link module, to be replaced by the real optical link
742 
   COMPONENT pseudo_protocol_module
743 
   PORT (
744 
         -- DAQ Tx
745 
         data2send_start          : IN    std_logic;
746 
         data2send_end            : IN    std_logic;
747 
         data2send                : IN    std_logic_vector(64-1 downto 0);
748 
         crc_error_send           : IN    std_logic;
749 
         data2send_stop           : OUT   std_logic;
750 
 
751 
         -- DAQ Rx
752 
         data_rec_start           : OUT   std_logic;
753 
         data_rec_end             : OUT   std_logic;
754 
         data_rec                 : OUT   std_logic_vector(64-1 downto 0);
755 
         crc_error_rec            : OUT   std_logic;
756 
         data_rec_stop            : IN    std_logic;
757 
 
758 
         -- CTL Tx
759 
         ctrl2send_start          : IN    std_logic;
760 
         ctrl2send_end            : IN    std_logic;
761 
         ctrl2send                : IN    std_logic_vector(16-1 downto 0);
762 
         ctrl2send_stop           : OUT   std_logic;
763 
 
764 
         -- CTL Rx
765 
         ctrl_rec_start           : OUT   std_logic;
766 
         ctrl_rec_end             : OUT   std_logic;
767 
         ctrl_rec                 : OUT   std_logic_vector(16-1 downto 0);
768 
         ctrl_rec_stop            : IN    std_logic;
769 
 
770 
         -- DLM Tx
771 
         dlm2send_va              : IN    std_logic;
772 
         dlm2send_type            : IN    std_logic_vector(4-1 downto 0);
773 
 
774 
         -- DLM Rx
775 
         dlm_rec_va               : OUT   std_logic;
776 
         dlm_rec_type             : OUT   std_logic_vector(4-1 downto 0);
777 
 
778 
         -- dummy pin input
779 
         dummy_pin_in             : IN    std_logic_vector(3-1 downto 0);
780 
 
781 
         -- Common interface
782 
         link_tx_clk              : OUT   std_logic;
783 
         link_rx_clk              : OUT   std_logic;
784 
         link_active              : OUT   std_logic_vector(2-1 downto 0);
785 
         clk                      : IN    std_logic;
786 
         res_n                    : IN    std_logic
787 
    );
788 
   END COMPONENT;
789 
 
790 
 
791 
   signal  Link_Buf_full             : std_logic;
792 
 
793 
 
794 
------------- COMPONENT Declaration: tlpControl   ------
795 
--
796 
 component tlpControl
797 
   port (
798 
        --  Test pin, emulating DDR data flow discontinuity
799 
        mbuf_UserFull                : IN  std_logic;
800 
        trn_Blinker                  : OUT std_logic;
801 
 
802 
        -- DCB protocol interface
803 
        protocol_link_act            : IN  std_logic_vector(2-1 downto 0);
804 
        protocol_rst                 : OUT std_logic;
805 
 
806 
        -- Interrupter triggers
807 
        DAQ_irq                      : IN  std_logic;
808 
        CTL_irq                      : IN  std_logic;
809 
        DLM_irq                      : IN  std_logic;
810 
 
811 
        -- Fabric side: CTL Rx
812 
        ctl_rv                       : OUT std_logic;
813 
        ctl_rd                       : OUT std_logic_vector(C_DBUS_WIDTH/2-1 downto 0);
814 
 
815 
        -- Fabric side: CTL Tx
816 
        ctl_ttake                    : OUT std_logic;
817 
        ctl_tv                       : IN  std_logic;
818 
        ctl_td                       : IN  std_logic_vector(C_DBUS_WIDTH/2-1 downto 0);
819 
        ctl_tstop                    : OUT std_logic;
820 
 
821 
        ctl_reset                    : OUT std_logic;
822 
        ctl_status                   : IN  std_logic_vector(C_DBUS_WIDTH/2-1 downto 0);
823 
 
824 
        -- Fabric side: DLM Rx
825 
        dlm_rv                       : OUT std_logic;
826 
        dlm_rd                       : OUT std_logic_vector(C_DBUS_WIDTH/2-1 downto 0);
827 
 
828 
        -- Fabric side: DLM Tx
829 
        dlm_tv                       : IN  std_logic;
830 
        dlm_td                       : IN  std_logic_vector(C_DBUS_WIDTH/2-1 downto 0);
831 
 
832 
        Link_Buf_full                : IN  std_logic;
833 
 
834 
        -- Event Buffer FIFO interface
835 
        eb_FIFO_we                   : OUT std_logic;
836 
        eb_FIFO_wsof                 : OUT std_logic;
837 
        eb_FIFO_weof                 : OUT std_logic;
838 
        eb_FIFO_din                  : OUT std_logic_vector(C_DBUS_WIDTH-1 downto 0);
839 
 
840 
        eb_FIFO_re                   : OUT std_logic;
841 
        eb_FIFO_empty                : IN  std_logic;
842 
        eb_FIFO_qout                 : IN  std_logic_vector(C_DBUS_WIDTH-1 downto 0);
843 
        eb_FIFO_data_count           : IN  std_logic_vector(C_FIFO_DC_WIDTH downto 0);
844 
 
845 
        eb_FIFO_ow                   : IN  std_logic;
846 
 
847 
        pio_reading_status           : OUT std_logic;
848 
        eb_FIFO_Status               : IN  std_logic_vector(C_DBUS_WIDTH-1 downto 0);
849 
        eb_FIFO_Rst                  : OUT std_logic;
850 
 
851 
        -- Debugging signals
852 
        DMA_us_Done                  : OUT std_logic;
853 
        DMA_us_Busy                  : OUT std_logic;
854 
        DMA_us_Busy_LED              : OUT std_logic;
855 
        DMA_ds_Done                  : OUT std_logic;
856 
        DMA_ds_Busy                  : OUT std_logic;
857 
        DMA_ds_Busy_LED              : OUT std_logic;
858 
 
859 
        -- DDR control interface
860 
        DDR_Ready                    : IN    std_logic;
861 
 
862 
        DDR_wr_sof                   : OUT   std_logic;
863 
        DDR_wr_eof                   : OUT   std_logic;
864 
        DDR_wr_v                     : OUT   std_logic;
865 
        DDR_wr_FA                    : OUT   std_logic;
866 
        DDR_wr_Shift                 : OUT   std_logic;
867 
        DDR_wr_Mask                  : OUT   std_logic_vector(2-1 downto 0);
868 
        DDR_wr_din                   : OUT   std_logic_vector(C_DBUS_WIDTH-1 downto 0);
869 
        DDR_wr_full                  : IN    std_logic;
870 
 
871 
        DDR_rdc_sof                  : OUT   std_logic;
872 
        DDR_rdc_eof                  : OUT   std_logic;
873 
        DDR_rdc_v                    : OUT   std_logic;
874 
        DDR_rdc_FA                   : OUT   std_logic;
875 
        DDR_rdc_Shift                : OUT   std_logic;
876 
        DDR_rdc_din                  : OUT   std_logic_vector(C_DBUS_WIDTH-1 downto 0);
877 
        DDR_rdc_full                 : IN    std_logic;
878 
 
879 
--        DDR_rdD_sof                  : IN    std_logic;
880 
--        DDR_rdD_eof                  : IN    std_logic;
881 
--        DDR_rdDout_V                 : IN    std_logic;
882 
--        DDR_rdDout                   : IN    std_logic_vector(C_DBUS_WIDTH-1 downto 0);
883 
 
884 
        -- DDR payload FIFO Read Port
885 
        DDR_FIFO_RdEn                : OUT std_logic;
886 
        DDR_FIFO_Empty               : IN  std_logic;
887 
        DDR_FIFO_RdQout              : IN  std_logic_vector(C_DBUS_WIDTH-1 downto 0);
888 
 
889 
        -- Data generator table write
890 
        tab_we                       : OUT std_logic_vector(2-1 downto 0);
891 
        tab_wa                       : OUT std_logic_vector(12-1 downto 0);
892 
        tab_wd                       : OUT std_logic_vector(C_DBUS_WIDTH-1 downto 0);
893 
 
894 
        -- Data generator control
895 
        DG_is_Running                : IN  std_logic;
896 
        DG_Reset                     : OUT std_logic;
897 
        DG_Mask                      : OUT std_logic;
898 
 
899 
        -- Transaction layer interface
900 
        trn_lnk_up_n                 : IN  std_logic;
901 
        trn_rsrc_dsc_n               : IN  std_logic;
902 
        trn_rnp_ok_n                 : OUT std_logic;
903 
        trn_tsrc_dsc_n               : OUT std_logic;
904 
        trn_tdst_dsc_n               : IN  std_logic;
905 
        trn_tbuf_av                  : IN  std_logic_vector(C_TBUF_AWIDTH-1 downto 0);
906 
        trn_terrfwd_n                : OUT std_logic;
907 
 
908 
        trn_clk                      : IN  std_logic;
909 
        trn_reset_n                  : IN  std_logic;
910 
        trn_rsrc_rdy_n               : IN  std_logic;
911 
        trn_tdst_rdy_n               : IN  std_logic;
912 
        trn_rsof_n                   : IN  std_logic;
913 
        trn_reof_n                   : IN  std_logic;
914 
        trn_rerrfwd_n                : IN  std_logic;
915 
        trn_rrem_n                   : IN  std_logic_vector(C_DBUS_WIDTH/8-1 downto 0);
916 
        trn_rd                       : IN  std_logic_vector(C_DBUS_WIDTH-1 downto 0);
917 
 
918 
        cfg_dcommand                 : IN  std_logic_vector(15 downto 0);
919 
        pcie_link_width              : IN  std_logic_vector( 5 downto 0);
920 
        localId                      : IN  std_logic_vector(15 downto 0);
921 
 
922 
        cfg_interrupt_n              : OUT std_logic;
923 
        cfg_interrupt_rdy_n          : IN  std_logic;
924 
        cfg_interrupt_mmenable       : IN  std_logic_vector(2 downto 0);
925 
        cfg_interrupt_msienable      : IN  std_logic;
926 
        cfg_interrupt_di             : OUT std_logic_vector(7 downto 0);
927 
        cfg_interrupt_do             : IN  std_logic_vector(7 downto 0);
928 
        cfg_interrupt_assert_n       : OUT std_logic;
929 
 
930 
        Format_Shower                : OUT   std_logic;
931 
 
932 
        trn_rbar_hit_n               : IN  std_logic_vector(6 downto 0);
933 
        trn_tsrc_rdy_n               : OUT std_logic;
934 
        trn_rdst_rdy_n               : OUT std_logic;
935 
        trn_tsof_n                   : OUT std_logic;
936 
        trn_teof_n                   : OUT std_logic;
937 
        trn_trem_n                   : OUT std_logic_vector(C_DBUS_WIDTH/8-1 downto 0);
938 
        trn_td                       : OUT std_logic_vector(C_DBUS_WIDTH-1 downto 0)
939 
        );
940 
 end component;
941 
 
942 
 signal   Format_Shower              : std_logic;
943 
 
944 
-- component BUFG is
945 
--   port(
946 
--        I : IN  std_logic;
947 
--        O : OUT std_logic
948 
--        );
949 
-- end component;
950 
--
951 
-- component IBUF is
952 
--   port(
953 
--        i : IN  std_logic;
954 
--        o : OUT std_logic
955 
--        );
956 
-- end component;
957 
--
958 
-- component IBUFDS is
959 
--   port(
960 
--        i  : IN  std_logic;
961 
--        ib : IN  std_logic;
962 
--        o  : OUT std_logic
963 
--        );
964 
-- end component;
965 
--
966 
-- component GT11CLK_MGT is
967 
--   port(
968 
--        mgtclkp     : IN  std_logic;
969 
--        mgtclkn     : IN  std_logic;
970 
--        synclk1out  : OUT std_logic;
971 
--        synclk2out  : OUT std_logic
972 
--        );
973 
-- end component;
974 
 
975 
 
976 
  -- TRN Layer signals
977 
 
978 
  signal trn_terr_drop_n                 : std_logic;
979 
  signal trn_tcfg_gnt_n                  : std_logic;
980 
  signal trn_tstr_n                      : std_logic;
981 
  signal trn_fc_cpld                     : STD_LOGIC_vector (12-1 downto 0);
982 
  signal trn_fc_cplh                     : STD_LOGIC_vector (8-1 downto 0);
983 
  signal trn_fc_npd                      : STD_LOGIC_vector (12-1 downto 0);
984 
  signal trn_fc_nph                      : STD_LOGIC_vector (8-1 downto 0);
985 
  signal trn_fc_pd                       : STD_LOGIC_vector (12-1 downto 0);
986 
  signal trn_fc_ph                       : STD_LOGIC_vector (8-1 downto 0);
987 
  signal trn_fc_sel                      : STD_LOGIC_vector (3-1 downto 0);
988 
 
989 
  signal cfg_interrupt_msixenable        : std_logic;
990 
  signal cfg_interrupt_msixfm            : std_logic;
991 
  signal cfg_dcommand2                   : std_logic_vector (16-1 downto 0);
992 
  signal trn_tcfg_req_n                  : std_logic;
993 
 
994 
 
995 
  signal  pl_initial_link_width          : STD_LOGIC_vector (3-1 downto 0);
996 
  signal  pl_lane_reversal_mode          : STD_LOGIC_vector (2-1 downto 0);
997 
  signal  pl_link_gen2_capable           : STD_LOGIC;
998 
  signal  pl_link_partner_gen2_supported : STD_LOGIC;
999 
  signal  pl_link_upcfg_capable          : STD_LOGIC;
1000 
  signal  pl_ltssm_state                 : STD_LOGIC_vector (6-1 downto 0);
1001 
  signal  pl_received_hot_rst            : STD_LOGIC;
1002 
  signal  pl_sel_link_rate               : STD_LOGIC;
1003 
  signal  pl_sel_link_width              : STD_LOGIC_vector (2-1 downto 0);
1004 
  signal  pl_directed_link_auton         : STD_LOGIC;
1005 
  signal  pl_directed_link_change        : STD_LOGIC_vector (2-1 downto 0);
1006 
  signal  pl_directed_link_speed         : STD_LOGIC;
1007 
  signal  pl_directed_link_width         : STD_LOGIC_vector (2-1 downto 0);
1008 
  signal  pl_upstream_prefer_deemph      : STD_LOGIC;
1009 
 
1010 
  signal  trn_reset_n_int1       : STD_LOGIC;
1011 
  signal  trn_lnk_up_n_int1      : STD_LOGIC;
1012 
 
1013 
 
1014 
 
1015 
  signal trn_clk                     : std_logic;
1016 
  signal trn_reset_n                 : std_logic;
1017 
  signal trn_lnk_up_n                : std_logic;
1018 
  signal trn_td                      : std_logic_vector(63 downto 0);
1019 
  signal trn_trem_n                  : std_logic_vector(7 downto 0);
1020 
  signal trn_tsof_n                  : std_logic;
1021 
  signal trn_teof_n                  : std_logic;
1022 
  signal trn_tsrc_rdy_n              : std_logic;
1023 
  signal trn_tdst_rdy_n              : std_logic;
1024 
  signal trn_tdst_dsc_n              : std_logic;
1025 
  signal trn_tsrc_dsc_n              : std_logic;
1026 
  signal trn_terrfwd_n               : std_logic;
1027 
  signal trn_tbuf_av                 : std_logic_vector(5 downto 0);
1028 
  signal trn_rd                      : std_logic_vector(63 downto 0);
1029 
  signal trn_rrem_n                  : std_logic_vector(7 downto 0);
1030 
  signal trn_rsof_n                  : std_logic;
1031 
  signal trn_reof_n                  : std_logic;
1032 
  signal trn_rsrc_rdy_n              : std_logic;
1033 
  signal trn_rsrc_dsc_n              : std_logic;
1034 
  signal trn_rdst_rdy_n              : std_logic;
1035 
  signal trn_rerrfwd_n               : std_logic;
1036 
  signal trn_rnp_ok_n                : std_logic;
1037 
  signal trn_rbar_hit_n              : std_logic_vector(6 downto 0);
1038 
  signal trn_rfc_nph_av              : std_logic_vector(7 downto 0);
1039 
  signal trn_rfc_npd_av              : std_logic_vector(11 downto 0);
1040 
  signal trn_rfc_ph_av               : std_logic_vector(7 downto 0);
1041 
  signal trn_rfc_pd_av               : std_logic_vector(11 downto 0);
1042 
  signal trn_rfc_cplh_av             : std_logic_vector(7 downto 0);
1043 
  signal trn_rfc_cpld_av             : std_logic_vector(11 downto 0);
1044 
  signal trn_rcpl_streaming_n        : std_logic;
1045 
  signal cfg_do                      : std_logic_vector(31 downto 0);
1046 
  signal cfg_rd_wr_done_n            : std_logic;
1047 
  signal cfg_di                      : std_logic_vector(31 downto 0);
1048 
  signal cfg_byte_en_n               : std_logic_vector(3 downto 0);
1049 
  signal cfg_dwaddr                  : std_logic_vector(9 downto 0);
1050 
  signal cfg_wr_en_n                 : std_logic;
1051 
  signal cfg_rd_en_n                 : std_logic;
1052 
  signal cfg_err_cor_n               : std_logic;
1053 
  signal cfg_err_ur_n                : std_logic;
1054 
  signal cfg_err_cpl_rdy_n           : std_logic;
1055 
  signal cfg_err_ecrc_n              : std_logic;
1056 
  signal cfg_err_cpl_timeout_n       : std_logic;
1057 
  signal cfg_err_cpl_abort_n         : std_logic;
1058 
  signal cfg_err_cpl_unexpect_n      : std_logic;
1059 
  signal cfg_err_posted_n            : std_logic;
1060 
  signal cfg_err_locked_n            : std_logic;
1061 
  signal cfg_err_tlp_cpl_header      : std_logic_vector(47 downto 0);
1062 
  signal cfg_interrupt_n             : std_logic;
1063 
  signal cfg_interrupt_rdy_n         : std_logic;
1064 
  signal cfg_interrupt_mmenable      : std_logic_vector(2 downto 0);
1065 
  signal cfg_interrupt_msienable     : std_logic;
1066 
  signal cfg_interrupt_di            : std_logic_vector(7 downto 0);
1067 
  signal cfg_interrupt_do            : std_logic_vector(7 downto 0);
1068 
  signal cfg_interrupt_assert_n      : std_logic;
1069 
  signal cfg_turnoff_ok_n            : std_logic;
1070 
  signal cfg_to_turnoff_n            : std_logic;
1071 
  signal cfg_pm_wake_n               : std_logic;
1072 
  signal cfg_pcie_link_state_n       : std_logic_vector(2 downto 0);
1073 
  signal cfg_trn_pending_n           : std_logic;
1074 
  signal cfg_bus_number              : std_logic_vector(7 downto 0);
1075 
  signal cfg_device_number           : std_logic_vector(4 downto 0);
1076 
  signal cfg_function_number         : std_logic_vector(2 downto 0);
1077 
  signal cfg_dsn                     : std_logic_vector(63 downto 0);
1078 
  signal cfg_status                  : std_logic_vector(15 downto 0);
1079 
  signal cfg_command                 : std_logic_vector(15 downto 0);
1080 
  signal cfg_dstatus                 : std_logic_vector(15 downto 0);
1081 
  signal cfg_dcommand                : std_logic_vector(15 downto 0);
1082 
  signal cfg_lstatus                 : std_logic_vector(15 downto 0);
1083 
  signal cfg_lcommand                : std_logic_vector(15 downto 0);
1084 
  signal fast_train_simulation_only  : std_logic;
1085 
  signal two_plm_auto_config         : std_logic_vector(1 downto 0);
1086 
  signal sys_clk_c                   : std_logic;
1087 
  signal sys_reset_n_c               : std_logic;
1088 
  signal reset_n                     : std_logic;
1089 
 
1090 
  signal localId                     : std_logic_vector(15 downto 0);
1091 
  signal pcie_link_width             : std_logic_vector( 5 downto 0);
1092 
 
1093 
  signal synclk2out                  : std_logic;
1094 
 
1095 
 
1096 
  --
1097 
  signal   trn_Blinker          : std_logic;
1098 
 
1099 
 
1100 
begin
1101 
 
1102 
 
1103 
 
1104 
my_pcie_userlogic_01_cw : pcie_userlogic_01_cw
1105 
  port map (
1106 
    ce        => '1',
1107 
    clk       => user_clk,
1108 
    rst_i     => trn_reset_n,
1109 
    rst_o     => LEDs_IO_pin(0) ,
1110 
    rst_o_pls => LEDs_IO_pin(1)
1111 
  );
1112 
 
1113 
   sys_reset_n_ibuf : IBUF
1114 
      port map (
1115 
                 O      =>  sys_reset_n_c,
1116 
                 I      =>  sys_reset_n
1117 
                );
1118 
 
1119 
   refclk_ibuf : IBUFDS_GTXE1
1120 
      port map (
1121 
                 O      =>  sys_clk_c,
1122 
                 ODIV2  =>  open,
1123 
                 I      =>  sys_clk_p,
1124 
                 IB     =>  sys_clk_n,
1125 
                 CEB    =>  '0'
1126 
                );
1127 
 
1128 
--   refclk_ibuf : IBUFDS
1129 
--      port map (
1130 
--                 O  => sys_clk,
1131 
--                 I  => sys_clk_p,
1132 
--                 IB => sys_clk_n
1133 
--                );
1134 
 
1135 
--   ddr_sys_clk_bufg : BUFG
1136 
--      PORT MAP ( I  => ddr2_sys_clk,
1137 
--                 O  => ddr2_sys_clk_i
1138 
--                );
1139 
 
1140 
 
1141 
--
1142 
--
1143 
   cfg_err_cor_n              <= '1';
1144 
   cfg_err_ur_n               <= '1';
1145 
   cfg_err_ecrc_n             <= '1';
1146 
   cfg_err_cpl_timeout_n      <= '1';
1147 
   cfg_err_cpl_abort_n        <= '1';
1148 
   cfg_err_cpl_unexpect_n     <= '1';
1149 
   cfg_err_posted_n           <= '0';
1150 
   cfg_err_locked_n           <= '0';
1151 
   cfg_err_tlp_cpl_header     <= (OTHERS=>'0');
1152 
   cfg_trn_pending_n          <= '1';
1153 
   cfg_pm_wake_n              <= '1';
1154 
 
1155 
 
1156 
--
1157 
   trn_fc_sel                 <= (OTHERS=>'0');
1158 
 
1159 
   pl_directed_link_auton     <= '0';
1160 
   pl_directed_link_change    <= (OTHERS=>'0');
1161 
   pl_directed_link_speed     <= '0';
1162 
   pl_directed_link_width     <= (OTHERS=>'0');
1163 
   pl_upstream_prefer_deemph  <= '0';
1164 
 
1165 
   trn_tcfg_gnt_n             <= '0';
1166 
   trn_tstr_n                 <= '0';  -- '1';
1167 
 
1168 
--
1169 
 
1170 
   trn_tdst_dsc_n             <= '1';
1171 
 
1172 
--
1173 
   cfg_di                     <= (OTHERS=>'0');
1174 
   cfg_dwaddr                 <= (OTHERS=>'1');
1175 
   cfg_byte_en_n              <= (OTHERS=>'1');
1176 
   cfg_wr_en_n                <= '1';
1177 
   cfg_rd_en_n                <= '1';
1178 
   cfg_dsn      <= X"00000001" &  X"01" & X"000A35";   -- //this is taken from GUI -
1179 
 
1180 
   cfg_turnoff_ok_n           <= '0';
1181 
 
1182 
 
1183 
   localId                    <= cfg_bus_number & cfg_device_number & cfg_function_number;
1184 
 
1185 
   pcie_link_width            <= cfg_lstatus(9 downto 4);
1186 
 
1187 
 
1188 
 
1189 
   trn_lnk_up_n_int_i: FDCP
1190 
     generic map (
1191 
                 INIT  => '1'
1192 
             )
1193 
     port map (
1194 
               Q     =>  trn_lnk_up_n,
1195 
               D     =>  trn_lnk_up_n_int1,
1196 
               C     =>  trn_clk,
1197 
               CLR   =>  '0',
1198 
               PRE   =>  '0'
1199 
              );
1200 
 
1201 
 
1202 
   trn_reset_n_i: FDCP
1203 
     generic map (
1204 
                 INIT  => '1'
1205 
              )
1206 
     port map (
1207 
               Q     =>  trn_reset_n,
1208 
               D     =>  trn_reset_n_int1,
1209 
               C     =>  trn_clk,
1210 
               CLR   =>  '0',
1211 
               PRE   =>  '0'
1212 
              );
1213 
 
1214 
 
1215 
-- --------------------------------------------------------------
1216 
-- --------------------------------------------------------------
1217 
 
1218 
make4Lanes: if pcieLanes = 4 generate
1219 
  pcieCore : v6_pcie_v1_3
1220 
    generic map (
1221 
                 PL_FAST_TRAIN  => FALSE
1222 
             )
1223 
    port map (
1224 
 
1225 
      ---------------------------------------------------------
1226 
      -- 1. PCI Express (pci_exp) Interface
1227 
      ---------------------------------------------------------
1228 
 
1229 
      -- Tx
1230 
      pci_exp_txp       =>     pci_exp_txp           ,
1231 
      pci_exp_txn       =>     pci_exp_txn           ,
1232 
 
1233 
      -- Rx
1234 
      pci_exp_rxp       =>     pci_exp_rxp           ,
1235 
      pci_exp_rxn       =>     pci_exp_rxn           ,
1236 
 
1237 
      ---------------------------------------------------------
1238 
      -- 2. Transaction (TRN) Interface
1239 
      ---------------------------------------------------------
1240 
 
1241 
      -- Common
1242 
      trn_clk           =>     trn_clk               ,
1243 
      trn_reset_n       =>     trn_reset_n_int1      ,
1244 
      trn_lnk_up_n      =>     trn_lnk_up_n_int1     ,
1245 
 
1246 
      -- Tx
1247 
      trn_tbuf_av       =>     trn_tbuf_av           ,
1248 
      trn_tcfg_req_n    =>     trn_tcfg_req_n        ,
1249 
      trn_terr_drop_n   =>     trn_terr_drop_n       ,
1250 
      trn_tdst_rdy_n    =>     trn_tdst_rdy_n        ,
1251 
      trn_td            =>     trn_td                ,
1252 
      trn_trem_n        =>     trn_trem_n(0)         ,
1253 
      trn_tsof_n        =>     trn_tsof_n            ,
1254 
      trn_teof_n        =>     trn_teof_n            ,
1255 
      trn_tsrc_rdy_n    =>     trn_tsrc_rdy_n        ,
1256 
      trn_tsrc_dsc_n    =>     trn_tsrc_dsc_n        ,
1257 
      trn_terrfwd_n     =>     trn_terrfwd_n         ,
1258 
      trn_tcfg_gnt_n    =>     trn_tcfg_gnt_n        ,
1259 
      trn_tstr_n        =>     trn_tstr_n            ,
1260 
 
1261 
      -- Rx
1262 
      trn_rd            =>     trn_rd                ,
1263 
      trn_rrem_n        =>     trn_rrem_n(0)         ,
1264 
      trn_rsof_n        =>     trn_rsof_n            ,
1265 
      trn_reof_n        =>     trn_reof_n            ,
1266 
      trn_rsrc_rdy_n    =>     trn_rsrc_rdy_n        ,
1267 
      trn_rsrc_dsc_n    =>     trn_rsrc_dsc_n        ,
1268 
      trn_rerrfwd_n     =>     trn_rerrfwd_n         ,
1269 
      trn_rbar_hit_n    =>     trn_rbar_hit_n        ,
1270 
      trn_rdst_rdy_n    =>     trn_rdst_rdy_n        ,
1271 
      trn_rnp_ok_n      =>     trn_rnp_ok_n          ,
1272 
 
1273 
      -- Flow Control
1274 
      trn_fc_cpld       =>     trn_fc_cpld           ,
1275 
      trn_fc_cplh       =>     trn_fc_cplh           ,
1276 
      trn_fc_npd        =>     trn_fc_npd            ,
1277 
      trn_fc_nph        =>     trn_fc_nph            ,
1278 
      trn_fc_pd         =>     trn_fc_pd             ,
1279 
      trn_fc_ph         =>     trn_fc_ph             ,
1280 
      trn_fc_sel        =>     trn_fc_sel            ,
1281 
 
1282 
 
1283 
      ---------------------------------------------------------
1284 
      -- 3. Configuration (CFG) Interface
1285 
      ---------------------------------------------------------
1286 
 
1287 
      cfg_do                   =>     cfg_do                     ,
1288 
      cfg_rd_wr_done_n         =>     cfg_rd_wr_done_n           ,
1289 
      cfg_di                   =>     cfg_di                     ,
1290 
      cfg_byte_en_n            =>     cfg_byte_en_n              ,
1291 
      cfg_dwaddr               =>     cfg_dwaddr                 ,
1292 
      cfg_wr_en_n              =>     cfg_wr_en_n                ,
1293 
      cfg_rd_en_n              =>     cfg_rd_en_n                ,
1294 
 
1295 
      cfg_err_cor_n            =>     cfg_err_cor_n              ,
1296 
      cfg_err_ur_n             =>     cfg_err_ur_n               ,
1297 
      cfg_err_ecrc_n           =>     cfg_err_ecrc_n             ,
1298 
      cfg_err_cpl_timeout_n    =>     cfg_err_cpl_timeout_n      ,
1299 
      cfg_err_cpl_abort_n      =>     cfg_err_cpl_abort_n        ,
1300 
      cfg_err_cpl_unexpect_n   =>     cfg_err_cpl_unexpect_n     ,
1301 
      cfg_err_posted_n         =>     cfg_err_posted_n           ,
1302 
      cfg_err_locked_n         =>     cfg_err_locked_n           ,
1303 
      cfg_err_tlp_cpl_header   =>     cfg_err_tlp_cpl_header     ,
1304 
      cfg_err_cpl_rdy_n        =>     cfg_err_cpl_rdy_n          ,
1305 
      cfg_interrupt_n          =>     cfg_interrupt_n            ,
1306 
      cfg_interrupt_rdy_n      =>     cfg_interrupt_rdy_n        ,
1307 
      cfg_interrupt_assert_n   =>     cfg_interrupt_assert_n     ,
1308 
      cfg_interrupt_di         =>     cfg_interrupt_di           ,
1309 
      cfg_interrupt_do         =>     cfg_interrupt_do           ,
1310 
      cfg_interrupt_mmenable   =>     cfg_interrupt_mmenable     ,
1311 
      cfg_interrupt_msienable  =>     cfg_interrupt_msienable    ,
1312 
      cfg_interrupt_msixenable =>     cfg_interrupt_msixenable   ,
1313 
      cfg_interrupt_msixfm     =>     cfg_interrupt_msixfm       ,
1314 
      cfg_turnoff_ok_n         =>     cfg_turnoff_ok_n           ,
1315 
      cfg_to_turnoff_n         =>     cfg_to_turnoff_n           ,
1316 
      cfg_trn_pending_n        =>     cfg_trn_pending_n          ,
1317 
      cfg_pm_wake_n            =>     cfg_pm_wake_n              ,
1318 
      cfg_bus_number           =>     cfg_bus_number             ,
1319 
      cfg_device_number        =>     cfg_device_number          ,
1320 
      cfg_function_number      =>     cfg_function_number        ,
1321 
      cfg_status               =>     cfg_status                 ,
1322 
      cfg_command              =>     cfg_command                ,
1323 
      cfg_dstatus              =>     cfg_dstatus                ,
1324 
      cfg_dcommand             =>     cfg_dcommand               ,
1325 
      cfg_lstatus              =>     cfg_lstatus                ,
1326 
      cfg_lcommand             =>     cfg_lcommand               ,
1327 
      cfg_dcommand2            =>     cfg_dcommand2              ,
1328 
      cfg_pcie_link_state_n    =>     cfg_pcie_link_state_n      ,
1329 
      cfg_dsn                  =>     cfg_dsn                    ,
1330 
 
1331 
      ---------------------------------------------------------
1332 
      -- 4. Physical Layer Control and Status (PL) Interface
1333 
      ---------------------------------------------------------
1334 
 
1335 
      pl_initial_link_width            =>     pl_initial_link_width           ,
1336 
      pl_lane_reversal_mode            =>     pl_lane_reversal_mode           ,
1337 
      pl_link_gen2_capable             =>     pl_link_gen2_capable            ,
1338 
      pl_link_partner_gen2_supported   =>     pl_link_partner_gen2_supported  ,
1339 
      pl_link_upcfg_capable            =>     pl_link_upcfg_capable           ,
1340 
      pl_ltssm_state                   =>     pl_ltssm_state                  ,
1341 
      pl_received_hot_rst              =>     pl_received_hot_rst             ,
1342 
      pl_sel_link_rate                 =>     pl_sel_link_rate                ,
1343 
      pl_sel_link_width                =>     pl_sel_link_width               ,
1344 
      pl_directed_link_auton           =>     pl_directed_link_auton          ,
1345 
      pl_directed_link_change          =>     pl_directed_link_change         ,
1346 
      pl_directed_link_speed           =>     pl_directed_link_speed          ,
1347 
      pl_directed_link_width           =>     pl_directed_link_width          ,
1348 
      pl_upstream_prefer_deemph        =>     pl_upstream_prefer_deemph       ,
1349 
 
1350 
      ---------------------------------------------------------
1351 
      -- 5. System  (SYS) Interface
1352 
      ---------------------------------------------------------
1353 
 
1354 
      sys_clk                          =>     sys_clk_c     ,
1355 
      sys_reset_n                      =>     sys_reset_n_c
1356 
 
1357 
);
1358 
 
1359 
 end generate;
1360 
 
1361 
 
1362 
make8Lanes: if pcieLanes = 8 generate
1363 
  pcieCore : v6_pcie_v1_3x8
1364 
    generic map (
1365 
                 PL_FAST_TRAIN  => FALSE
1366 
             )
1367 
    port map (
1368 
 
1369 
      ---------------------------------------------------------
1370 
      -- 1. PCI Express (pci_exp) Interface
1371 
      ---------------------------------------------------------
1372 
 
1373 
      -- Tx
1374 
      pci_exp_txp       =>     pci_exp_txp           ,
1375 
      pci_exp_txn       =>     pci_exp_txn           ,
1376 
 
1377 
      -- Rx
1378 
      pci_exp_rxp       =>     pci_exp_rxp           ,
1379 
      pci_exp_rxn       =>     pci_exp_rxn           ,
1380 
 
1381 
      ---------------------------------------------------------
1382 
      -- 2. Transaction (TRN) Interface
1383 
      ---------------------------------------------------------
1384 
 
1385 
      -- Common
1386 
      trn_clk           =>     trn_clk               ,
1387 
      trn_reset_n       =>     trn_reset_n_int1      ,
1388 
      trn_lnk_up_n      =>     trn_lnk_up_n_int1     ,
1389 
 
1390 
      -- Tx
1391 
      trn_tbuf_av       =>     trn_tbuf_av           ,
1392 
      trn_tcfg_req_n    =>     trn_tcfg_req_n        ,
1393 
      trn_terr_drop_n   =>     trn_terr_drop_n       ,
1394 
      trn_tdst_rdy_n    =>     trn_tdst_rdy_n        ,
1395 
      trn_td            =>     trn_td                ,
1396 
      trn_trem_n        =>     trn_trem_n(0)         ,
1397 
      trn_tsof_n        =>     trn_tsof_n            ,
1398 
      trn_teof_n        =>     trn_teof_n            ,
1399 
      trn_tsrc_rdy_n    =>     trn_tsrc_rdy_n        ,
1400 
      trn_tsrc_dsc_n    =>     trn_tsrc_dsc_n        ,
1401 
      trn_terrfwd_n     =>     trn_terrfwd_n         ,
1402 
      trn_tcfg_gnt_n    =>     trn_tcfg_gnt_n        ,
1403 
      trn_tstr_n        =>     trn_tstr_n            ,
1404 
 
1405 
      -- Rx
1406 
      trn_rd            =>     trn_rd                ,
1407 
      trn_rrem_n        =>     trn_rrem_n(0)         ,
1408 
      trn_rsof_n        =>     trn_rsof_n            ,
1409 
      trn_reof_n        =>     trn_reof_n            ,
1410 
      trn_rsrc_rdy_n    =>     trn_rsrc_rdy_n        ,
1411 
      trn_rsrc_dsc_n    =>     trn_rsrc_dsc_n        ,
1412 
      trn_rerrfwd_n     =>     trn_rerrfwd_n         ,
1413 
      trn_rbar_hit_n    =>     trn_rbar_hit_n        ,
1414 
      trn_rdst_rdy_n    =>     trn_rdst_rdy_n        ,
1415 
      trn_rnp_ok_n      =>     trn_rnp_ok_n          ,
1416 
 
1417 
      -- Flow Control
1418 
      trn_fc_cpld       =>     trn_fc_cpld           ,
1419 
      trn_fc_cplh       =>     trn_fc_cplh           ,
1420 
      trn_fc_npd        =>     trn_fc_npd            ,
1421 
      trn_fc_nph        =>     trn_fc_nph            ,
1422 
      trn_fc_pd         =>     trn_fc_pd             ,
1423 
      trn_fc_ph         =>     trn_fc_ph             ,
1424 
      trn_fc_sel        =>     trn_fc_sel            ,
1425 
 
1426 
 
1427 
      ---------------------------------------------------------
1428 
      -- 3. Configuration (CFG) Interface
1429 
      ---------------------------------------------------------
1430 
 
1431 
      cfg_do                   =>     cfg_do                     ,
1432 
      cfg_rd_wr_done_n         =>     cfg_rd_wr_done_n           ,
1433 
      cfg_di                   =>     cfg_di                     ,
1434 
      cfg_byte_en_n            =>     cfg_byte_en_n              ,
1435 
      cfg_dwaddr               =>     cfg_dwaddr                 ,
1436 
      cfg_wr_en_n              =>     cfg_wr_en_n                ,
1437 
      cfg_rd_en_n              =>     cfg_rd_en_n                ,
1438 
 
1439 
      cfg_err_cor_n            =>     cfg_err_cor_n              ,
1440 
      cfg_err_ur_n             =>     cfg_err_ur_n               ,
1441 
      cfg_err_ecrc_n           =>     cfg_err_ecrc_n             ,
1442 
      cfg_err_cpl_timeout_n    =>     cfg_err_cpl_timeout_n      ,
1443 
      cfg_err_cpl_abort_n      =>     cfg_err_cpl_abort_n        ,
1444 
      cfg_err_cpl_unexpect_n   =>     cfg_err_cpl_unexpect_n     ,
1445 
      cfg_err_posted_n         =>     cfg_err_posted_n           ,
1446 
      cfg_err_locked_n         =>     cfg_err_locked_n           ,
1447 
      cfg_err_tlp_cpl_header   =>     cfg_err_tlp_cpl_header     ,
1448 
      cfg_err_cpl_rdy_n        =>     cfg_err_cpl_rdy_n          ,
1449 
      cfg_interrupt_n          =>     cfg_interrupt_n            ,
1450 
      cfg_interrupt_rdy_n      =>     cfg_interrupt_rdy_n        ,
1451 
      cfg_interrupt_assert_n   =>     cfg_interrupt_assert_n     ,
1452 
      cfg_interrupt_di         =>     cfg_interrupt_di           ,
1453 
      cfg_interrupt_do         =>     cfg_interrupt_do           ,
1454 
      cfg_interrupt_mmenable   =>     cfg_interrupt_mmenable     ,
1455 
      cfg_interrupt_msienable  =>     cfg_interrupt_msienable    ,
1456 
      cfg_interrupt_msixenable =>     cfg_interrupt_msixenable   ,
1457 
      cfg_interrupt_msixfm     =>     cfg_interrupt_msixfm       ,
1458 
      cfg_turnoff_ok_n         =>     cfg_turnoff_ok_n           ,
1459 
      cfg_to_turnoff_n         =>     cfg_to_turnoff_n           ,
1460 
      cfg_trn_pending_n        =>     cfg_trn_pending_n          ,
1461 
      cfg_pm_wake_n            =>     cfg_pm_wake_n              ,
1462 
      cfg_bus_number           =>     cfg_bus_number             ,
1463 
      cfg_device_number        =>     cfg_device_number          ,
1464 
      cfg_function_number      =>     cfg_function_number        ,
1465 
      cfg_status               =>     cfg_status                 ,
1466 
      cfg_command              =>     cfg_command                ,
1467 
      cfg_dstatus              =>     cfg_dstatus                ,
1468 
      cfg_dcommand             =>     cfg_dcommand               ,
1469 
      cfg_lstatus              =>     cfg_lstatus                ,
1470 
      cfg_lcommand             =>     cfg_lcommand               ,
1471 
      cfg_dcommand2            =>     cfg_dcommand2              ,
1472 
      cfg_pcie_link_state_n    =>     cfg_pcie_link_state_n      ,
1473 
      cfg_dsn                  =>     cfg_dsn                    ,
1474 
 
1475 
      ---------------------------------------------------------
1476 
      -- 4. Physical Layer Control and Status (PL) Interface
1477 
      ---------------------------------------------------------
1478 
 
1479 
      pl_initial_link_width            =>     pl_initial_link_width           ,
1480 
      pl_lane_reversal_mode            =>     pl_lane_reversal_mode           ,
1481 
      pl_link_gen2_capable             =>     pl_link_gen2_capable            ,
1482 
      pl_link_partner_gen2_supported   =>     pl_link_partner_gen2_supported  ,
1483 
      pl_link_upcfg_capable            =>     pl_link_upcfg_capable           ,
1484 
      pl_ltssm_state                   =>     pl_ltssm_state                  ,
1485 
      pl_received_hot_rst              =>     pl_received_hot_rst             ,
1486 
      pl_sel_link_rate                 =>     pl_sel_link_rate                ,
1487 
      pl_sel_link_width                =>     pl_sel_link_width               ,
1488 
      pl_directed_link_auton           =>     pl_directed_link_auton          ,
1489 
      pl_directed_link_change          =>     pl_directed_link_change         ,
1490 
      pl_directed_link_speed           =>     pl_directed_link_speed          ,
1491 
      pl_directed_link_width           =>     pl_directed_link_width          ,
1492 
      pl_upstream_prefer_deemph        =>     pl_upstream_prefer_deemph       ,
1493 
 
1494 
      ---------------------------------------------------------
1495 
      -- 5. System  (SYS) Interface
1496 
      ---------------------------------------------------------
1497 
 
1498 
      sys_clk                          =>     sys_clk_c     ,
1499 
      sys_reset_n                      =>     sys_reset_n_c
1500 
 
1501 
);
1502 
 
1503 
 end generate;
1504 
 
1505 
 
1506 
   DAQ_irq              <= eb_empty;
1507 
 
1508 
 
1509 
-- ---------------------------------------------------------------
1510 
-- tlp control module
1511 
--
1512 
   trn_rrem_n(7 downto 1) <= X"0" & trn_rrem_n(0) & trn_rrem_n(0) & trn_rrem_n(0);
1513 
 
1514 
   theTlpControl:
1515 
   tlpControl
1516 
   port map (
1517 
 
1518 
           mbuf_UserFull               => '0'                 ,
1519 
           trn_Blinker                 => trn_Blinker         ,
1520 
 
1521 
           -- DCB protocol interface
1522 
           protocol_link_act           =>  protocol_link_act  ,  -- IN  std_logic_vector(2-1 downto 0);
1523 
           protocol_rst                =>  protocol_rst       ,  -- OUT std_logic;
1524 
 
1525 
           Link_Buf_Full               =>  daq_rstop          ,  -- IN  std_logic;
1526 
 
1527 
           -- Interrupter triggers
1528 
           DAQ_irq                     =>  DAQ_irq            ,  -- IN  std_logic;
1529 
           CTL_irq                     =>  CTL_irq            ,  -- IN  std_logic;
1530 
           DLM_irq                     =>  DLM_irq            ,  -- IN  std_logic;
1531 
 
1532 
           -- Fabric side: CTL Rx
1533 
           ctl_rv                      =>  ctl_rv             ,  -- OUT std_logic;
1534 
           ctl_rd                      =>  ctl_rd             ,  -- OUT std_logic_vector(C_DBUS_WIDTH/2-1 downto 0);
1535 
 
1536 
           -- Fabric side: CTL Tx
1537 
           ctl_ttake                   =>  ctl_ttake          ,  -- OUT std_logic;
1538 
           ctl_tv                      =>  ctl_tv             ,  -- IN  std_logic;
1539 
           ctl_td                      =>  ctl_td             ,  -- IN  std_logic_vector(C_DBUS_WIDTH/2-1 downto 0);
1540 
           ctl_tstop                   =>  ctl_tstop          ,  -- OUT std_logic;
1541 
 
1542 
           ctl_reset                   =>  ctl_reset          ,  -- OUT std_logic;
1543 
           ctl_status                  =>  ctl_status         ,  -- IN  std_logic_vector(C_DBUS_WIDTH/2-1 downto 0);
1544 
 
1545 
           -- Fabric side: DLM Rx
1546 
           dlm_rv                      =>  dlm_rv             ,  -- OUT std_logic;
1547 
           dlm_rd                      =>  dlm_rd             ,  -- OUT std_logic_vector(C_DBUS_WIDTH/2-1 downto 0);
1548 
 
1549 
           -- Fabric side: DLM Tx
1550 
           dlm_tv                      =>  dlm_tv             ,  -- IN  std_logic;
1551 
           dlm_td                      =>  dlm_td             ,  -- IN  std_logic_vector(C_DBUS_WIDTH/2-1 downto 0);
1552 
 
1553 
           -- Event Buffer FIFO interface
1554 
           eb_FIFO_we                  => eb_we               , --  OUT std_logic;
1555 
           eb_FIFO_wsof                => eb_wsof             , --  OUT std_logic;
1556 
           eb_FIFO_weof                => eb_weof             , --  OUT std_logic;
1557 
           eb_FIFO_din                 => eb_din(C_DBUS_WIDTH-1 downto 0) , --  OUT std_logic_vector(C_DBUS_WIDTH-1 downto 0);
1558 
 
1559 
           eb_FIFO_re                  => eb_re               , --  OUT std_logic;
1560 
           eb_FIFO_empty               => eb_empty            , --  IN  std_logic;
1561 
           eb_FIFO_qout                => eb_dout(C_DBUS_WIDTH-1 downto 0) , --  IN  std_logic_vector(C_DBUS_WIDTH-1 downto 0);
1562 
           eb_FIFO_data_count          => eb_data_count       , --  IN  std_logic_vector(C_FIFO_DC_WIDTH downto 0);
1563 
 
1564 
           eb_FIFO_ow                  => eb_FIFO_ow          , --  IN  std_logic;
1565 
 
1566 
           pio_reading_status          => pio_reading_status  , --  OUT std_logic;
1567 
 
1568 
           eb_FIFO_Status              => eb_FIFO_Status      , --  IN  std_logic_vector(C_DBUS_WIDTH-1 downto 0);
1569 
           eb_FIFO_Rst                 => eb_rst              , --  OUT std_logic;
1570 
 
1571 
           -- Debugging signals
1572 
           DMA_us_Done                 => LEDs_IO_pin(7)      , -- OUT std_logic;
1573 
           DMA_us_Busy                 => open                , -- OUT std_logic;
1574 
           DMA_us_Busy_LED             => LEDs_IO_pin(6)      , -- OUT std_logic;
1575 
           DMA_ds_Done                 => LEDs_IO_pin(5)      , -- OUT std_logic;
1576 
           DMA_ds_Busy                 => open                , -- OUT std_logic;
1577 
           DMA_ds_Busy_LED             => LEDs_IO_pin(4)      , -- OUT std_logic;
1578 
 
1579 
           -------------------
1580 
           -- DDR Interface
1581 
           DDR_Ready                   => DDR_Ready           , --  IN    std_logic;
1582 
 
1583 
           DDR_wr_sof                  => DDR_wr_sof          , --  OUT   std_logic;
1584 
           DDR_wr_eof                  => DDR_wr_eof          , --  OUT   std_logic;
1585 
           DDR_wr_v                    => DDR_wr_v            , --  OUT   std_logic;
1586 
           DDR_wr_FA                   => DDR_wr_FA           , --  OUT   std_logic;
1587 
           DDR_wr_Shift                => DDR_wr_Shift        , --  OUT   std_logic;
1588 
           DDR_wr_Mask                 => DDR_wr_Mask         , --  OUT   std_logic_vector(2-1 downto 0);
1589 
           DDR_wr_din                  => DDR_wr_din          , --  OUT   std_logic_vector(C_DBUS_WIDTH-1 downto 0);
1590 
           DDR_wr_full                 => DDR_wr_full         , --  IN    std_logic;
1591 
 
1592 
           DDR_rdc_sof                 => DDR_rdc_sof         , --  OUT   std_logic;
1593 
           DDR_rdc_eof                 => DDR_rdc_eof         , --  OUT   std_logic;
1594 
           DDR_rdc_v                   => DDR_rdc_v           , --  OUT   std_logic;
1595 
           DDR_rdc_FA                  => DDR_rdc_FA          , --  OUT   std_logic;
1596 
           DDR_rdc_Shift               => DDR_rdc_Shift       , --  OUT   std_logic;
1597 
           DDR_rdc_din                 => DDR_rdc_din         , --  OUT   std_logic_vector(C_DBUS_WIDTH-1 downto 0);
1598 
           DDR_rdc_full                => DDR_rdc_full        , --  IN    std_logic;
1599 
 
1600 
--           DDR_rdD_sof                 => DDR_rdD_sof         , --  IN    std_logic;
1601 
--           DDR_rdD_eof                 => DDR_rdD_eof         , --  IN    std_logic;
1602 
--           DDR_rdDout_V                => DDR_rdDout_V        , --  IN    std_logic;
1603 
--           DDR_rdDout                  => DDR_rdDout          , --  IN    std_logic_vector(C_DBUS_WIDTH-1 downto 0);
1604 
 
1605 
           -- DDR payload FIFO Read Port
1606 
           DDR_FIFO_RdEn               => DDR_FIFO_RdEn      ,  -- OUT std_logic;
1607 
           DDR_FIFO_Empty              => DDR_FIFO_Empty     ,  -- IN  std_logic;
1608 
           DDR_FIFO_RdQout             => DDR_FIFO_RdQout    ,  -- IN  std_logic_vector(C_DBUS_WIDTH-1 downto 0);
1609 
 
1610 
           -- Data generator table write
1611 
           tab_we                      =>  tab_we            ,  -- OUT std_logic_vector(2-1 downto 0);
1612 
           tab_wa                      =>  tab_wa            ,  -- OUT std_logic_vector(12-1 downto 0);
1613 
           tab_wd                      =>  tab_wd            ,  -- OUT std_logic_vector(C_DBUS_WIDTH-1 downto 0);
1614 
 
1615 
           DG_is_Running               =>  dg_running        ,  -- IN  std_logic;
1616 
           DG_Reset                    =>  dg_rst            ,  -- OUT   STD_LOGIC;
1617 
           DG_Mask                     =>  dg_mask           ,  -- OUT   STD_LOGIC
1618 
 
1619 
           -------------------
1620 
           -- Transaction Interface
1621 
           trn_lnk_up_n                => trn_lnk_up_n            ,
1622 
           trn_rsrc_dsc_n              => trn_rsrc_dsc_n          ,
1623 
           trn_rnp_ok_n                => trn_rnp_ok_n            ,
1624 
           trn_tsrc_dsc_n              => trn_tsrc_dsc_n          ,
1625 
           trn_tdst_dsc_n              => trn_tdst_dsc_n          ,
1626 
           trn_tbuf_av                 => trn_tbuf_av             ,
1627 
           trn_terrfwd_n               => trn_terrfwd_n           ,
1628 
 
1629 
           trn_clk                     => trn_clk                 ,
1630 
           trn_reset_n                 => trn_reset_n             ,
1631 
           trn_rsrc_rdy_n              => trn_rsrc_rdy_n          ,
1632 
           trn_tdst_rdy_n              => trn_tdst_rdy_n          ,
1633 
           trn_rsof_n                  => trn_rsof_n              ,
1634 
           trn_reof_n                  => trn_reof_n              ,
1635 
           trn_rerrfwd_n               => trn_rerrfwd_n           ,
1636 
           trn_rrem_n                  => trn_rrem_n              ,
1637 
           trn_rd                      => trn_rd                  ,
1638 
 
1639 
           cfg_interrupt_n             => cfg_interrupt_n         ,
1640 
           cfg_interrupt_rdy_n         => cfg_interrupt_rdy_n     ,
1641 
           cfg_interrupt_mmenable      => cfg_interrupt_mmenable  ,
1642 
           cfg_interrupt_msienable     => cfg_interrupt_msienable ,
1643 
           cfg_interrupt_di            => cfg_interrupt_di        ,
1644 
           cfg_interrupt_do            => cfg_interrupt_do        ,
1645 
           cfg_interrupt_assert_n      => cfg_interrupt_assert_n  ,
1646 
 
1647 
           trn_rbar_hit_n              => trn_rbar_hit_n          ,
1648 
           trn_tsrc_rdy_n              => trn_tsrc_rdy_n          ,
1649 
           trn_rdst_rdy_n              => trn_rdst_rdy_n          ,
1650 
           trn_tsof_n                  => trn_tsof_n              ,
1651 
           trn_teof_n                  => trn_teof_n              ,
1652 
           trn_trem_n                  => trn_trem_n              ,
1653 
           trn_td                      => trn_td                  ,
1654 
 
1655 
           Format_Shower               => Format_Shower           ,
1656 
 
1657 
           cfg_dcommand                => cfg_dcommand            ,
1658 
           pcie_link_width             => pcie_link_width         ,
1659 
           localId                     => localId
1660 
           );
1661 
 
1662 
 
1663 
  -- -----------------------------------------------------------------------
1664 
  --  DDR SDRAM control module
1665 
  --
1666 
   DDRs_ctrl_module:
1667 
   bram_DDRs_Control
1668 
   GENERIC MAP (
1669 
                C_ASYNFIFO_WIDTH    => 72 ,
1670 
                P_SIMULATION        => FALSE
1671 
               )
1672 
   PORT MAP(
1673 
 
1674 
      -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
1675 
      DDR_wr_sof               => DDR_wr_sof          , --  IN    std_logic;
1676 
      DDR_wr_eof               => DDR_wr_eof          , --  IN    std_logic;
1677 
      DDR_wr_v                 => DDR_wr_v            , --  IN    std_logic;
1678 
      DDR_wr_FA                => DDR_wr_FA           , --  IN    std_logic;
1679 
      DDR_wr_Shift             => DDR_wr_Shift        , --  IN    std_logic;
1680 
      DDR_wr_Mask              => DDR_wr_Mask         , --  IN    std_logic_vector(2-1 downto 0);
1681 
      DDR_wr_din               => DDR_wr_din          , --  IN    std_logic_vector(C_DBUS_WIDTH-1 downto 0);
1682 
      DDR_wr_full              => DDR_wr_full         , --  OUT   std_logic;
1683 
 
1684 
      DDR_rdc_sof              => DDR_rdc_sof         , --  IN    std_logic;
1685 
      DDR_rdc_eof              => DDR_rdc_eof         , --  IN    std_logic;
1686 
      DDR_rdc_v                => DDR_rdc_v           , --  IN    std_logic;
1687 
      DDR_rdc_FA               => DDR_rdc_FA          , --  IN    std_logic;
1688 
      DDR_rdc_Shift            => DDR_rdc_Shift       , --  IN    std_logic;
1689 
      DDR_rdc_din              => DDR_rdc_din         , --  IN    std_logic_vector(C_DBUS_WIDTH-1 downto 0);
1690 
      DDR_rdc_full             => DDR_rdc_full        , --  OUT   std_logic;
1691 
 
1692 
--      DDR_rdD_sof              => DDR_rdD_sof         , --  OUT   std_logic;
1693 
--      DDR_rdD_eof              => DDR_rdD_eof         , --  OUT   std_logic;
1694 
--      DDR_rdDout_V             => DDR_rdDout_V        , --  OUT   std_logic;
1695 
--      DDR_rdDout               => DDR_rdDout          , --  OUT   std_logic_vector(C_DBUS_WIDTH-1 downto 0);
1696 
 
1697 
      -- DDR payload FIFO Read Port
1698 
      DDR_FIFO_RdEn            => DDR_FIFO_RdEn       ,  -- IN    std_logic;
1699 
      DDR_FIFO_Empty           => DDR_FIFO_Empty      ,  -- OUT   std_logic;
1700 
      DDR_FIFO_RdQout          => DDR_FIFO_RdQout     ,  -- OUT   std_logic_vector(C_DBUS_WIDTH-1 downto 0);
1701 
 
1702 
      -- Common interface
1703 
      DDR_Ready                => DDR_Ready           , --  OUT   std_logic;
1704 
      DDR_Blinker              => DDR_Blinker         , --  OUT   std_logic;
1705 
      mem_clk                  => trn_clk,   -- mem_clk             , --  IN
1706 
      trn_clk                  => trn_clk             , --  IN    std_logic;
1707 
      trn_reset_n              => trn_reset_n           --  IN    std_logic
1708 
    );
1709 
 
1710 
 
1711 
 
1712 
    --
1713 
    -- Event Buffer wrapper
1714 
    --
1715 
    Pseudo_EB: if not USE_DDR2_MODULE generate
1716 
 
1717 
 
1718 
    --S LEDs_IO_pin(0)    <= trn_reset_n xor Format_Shower;
1719 
    --S LEDs_IO_pin(1)    <= trn_lnk_up_n;
1720 
    LEDs_IO_pin(2)    <= link_active(0);
1721 
    LEDs_IO_pin(3)    <= trn_Blinker   ;  -- link_active(1);   -- dg_debug_led;
1722 
 
1723 
 
1724 
    event_buffer0:
1725 
    eb_wrapper
1726 
      port map (
1727 
         wr_clk     => trn_clk   ,  -- eb_wclk   ,
1728 
         wr_en      => eb_we_up  ,
1729 
         din        => eb_din_up ,
1730 
         pfull      => eb_pfull  ,
1731 
         full       => eb_full   ,
1732 
 
1733 
         rd_clk     => trn_clk   ,  -- eb_rclk   ,
1734 
         rd_en      => eb_re     ,
1735 
         dout       => eb_dout   ,
1736 
         pempty     => eb_pempty ,
1737 
         empty      => eb_empty  ,
1738 
 
1739 
         data_count => eb_data_count(C_EMU_FIFO_DC_WIDTH-1+1 downto 1) ,
1740 
         rst        => eb_rst
1741 
         );
1742 
 
1743 
--      eb_FIFO_Status(C_FIFO_DC_WIDTH+2)  <= '0';
1744 
      eb_data_count(C_FIFO_DC_WIDTH downto C_EMU_FIFO_DC_WIDTH+1)
1745 
                      <= C_ALL_ZEROS(C_FIFO_DC_WIDTH downto C_EMU_FIFO_DC_WIDTH+1);
1746 
      eb_data_count(0)        -- 64 bits to 32 bits transformation
1747 
                      <= '0';
1748 
      fifo_reset_done <= not eb_rst;
1749 
 
1750 
    end generate;
1751 
 
1752 
 
1753 
 
1754 
--    eb_wclk            <= trn_clk;
1755 
--    eb_rclk            <= trn_clk;
1756 
    eb_din(72-1 downto C_DBUS_WIDTH)       <= (OTHERS=>'0');
1757 
    eb_FIFO_Status(C_DBUS_WIDTH-1 downto C_FIFO_DC_WIDTH+3)
1758 
                         <= (OTHERS=>'0');
1759 
    eb_FIFO_Status(C_FIFO_DC_WIDTH+2 downto 3)
1760 
                         <= eb_data_count(C_FIFO_DC_WIDTH downto 1);
1761 
    eb_FIFO_Status(2)    <= '0';      -- daq_rstop;
1762 
    eb_FIFO_Status(1)    <= eb_pfull;
1763 
    eb_FIFO_Status(0)    <= eb_empty and fifo_reset_done;
1764 
    eb_FIFO_ow           <= eb_we_up and eb_full;
1765 
 
1766 
 
1767 
    --
1768 
    --   .......................
1769 
    --
1770 
 
1771 
    daq_rv              <=  eb_we;
1772 
    daq_rsof            <=  eb_wsof;
1773 
    daq_reof            <=  eb_weof;
1774 
    daq_rd              <=  eb_din(C_DBUS_WIDTH-1 downto 0);
1775 
 
1776 
    eb_we_up            <=  daq_tv;
1777 
    eb_din_up           <=  C_ALL_ZEROS(72-1 downto C_DBUS_WIDTH+2) & daq_tsof & daq_teof & daq_td;
1778 
    daq_tstop           <=  eb_pfull;
1779 
 
1780 
 
1781 
    --
1782 
    --     Protocol Interface
1783 
    --
1784 
    ABB_DCB_Interface0:
1785 
    protocol_IF
1786 
      port map (
1787 
           -- DAQ Tx
1788 
           data2send_start          => data2send_start      ,   -- OUT   std_logic;
1789 
           data2send_end            => data2send_end        ,   -- OUT   std_logic;
1790 
           data2send                => data2send            ,   -- OUT   std_logic_vector(16-1 downto 0);
1791 
           crc_error_send           => crc_error_send       ,   -- OUT   std_logic;
1792 
           data2send_stop           => data2send_stop       ,   -- IN    std_logic;
1793 
 
1794 
           -- DAQ Rx
1795 
           data_rec_start           => data_rec_start       ,   -- IN    std_logic;
1796 
           data_rec_end             => data_rec_end         ,   -- IN    std_logic;
1797 
           data_rec                 => data_rec             ,   -- IN    std_logic_vector(16-1 downto 0);
1798 
           crc_error_rec            => crc_error_rec        ,   -- IN    std_logic;
1799 
           data_rec_stop            => data_rec_stop        ,   -- OUT   std_logic;
1800 
 
1801 
           -- CTL Tx
1802 
           ctrl2send_start          => ctrl2send_start      ,   -- OUT   std_logic;
1803 
           ctrl2send_end            => ctrl2send_end        ,   -- OUT   std_logic;
1804 
           ctrl2send                => ctrl2send            ,   -- OUT   std_logic_vector(16-1 downto 0);
1805 
           ctrl2send_stop           => ctrl2send_stop       ,   -- IN    std_logic;
1806 
 
1807 
           -- CTL Rx
1808 
           ctrl_rec_start           => ctrl_rec_start       ,   -- IN    std_logic;
1809 
           ctrl_rec_end             => ctrl_rec_end         ,   -- IN    std_logic;
1810 
           ctrl_rec                 => ctrl_rec             ,   -- IN    std_logic_vector(16-1 downto 0);
1811 
           ctrl_rec_stop            => ctrl_rec_stop        ,   -- OUT   std_logic;
1812 
 
1813 
           -- DLM Tx
1814 
           dlm2send_va              => dlm2send_va          ,   -- OUT   std_logic;
1815 
           dlm2send_type            => dlm2send_type        ,   -- OUT   std_logic_vector(4-1 downto 0);
1816 
 
1817 
           -- DLM Rx
1818 
           dlm_rec_va               => dlm_rec_va           ,   -- IN    std_logic;
1819 
           dlm_rec_type             => dlm_rec_type         ,   -- IN    std_logic_vector(4-1 downto 0);
1820 
 
1821 
           -- Common signals
1822 
           link_tx_clk              => link_tx_clk          ,   -- IN    std_logic;
1823 
           link_rx_clk              => link_rx_clk          ,   -- IN    std_logic;
1824 
           link_active              => link_active          ,   -- IN    std_logic_vector(2-1 downto 0);
1825 
           protocol_clk             => protocol_clk         ,   -- OUT   std_logic;
1826 
           protocol_res_n           => protocol_res_n       ,   -- OUT   std_logic;
1827 
 
1828 
 
1829 
           -- Fabric side: DAQ Rx
1830 
           daq_rv                   => daq_rv               ,   -- IN    std_logic;
1831 
           daq_rsof                 => daq_rsof             ,   -- IN    std_logic;
1832 
           daq_reof                 => daq_reof             ,   -- IN    std_logic;
1833 
           daq_rd                   => daq_rd               ,   -- IN    std_logic_vector(64-1 downto 0);
1834 
           daq_rstop                => daq_rstop            ,   -- OUT   std_logic;
1835 
 
1836 
           -- Fabric side: DAQ Tx
1837 
           daq_tv                   => daq_tv               ,   -- OUT   std_logic;
1838 
           daq_tsof                 => daq_tsof             ,   -- OUT   std_logic;
1839 
           daq_teof                 => daq_teof             ,   -- OUT   std_logic;
1840 
           daq_td                   => daq_td               ,   -- OUT   std_logic_vector(64-1 downto 0);
1841 
           daq_tstop                => daq_tstop            ,   -- IN    std_logic;
1842 
 
1843 
           -- Fabric side: CTL Rx
1844 
           ctl_rv                   => ctl_rv               ,   -- IN    std_logic;
1845 
           ctl_rd                   => ctl_rd               ,   -- IN    std_logic_vector(32-1 downto 0);
1846 
           ctl_rstop                => ctl_rstop            ,   -- OUT   std_logic;
1847 
 
1848 
           -- Fabric side: CTL Tx
1849 
           ctl_ttake                => ctl_ttake            ,   -- IN    std_logic;
1850 
           ctl_tv                   => ctl_tv               ,   -- OUT   std_logic;
1851 
           ctl_td                   => ctl_td               ,   -- OUT   std_logic_vector(32-1 downto 0);
1852 
           ctl_tstop                => ctl_tstop            ,   -- IN    std_logic;
1853 
 
1854 
           ctl_reset                => ctl_reset            ,   -- IN    std_logic;
1855 
           ctl_status               => ctl_status           ,   -- OUT   std_logic_vector(32-1 downto 0);
1856 
 
1857 
           -- Fabric side: DLM Rx
1858 
           dlm_rv                   => dlm_rv               ,   -- IN    std_logic;
1859 
           dlm_rd                   => dlm_rd               ,   -- IN    std_logic_vector(4-1 downto 0);
1860 
 
1861 
           -- Fabric side: DLM Tx
1862 
           dlm_tv                   => dlm_tv               ,   -- OUT   std_logic;
1863 
           dlm_td                   => dlm_td               ,   -- OUT   std_logic_vector(4-1 downto 0);
1864 
 
1865 
           -- Interrupter triggers
1866 
           DAQ_irq                  => open,  -- DAQ_irq              ,   -- OUT   std_logic;
1867 
           CTL_irq                  => CTL_irq              ,   -- OUT   std_logic;
1868 
           DLM_irq                  => DLM_irq              ,   -- OUT   std_logic;
1869 
 
1870 
           -- Data generator table write port
1871 
           tab_sel                  => '1'                  , -- IN    STD_LOGIC;
1872 
           tab_we                   => tab_we               , -- IN    STD_LOGIC_VECTOR (2-1 downto 0);
1873 
           tab_wa                   => tab_wa               , -- IN    STD_LOGIC_VECTOR (12-1 downto 0);
1874 
           tab_wd                   => tab_wd               , -- IN    STD_LOGIC_VECTOR (64-1 downto 0);
1875 
 
1876 
           -- DG control/status signal
1877 
           dg_running               => dg_running           , -- OUT   STD_LOGIC;
1878 
           dg_mask                  => dg_mask              , -- IN    STD_LOGIC;
1879 
           dg_rst                   => dg_rst               , -- IN    STD_LOGIC
1880 
 
1881 
           -- DG debug signal
1882 
           daq_start_led            => dg_debug_led         , -- OUT   STD_LOGIC;
1883 
 
1884 
           -- Fabric side: Common signals
1885 
           trn_clk                  => trn_clk              ,   -- IN    std_logic;
1886 
           protocol_link_act        => protocol_link_act    ,   -- OUT   std_logic_vector(2-1 downto 0);
1887 
           protocol_rst             => protocol_rst             -- IN    std_logic
1888 
      );
1889 
 
1890 
 
1891 
    --
1892 
    --     Module emulating the link
1893 
    --
1894 
  Gen_EMU_Links: if not USE_OPTO_LINKS generate
1895 
 
1896 
    DCB_Link_module0:
1897 
    pseudo_protocol_module
1898 
      port map (
1899 
           -- DAQ Tx
1900 
           data2send_start          => data2send_start       ,   -- IN    std_logic;
1901 
           data2send_end            => data2send_end         ,   -- IN    std_logic;
1902 
           data2send                => data2send             ,   -- IN    std_logic_vector(16-1 downto 0);
1903 
           crc_error_send           => crc_error_send        ,   -- IN    std_logic;
1904 
           data2send_stop           => data2send_stop        ,   -- OUT   std_logic;
1905 
 
1906 
           -- DAQ Rx
1907 
           data_rec_start           => data_rec_start        ,   -- OUT   std_logic;
1908 
           data_rec_end             => data_rec_end          ,   -- OUT   std_logic;
1909 
           data_rec                 => data_rec              ,   -- OUT   std_logic_vector(16-1 downto 0);
1910 
           crc_error_rec            => crc_error_rec         ,   -- OUT   std_logic;
1911 
           data_rec_stop            => data_rec_stop         ,   -- IN    std_logic;
1912 
 
1913 
           -- CTL Tx
1914 
           ctrl2send_start          => ctrl2send_start       ,   -- IN    std_logic;
1915 
           ctrl2send_end            => ctrl2send_end         ,   -- IN    std_logic;
1916 
           ctrl2send                => ctrl2send             ,   -- IN    std_logic_vector(16-1 downto 0);
1917 
           ctrl2send_stop           => ctrl2send_stop        ,   -- OUT   std_logic;
1918 
 
1919 
           -- CTL Rx
1920 
           ctrl_rec_start           => ctrl_rec_start        ,   -- OUT   std_logic;
1921 
           ctrl_rec_end             => ctrl_rec_end          ,   -- OUT   std_logic;
1922 
           ctrl_rec                 => ctrl_rec              ,   -- OUT   std_logic_vector(16-1 downto 0);
1923 
           ctrl_rec_stop            => ctrl_rec_stop         ,   -- IN    std_logic;
1924 
 
1925 
           -- DLM Tx
1926 
           dlm2send_va              => dlm2send_va           ,   -- IN    std_logic;
1927 
           dlm2send_type            => dlm2send_type         ,   -- IN    std_logic_vector(4-1 downto 0);
1928 
 
1929 
           -- DLM Rx
1930 
           dlm_rec_va               => dlm_rec_va            ,   -- OUT   std_logic;
1931 
           dlm_rec_type             => dlm_rec_type          ,   -- OUT   std_logic_vector(4-1 downto 0);
1932 
 
1933 
           -- dummy pin input  !!!! not really exists
1934 
           dummy_pin_in             => "000",  -- dummy_pin_in          ,   -- IN    std_logic_vector(3-1 downto 0);
1935 
--           dummy_pin_in             => dummy_pin_in          ,   -- IN    std_logic_vector(3-1 downto 0);
1936 
 
1937 
           -- Common interface
1938 
           link_tx_clk              => link_tx_clk           ,   -- OUT   std_logic;
1939 
           link_rx_clk              => link_rx_clk           ,   -- OUT   std_logic;
1940 
           link_active              => link_active           ,   -- OUT   std_logic_vector(2-1 downto 0);
1941 
           clk                      => protocol_clk          ,   -- IN    std_logic;
1942 
           res_n                    => protocol_res_n            -- IN    std_logic
1943 
      );
1944 
 
1945 
 
1946 
  end generate;
1947 
 
1948 
 
1949 
end Behavioral;

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