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[/] [pcie_sg_dma/] [branches/] [Virtex6/] [ML605_ISE13.3/] [MySource/] [Interrupts.vhd] - Blame information for rev 13

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----------------------------------------------------------------------------------
-- Company: 
-- Engineer: 
-- 
-- Design Name: 
-- Module Name:    Interrupts - Behavioral 
-- Project Name: 
-- Target Devices: 
-- Tool versions: 
-- Description: 
--
-- Dependencies: 
--
-- Revision: 
-- Revision 1.00 - File Created  14.05.2007
-- 
-- Revision 1.10 - Msg Tag incremented.  20.07.2007
-- 
-- Additional Comments: 
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
 
library work;
use work.abb64Package.all;
 
---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
 
entity Interrupts is
    port (
      -- System Interrupt register from Registers module
      Sys_IRQ                     : IN  std_logic_vector(C_DBUS_WIDTH-1   downto 0);
 
      -- Interrupt generator signals
      IG_Reset                    : IN  std_logic;
      IG_Host_Clear               : IN  std_logic;
      IG_Latency                  : IN  std_logic_vector(C_DBUS_WIDTH-1   downto 0);
      IG_Num_Assert               : OUT std_logic_vector(C_DBUS_WIDTH-1   downto 0);
      IG_Num_Deassert             : OUT std_logic_vector(C_DBUS_WIDTH-1   downto 0);
      IG_Asserting                : OUT std_logic;
 
 
      -- Interrupt Interface 
      cfg_interrupt_n             : OUT std_logic;
      cfg_interrupt_rdy_n         : IN  std_logic;
      cfg_interrupt_mmenable      : IN  std_logic_VECTOR(2 downto 0);
      cfg_interrupt_msienable     : IN  std_logic;
      cfg_interrupt_di            : OUT std_logic_VECTOR(7 downto 0);
      cfg_interrupt_do            : IN  std_logic_VECTOR(7 downto 0);
      cfg_interrupt_assert_n      : OUT std_logic;
 
      -- Irpt Channel
      Irpt_Req                    : OUT std_logic;
      Irpt_RE                     : IN  std_logic;
      Irpt_Qout                   : OUT std_logic_vector(C_CHANNEL_BUF_WIDTH-1 downto 0);
 
      -- Clock and reset
      trn_clk                     : IN  std_logic;
      trn_reset_n                 : IN  std_logic
 
    );
end Interrupts;
 
 
architecture Behavioral of Interrupts is
 
  -- State machine: Interrupt control
  type IrptStates is              ( IntST_RST
                                  , IntST_Idle
                                  , IntST_Asserting
                                  , IntST_Asserted
                                  , IntST_Deasserting
                                  );
 
  signal edge_Intrpt_State        : IrptStates;
  signal level_Intrpt_State       : IrptStates;
 
  signal cfg_interrupt_n_i        : std_logic;
  signal cfg_interrupt_rdy_n_i    : std_logic;
  signal cfg_interrupt_di_i       : std_logic_vector(7 downto 0);
  signal cfg_interrupt_assert_n_i : std_logic;
 
  signal edge_Irpt_Req_i          : std_logic;
  signal level_Irpt_Req_i         : std_logic;
 
  signal Irpt_RE_i                : std_logic;
  signal Irpt_Qout_i              : std_logic_vector(C_CHANNEL_BUF_WIDTH-1 downto 0)
                                  := (OTHERS=>'0');
 
  signal Msg_Tag_Lo               : std_logic_vector( 3 downto 0);
  signal Msg_Code                 : std_logic_vector( 7 downto 0);
 
  signal edge_MsgCode_is_ASSERT   : std_logic;
  signal level_MsgCode_is_ASSERT  : std_logic;
 
  signal Interrupts_ORed          : std_logic;
 
  -- Interrupt Generator 
  signal IG_Trigger_i             : std_logic;
 
  -- Interrupt Generator Counter
  signal IG_Counter               : std_logic_vector(C_CNT_GINT_WIDTH-1 downto 0);
  signal IG_Run                   : std_logic;
 
  -- Interrupt Generator Statistic: Assert number
  signal IG_Num_Assert_i          : std_logic_vector(C_DBUS_WIDTH-1   downto 0);
 
  -- Interrupt Generator Statistic: Deassert number
  signal IG_Num_Deassert_i        : std_logic_vector(C_DBUS_WIDTH-1   downto 0);
 
  -- Interrupt Generator indicator
  signal IG_Asserting_i           : std_logic;
 
 
begin
 
  -- Interrupt interface
  -- cfg_interrupt_n should be explicitly clarified!
  cfg_interrupt_assert_n          <= cfg_interrupt_assert_n_i;
  cfg_interrupt_rdy_n_i           <= cfg_interrupt_rdy_n;
  -- Only Legacy IntA for the moment ...
  cfg_interrupt_di                <= cfg_interrupt_di_i;
  cfg_interrupt_di_i              <= (Others=>'0');
 
  -- Channel mode interface.
  Irpt_RE_i       <= Irpt_RE;
  Irpt_Qout       <= Irpt_Qout_i;
 
 
--  ---------------------------------------------------
--  emulates a channel buffer output
--     Note: Type not shows in this buffer
--
--  127 ~  97 : reserved
--         96 : reserved
--         95 : reserved
--         94 : Valid
--   93 ~  35 : reserved
--   34 ~  27 : Msg code
--   26 ~  19 : Tag
--
--   18 ~  17 : Format
--   16 ~  14 : TC
--         13 : TD
--         12 : EP
--   11 ~  10 : Attribute
--    9 ~   0 : Length
-- 
  Irpt_Qout_i(C_CHBUF_QVALID_BIT)                                       <= '1';
  Irpt_Qout_i(C_CHBUF_TAG_BIT_TOP downto C_CHBUF_TAG_BIT_BOT)           <= C_MSG_TAG_HI & Msg_Tag_Lo;
  Irpt_Qout_i(C_CHBUF_MSG_CODE_BIT_TOP downto C_CHBUF_MSG_CODE_BIT_BOT) <= Msg_Code;
  Irpt_Qout_i(C_CHBUF_FMT_BIT_TOP downto C_CHBUF_FMT_BIT_BOT)           <= C_FMT4_NO_DATA;
  Irpt_Qout_i(C_CHBUF_LENG_BIT_TOP downto C_CHBUF_LENG_BIT_BOT)         <= C_ALL_ZEROS(C_CHBUF_LENG_BIT_TOP downto C_CHBUF_LENG_BIT_BOT);
 
 
 
-- ---------------------------------------------------------------
-- All Interrups are OR'ed
--
   Syn_Interrupts_ORed:
   process ( trn_clk )
   begin
      if trn_clk'event and trn_clk = '1' then
         if Sys_IRQ(C_NUM_OF_INTERRUPTS-1 downto 0)
              = C_ALL_ZEROS(C_NUM_OF_INTERRUPTS-1 downto 0)
            then
            Interrupts_ORed      <= '0';
         else
            Interrupts_ORed      <= '1';
         end if;
      end if;
   end process;
 
 
 
-------------------------------------------
---- Cfg Interface mode
-------------------------------------------
 Gen_Cfg_Irpt: if USE_CFG_INTERRUPT generate
 
   cfg_interrupt_n      <= cfg_interrupt_n_i;
   Irpt_Req             <= '0';               -- Cfg interface mode, channel disabled.
   Msg_Code             <= (Others=>'0');
 
   States_Machine_Irpt:
   process ( trn_clk, trn_reset_n)
   begin
      if trn_reset_n = '0' then
         edge_Intrpt_State      <= IntST_RST;
         cfg_interrupt_n_i <= '1';
         cfg_interrupt_assert_n_i  <= '1';
 
      elsif trn_clk'event and trn_clk = '1' then
 
        case edge_Intrpt_State is
 
          when IntST_RST =>
              edge_Intrpt_State      <= IntST_Idle;
              cfg_interrupt_n_i <= '1';
              cfg_interrupt_assert_n_i  <= '1';
 
          when IntST_Idle =>
            if Interrupts_ORed='1' then
              edge_Intrpt_State      <= IntST_Asserting;
              cfg_interrupt_n_i <= '0';
              cfg_interrupt_assert_n_i  <= '0';
            else
              edge_Intrpt_State      <= IntST_Idle;
              cfg_interrupt_n_i <= '1';
              cfg_interrupt_assert_n_i  <= '1';
            end if;
 
          when IntST_Asserting =>
            if cfg_interrupt_rdy_n='1' then
              edge_Intrpt_State      <= IntST_Asserting;
              cfg_interrupt_n_i <= '0';
              cfg_interrupt_assert_n_i  <= '0';
            else
              edge_Intrpt_State      <= IntST_Asserted;
              cfg_interrupt_n_i <= '1';
              cfg_interrupt_assert_n_i  <= '0';
            end if;
 
 
          when IntST_Asserted =>
            if Interrupts_ORed='0' then
              edge_Intrpt_State      <= IntST_Deasserting;
              cfg_interrupt_n_i <= '0';
              cfg_interrupt_assert_n_i  <= '1';
            else
              edge_Intrpt_State      <= IntST_Asserted;
              cfg_interrupt_n_i <= '1';
              cfg_interrupt_assert_n_i  <= '0';
            end if;
 
 
          when IntST_Deasserting =>
            if Irpt_RE_i='0' then
              edge_Intrpt_State      <= IntST_Deasserting;
              cfg_interrupt_n_i <= '0';
              cfg_interrupt_assert_n_i  <= '1';
            else
              edge_Intrpt_State      <= IntST_Idle;
              cfg_interrupt_n_i <= '1';
              cfg_interrupt_assert_n_i  <= '1';
            end if;
 
 
          when OTHERS  =>
              edge_Intrpt_State      <= IntST_Idle;
              cfg_interrupt_n_i <= '1';
              cfg_interrupt_assert_n_i  <= '1';
 
        end case;
 
      end if;
   end process;
 
 end generate;
 
 
----------------------------------------------
--  Channel mode
----------------------------------------------
 Gen_Chan_MSI: if not USE_CFG_INTERRUPT generate
 
   cfg_interrupt_n      <= '1';          -- Channel mode, cfg interface disabled.
   cfg_interrupt_assert_n_i  <= '1';
 
   Irpt_Req             <= edge_Irpt_Req_i;
   Msg_Code             <= C_MSGCODE_INTA when edge_MsgCode_is_ASSERT='1'
                           else C_MSGCODE_INTA_N;
 
   -- State Machine for edge interrupts
   State_Machine_edge_Irpt:
   process ( trn_clk, trn_reset_n)
   begin
      if trn_reset_n = '0' then
         edge_Intrpt_State      <= IntST_RST;
         edge_Irpt_Req_i        <= '0';
         edge_MsgCode_is_ASSERT <= '0';
 
      elsif trn_clk'event and trn_clk = '1' then
 
        case edge_Intrpt_State is
 
          when IntST_RST =>
              edge_Intrpt_State      <= IntST_Idle;
              edge_Irpt_Req_i        <= '0';
                        edge_MsgCode_is_ASSERT <= '0';
 
          when IntST_Idle =>
            if Interrupts_ORed='1' then
              edge_Intrpt_State      <= IntST_Asserting;
              edge_Irpt_Req_i        <= '1';
                        edge_MsgCode_is_ASSERT <= edge_MsgCode_is_ASSERT;  -- '1';
            else
              edge_Intrpt_State      <= IntST_Idle;
              edge_Irpt_Req_i        <= '0';
                        edge_MsgCode_is_ASSERT <= edge_MsgCode_is_ASSERT;
            end if;
 
          when IntST_Asserting =>
            if Irpt_RE_i='0' then
              edge_Intrpt_State      <= IntST_Asserting;
              edge_Irpt_Req_i        <= '1';
                        edge_MsgCode_is_ASSERT <= edge_MsgCode_is_ASSERT; -- '1';
            else
              edge_Intrpt_State      <= IntST_Asserted;
              edge_Irpt_Req_i        <= '0';
                        edge_MsgCode_is_ASSERT <= '1';
            end if;
 
          when IntST_Asserted =>
            if Interrupts_ORed='0' then
              edge_Intrpt_State      <= IntST_Deasserting;
              edge_Irpt_Req_i        <= '1';
                        edge_MsgCode_is_ASSERT <= edge_MsgCode_is_ASSERT;  -- !!
            else
              edge_Intrpt_State      <= IntST_Asserted;
              edge_Irpt_Req_i        <= '0';
                        edge_MsgCode_is_ASSERT <= edge_MsgCode_is_ASSERT;  -- '1';
            end if;
 
          when IntST_Deasserting =>
            if Irpt_RE_i='0' then
              edge_Intrpt_State      <= IntST_Deasserting;
              edge_Irpt_Req_i        <= '1';
                        edge_MsgCode_is_ASSERT <= edge_MsgCode_is_ASSERT; -- '0';
            else
              edge_Intrpt_State      <= IntST_Idle;
              edge_Irpt_Req_i        <= '0';
                        edge_MsgCode_is_ASSERT <= '0';
            end if;
 
          when OTHERS  =>
              edge_Intrpt_State      <= IntST_Idle;
              edge_Irpt_Req_i        <= '0';
                        edge_MsgCode_is_ASSERT <= '0';
 
        end case;
 
      end if;
   end process;
 
 
 
 
   --  Tag of Msg TLP increments
   Sync_Msg_Tag_Increment:
   process ( trn_clk, trn_reset_n)
   begin
      if trn_reset_n = '0' then
         Msg_Tag_Lo        <= (Others=>'0');
 
      elsif trn_clk'event and trn_clk = '1' then
         if Irpt_RE_i = '1' then
            Msg_Tag_Lo  <=  Msg_Tag_Lo + '1';
         else
            Msg_Tag_Lo  <=  Msg_Tag_Lo;
         end if;
 
      end if;
   end process;
 
 
 end generate;   -- Gen_Chan_MSI: if not USE_CFG_INTERRUPT
 
 
 -- 
 --------------      Generate Interrupt Generator       ------------------
 --
 Gen_IG:  if IMP_INT_GENERATOR generate
 
   IG_Num_Assert   <= IG_Num_Assert_i;
   IG_Num_Deassert <= IG_Num_Deassert_i;
   IG_Asserting    <= IG_Asserting_i;
 
-- -------------------------------------------------------
-- FSM: generating interrupts
   FSM_Generate_Interrupts:
   process ( trn_clk, trn_reset_n)
   begin
      if trn_reset_n = '0' then
         IG_Counter    <= (Others=>'0');
 
      elsif trn_clk'event and trn_clk = '1' then
 
        if IG_Reset = '1' then
           IG_Counter    <= (Others=>'0');
        elsif IG_Counter /= C_ALL_ZEROS(C_CNT_GINT_WIDTH-1 downto 0) then
           IG_Counter    <= IG_Counter - '1';
        elsif IG_Run = '0' then
           IG_Counter    <= (Others=>'0');
        else
           IG_Counter    <= IG_Latency(C_CNT_GINT_WIDTH-1 downto 0);
        end if;
 
      end if;
   end process;
 
 
-- -------------------------------------------------------
-- Issuing: Interrupt trigger
   Synch_Interrupt_Trigger:
   process ( trn_clk, trn_reset_n)
   begin
      if trn_reset_n = '0' then
         IG_Trigger_i  <= '0';
 
      elsif trn_clk'event and trn_clk = '1' then
 
        if IG_Reset = '1' then
           IG_Trigger_i  <= '0';
        elsif IG_Counter = CONV_STD_LOGIC_VECTOR(1, C_CNT_GINT_WIDTH) then
           IG_Trigger_i  <= '1';
        else
           IG_Trigger_i  <= '0';
        end if;
 
      end if;
   end process;
 
 
-- -------------------------------------------------------
-- register: IG_Run
   Synch_IG_Run:
   process ( trn_clk, trn_reset_n)
   begin
      if trn_reset_n = '0' then
         IG_Run   <= '0';
 
      elsif trn_clk'event and trn_clk = '1' then
 
        if IG_Reset = '1' then
           IG_Run   <= '0';
        elsif IG_Latency(C_DBUS_WIDTH-1 downto 2)=C_ALL_ZEROS(C_DBUS_WIDTH-1 downto 2) then
           IG_Run   <= '0';
        else
           IG_Run   <= '1';
        end if;
 
      end if;
   end process;
 
 
-- -----------------------------------------------
-- Synchronous Register: IG_Num_Assert_i
   SysReg_IntGen_Number_of_Assert:
   process ( trn_clk, trn_reset_n)
   begin
      if trn_reset_n = '0' then
         IG_Num_Assert_i       <= (OTHERS => '0');
 
      elsif trn_clk'event and trn_clk = '1' then
 
        if IG_Reset='1' then
            IG_Num_Assert_i    <=  (OTHERS => '0');
        elsif IG_Trigger_i = '1'  then
            IG_Num_Assert_i    <=  IG_Num_Assert_i + '1';
        else
            IG_Num_Assert_i    <=  IG_Num_Assert_i;
        end if;
 
      end if;
   end process;
 
 
-- -----------------------------------------------
-- Synchronous Register: IG_Num_Deassert_i
   SysReg_IntGen_Number_of_Deassert:
   process ( trn_clk, trn_reset_n)
   begin
      if trn_reset_n = '0' then
         IG_Num_Deassert_i       <= (OTHERS => '0');
 
      elsif trn_clk'event and trn_clk = '1' then
 
        if IG_Reset='1' then
            IG_Num_Deassert_i    <=  (OTHERS => '0');
        elsif IG_Host_Clear='1' and IG_Asserting_i='1' then
            IG_Num_Deassert_i    <=  IG_Num_Deassert_i + '1';
        else
            IG_Num_Deassert_i    <=  IG_Num_Deassert_i;
        end if;
 
      end if;
   end process;
 
 
-- -----------------------------------------------
-- Synchronous Register: IG_Asserting_i
   SysReg_IntGen_IG_Asserting_i:
   process ( trn_clk, trn_reset_n)
   begin
      if trn_reset_n = '0' then
         IG_Asserting_i       <= '0';
 
      elsif trn_clk'event and trn_clk = '1' then
 
        if IG_Reset='1' then
            IG_Asserting_i    <=  '0';
        elsif IG_Asserting_i='0' and IG_Trigger_i='1' then
            IG_Asserting_i    <=  '1';
        elsif IG_Asserting_i='0' and IG_Trigger_i='0' then
            IG_Asserting_i    <=  '0';
        elsif IG_Asserting_i='1' and IG_Host_Clear='0' then
            IG_Asserting_i    <=  '1';
        elsif IG_Asserting_i='1' and IG_Host_Clear='1' then
            IG_Asserting_i    <=  '0';
        else
            IG_Asserting_i    <=  IG_Asserting_i;
        end if;
 
      end if;
   end process;
 
 end generate;
 
 
 -- 
 --------------    No Generation of Interrupt Generator     ----------------
 --
 
 NotGen_IG:  if not IMP_INT_GENERATOR generate
 
   IG_Num_Assert   <= (OTHERS=>'0');
   IG_Num_Deassert <= (OTHERS=>'0');
   IG_Asserting    <= '0';
 
 end generate;
 
end Behavioral;

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Subversion Repositories pcie_sg_dma

[/] [pcie_sg_dma/] [branches/] [Virtex6/] [ML605_ISE13.3/] [MySource/] [Interrupts.vhd] - Blame information for rev 13

Line No.	Rev	Author	Line
1	13	barabba	`----------------------------------------------------------------------------------`
2			`-- Company:`
3			`-- Engineer:`
4			`--`
5			`-- Design Name:`
6			`-- Module Name: Interrupts - Behavioral`
7			`-- Project Name:`
8			`-- Target Devices:`
9			`-- Tool versions:`
10			`-- Description:`
11			`--`
12			`-- Dependencies:`
13			`--`
14			`-- Revision:`
15			`-- Revision 1.00 - File Created 14.05.2007`
16			`--`
17			`-- Revision 1.10 - Msg Tag incremented. 20.07.2007`
18			`--`
19			`-- Additional Comments:`
20			`--`
21			`----------------------------------------------------------------------------------`
22			`library IEEE;`
23			`use IEEE.STD_LOGIC_1164.ALL;`
24			`use IEEE.STD_LOGIC_ARITH.ALL;`
25			`use IEEE.STD_LOGIC_UNSIGNED.ALL;`
26
27			`library work;`
28			`use work.abb64Package.all;`
29
30			`---- Uncomment the following library declaration if instantiating`
31			`---- any Xilinx primitives in this code.`
32			`--library UNISIM;`
33			`--use UNISIM.VComponents.all;`
34
35			`entity Interrupts is`
36			`port (`
37			`-- System Interrupt register from Registers module`
38			`Sys_IRQ : IN std_logic_vector(C_DBUS_WIDTH-1 downto 0);`
39
40			`-- Interrupt generator signals`
41			`IG_Reset : IN std_logic;`
42			`IG_Host_Clear : IN std_logic;`
43			`IG_Latency : IN std_logic_vector(C_DBUS_WIDTH-1 downto 0);`
44			`IG_Num_Assert : OUT std_logic_vector(C_DBUS_WIDTH-1 downto 0);`
45			`IG_Num_Deassert : OUT std_logic_vector(C_DBUS_WIDTH-1 downto 0);`
46			`IG_Asserting : OUT std_logic;`
47
48
49			`-- Interrupt Interface`
50			`cfg_interrupt_n : OUT std_logic;`
51			`cfg_interrupt_rdy_n : IN std_logic;`
52			`cfg_interrupt_mmenable : IN std_logic_VECTOR(2 downto 0);`
53			`cfg_interrupt_msienable : IN std_logic;`
54			`cfg_interrupt_di : OUT std_logic_VECTOR(7 downto 0);`
55			`cfg_interrupt_do : IN std_logic_VECTOR(7 downto 0);`
56			`cfg_interrupt_assert_n : OUT std_logic;`
57
58			`-- Irpt Channel`
59			`Irpt_Req : OUT std_logic;`
60			`Irpt_RE : IN std_logic;`
61			`Irpt_Qout : OUT std_logic_vector(C_CHANNEL_BUF_WIDTH-1 downto 0);`
62
63			`-- Clock and reset`
64			`trn_clk : IN std_logic;`
65			`trn_reset_n : IN std_logic`
66
67			`);`
68			`end Interrupts;`
69
70
71			`architecture Behavioral of Interrupts is`
72
73			`-- State machine: Interrupt control`
74			`type IrptStates is ( IntST_RST`
75			`, IntST_Idle`
76			`, IntST_Asserting`
77			`, IntST_Asserted`
78			`, IntST_Deasserting`
79			`);`
80
81			`signal edge_Intrpt_State : IrptStates;`
82			`signal level_Intrpt_State : IrptStates;`
83
84			`signal cfg_interrupt_n_i : std_logic;`
85			`signal cfg_interrupt_rdy_n_i : std_logic;`
86			`signal cfg_interrupt_di_i : std_logic_vector(7 downto 0);`
87			`signal cfg_interrupt_assert_n_i : std_logic;`
88
89			`signal edge_Irpt_Req_i : std_logic;`
90			`signal level_Irpt_Req_i : std_logic;`
91
92			`signal Irpt_RE_i : std_logic;`
93			`signal Irpt_Qout_i : std_logic_vector(C_CHANNEL_BUF_WIDTH-1 downto 0)`
94			`:= (OTHERS=>'0');`
95
96			`signal Msg_Tag_Lo : std_logic_vector( 3 downto 0);`
97			`signal Msg_Code : std_logic_vector( 7 downto 0);`
98
99			`signal edge_MsgCode_is_ASSERT : std_logic;`
100			`signal level_MsgCode_is_ASSERT : std_logic;`
101
102			`signal Interrupts_ORed : std_logic;`
103
104			`-- Interrupt Generator`
105			`signal IG_Trigger_i : std_logic;`
106
107			`-- Interrupt Generator Counter`
108			`signal IG_Counter : std_logic_vector(C_CNT_GINT_WIDTH-1 downto 0);`
109			`signal IG_Run : std_logic;`
110
111			`-- Interrupt Generator Statistic: Assert number`
112			`signal IG_Num_Assert_i : std_logic_vector(C_DBUS_WIDTH-1 downto 0);`
113
114			`-- Interrupt Generator Statistic: Deassert number`
115			`signal IG_Num_Deassert_i : std_logic_vector(C_DBUS_WIDTH-1 downto 0);`
116
117			`-- Interrupt Generator indicator`
118			`signal IG_Asserting_i : std_logic;`
119
120
121			`begin`
122
123			`-- Interrupt interface`
124			`-- cfg_interrupt_n should be explicitly clarified!`
125			`cfg_interrupt_assert_n <= cfg_interrupt_assert_n_i;`
126			`cfg_interrupt_rdy_n_i <= cfg_interrupt_rdy_n;`
127			`-- Only Legacy IntA for the moment ...`
128			`cfg_interrupt_di <= cfg_interrupt_di_i;`
129			`cfg_interrupt_di_i <= (Others=>'0');`
130
131			`-- Channel mode interface.`
132			`Irpt_RE_i <= Irpt_RE;`
133			`Irpt_Qout <= Irpt_Qout_i;`
134
135
136			`-- ---------------------------------------------------`
137			`-- emulates a channel buffer output`
138			`-- Note: Type not shows in this buffer`
139			`--`
140			`-- 127 ~ 97 : reserved`
141			`-- 96 : reserved`
142			`-- 95 : reserved`
143			`-- 94 : Valid`
144			`-- 93 ~ 35 : reserved`
145			`-- 34 ~ 27 : Msg code`
146			`-- 26 ~ 19 : Tag`
147			`--`
148			`-- 18 ~ 17 : Format`
149			`-- 16 ~ 14 : TC`
150			`-- 13 : TD`
151			`-- 12 : EP`
152			`-- 11 ~ 10 : Attribute`
153			`-- 9 ~ 0 : Length`
154			`--`
155			`Irpt_Qout_i(C_CHBUF_QVALID_BIT) <= '1';`
156			`Irpt_Qout_i(C_CHBUF_TAG_BIT_TOP downto C_CHBUF_TAG_BIT_BOT) <= C_MSG_TAG_HI & Msg_Tag_Lo;`
157			`Irpt_Qout_i(C_CHBUF_MSG_CODE_BIT_TOP downto C_CHBUF_MSG_CODE_BIT_BOT) <= Msg_Code;`
158			`Irpt_Qout_i(C_CHBUF_FMT_BIT_TOP downto C_CHBUF_FMT_BIT_BOT) <= C_FMT4_NO_DATA;`
159			`Irpt_Qout_i(C_CHBUF_LENG_BIT_TOP downto C_CHBUF_LENG_BIT_BOT) <= C_ALL_ZEROS(C_CHBUF_LENG_BIT_TOP downto C_CHBUF_LENG_BIT_BOT);`
160
161
162
163			`-- ---------------------------------------------------------------`
164			`-- All Interrups are OR'ed`
165			`--`
166			`Syn_Interrupts_ORed:`
167			`process ( trn_clk )`
168			`begin`
169			`if trn_clk'event and trn_clk = '1' then`
170			`if Sys_IRQ(C_NUM_OF_INTERRUPTS-1 downto 0)`
171			`= C_ALL_ZEROS(C_NUM_OF_INTERRUPTS-1 downto 0)`
172			`then`
173			`Interrupts_ORed <= '0';`
174			`else`
175			`Interrupts_ORed <= '1';`
176			`end if;`
177			`end if;`
178			`end process;`
179
180
181
182			`-------------------------------------------`
183			`---- Cfg Interface mode`
184			`-------------------------------------------`
185			`Gen_Cfg_Irpt: if USE_CFG_INTERRUPT generate`
186
187			`cfg_interrupt_n <= cfg_interrupt_n_i;`
188			`Irpt_Req <= '0'; -- Cfg interface mode, channel disabled.`
189			`Msg_Code <= (Others=>'0');`
190
191			`States_Machine_Irpt:`
192			`process ( trn_clk, trn_reset_n)`
193			`begin`
194			`if trn_reset_n = '0' then`
195			`edge_Intrpt_State <= IntST_RST;`
196			`cfg_interrupt_n_i <= '1';`
197			`cfg_interrupt_assert_n_i <= '1';`
198
199			`elsif trn_clk'event and trn_clk = '1' then`
200
201			`case edge_Intrpt_State is`
202
203			`when IntST_RST =>`
204			`edge_Intrpt_State <= IntST_Idle;`
205			`cfg_interrupt_n_i <= '1';`
206			`cfg_interrupt_assert_n_i <= '1';`
207
208			`when IntST_Idle =>`
209			`if Interrupts_ORed='1' then`
210			`edge_Intrpt_State <= IntST_Asserting;`
211			`cfg_interrupt_n_i <= '0';`
212			`cfg_interrupt_assert_n_i <= '0';`
213			`else`
214			`edge_Intrpt_State <= IntST_Idle;`
215			`cfg_interrupt_n_i <= '1';`
216			`cfg_interrupt_assert_n_i <= '1';`
217			`end if;`
218
219			`when IntST_Asserting =>`
220			`if cfg_interrupt_rdy_n='1' then`
221			`edge_Intrpt_State <= IntST_Asserting;`
222			`cfg_interrupt_n_i <= '0';`
223			`cfg_interrupt_assert_n_i <= '0';`
224			`else`
225			`edge_Intrpt_State <= IntST_Asserted;`
226			`cfg_interrupt_n_i <= '1';`
227			`cfg_interrupt_assert_n_i <= '0';`
228			`end if;`
229
230
231			`when IntST_Asserted =>`
232			`if Interrupts_ORed='0' then`
233			`edge_Intrpt_State <= IntST_Deasserting;`
234			`cfg_interrupt_n_i <= '0';`
235			`cfg_interrupt_assert_n_i <= '1';`
236			`else`
237			`edge_Intrpt_State <= IntST_Asserted;`
238			`cfg_interrupt_n_i <= '1';`
239			`cfg_interrupt_assert_n_i <= '0';`
240			`end if;`
241
242
243			`when IntST_Deasserting =>`
244			`if Irpt_RE_i='0' then`
245			`edge_Intrpt_State <= IntST_Deasserting;`
246			`cfg_interrupt_n_i <= '0';`
247			`cfg_interrupt_assert_n_i <= '1';`
248			`else`
249			`edge_Intrpt_State <= IntST_Idle;`
250			`cfg_interrupt_n_i <= '1';`
251			`cfg_interrupt_assert_n_i <= '1';`
252			`end if;`
253
254
255			`when OTHERS =>`
256			`edge_Intrpt_State <= IntST_Idle;`
257			`cfg_interrupt_n_i <= '1';`
258			`cfg_interrupt_assert_n_i <= '1';`
259
260			`end case;`
261
262			`end if;`
263			`end process;`
264
265			`end generate;`
266
267
268			`----------------------------------------------`
269			`-- Channel mode`
270			`----------------------------------------------`
271			`Gen_Chan_MSI: if not USE_CFG_INTERRUPT generate`
272
273			`cfg_interrupt_n <= '1'; -- Channel mode, cfg interface disabled.`
274			`cfg_interrupt_assert_n_i <= '1';`
275
276			`Irpt_Req <= edge_Irpt_Req_i;`
277			`Msg_Code <= C_MSGCODE_INTA when edge_MsgCode_is_ASSERT='1'`
278			`else C_MSGCODE_INTA_N;`
279
280			`-- State Machine for edge interrupts`
281			`State_Machine_edge_Irpt:`
282			`process ( trn_clk, trn_reset_n)`
283			`begin`
284			`if trn_reset_n = '0' then`
285			`edge_Intrpt_State <= IntST_RST;`
286			`edge_Irpt_Req_i <= '0';`
287			`edge_MsgCode_is_ASSERT <= '0';`
288
289			`elsif trn_clk'event and trn_clk = '1' then`
290
291			`case edge_Intrpt_State is`
292
293			`when IntST_RST =>`
294			`edge_Intrpt_State <= IntST_Idle;`
295			`edge_Irpt_Req_i <= '0';`
296			`edge_MsgCode_is_ASSERT <= '0';`
297
298			`when IntST_Idle =>`
299			`if Interrupts_ORed='1' then`
300			`edge_Intrpt_State <= IntST_Asserting;`
301			`edge_Irpt_Req_i <= '1';`
302			`edge_MsgCode_is_ASSERT <= edge_MsgCode_is_ASSERT; -- '1';`
303			`else`
304			`edge_Intrpt_State <= IntST_Idle;`
305			`edge_Irpt_Req_i <= '0';`
306			`edge_MsgCode_is_ASSERT <= edge_MsgCode_is_ASSERT;`
307			`end if;`
308
309			`when IntST_Asserting =>`
310			`if Irpt_RE_i='0' then`
311			`edge_Intrpt_State <= IntST_Asserting;`
312			`edge_Irpt_Req_i <= '1';`
313			`edge_MsgCode_is_ASSERT <= edge_MsgCode_is_ASSERT; -- '1';`
314			`else`
315			`edge_Intrpt_State <= IntST_Asserted;`
316			`edge_Irpt_Req_i <= '0';`
317			`edge_MsgCode_is_ASSERT <= '1';`
318			`end if;`
319
320			`when IntST_Asserted =>`
321			`if Interrupts_ORed='0' then`
322			`edge_Intrpt_State <= IntST_Deasserting;`
323			`edge_Irpt_Req_i <= '1';`
324			`edge_MsgCode_is_ASSERT <= edge_MsgCode_is_ASSERT; -- !!`
325			`else`
326			`edge_Intrpt_State <= IntST_Asserted;`
327			`edge_Irpt_Req_i <= '0';`
328			`edge_MsgCode_is_ASSERT <= edge_MsgCode_is_ASSERT; -- '1';`
329			`end if;`
330
331			`when IntST_Deasserting =>`
332			`if Irpt_RE_i='0' then`
333			`edge_Intrpt_State <= IntST_Deasserting;`
334			`edge_Irpt_Req_i <= '1';`
335			`edge_MsgCode_is_ASSERT <= edge_MsgCode_is_ASSERT; -- '0';`
336			`else`
337			`edge_Intrpt_State <= IntST_Idle;`
338			`edge_Irpt_Req_i <= '0';`
339			`edge_MsgCode_is_ASSERT <= '0';`
340			`end if;`
341
342			`when OTHERS =>`
343			`edge_Intrpt_State <= IntST_Idle;`
344			`edge_Irpt_Req_i <= '0';`
345			`edge_MsgCode_is_ASSERT <= '0';`
346
347			`end case;`
348
349			`end if;`
350			`end process;`
351
352
353
354
355			`-- Tag of Msg TLP increments`
356			`Sync_Msg_Tag_Increment:`
357			`process ( trn_clk, trn_reset_n)`
358			`begin`
359			`if trn_reset_n = '0' then`
360			`Msg_Tag_Lo <= (Others=>'0');`
361
362			`elsif trn_clk'event and trn_clk = '1' then`
363			`if Irpt_RE_i = '1' then`
364			`Msg_Tag_Lo <= Msg_Tag_Lo + '1';`
365			`else`
366			`Msg_Tag_Lo <= Msg_Tag_Lo;`
367			`end if;`
368
369			`end if;`
370			`end process;`
371
372
373			`end generate; -- Gen_Chan_MSI: if not USE_CFG_INTERRUPT`
374
375
376			`--`
377			`-------------- Generate Interrupt Generator ------------------`
378			`--`
379			`Gen_IG: if IMP_INT_GENERATOR generate`
380
381			`IG_Num_Assert <= IG_Num_Assert_i;`
382			`IG_Num_Deassert <= IG_Num_Deassert_i;`
383			`IG_Asserting <= IG_Asserting_i;`
384
385			`-- -------------------------------------------------------`
386			`-- FSM: generating interrupts`
387			`FSM_Generate_Interrupts:`
388			`process ( trn_clk, trn_reset_n)`
389			`begin`
390			`if trn_reset_n = '0' then`
391			`IG_Counter <= (Others=>'0');`
392
393			`elsif trn_clk'event and trn_clk = '1' then`
394
395			`if IG_Reset = '1' then`
396			`IG_Counter <= (Others=>'0');`
397			`elsif IG_Counter /= C_ALL_ZEROS(C_CNT_GINT_WIDTH-1 downto 0) then`
398			`IG_Counter <= IG_Counter - '1';`
399			`elsif IG_Run = '0' then`
400			`IG_Counter <= (Others=>'0');`
401			`else`
402			`IG_Counter <= IG_Latency(C_CNT_GINT_WIDTH-1 downto 0);`
403			`end if;`
404
405			`end if;`
406			`end process;`
407
408
409			`-- -------------------------------------------------------`
410			`-- Issuing: Interrupt trigger`
411			`Synch_Interrupt_Trigger:`
412			`process ( trn_clk, trn_reset_n)`
413			`begin`
414			`if trn_reset_n = '0' then`
415			`IG_Trigger_i <= '0';`
416
417			`elsif trn_clk'event and trn_clk = '1' then`
418
419			`if IG_Reset = '1' then`
420			`IG_Trigger_i <= '0';`
421			`elsif IG_Counter = CONV_STD_LOGIC_VECTOR(1, C_CNT_GINT_WIDTH) then`
422			`IG_Trigger_i <= '1';`
423			`else`
424			`IG_Trigger_i <= '0';`
425			`end if;`
426
427			`end if;`
428			`end process;`
429
430
431			`-- -------------------------------------------------------`
432			`-- register: IG_Run`
433			`Synch_IG_Run:`
434			`process ( trn_clk, trn_reset_n)`
435			`begin`
436			`if trn_reset_n = '0' then`
437			`IG_Run <= '0';`
438
439			`elsif trn_clk'event and trn_clk = '1' then`
440
441			`if IG_Reset = '1' then`
442			`IG_Run <= '0';`
443			`elsif IG_Latency(C_DBUS_WIDTH-1 downto 2)=C_ALL_ZEROS(C_DBUS_WIDTH-1 downto 2) then`
444			`IG_Run <= '0';`
445			`else`
446			`IG_Run <= '1';`
447			`end if;`
448
449			`end if;`
450			`end process;`
451
452
453			`-- -----------------------------------------------`
454			`-- Synchronous Register: IG_Num_Assert_i`
455			`SysReg_IntGen_Number_of_Assert:`
456			`process ( trn_clk, trn_reset_n)`
457			`begin`
458			`if trn_reset_n = '0' then`
459			`IG_Num_Assert_i <= (OTHERS => '0');`
460
461			`elsif trn_clk'event and trn_clk = '1' then`
462
463			`if IG_Reset='1' then`
464			`IG_Num_Assert_i <= (OTHERS => '0');`
465			`elsif IG_Trigger_i = '1' then`
466			`IG_Num_Assert_i <= IG_Num_Assert_i + '1';`
467			`else`
468			`IG_Num_Assert_i <= IG_Num_Assert_i;`
469			`end if;`
470
471			`end if;`
472			`end process;`
473
474
475			`-- -----------------------------------------------`
476			`-- Synchronous Register: IG_Num_Deassert_i`
477			`SysReg_IntGen_Number_of_Deassert:`
478			`process ( trn_clk, trn_reset_n)`
479			`begin`
480			`if trn_reset_n = '0' then`
481			`IG_Num_Deassert_i <= (OTHERS => '0');`
482
483			`elsif trn_clk'event and trn_clk = '1' then`
484
485			`if IG_Reset='1' then`
486			`IG_Num_Deassert_i <= (OTHERS => '0');`
487			`elsif IG_Host_Clear='1' and IG_Asserting_i='1' then`
488			`IG_Num_Deassert_i <= IG_Num_Deassert_i + '1';`
489			`else`
490			`IG_Num_Deassert_i <= IG_Num_Deassert_i;`
491			`end if;`
492
493			`end if;`
494			`end process;`
495
496
497			`-- -----------------------------------------------`
498			`-- Synchronous Register: IG_Asserting_i`
499			`SysReg_IntGen_IG_Asserting_i:`
500			`process ( trn_clk, trn_reset_n)`
501			`begin`
502			`if trn_reset_n = '0' then`
503			`IG_Asserting_i <= '0';`
504
505			`elsif trn_clk'event and trn_clk = '1' then`
506
507			`if IG_Reset='1' then`
508			`IG_Asserting_i <= '0';`
509			`elsif IG_Asserting_i='0' and IG_Trigger_i='1' then`
510			`IG_Asserting_i <= '1';`
511			`elsif IG_Asserting_i='0' and IG_Trigger_i='0' then`
512			`IG_Asserting_i <= '0';`
513			`elsif IG_Asserting_i='1' and IG_Host_Clear='0' then`
514			`IG_Asserting_i <= '1';`
515			`elsif IG_Asserting_i='1' and IG_Host_Clear='1' then`
516			`IG_Asserting_i <= '0';`
517			`else`
518			`IG_Asserting_i <= IG_Asserting_i;`
519			`end if;`
520
521			`end if;`
522			`end process;`
523
524			`end generate;`
525
526
527			`--`
528			`-------------- No Generation of Interrupt Generator ----------------`
529			`--`
530
531			`NotGen_IG: if not IMP_INT_GENERATOR generate`
532
533			`IG_Num_Assert <= (OTHERS=>'0');`
534			`IG_Num_Deassert <= (OTHERS=>'0');`
535			`IG_Asserting <= '0';`
536
537			`end generate;`
538
539			`end Behavioral;`