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[/] [pcie_sg_dma/] [branches/] [Virtex6/] [ML605_ISE13.3/] [MySource/] [tlpControl.vhd] - Blame information for rev 13

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Line No. Rev Author Line
1 13 barabba 
----------------------------------------------------------------------------------
2 
-- Company:
3 
-- Engineer:
4 
--
5 
-- Create Date:    11:09:49 10/18/2006
6 
-- Design Name:
7 
-- Module Name:    tlpControl - Behavioral
8 
-- Project Name:
9 
-- Target Devices:
10 
-- Tool versions:
11 
-- Description:
12 
--
13 
-- Dependencies:
14 
--
15 
-- Revision 1.20 - Memory space repartitioned.   13.07.2007
16 
--
17 
-- Revision 1.10 - x4 timing constraints met.   02.02.2007
18 
--
19 
-- Revision 1.06 - Timing improved.     17.01.2007
20 
--
21 
-- Revision 1.04 - FIFO added.     20.12.2006
22 
--
23 
-- Revision 1.02 - second release. 14.12.2006
24 
--
25 
-- Revision 1.00 - first release.  18.10.2006
26 
--
27 
-- Additional Comments:
28 
--
29 
----------------------------------------------------------------------------------
30 
 
31 
library IEEE;
32 
use IEEE.STD_LOGIC_1164.ALL;
33 
use IEEE.STD_LOGIC_ARITH.ALL;
34 
use IEEE.STD_LOGIC_UNSIGNED.ALL;
35 
 
36 
library work;
37 
use work.abb64Package.all;
38 
--use work.busmacro_xc4v_pkg.all;
39 
 
40 
-- Uncomment the following library declaration if instantiating
41 
-- any Xilinx primitives in this code.
42 
--library UNISIM;
43 
--use UNISIM.VComponents.all;
44 
 
45 
entity tlpControl is
46 
    port (
47 
 
48 
      --  Test pin, emulating DDR data flow discontinuity
49 
      mbuf_UserFull            : IN   std_logic;
50 
      trn_Blinker              : OUT  std_logic;
51 
 
52 
      -- DCB protocol interface
53 
      protocol_link_act        : IN  std_logic_vector(2-1 downto 0);
54 
      protocol_rst             : OUT std_logic;
55 
 
56 
      -- Interrupter triggers
57 
      DAQ_irq                  : IN  std_logic;
58 
      CTL_irq                  : IN  std_logic;
59 
      DLM_irq                  : IN  std_logic;
60 
 
61 
      -- Fabric side: CTL Rx
62 
      ctl_rv                   : OUT std_logic;
63 
      ctl_rd                   : OUT std_logic_vector(C_DBUS_WIDTH/2-1 downto 0);
64 
 
65 
      -- Fabric side: CTL Tx
66 
      ctl_ttake                : OUT std_logic;
67 
      ctl_tv                   : IN  std_logic;
68 
      ctl_td                   : IN  std_logic_vector(C_DBUS_WIDTH/2-1 downto 0);
69 
      ctl_tstop                : OUT std_logic;
70 
 
71 
      ctl_reset                : OUT std_logic;
72 
      ctl_status               : IN  std_logic_vector(C_DBUS_WIDTH/2-1 downto 0);
73 
 
74 
      -- Fabric side: DLM Rx
75 
      dlm_tv                   : OUT std_logic;
76 
      dlm_td                   : OUT std_logic_vector(C_DBUS_WIDTH/2-1 downto 0);
77 
 
78 
      -- Fabric side: DLM Tx
79 
      dlm_rv                   : IN  std_logic;
80 
      dlm_rd                   : IN  std_logic_vector(C_DBUS_WIDTH/2-1 downto 0);
81 
 
82 
 
83 
      -- SIMONE Register: PC-->FPGA
84 
      reg01_tv                   : OUT std_logic;
85 
      reg01_td                   : OUT std_logic_vector(C_DBUS_WIDTH/2-1 downto 0);
86 
      reg02_tv                   : OUT std_logic;
87 
      reg02_td                   : OUT std_logic_vector(C_DBUS_WIDTH/2-1 downto 0);
88 
      reg03_tv                   : OUT std_logic;
89 
      reg03_td                   : OUT std_logic_vector(C_DBUS_WIDTH/2-1 downto 0);
90 
      reg04_tv                   : OUT std_logic;
91 
      reg04_td                   : OUT std_logic_vector(C_DBUS_WIDTH/2-1 downto 0);
92 
      reg05_tv                   : OUT std_logic;
93 
      reg05_td                   : OUT std_logic_vector(C_DBUS_WIDTH/2-1 downto 0);
94 
      reg06_tv                   : OUT std_logic;
95 
      reg06_td                   : OUT std_logic_vector(C_DBUS_WIDTH/2-1 downto 0);
96 
      reg07_tv                   : OUT std_logic;
97 
      reg07_td                   : OUT std_logic_vector(C_DBUS_WIDTH/2-1 downto 0);
98 
      reg08_tv                   : OUT std_logic;
99 
      reg08_td                   : OUT std_logic_vector(C_DBUS_WIDTH/2-1 downto 0);
100 
      reg09_tv                   : OUT std_logic;
101 
      reg09_td                   : OUT std_logic_vector(C_DBUS_WIDTH/2-1 downto 0);
102 
      reg10_tv                   : OUT std_logic;
103 
      reg10_td                   : OUT std_logic_vector(C_DBUS_WIDTH/2-1 downto 0);
104 
      reg11_tv                   : OUT std_logic;
105 
      reg11_td                   : OUT std_logic_vector(C_DBUS_WIDTH/2-1 downto 0);
106 
      reg12_tv                   : OUT std_logic;
107 
      reg12_td                   : OUT std_logic_vector(C_DBUS_WIDTH/2-1 downto 0);
108 
      reg13_tv                   : OUT std_logic;
109 
      reg13_td                   : OUT std_logic_vector(C_DBUS_WIDTH/2-1 downto 0);
110 
      reg14_tv                   : OUT std_logic;
111 
      reg14_td                   : OUT std_logic_vector(C_DBUS_WIDTH/2-1 downto 0);
112 
 
113 
      -- SIMONE Register: FPGA-->PC
114 
      reg01_rv                   : IN  std_logic;
115 
      reg01_rd                   : IN  std_logic_vector(C_DBUS_WIDTH/2-1 downto 0);
116 
      reg02_rv                   : IN  std_logic;
117 
      reg02_rd                   : IN  std_logic_vector(C_DBUS_WIDTH/2-1 downto 0);
118 
      reg03_rv                   : IN  std_logic;
119 
      reg03_rd                   : IN  std_logic_vector(C_DBUS_WIDTH/2-1 downto 0);
120 
      reg04_rv                   : IN  std_logic;
121 
      reg04_rd                   : IN  std_logic_vector(C_DBUS_WIDTH/2-1 downto 0);
122 
      reg05_rv                   : IN  std_logic;
123 
      reg05_rd                   : IN  std_logic_vector(C_DBUS_WIDTH/2-1 downto 0);
124 
      reg06_rv                   : IN  std_logic;
125 
      reg06_rd                   : IN  std_logic_vector(C_DBUS_WIDTH/2-1 downto 0);
126 
      reg07_rv                   : IN  std_logic;
127 
      reg07_rd                   : IN  std_logic_vector(C_DBUS_WIDTH/2-1 downto 0);
128 
      reg08_rv                   : IN  std_logic;
129 
      reg08_rd                   : IN  std_logic_vector(C_DBUS_WIDTH/2-1 downto 0);
130 
      reg09_rv                   : IN  std_logic;
131 
      reg09_rd                   : IN  std_logic_vector(C_DBUS_WIDTH/2-1 downto 0);
132 
      reg10_rv                   : IN  std_logic;
133 
      reg10_rd                   : IN  std_logic_vector(C_DBUS_WIDTH/2-1 downto 0);
134 
      reg11_rv                   : IN  std_logic;
135 
      reg11_rd                   : IN  std_logic_vector(C_DBUS_WIDTH/2-1 downto 0);
136 
      reg12_rv                   : IN  std_logic;
137 
      reg12_rd                   : IN  std_logic_vector(C_DBUS_WIDTH/2-1 downto 0);
138 
      reg13_rv                   : IN  std_logic;
139 
      reg13_rd                   : IN  std_logic_vector(C_DBUS_WIDTH/2-1 downto 0);
140 
      reg14_rv                   : IN  std_logic;
141 
      reg14_rd                   : IN  std_logic_vector(C_DBUS_WIDTH/2-1 downto 0);
142 
 
143 
                -- SIMONE debug signals
144 
      debug_in_1i                                               : OUT std_logic_vector(31 downto 0);
145 
      debug_in_2i                                               : OUT std_logic_vector(31 downto 0);
146 
      debug_in_3i                                          : OUT std_logic_vector(31 downto 0);
147 
      debug_in_4i                                          : OUT std_logic_vector(31 downto 0);
148 
 
149 
      -- Event Buffer FIFO interface
150 
      eb_FIFO_we               : OUT std_logic;
151 
      eb_FIFO_wsof             : OUT std_logic;
152 
      eb_FIFO_weof             : OUT std_logic;
153 
      eb_FIFO_din              : OUT std_logic_vector(C_DBUS_WIDTH-1 downto 0);
154 
      eb_FIFO_re               : OUT std_logic;
155 
      eb_FIFO_empty            : IN  std_logic;
156 
      eb_FIFO_qout             : IN  std_logic_vector(C_DBUS_WIDTH-1 downto 0);
157 
      eb_FIFO_ow               : IN  std_logic;
158 
 
159 
      eb_FIFO_data_count       : IN  std_logic_vector(C_FIFO_DC_WIDTH downto 0);
160 
 
161 
      pio_reading_status       : OUT std_logic;
162 
      eb_FIFO_Status           : IN  std_logic_vector(C_DBUS_WIDTH-1 downto 0);
163 
      eb_FIFO_Rst              : OUT std_logic;
164 
 
165 
           H2B_FIFO_Status                       : IN std_logic_VECTOR(C_DBUS_WIDTH-1 downto 0);
166 
           B2H_FIFO_Status                       : IN std_logic_VECTOR(C_DBUS_WIDTH-1 downto 0);
167 
 
168 
      Link_Buf_full            : IN  std_logic;
169 
 
170 
      -- Debugging signals
171 
      DMA_us_Done              : OUT std_logic;
172 
      DMA_us_Busy              : OUT std_logic;
173 
      DMA_us_Busy_LED          : OUT std_logic;
174 
      DMA_ds_Done              : OUT std_logic;
175 
      DMA_ds_Busy              : OUT std_logic;
176 
      DMA_ds_Busy_LED          : OUT std_logic;
177 
 
178 
      -- DDR control interface
179 
      DDR_Ready                : IN    std_logic;
180 
 
181 
      DDR_wr_sof               : OUT   std_logic;
182 
      DDR_wr_eof               : OUT   std_logic;
183 
      DDR_wr_v                 : OUT   std_logic;
184 
      DDR_wr_FA                : OUT   std_logic;
185 
      DDR_wr_Shift             : OUT   std_logic;
186 
      DDR_wr_Mask              : OUT   std_logic_vector(2-1 downto 0);
187 
      DDR_wr_din               : OUT   std_logic_vector(C_DBUS_WIDTH-1 downto 0);
188 
      DDR_wr_full              : IN    std_logic;
189 
 
190 
      DDR_rdc_sof              : OUT   std_logic;
191 
      DDR_rdc_eof              : OUT   std_logic;
192 
      DDR_rdc_v                : OUT   std_logic;
193 
      DDR_rdc_FA               : OUT   std_logic;
194 
      DDR_rdc_Shift            : OUT   std_logic;
195 
      DDR_rdc_din              : OUT   std_logic_vector(C_DBUS_WIDTH-1 downto 0);
196 
      DDR_rdc_full             : IN    std_logic;
197 
 
198 
--      DDR_rdD_sof              : IN    std_logic;
199 
--      DDR_rdD_eof              : IN    std_logic;
200 
--      DDR_rdDout_V             : IN    std_logic;
201 
--      DDR_rdDout               : IN    std_logic_vector(C_DBUS_WIDTH-1 downto 0);
202 
 
203 
      -- DDR payload FIFO Read Port
204 
      DDR_FIFO_RdEn            : OUT std_logic;
205 
      DDR_FIFO_Empty           : IN  std_logic;
206 
      DDR_FIFO_RdQout          : IN  std_logic_vector(C_DBUS_WIDTH-1 downto 0);
207 
 
208 
      -- Data generator table write
209 
      tab_we                   : OUT std_logic_vector(2-1 downto 0);
210 
      tab_wa                   : OUT std_logic_vector(12-1 downto 0);
211 
      tab_wd                   : OUT std_logic_vector(C_DBUS_WIDTH-1 downto 0);
212 
 
213 
      DG_is_Running            : IN  std_logic;
214 
      DG_Reset                 : OUT std_logic;
215 
      DG_Mask                  : OUT std_logic;
216 
 
217 
      -- Common interface
218 
      trn_clk                  : IN  std_logic;
219 
      trn_reset_n              : IN  std_logic;
220 
      trn_lnk_up_n             : IN  std_logic;
221 
 
222 
      -- Transaction receive interface
223 
      trn_rsof_n               : IN  std_logic;
224 
      trn_reof_n               : IN  std_logic;
225 
      trn_rd                   : IN  std_logic_vector(C_DBUS_WIDTH-1 downto 0);
226 
      trn_rrem_n               : IN  std_logic_vector(C_DBUS_WIDTH/8-1 downto 0);
227 
      trn_rerrfwd_n            : IN  std_logic;
228 
      trn_rsrc_rdy_n           : IN  std_logic;
229 
      trn_rdst_rdy_n           : OUT std_logic;
230 
      trn_rnp_ok_n             : OUT std_logic;
231 
      trn_rsrc_dsc_n           : IN  std_logic;
232 
      trn_rbar_hit_n           : IN  std_logic_vector(C_BAR_NUMBER-1 downto 0);
233 
--    trn_rfc_ph_av              : IN  std_logic_vector(7 downto 0);
234 
--    trn_rfc_pd_av              : IN  std_logic_vector(11 downto 0);
235 
--    trn_rfc_nph_av             : IN  std_logic_vector(7 downto 0);
236 
--    trn_rfc_npd_av             : IN  std_logic_vector(11 downto 0);
237 
--    trn_rfc_cplh_av            : IN  std_logic_vector(7 downto 0);
238 
--    trn_rfc_cpld_av            : IN  std_logic_vector(11 downto 0);
239 
 
240 
      -- Transaction transmit interface
241 
      trn_tsof_n              : OUT std_logic;
242 
      trn_teof_n              : OUT std_logic;
243 
      trn_td                  : OUT std_logic_vector(C_DBUS_WIDTH-1 downto 0);
244 
      trn_trem_n              : OUT std_logic_vector(C_DBUS_WIDTH/8-1 downto 0);
245 
      trn_terrfwd_n           : OUT std_logic;
246 
      trn_tsrc_rdy_n          : OUT std_logic;
247 
      trn_tdst_rdy_n          : IN  std_logic;
248 
      trn_tsrc_dsc_n          : OUT std_logic;
249 
      trn_tdst_dsc_n          : IN  std_logic;
250 
      trn_tbuf_av             : IN  std_logic_vector(C_TBUF_AWIDTH-1 downto 0);
251 
 
252 
      Format_Shower           : OUT   std_logic;
253 
 
254 
      -- Interrupt Interface
255 
                cfg_interrupt_n         : OUT std_logic;
256 
                cfg_interrupt_rdy_n     : IN  std_logic;
257 
                cfg_interrupt_mmenable  : IN  std_logic_VECTOR(2 downto 0);
258 
                cfg_interrupt_msienable : IN  std_logic;
259 
                cfg_interrupt_di        : OUT std_logic_VECTOR(7 downto 0);
260 
                cfg_interrupt_do        : IN  std_logic_VECTOR(7 downto 0);
261 
                cfg_interrupt_assert_n  : OUT std_logic;
262 
 
263 
      -- Local signals
264 
      pcie_link_width         : IN  std_logic_vector(CINT_BIT_LWIDTH_IN_GSR_TOP-CINT_BIT_LWIDTH_IN_GSR_BOT downto 0);
265 
      cfg_dcommand            : IN  std_logic_vector(16-1 downto 0);
266 
      localID                 : IN  std_logic_vector(C_ID_WIDTH-1 downto 0)
267 
         );
268 
 
269 
end entity tlpControl;
270 
 
271 
 
272 
 
273 
architecture Behavioral of tlpControl is
274 
 
275 
  signal trn_lnk_up_i       : std_logic;
276 
 
277 
---- Rx transaction control
278 
  component rx_Transact
279 
    port (
280 
      -- Common ports
281 
      trn_clk            : IN  std_logic;
282 
      trn_reset_n        : IN  std_logic;
283 
      trn_lnk_up_n       : IN  std_logic;
284 
 
285 
      -- Transaction receive interface
286 
      trn_rsof_n         : IN  std_logic;
287 
      trn_reof_n         : IN  std_logic;
288 
      trn_rd             : IN  std_logic_vector(C_DBUS_WIDTH-1 downto 0);
289 
      trn_rrem_n         : IN  std_logic_vector(C_DBUS_WIDTH/8-1 downto 0);
290 
      trn_rerrfwd_n      : IN  std_logic;
291 
      trn_rsrc_rdy_n     : IN  std_logic;
292 
      trn_rdst_rdy_n     : OUT std_logic;
293 
      trn_rnp_ok_n       : OUT std_logic;
294 
      trn_rsrc_dsc_n     : IN  std_logic;
295 
      trn_rbar_hit_n     : IN  std_logic_vector(C_BAR_NUMBER-1 downto 0);
296 
 
297 
--      trn_rfc_ph_av      : IN  std_logic_vector(7 downto 0);
298 
--      trn_rfc_pd_av      : IN  std_logic_vector(11 downto 0);
299 
--      trn_rfc_nph_av     : IN  std_logic_vector(7 downto 0);
300 
--      trn_rfc_npd_av     : IN  std_logic_vector(11 downto 0);
301 
--      trn_rfc_cplh_av    : IN  std_logic_vector(7 downto 0);
302 
--      trn_rfc_cpld_av    : IN  std_logic_vector(11 downto 0);
303 
 
304 
 
305 
      -- MRd Channel
306 
      pioCplD_Req        : OUT std_logic;
307 
      pioCplD_RE         : IN  std_logic;
308 
      pioCplD_Qout       : OUT std_logic_vector(C_CHANNEL_BUF_WIDTH-1 downto 0);
309 
      pio_FC_stop        : IN  std_logic;
310 
 
311 
 
312 
      -- MRd-downstream packet Channel
313 
      dsMRd_Req          : OUT std_logic;
314 
      dsMRd_RE           : IN  std_logic;
315 
      dsMRd_Qout         : OUT std_logic_vector(C_CHANNEL_BUF_WIDTH-1 downto 0);
316 
 
317 
 
318 
      -- Upstream MWr/MRd Channel
319 
      usTlp_Req          : OUT std_logic;
320 
      usTlp_RE           : IN  std_logic;
321 
      usTlp_Qout         : OUT std_logic_vector(C_CHANNEL_BUF_WIDTH-1 downto 0);
322 
      us_FC_stop         : IN  std_logic;
323 
      us_Last_sof        : IN  std_logic;
324 
      us_Last_eof        : IN  std_logic;
325 
 
326 
      -- Irpt Channel
327 
      Irpt_Req           : OUT std_logic;
328 
      Irpt_RE            : IN  std_logic;
329 
      Irpt_Qout          : OUT std_logic_vector(C_CHANNEL_BUF_WIDTH-1 downto 0);
330 
 
331 
 
332 
      -- Interrupt Interface
333 
                cfg_interrupt_n         : OUT std_logic;
334 
                cfg_interrupt_rdy_n     : IN  std_logic;
335 
                cfg_interrupt_mmenable  : IN  std_logic_VECTOR(2 downto 0);
336 
                cfg_interrupt_msienable : IN  std_logic;
337 
                cfg_interrupt_di        : OUT std_logic_VECTOR(7 downto 0);
338 
                cfg_interrupt_do        : IN  std_logic_VECTOR(7 downto 0);
339 
                cfg_interrupt_assert_n  : OUT std_logic;
340 
 
341 
 
342 
      -- Event Buffer write port
343 
      eb_FIFO_we              : OUT std_logic;
344 
      eb_FIFO_wsof            : OUT std_logic;
345 
      eb_FIFO_weof            : OUT std_logic;
346 
      eb_FIFO_din             : OUT std_logic_vector(C_DBUS_WIDTH-1 downto 0);
347 
 
348 
      eb_FIFO_data_count      : IN  std_logic_vector(C_FIFO_DC_WIDTH downto 0);
349 
      eb_FIFO_Empty           : IN  std_logic;
350 
      eb_FIFO_Reading         : IN  std_logic;
351 
      pio_reading_status      : OUT std_logic;
352 
 
353 
      -- Registers Write Port
354 
      Regs_WrEn0         : OUT std_logic;
355 
      Regs_WrMask0       : OUT std_logic_vector(2-1 downto 0);
356 
      Regs_WrAddr0       : OUT std_logic_vector(C_EP_AWIDTH-1 downto 0);
357 
      Regs_WrDin0        : OUT std_logic_vector(C_DBUS_WIDTH-1 downto 0);
358 
 
359 
      Regs_WrEn1         : OUT std_logic;
360 
      Regs_WrMask1       : OUT std_logic_vector(2-1 downto 0);
361 
      Regs_WrAddr1       : OUT std_logic_vector(C_EP_AWIDTH-1 downto 0);
362 
      Regs_WrDin1        : OUT std_logic_vector(C_DBUS_WIDTH-1 downto 0);
363 
 
364 
      -- Downstream DMA transferred bytes count up
365 
      ds_DMA_Bytes_Add   : OUT std_logic;
366 
      ds_DMA_Bytes       : OUT std_logic_vector(C_TLP_FLD_WIDTH_OF_LENG+2 downto 0);
367 
 
368 
      -- --------------------------
369 
      -- Registers
370 
      DMA_ds_PA          : IN  std_logic_vector(C_DBUS_WIDTH-1 downto 0);
371 
      DMA_ds_HA          : IN  std_logic_vector(C_DBUS_WIDTH-1 downto 0);
372 
      DMA_ds_BDA         : IN  std_logic_vector(C_DBUS_WIDTH-1 downto 0);
373 
      DMA_ds_Length      : IN  std_logic_vector(C_DBUS_WIDTH-1 downto 0);
374 
      DMA_ds_Control     : IN  std_logic_vector(C_DBUS_WIDTH-1 downto 0);
375 
      dsDMA_BDA_eq_Null  : IN  std_logic;
376 
      DMA_ds_Status      : OUT std_logic_vector(C_DBUS_WIDTH-1 downto 0);
377 
      DMA_ds_Done        : OUT std_logic;
378 
      DMA_ds_Busy        : OUT std_logic;
379 
      DMA_ds_Tout        : OUT std_logic;
380 
 
381 
      -- Calculation in advance, for better timing
382 
      dsHA_is_64b        : IN  std_logic;
383 
      dsBDA_is_64b       : IN  std_logic;
384 
 
385 
      -- Calculation in advance, for better timing
386 
      dsLeng_Hi19b_True  : IN  std_logic;
387 
      dsLeng_Lo7b_True   : IN  std_logic;
388 
 
389 
 
390 
      dsDMA_Start        : IN  std_logic;
391 
      dsDMA_Stop         : IN  std_logic;
392 
      dsDMA_Start2       : IN  std_logic;
393 
      dsDMA_Stop2        : IN  std_logic;
394 
      dsDMA_Channel_Rst  : IN  std_logic;
395 
      dsDMA_Cmd_Ack      : OUT std_logic;
396 
 
397 
      DMA_us_PA          : IN  std_logic_vector(C_DBUS_WIDTH-1 downto 0);
398 
      DMA_us_HA          : IN  std_logic_vector(C_DBUS_WIDTH-1 downto 0);
399 
      DMA_us_BDA         : IN  std_logic_vector(C_DBUS_WIDTH-1 downto 0);
400 
      DMA_us_Length      : IN  std_logic_vector(C_DBUS_WIDTH-1 downto 0);
401 
      DMA_us_Control     : IN  std_logic_vector(C_DBUS_WIDTH-1 downto 0);
402 
      usDMA_BDA_eq_Null  : IN  std_logic;
403 
      us_MWr_Param_Vec   : IN  std_logic_vector(6-1   downto 0);
404 
      DMA_us_Status      : OUT std_logic_vector(C_DBUS_WIDTH-1 downto 0);
405 
      DMA_us_Done        : OUT std_logic;
406 
      DMA_us_Busy        : OUT std_logic;
407 
      DMA_us_Tout        : OUT std_logic;
408 
 
409 
      -- Calculation in advance, for better timing
410 
      usHA_is_64b        : IN  std_logic;
411 
      usBDA_is_64b       : IN  std_logic;
412 
 
413 
      -- Calculation in advance, for better timing
414 
      usLeng_Hi19b_True  : IN  std_logic;
415 
      usLeng_Lo7b_True   : IN  std_logic;
416 
 
417 
 
418 
      usDMA_Start        : IN  std_logic;
419 
      usDMA_Stop         : IN  std_logic;
420 
      usDMA_Start2       : IN  std_logic;
421 
      usDMA_Stop2        : IN  std_logic;
422 
      usDMA_Channel_Rst  : IN  std_logic;
423 
      usDMA_Cmd_Ack      : OUT std_logic;
424 
 
425 
      MRd_Channel_Rst    : IN  std_logic;
426 
 
427 
      Sys_IRQ            : IN  std_logic_vector(C_DBUS_WIDTH-1 downto 0);
428 
 
429 
 
430 
      -- DDR write port
431 
      DDR_wr_sof_A       : OUT   std_logic;
432 
      DDR_wr_eof_A       : OUT   std_logic;
433 
      DDR_wr_v_A         : OUT   std_logic;
434 
      DDR_wr_FA_A        : OUT   std_logic;
435 
      DDR_wr_Shift_A     : OUT   std_logic;
436 
      DDR_wr_Mask_A      : OUT   std_logic_vector(2-1 downto 0);
437 
      DDR_wr_din_A       : OUT   std_logic_vector(C_DBUS_WIDTH-1 downto 0);
438 
 
439 
      DDR_wr_sof_B       : OUT   std_logic;
440 
      DDR_wr_eof_B       : OUT   std_logic;
441 
      DDR_wr_v_B         : OUT   std_logic;
442 
      DDR_wr_FA_B        : OUT   std_logic;
443 
      DDR_wr_Shift_B     : OUT   std_logic;
444 
      DDR_wr_Mask_B      : OUT   std_logic_vector(2-1 downto 0);
445 
      DDR_wr_din_B       : OUT   std_logic_vector(C_DBUS_WIDTH-1 downto 0);
446 
 
447 
      DDR_wr_full        : IN    std_logic;
448 
 
449 
      Link_Buf_full      : IN  std_logic;
450 
 
451 
      -- Data generator table write
452 
      tab_we             : OUT std_logic_vector(2-1 downto 0);
453 
      tab_wa             : OUT std_logic_vector(12-1 downto 0);
454 
      tab_wd             : OUT std_logic_vector(C_DBUS_WIDTH-1 downto 0);
455 
 
456 
      -- Interrupt generator signals
457 
      IG_Reset           : IN  std_logic;
458 
      IG_Host_Clear      : IN  std_logic;
459 
      IG_Latency         : IN  std_logic_vector(C_DBUS_WIDTH-1   downto 0);
460 
      IG_Num_Assert      : OUT std_logic_vector(C_DBUS_WIDTH-1   downto 0);
461 
      IG_Num_Deassert    : OUT std_logic_vector(C_DBUS_WIDTH-1   downto 0);
462 
      IG_Asserting       : OUT std_logic;
463 
 
464 
 
465 
      -- Additional
466 
      cfg_dcommand       : IN  std_logic_vector(16-1 downto 0);
467 
      localID            : IN  std_logic_vector(C_ID_WIDTH-1 downto 0)
468 
    );
469 
  end component rx_Transact;
470 
 
471 
  -- Downstream DMA transferred bytes count up
472 
  signal ds_DMA_Bytes_Add   : std_logic;
473 
  signal ds_DMA_Bytes       : std_logic_vector(C_TLP_FLD_WIDTH_OF_LENG+2 downto 0);
474 
 
475 
 
476 
---- Tx transaction control
477 
  component tx_Transact
478 
    port (
479 
      -- Common ports
480 
      trn_clk            : IN  std_logic;
481 
      trn_reset_n        : IN  std_logic;
482 
      trn_lnk_up_n       : IN  std_logic;
483 
 
484 
      -- Transaction
485 
      trn_tsof_n         : OUT std_logic;
486 
      trn_teof_n         : OUT std_logic;
487 
      trn_td             : OUT std_logic_vector(C_DBUS_WIDTH-1 downto 0);
488 
      trn_trem_n         : OUT std_logic_vector(C_DBUS_WIDTH/8-1 downto 0);
489 
      trn_terrfwd_n      : OUT std_logic;
490 
      trn_tsrc_rdy_n     : OUT std_logic;
491 
      trn_tdst_rdy_n     : IN  std_logic;
492 
      trn_tsrc_dsc_n     : OUT std_logic;
493 
      trn_tdst_dsc_n     : IN  std_logic;
494 
      trn_tbuf_av        : IN  std_logic_vector(C_TBUF_AWIDTH-1 downto 0);
495 
 
496 
      -- Upstream DMA transferred bytes count up
497 
      us_DMA_Bytes_Add   : OUT std_logic;
498 
      us_DMA_Bytes       : OUT std_logic_vector(C_TLP_FLD_WIDTH_OF_LENG+2 downto 0);
499 
 
500 
      -- MRd Channel
501 
      pioCplD_Req        : IN  std_logic;
502 
      pioCplD_RE         : OUT std_logic;
503 
      pioCplD_Qout       : IN  std_logic_vector(C_CHANNEL_BUF_WIDTH-1 downto 0);
504 
      pio_FC_stop        : OUT std_logic;
505 
 
506 
 
507 
      -- MRd-downstream packet Channel
508 
      dsMRd_Req          : IN  std_logic;
509 
      dsMRd_RE           : OUT std_logic;
510 
      dsMRd_Qout         : IN  std_logic_vector(C_CHANNEL_BUF_WIDTH-1 downto 0);
511 
 
512 
 
513 
      -- Upstream MWr Channel
514 
      usTlp_Req          : IN  std_logic;
515 
      usTlp_RE           : OUT std_logic;
516 
      usTlp_Qout         : IN  std_logic_vector(C_CHANNEL_BUF_WIDTH-1 downto 0);
517 
      us_FC_stop         : OUT std_logic;
518 
      us_Last_sof        : OUT std_logic;
519 
      us_Last_eof        : OUT std_logic;
520 
 
521 
 
522 
      -- Irpt Channel
523 
      Irpt_Req           : IN  std_logic;
524 
      Irpt_RE            : OUT std_logic;
525 
      Irpt_Qout          : IN  std_logic_vector(C_CHANNEL_BUF_WIDTH-1 downto 0);
526 
 
527 
 
528 
      -- Event Buffer FIFO read port
529 
      eb_FIFO_re         : OUT std_logic;
530 
      eb_FIFO_empty      : IN  std_logic;
531 
      eb_FIFO_qout       : IN  std_logic_vector(C_DBUS_WIDTH-1 downto 0);
532 
 
533 
      -- With Rx port
534 
      Regs_RdAddr        : OUT std_logic_vector(C_EP_AWIDTH-1 downto 0);
535 
      Regs_RdQout        : IN  std_logic_vector(C_DBUS_WIDTH-1 downto 0);
536 
 
537 
      -- Message routing method
538 
      Msg_Routing        : IN  std_logic_vector(C_GCR_MSG_ROUT_BIT_TOP-C_GCR_MSG_ROUT_BIT_BOT downto 0);
539 
 
540 
 
541 
      --  DDR read port
542 
      DDR_rdc_sof        : OUT   std_logic;
543 
      DDR_rdc_eof        : OUT   std_logic;
544 
      DDR_rdc_v          : OUT   std_logic;
545 
      DDR_rdc_FA         : OUT   std_logic;
546 
      DDR_rdc_Shift      : OUT   std_logic;
547 
      DDR_rdc_din        : OUT   std_logic_vector(C_DBUS_WIDTH-1 downto 0);
548 
      DDR_rdc_full       : IN    std_logic;
549 
 
550 
--      DDR_rdD_sof        : IN    std_logic;
551 
--      DDR_rdD_eof        : IN    std_logic;
552 
--      DDR_rdDout_V       : IN    std_logic;
553 
--      DDR_rdDout         : IN    std_logic_vector(C_DBUS_WIDTH-1 downto 0);
554 
 
555 
      -- DDR payload FIFO Read Port
556 
      DDR_FIFO_RdEn      : OUT std_logic;
557 
      DDR_FIFO_Empty     : IN  std_logic;
558 
      DDR_FIFO_RdQout    : IN  std_logic_vector(C_DBUS_WIDTH-1 downto 0);
559 
 
560 
      -- Additional
561 
      Tx_TimeOut         : OUT std_logic;
562 
      Tx_eb_TimeOut      : OUT std_logic;
563 
      Format_Shower      : OUT   std_logic;
564 
      Tx_Reset           : IN  std_logic;
565 
      mbuf_UserFull      : IN  std_logic;
566 
      localID            : IN  std_logic_vector(C_ID_WIDTH-1 downto 0)
567 
    );
568 
  end component tx_Transact;
569 
 
570 
 
571 
  -- Upstream DMA transferred bytes count up
572 
  signal   us_DMA_Bytes_Add   : std_logic;
573 
  signal   us_DMA_Bytes       : std_logic_vector(C_TLP_FLD_WIDTH_OF_LENG+2 downto 0);
574 
 
575 
  -- ------------------------------------------------
576 
  -- United memory space consisting of registers.
577 
  --
578 
  component Regs_Group
579 
    port (
580 
 
581 
      -- DCB protocol interface
582 
                protocol_link_act        : IN  std_logic_vector(2-1 downto 0);
583 
                protocol_rst             : OUT std_logic;
584 
 
585 
      -- Fabric side: CTL Rx
586 
      ctl_rv                   : OUT std_logic;
587 
      ctl_rd                   : OUT std_logic_vector(C_DBUS_WIDTH/2-1 downto 0);
588 
 
589 
      -- Fabric side: CTL Tx
590 
      ctl_ttake                : OUT std_logic;
591 
      ctl_tv                   : IN  std_logic;
592 
      ctl_td                   : IN  std_logic_vector(C_DBUS_WIDTH/2-1 downto 0);
593 
      ctl_tstop                : OUT std_logic;
594 
 
595 
      ctl_reset                : OUT std_logic;
596 
      ctl_status               : IN  std_logic_vector(C_DBUS_WIDTH/2-1 downto 0);
597 
 
598 
      -- Fabric side: DLM Rx
599 
      dlm_tv                   : OUT std_logic;
600 
      dlm_td                   : OUT std_logic_vector(C_DBUS_WIDTH/2-1 downto 0);
601 
 
602 
      -- Fabric side: DLM Tx
603 
      dlm_rv                   : IN  std_logic;
604 
      dlm_rd                   : IN  std_logic_vector(C_DBUS_WIDTH/2-1 downto 0);
605 
 
606 
      -- Event Buffer status
607 
      eb_FIFO_Status           : IN  std_logic_vector(C_DBUS_WIDTH-1 downto 0);
608 
      eb_FIFO_Rst              : OUT std_logic;
609 
           H2B_FIFO_Status                       : IN std_logic_VECTOR(C_DBUS_WIDTH-1 downto 0);
610 
           B2H_FIFO_Status                       : IN std_logic_VECTOR(C_DBUS_WIDTH-1 downto 0);
611 
 
612 
 
613 
      -- Register Write
614 
      Regs_WrEnA               : IN  std_logic;
615 
      Regs_WrMaskA             : IN  std_logic_vector(2-1 downto 0);
616 
      Regs_WrAddrA             : IN  std_logic_vector(C_EP_AWIDTH-1   downto 0);
617 
      Regs_WrDinA              : IN  std_logic_vector(C_DBUS_WIDTH-1   downto 0);
618 
 
619 
      Regs_WrEnB               : IN  std_logic;
620 
      Regs_WrMaskB             : IN  std_logic_vector(2-1 downto 0);
621 
      Regs_WrAddrB             : IN  std_logic_vector(C_EP_AWIDTH-1   downto 0);
622 
      Regs_WrDinB              : IN  std_logic_vector(C_DBUS_WIDTH-1   downto 0);
623 
 
624 
      Regs_RdAddr              : IN  std_logic_vector(C_EP_AWIDTH-1   downto 0);
625 
      Regs_RdQout              : OUT std_logic_vector(C_DBUS_WIDTH-1   downto 0);
626 
 
627 
      -- Downstream DMA transferred bytes count up
628 
      ds_DMA_Bytes_Add         : IN  std_logic;
629 
      ds_DMA_Bytes             : IN  std_logic_vector(C_TLP_FLD_WIDTH_OF_LENG+2 downto 0);
630 
 
631 
      -- Register Values
632 
      DMA_ds_PA                : OUT std_logic_vector(C_DBUS_WIDTH-1 downto 0);
633 
      DMA_ds_HA                : OUT std_logic_vector(C_DBUS_WIDTH-1 downto 0);
634 
      DMA_ds_BDA               : OUT std_logic_vector(C_DBUS_WIDTH-1 downto 0);
635 
      DMA_ds_Length            : OUT std_logic_vector(C_DBUS_WIDTH-1 downto 0);
636 
      DMA_ds_Control           : OUT std_logic_vector(C_DBUS_WIDTH-1 downto 0);
637 
      dsDMA_BDA_eq_Null        : OUT std_logic;
638 
      DMA_ds_Status            : IN  std_logic_vector(C_DBUS_WIDTH-1 downto 0);
639 
      DMA_ds_Done              : IN  std_logic;
640 
--      DMA_ds_Busy              : IN  std_logic;
641 
      DMA_ds_Tout              : IN  std_logic;
642 
 
643 
      -- Calculation in advance, for better timing
644 
      dsHA_is_64b              : OUT std_logic;
645 
      dsBDA_is_64b             : OUT std_logic;
646 
 
647 
      -- Calculation in advance, for better timing
648 
      dsLeng_Hi19b_True        : OUT std_logic;
649 
      dsLeng_Lo7b_True         : OUT std_logic;
650 
 
651 
 
652 
      dsDMA_Start              : OUT std_logic;
653 
      dsDMA_Stop               : OUT std_logic;
654 
      dsDMA_Start2             : OUT std_logic;
655 
      dsDMA_Stop2              : OUT std_logic;
656 
      dsDMA_Channel_Rst        : OUT std_logic;
657 
      dsDMA_Cmd_Ack            : IN  std_logic;
658 
 
659 
      -- Upstream DMA transferred bytes count up
660 
      us_DMA_Bytes_Add         : IN  std_logic;
661 
      us_DMA_Bytes             : IN  std_logic_vector(C_TLP_FLD_WIDTH_OF_LENG+2 downto 0);
662 
 
663 
      DMA_us_PA                : OUT std_logic_vector(C_DBUS_WIDTH-1 downto 0);
664 
      DMA_us_HA                : OUT std_logic_vector(C_DBUS_WIDTH-1 downto 0);
665 
      DMA_us_BDA               : OUT std_logic_vector(C_DBUS_WIDTH-1 downto 0);
666 
      DMA_us_Length            : OUT std_logic_vector(C_DBUS_WIDTH-1 downto 0);
667 
      DMA_us_Control           : OUT std_logic_vector(C_DBUS_WIDTH-1 downto 0);
668 
      usDMA_BDA_eq_Null        : OUT std_logic;
669 
      us_MWr_Param_Vec         : OUT std_logic_vector(6-1   downto 0);
670 
      DMA_us_Status            : IN  std_logic_vector(C_DBUS_WIDTH-1 downto 0);
671 
      DMA_us_Done              : IN  std_logic;
672 
--      DMA_us_Busy              : IN  std_logic;
673 
      DMA_us_Tout              : IN  std_logic;
674 
 
675 
      -- Calculation in advance, for better timing
676 
      usHA_is_64b              : OUT std_logic;
677 
      usBDA_is_64b             : OUT std_logic;
678 
 
679 
      -- Calculation in advance, for better timing
680 
      usLeng_Hi19b_True        : OUT std_logic;
681 
      usLeng_Lo7b_True         : OUT std_logic;
682 
 
683 
 
684 
      usDMA_Start              : OUT std_logic;
685 
      usDMA_Stop               : OUT std_logic;
686 
      usDMA_Start2             : OUT std_logic;
687 
      usDMA_Stop2              : OUT std_logic;
688 
      usDMA_Channel_Rst        : OUT std_logic;
689 
      usDMA_Cmd_Ack            : IN  std_logic;
690 
 
691 
      -- Reset signals
692 
      MRd_Channel_Rst          : OUT std_logic;
693 
      Tx_Reset                 : OUT std_logic;
694 
 
695 
      -- to Interrupt module
696 
      Sys_IRQ                  : OUT std_logic_vector(C_DBUS_WIDTH-1 downto 0);
697 
      DAQ_irq                  : IN  std_logic;
698 
      CTL_irq                  : IN  std_logic;
699 
      DLM_irq                  : IN  std_logic;
700 
 
701 
      -- System error and info
702 
      eb_FIFO_ow               : IN  std_logic;
703 
      Tx_TimeOut               : IN  std_logic;
704 
      Tx_eb_TimeOut            : IN  std_logic;
705 
      Msg_Routing              : OUT std_logic_vector(C_GCR_MSG_ROUT_BIT_TOP-C_GCR_MSG_ROUT_BIT_BOT downto 0);
706 
      pcie_link_width          : IN  std_logic_vector(CINT_BIT_LWIDTH_IN_GSR_TOP-CINT_BIT_LWIDTH_IN_GSR_BOT downto 0);
707 
      cfg_dcommand             : IN  std_logic_vector(16-1 downto 0);
708 
 
709 
      -- Interrupt Generation Signals
710 
      IG_Reset                 : OUT std_logic;
711 
      IG_Host_Clear            : OUT std_logic;
712 
      IG_Latency               : OUT std_logic_vector(C_DBUS_WIDTH-1   downto 0);
713 
      IG_Num_Assert            : IN  std_logic_vector(C_DBUS_WIDTH-1   downto 0);
714 
      IG_Num_Deassert          : IN  std_logic_vector(C_DBUS_WIDTH-1   downto 0);
715 
      IG_Asserting             : IN  std_logic;
716 
 
717 
      -- Data generator control
718 
      DG_is_Running            : IN  std_logic;
719 
      DG_Reset                 : OUT std_logic;
720 
      DG_Mask                  : OUT std_logic;
721 
 
722 
      -- SIMONE Register: PC-->FPGA
723 
      reg01_tv                   : OUT std_logic;
724 
      reg01_td                   : OUT std_logic_vector(C_DBUS_WIDTH/2-1 downto 0);
725 
      reg02_tv                   : OUT std_logic;
726 
      reg02_td                   : OUT std_logic_vector(C_DBUS_WIDTH/2-1 downto 0);
727 
      reg03_tv                   : OUT std_logic;
728 
      reg03_td                   : OUT std_logic_vector(C_DBUS_WIDTH/2-1 downto 0);
729 
      reg04_tv                   : OUT std_logic;
730 
      reg04_td                   : OUT std_logic_vector(C_DBUS_WIDTH/2-1 downto 0);
731 
      reg05_tv                   : OUT std_logic;
732 
      reg05_td                   : OUT std_logic_vector(C_DBUS_WIDTH/2-1 downto 0);
733 
      reg06_tv                   : OUT std_logic;
734 
      reg06_td                   : OUT std_logic_vector(C_DBUS_WIDTH/2-1 downto 0);
735 
      reg07_tv                   : OUT std_logic;
736 
      reg07_td                   : OUT std_logic_vector(C_DBUS_WIDTH/2-1 downto 0);
737 
      reg08_tv                   : OUT std_logic;
738 
      reg08_td                   : OUT std_logic_vector(C_DBUS_WIDTH/2-1 downto 0);
739 
      reg09_tv                   : OUT std_logic;
740 
      reg09_td                   : OUT std_logic_vector(C_DBUS_WIDTH/2-1 downto 0);
741 
      reg10_tv                   : OUT std_logic;
742 
      reg10_td                   : OUT std_logic_vector(C_DBUS_WIDTH/2-1 downto 0);
743 
      reg11_tv                   : OUT std_logic;
744 
      reg11_td                   : OUT std_logic_vector(C_DBUS_WIDTH/2-1 downto 0);
745 
      reg12_tv                   : OUT std_logic;
746 
      reg12_td                   : OUT std_logic_vector(C_DBUS_WIDTH/2-1 downto 0);
747 
      reg13_tv                   : OUT std_logic;
748 
      reg13_td                   : OUT std_logic_vector(C_DBUS_WIDTH/2-1 downto 0);
749 
      reg14_tv                   : OUT std_logic;
750 
      reg14_td                   : OUT std_logic_vector(C_DBUS_WIDTH/2-1 downto 0);
751 
 
752 
      -- SIMONE Register: FPGA-->PC
753 
      reg01_rv                   : IN  std_logic;
754 
      reg01_rd                   : IN  std_logic_vector(C_DBUS_WIDTH/2-1 downto 0);
755 
      reg02_rv                   : IN  std_logic;
756 
      reg02_rd                   : IN  std_logic_vector(C_DBUS_WIDTH/2-1 downto 0);
757 
      reg03_rv                   : IN  std_logic;
758 
      reg03_rd                   : IN  std_logic_vector(C_DBUS_WIDTH/2-1 downto 0);
759 
      reg04_rv                   : IN  std_logic;
760 
      reg04_rd                   : IN  std_logic_vector(C_DBUS_WIDTH/2-1 downto 0);
761 
      reg05_rv                   : IN  std_logic;
762 
      reg05_rd                   : IN  std_logic_vector(C_DBUS_WIDTH/2-1 downto 0);
763 
      reg06_rv                   : IN  std_logic;
764 
      reg06_rd                   : IN  std_logic_vector(C_DBUS_WIDTH/2-1 downto 0);
765 
      reg07_rv                   : IN  std_logic;
766 
      reg07_rd                   : IN  std_logic_vector(C_DBUS_WIDTH/2-1 downto 0);
767 
      reg08_rv                   : IN  std_logic;
768 
      reg08_rd                   : IN  std_logic_vector(C_DBUS_WIDTH/2-1 downto 0);
769 
      reg09_rv                   : IN  std_logic;
770 
      reg09_rd                   : IN  std_logic_vector(C_DBUS_WIDTH/2-1 downto 0);
771 
      reg10_rv                   : IN  std_logic;
772 
      reg10_rd                   : IN  std_logic_vector(C_DBUS_WIDTH/2-1 downto 0);
773 
      reg11_rv                   : IN  std_logic;
774 
      reg11_rd                   : IN  std_logic_vector(C_DBUS_WIDTH/2-1 downto 0);
775 
      reg12_rv                   : IN  std_logic;
776 
      reg12_rd                   : IN  std_logic_vector(C_DBUS_WIDTH/2-1 downto 0);
777 
      reg13_rv                   : IN  std_logic;
778 
      reg13_rd                   : IN  std_logic_vector(C_DBUS_WIDTH/2-1 downto 0);
779 
      reg14_rv                   : IN  std_logic;
780 
      reg14_rd                   : IN  std_logic_vector(C_DBUS_WIDTH/2-1 downto 0);
781 
 
782 
                --SIMONE debug signals
783 
 
784 
      debug_in_1i                                               : OUT std_logic_vector(31 downto 0);
785 
      debug_in_2i                                               : OUT std_logic_vector(31 downto 0);
786 
      debug_in_3i                                               : OUT std_logic_vector(31 downto 0);
787 
      debug_in_4i                                               : OUT std_logic_vector(31 downto 0);
788 
 
789 
      -- Common interface
790 
      trn_clk                  : IN  std_logic;
791 
      trn_lnk_up_n             : IN  std_logic;
792 
      trn_reset_n              : IN  std_logic
793 
    );
794 
  end component Regs_Group;
795 
 
796 
 
797 
  -- DDR write port
798 
  signal  DDR_wr_sof_A         : std_logic;
799 
  signal  DDR_wr_eof_A         : std_logic;
800 
  signal  DDR_wr_v_A           : std_logic;
801 
  signal  DDR_wr_FA_A          : std_logic;
802 
  signal  DDR_wr_Shift_A       : std_logic;
803 
  signal  DDR_wr_Mask_A        : std_logic_vector(2-1 downto 0);
804 
  signal  DDR_wr_din_A         : std_logic_vector(C_DBUS_WIDTH-1 downto 0);
805 
 
806 
  signal  DDR_wr_sof_B         : std_logic;
807 
  signal  DDR_wr_eof_B         : std_logic;
808 
  signal  DDR_wr_v_B           : std_logic;
809 
  signal  DDR_wr_FA_B          : std_logic;
810 
  signal  DDR_wr_Shift_B       : std_logic;
811 
  signal  DDR_wr_Mask_B        : std_logic_vector(2-1 downto 0);
812 
  signal  DDR_wr_din_B         : std_logic_vector(C_DBUS_WIDTH-1 downto 0);
813 
 
814 
  signal  DDR_wr_sof_i         : std_logic;
815 
  signal  DDR_wr_eof_i         : std_logic;
816 
  signal  DDR_wr_v_i           : std_logic;
817 
  signal  DDR_wr_FA_i          : std_logic;
818 
  signal  DDR_wr_Shift_i       : std_logic;
819 
  signal  DDR_wr_Mask_i        : std_logic_vector(2-1 downto 0);
820 
  signal  DDR_wr_din_i         : std_logic_vector(C_DBUS_WIDTH-1 downto 0)
821 
                               := (OTHERS=>'0');
822 
 
823 
  signal  DDR_wr_sof_A_r1      : std_logic;
824 
  signal  DDR_wr_eof_A_r1      : std_logic;
825 
  signal  DDR_wr_v_A_r1        : std_logic;
826 
  signal  DDR_wr_FA_A_r1       : std_logic;
827 
  signal  DDR_wr_Shift_A_r1    : std_logic;
828 
  signal  DDR_wr_Mask_A_r1     : std_logic_vector(2-1 downto 0);
829 
  signal  DDR_wr_din_A_r1      : std_logic_vector(C_DBUS_WIDTH-1 downto 0);
830 
 
831 
  signal  DDR_wr_sof_A_r2      : std_logic;
832 
  signal  DDR_wr_eof_A_r2      : std_logic;
833 
  signal  DDR_wr_v_A_r2        : std_logic;
834 
  signal  DDR_wr_FA_A_r2       : std_logic;
835 
  signal  DDR_wr_Shift_A_r2    : std_logic;
836 
  signal  DDR_wr_Mask_A_r2     : std_logic_vector(2-1 downto 0);
837 
  signal  DDR_wr_din_A_r2      : std_logic_vector(C_DBUS_WIDTH-1 downto 0);
838 
 
839 
  signal  DDR_wr_sof_A_r3      : std_logic;
840 
  signal  DDR_wr_eof_A_r3      : std_logic;
841 
  signal  DDR_wr_v_A_r3        : std_logic;
842 
  signal  DDR_wr_FA_A_r3       : std_logic;
843 
  signal  DDR_wr_Shift_A_r3    : std_logic;
844 
  signal  DDR_wr_Mask_A_r3     : std_logic_vector(2-1 downto 0);
845 
  signal  DDR_wr_din_A_r3      : std_logic_vector(C_DBUS_WIDTH-1 downto 0);
846 
 
847 
  -- eb FIFO read enable
848 
  signal  eb_FIFO_RdEn_i       : std_logic;
849 
 
850 
  -- Flow control signals
851 
  signal  pio_FC_stop          : std_logic;
852 
  signal  us_FC_stop           : std_logic;
853 
  signal  us_Last_sof          : std_logic;
854 
  signal  us_Last_eof          : std_logic;
855 
 
856 
 
857 
  -- Signals between Tx_Transact and Rx_Transact
858 
  signal  pioCplD_Req          : std_logic;
859 
  signal  pioCplD_RE           : std_logic;
860 
  signal  pioCplD_Qout         : std_logic_vector(C_CHANNEL_BUF_WIDTH-1 downto 0);
861 
 
862 
  -- MRd-downstream packet Channel
863 
  signal  dsMRd_Req            : std_logic;
864 
  signal  dsMRd_RE             : std_logic;
865 
  signal  dsMRd_Qout           : std_logic_vector(C_CHANNEL_BUF_WIDTH-1 downto 0);
866 
 
867 
  -- Upstream MWr Channel
868 
  signal  usTlp_Req            : std_logic;
869 
  signal  usTlp_RE             : std_logic;
870 
  signal  usTlp_Qout           : std_logic_vector(C_CHANNEL_BUF_WIDTH-1 downto 0);
871 
 
872 
  -- Irpt Channel
873 
  signal  Irpt_Req             : std_logic;
874 
  signal  Irpt_RE              : std_logic;
875 
  signal  Irpt_Qout            : std_logic_vector(C_CHANNEL_BUF_WIDTH-1 downto 0);
876 
 
877 
 
878 
  -- Registers Write Port
879 
  signal  Regs_WrEnA           : std_logic;
880 
  signal  Regs_WrMaskA         : std_logic_vector(2-1 downto 0);
881 
  signal  Regs_WrAddrA         : std_logic_vector(C_EP_AWIDTH-1 downto 0);
882 
  signal  Regs_WrDinA          : std_logic_vector(C_DBUS_WIDTH-1 downto 0);
883 
 
884 
  signal  Regs_WrEnB           : std_logic;
885 
  signal  Regs_WrMaskB         : std_logic_vector(2-1 downto 0);
886 
  signal  Regs_WrAddrB         : std_logic_vector(C_EP_AWIDTH-1 downto 0);
887 
  signal  Regs_WrDinB          : std_logic_vector(C_DBUS_WIDTH-1 downto 0);
888 
 
889 
 
890 
  -- Dex parameters to downstream DMA
891 
  signal  DMA_ds_PA            : std_logic_vector(C_DBUS_WIDTH-1 downto 0);
892 
  signal  DMA_ds_HA            : std_logic_vector(C_DBUS_WIDTH-1 downto 0);
893 
  signal  DMA_ds_BDA           : std_logic_vector(C_DBUS_WIDTH-1 downto 0);
894 
  signal  DMA_ds_Length        : std_logic_vector(C_DBUS_WIDTH-1 downto 0);
895 
  signal  DMA_ds_Control       : std_logic_vector(C_DBUS_WIDTH-1 downto 0);
896 
  signal  dsDMA_BDA_eq_Null    : std_logic;
897 
  signal  DMA_ds_Status        : std_logic_vector(C_DBUS_WIDTH-1 downto 0);
898 
  signal  DMA_ds_Done_i        : std_logic;
899 
  signal  DMA_ds_Busy_i        : std_logic;
900 
  signal  DMA_ds_Busy_led_i    : std_logic;
901 
  signal  cnt_ds_Busy          : std_logic_vector(20-1   downto 0);
902 
  signal  DMA_ds_Tout          : std_logic;
903 
 
904 
  -- Calculation in advance, for better timing
905 
  signal  dsHA_is_64b          : std_logic;
906 
  signal  dsBDA_is_64b         : std_logic;
907 
  -- Calculation in advance, for better timing
908 
  signal  dsLeng_Hi19b_True    : std_logic;
909 
  signal  dsLeng_Lo7b_True     : std_logic;
910 
 
911 
  -- Downstream Control Signals
912 
  signal  dsDMA_Start          : std_logic;
913 
  signal  dsDMA_Stop           : std_logic;
914 
  signal  dsDMA_Start2         : std_logic;
915 
  signal  dsDMA_Stop2          : std_logic;
916 
  signal  dsDMA_Cmd_Ack        : std_logic;
917 
  signal  dsDMA_Channel_Rst    : std_logic;
918 
 
919 
  -- Dex parameters to upstream DMA
920 
  signal  DMA_us_PA            : std_logic_vector(C_DBUS_WIDTH-1 downto 0);
921 
  signal  DMA_us_HA            : std_logic_vector(C_DBUS_WIDTH-1 downto 0);
922 
  signal  DMA_us_BDA           : std_logic_vector(C_DBUS_WIDTH-1 downto 0);
923 
  signal  DMA_us_Length        : std_logic_vector(C_DBUS_WIDTH-1 downto 0);
924 
  signal  DMA_us_Control       : std_logic_vector(C_DBUS_WIDTH-1 downto 0);
925 
  signal  usDMA_BDA_eq_Null    : std_logic;
926 
  signal  us_MWr_Param_Vec     : std_logic_vector(6-1   downto 0);
927 
  signal  DMA_us_Status        : std_logic_vector(C_DBUS_WIDTH-1 downto 0);
928 
  signal  DMA_us_Done_i        : std_logic;
929 
  signal  DMA_us_Busy_i        : std_logic;
930 
  signal  DMA_us_Busy_led_i    : std_logic;
931 
  signal  cnt_us_Busy          : std_logic_vector(20-1   downto 0);
932 
  signal  DMA_us_Tout          : std_logic;
933 
 
934 
  -- Calculation in advance, for better timing
935 
  signal  usHA_is_64b          : std_logic;
936 
  signal  usBDA_is_64b         : std_logic;
937 
  -- Calculation in advance, for better timing
938 
  signal  usLeng_Hi19b_True    : std_logic;
939 
  signal  usLeng_Lo7b_True     : std_logic;
940 
 
941 
  -- Upstream Control Signals
942 
  signal  usDMA_Start          : std_logic;
943 
  signal  usDMA_Stop           : std_logic;
944 
  signal  usDMA_Start2         : std_logic;
945 
  signal  usDMA_Stop2          : std_logic;
946 
  signal  usDMA_Cmd_Ack        : std_logic;
947 
  signal  usDMA_Channel_Rst    : std_logic;
948 
 
949 
 
950 
  --      MRd Channel Reset
951 
  signal  MRd_Channel_Rst      : std_logic;
952 
 
953 
  --      Tx module Reset
954 
  signal  Tx_Reset             : std_logic;
955 
 
956 
  --      Tx time out
957 
  signal  Tx_TimeOut           : std_logic;
958 
  signal  Tx_eb_TimeOut        : std_logic;
959 
 
960 
  -- Registers read port
961 
  signal  Regs_RdAddr          : std_logic_vector(C_EP_AWIDTH-1 downto 0);
962 
  signal  Regs_RdQout          : std_logic_vector(C_DBUS_WIDTH-1 downto 0);
963 
 
964 
  -- Register to Interrupt module
965 
  signal  Sys_IRQ              : std_logic_vector(C_DBUS_WIDTH-1 downto 0);
966 
 
967 
  -- Message routing method
968 
  signal  Msg_Routing          : std_logic_vector(C_GCR_MSG_ROUT_BIT_TOP-C_GCR_MSG_ROUT_BIT_BOT downto 0);
969 
 
970 
  -- Interrupt Generation Signals
971 
  signal  IG_Reset             : std_logic;
972 
  signal  IG_Host_Clear        : std_logic;
973 
  signal  IG_Latency           : std_logic_vector(C_DBUS_WIDTH-1   downto 0);
974 
  signal  IG_Num_Assert        : std_logic_vector(C_DBUS_WIDTH-1   downto 0);
975 
  signal  IG_Num_Deassert      : std_logic_vector(C_DBUS_WIDTH-1   downto 0);
976 
  signal  IG_Asserting         : std_logic;
977 
 
978 
  -- Test blinker
979 
  signal  trn_Blinker_cnt      : std_logic_vector(31 downto 0) := (OTHERS=>'0');
980 
 
981 
begin
982 
 
983 
 
984 
   DDR_wr_v            <=  DDR_wr_v_i      ;
985 
   DDR_wr_sof          <=  DDR_wr_sof_i    ;
986 
   DDR_wr_eof          <=  DDR_wr_eof_i    ;
987 
   DDR_wr_FA           <=  DDR_wr_FA_i     ;
988 
   DDR_wr_Shift        <=  DDR_wr_Shift_i  ;
989 
   DDR_wr_Mask         <=  DDR_wr_Mask_i   ;
990 
   DDR_wr_din          <=  DDR_wr_din_i    ;
991 
 
992 
   trn_Blinker         <=  trn_Blinker_cnt(26)   ;
993 
 
994 
   DMA_us_Busy         <=  DMA_us_Busy_i   ;
995 
   DMA_us_Busy_LED     <=  DMA_us_Busy_led_i   ;
996 
   DMA_ds_Busy         <=  DMA_ds_Busy_i   ;
997 
   DMA_ds_Busy_LED     <=  DMA_ds_Busy_led_i   ;
998 
 
999 
   eb_FIFO_re          <=  eb_FIFO_RdEn_i  ;
1000 
 
1001 
   DMA_ds_Done         <=  DMA_ds_Done_i   ;
1002 
   DMA_us_Done         <=  DMA_us_Done_i   ;
1003 
 
1004 
   trn_lnk_up_i        <=  not trn_lnk_up_n;
1005 
 
1006 
   -- -------------------------------------------------------
1007 
   -- Delay DDR write port A for 2 cycles
1008 
   --
1009 
   SynDelay_DDR_write_PIO:
1010 
   process ( trn_clk )
1011 
   begin
1012 
      if trn_clk'event and trn_clk = '1' then
1013 
        DDR_wr_v_A_r1     <=  DDR_wr_v_A;
1014 
        DDR_wr_sof_A_r1   <=  DDR_wr_sof_A;
1015 
        DDR_wr_eof_A_r1   <=  DDR_wr_eof_A;
1016 
        DDR_wr_FA_A_r1    <=  DDR_wr_FA_A;
1017 
        DDR_wr_Shift_A_r1 <=  DDR_wr_Shift_A;
1018 
        DDR_wr_Mask_A_r1  <=  DDR_wr_Mask_A;
1019 
        DDR_wr_din_A_r1   <=  DDR_wr_din_A;
1020 
 
1021 
        DDR_wr_v_A_r2     <=  DDR_wr_v_A_r1;
1022 
        DDR_wr_sof_A_r2   <=  DDR_wr_sof_A_r1;
1023 
        DDR_wr_eof_A_r2   <=  DDR_wr_eof_A_r1;
1024 
        DDR_wr_FA_A_r2    <=  DDR_wr_FA_A_r1;
1025 
        DDR_wr_Shift_A_r2 <=  DDR_wr_Shift_A_r1;
1026 
        DDR_wr_Mask_A_r2  <=  DDR_wr_Mask_A_r1;
1027 
        DDR_wr_din_A_r2   <=  DDR_wr_din_A_r1;
1028 
 
1029 
        DDR_wr_v_A_r3     <=  DDR_wr_v_A_r2;
1030 
        DDR_wr_sof_A_r3   <=  DDR_wr_sof_A_r2;
1031 
        DDR_wr_eof_A_r3   <=  DDR_wr_eof_A_r2;
1032 
        DDR_wr_FA_A_r3    <=  DDR_wr_FA_A_r2;
1033 
        DDR_wr_Shift_A_r3 <=  DDR_wr_Shift_A_r2;
1034 
        DDR_wr_Mask_A_r3  <=  DDR_wr_Mask_A_r2;
1035 
        DDR_wr_din_A_r3   <=  DDR_wr_din_A_r2;
1036 
      end if;
1037 
   end process;
1038 
 
1039 
 
1040 
   -- -------------------------------------------------------
1041 
   -- DDR writes: DDR Writes
1042 
   --
1043 
   SynProc_DDR_write:
1044 
   process ( trn_clk )
1045 
   begin
1046 
      if trn_clk'event and trn_clk = '1' then
1047 
        DDR_wr_v_i     <=  DDR_wr_v_A_r3 or DDR_wr_v_B;
1048 
        if DDR_wr_v_A_r3 = '1' then
1049 
          DDR_wr_sof_i   <=  DDR_wr_sof_A_r3;
1050 
          DDR_wr_eof_i   <=  DDR_wr_eof_A_r3;
1051 
          DDR_wr_FA_i    <=  DDR_wr_FA_A_r3;
1052 
          DDR_wr_Shift_i <=  DDR_wr_Shift_A_r3;
1053 
          DDR_wr_Mask_i  <=  DDR_wr_Mask_A_r3;
1054 
          DDR_wr_din_i   <=  DDR_wr_din_A_r3;
1055 
        elsif DDR_wr_v_B = '1' then
1056 
          DDR_wr_sof_i   <=  DDR_wr_sof_B;
1057 
          DDR_wr_eof_i   <=  DDR_wr_eof_B;
1058 
          DDR_wr_FA_i    <=  DDR_wr_FA_B ;
1059 
          DDR_wr_Shift_i <=  DDR_wr_Shift_B ;
1060 
          DDR_wr_Mask_i  <=  DDR_wr_Mask_B;
1061 
          DDR_wr_din_i   <=  DDR_wr_din_B;
1062 
        else
1063 
          DDR_wr_sof_i   <=  DDR_wr_sof_i;
1064 
          DDR_wr_eof_i   <=  DDR_wr_eof_i;
1065 
          DDR_wr_FA_i    <=  DDR_wr_FA_i ;
1066 
          DDR_wr_Shift_i <=  DDR_wr_Shift_i ;
1067 
          DDR_wr_Mask_i  <=  DDR_wr_Mask_i;
1068 
          DDR_wr_din_i   <=  DDR_wr_din_i;
1069 
        end if;
1070 
      end if;
1071 
   end process;
1072 
 
1073 
   -- -------------------------------------------------------
1074 
   -- trn blink
1075 
   --
1076 
   SynProc_trn_blinker:
1077 
   process ( trn_clk )
1078 
   begin
1079 
      if trn_clk'event and trn_clk = '1' then
1080 
        trn_Blinker_cnt     <=  trn_Blinker_cnt + '1';
1081 
      end if;
1082 
   end process;
1083 
 
1084 
   -- -------------------------------------------------------
1085 
   -- DMA upstream Busy display
1086 
   --
1087 
   SynProc_DMA_us_Busy_LED:
1088 
   process ( trn_clk, DMA_us_Busy_i)
1089 
   begin
1090 
      if DMA_us_Busy_i='1' then
1091 
        DMA_us_Busy_led_i <=  '1';
1092 
        cnt_us_Busy       <=  (OTHERS=>'0');
1093 
      elsif trn_clk'event and trn_clk = '1' then
1094 
        if cnt_us_Busy=X"80000" then
1095 
          DMA_us_Busy_led_i <=  '0';
1096 
          cnt_us_Busy       <=  cnt_us_Busy;
1097 
        else
1098 
          DMA_us_Busy_led_i <=  DMA_us_Busy_led_i;
1099 
          cnt_us_Busy       <=  cnt_us_Busy + '1';
1100 
        end if;
1101 
      end if;
1102 
   end process;
1103 
 
1104 
   -- -------------------------------------------------------
1105 
   -- DMA downstream Busy display
1106 
   --
1107 
   SynProc_DMA_ds_Busy_LED:
1108 
   process ( trn_clk, DMA_ds_Busy_i)
1109 
   begin
1110 
      if DMA_ds_Busy_i='1' then
1111 
        DMA_ds_Busy_led_i <=  '1';
1112 
        cnt_ds_Busy       <=  (OTHERS=>'0');
1113 
      elsif trn_clk'event and trn_clk = '1' then
1114 
        if cnt_ds_Busy=X"FFFFF" then
1115 
          DMA_ds_Busy_led_i <=  '0';
1116 
          cnt_ds_Busy       <=  cnt_ds_Busy;
1117 
        else
1118 
          DMA_ds_Busy_led_i <=  DMA_ds_Busy_led_i;
1119 
          cnt_ds_Busy       <=  cnt_ds_Busy + '1';
1120 
        end if;
1121 
      end if;
1122 
   end process;
1123 
 
1124 
--    DDR_wr_v     <=  DDR_wr_v_A or DDR_wr_v_B;
1125 
--    DDR_wr_sof   <=  DDR_wr_sof_A  when DDR_wr_v_A='1'  else  DDR_wr_sof_B;
1126 
--    DDR_wr_eof   <=  DDR_wr_eof_A  when DDR_wr_v_A='1'  else  DDR_wr_eof_B;
1127 
--    DDR_wr_FA    <=  DDR_wr_FA_A   when DDR_wr_v_A='1'  else  DDR_wr_FA_B;
1128 
--    DDR_wr_din   <=  DDR_wr_din_A  when DDR_wr_v_A='1'  else  DDR_wr_din_B;
1129 
 
1130 
 
1131 
    -- Rx TLP interface
1132 
    rx_Itf:
1133 
    rx_Transact
1134 
    port map(
1135 
      -- Common ports
1136 
      trn_clk            => trn_clk,             -- IN  std_logic,
1137 
      trn_reset_n        => trn_lnk_up_i     , -- trn_reset_n,         -- IN  std_logic,
1138 
      trn_lnk_up_n       => trn_lnk_up_n,        -- IN  std_logic,
1139 
 
1140 
      -- Transaction receive interface
1141 
      trn_rsof_n         => trn_rsof_n,          -- IN  std_logic,
1142 
      trn_reof_n         => trn_reof_n,          -- IN  std_logic,
1143 
      trn_rd             => trn_rd,              -- IN  std_logic_vector(31 downto 0),
1144 
      trn_rrem_n         => trn_rrem_n,          -- IN  STD_LOGIC_VECTOR (  7 downto 0 );
1145 
      trn_rerrfwd_n      => trn_rerrfwd_n,       -- IN  std_logic,
1146 
      trn_rsrc_rdy_n     => trn_rsrc_rdy_n,      -- IN  std_logic,
1147 
      trn_rdst_rdy_n     => trn_rdst_rdy_n,      -- OUT std_logic,
1148 
      trn_rnp_ok_n       => trn_rnp_ok_n,        -- OUT std_logic,
1149 
      trn_rsrc_dsc_n     => trn_rsrc_dsc_n,      -- IN std_logic,
1150 
      trn_rbar_hit_n     => trn_rbar_hit_n,      -- IN  std_logic_vector(6 downto 0),
1151 
--    trn_rfc_ph_av        => trn_rfc_ph_av,       -- IN  std_logic_vector(7 downto 0),
1152 
--    trn_rfc_pd_av        => trn_rfc_pd_av,       -- IN  std_logic_vector(11 downto 0),
1153 
--    trn_rfc_nph_av       => trn_rfc_nph_av,      -- IN  std_logic_vector(7 downto 0),
1154 
--    trn_rfc_npd_av       => trn_rfc_npd_av,      -- IN  std_logic_vector(11 downto 0),
1155 
--    trn_rfc_cplh_av      => trn_rfc_cplh_av,     -- IN  std_logic_vector(7 downto 0),
1156 
--    trn_rfc_cpld_av      => trn_rfc_cpld_av,     -- IN  std_logic_vector(11 downto 0),
1157 
 
1158 
 
1159 
      -- MRd Channel
1160 
      pioCplD_Req        => pioCplD_Req,         -- OUT std_logic;
1161 
      pioCplD_RE         => pioCplD_RE,          -- IN  std_logic;
1162 
      pioCplD_Qout       => pioCplD_Qout,        -- OUT std_logic_vector(96 downto 0);
1163 
      pio_FC_stop        => pio_FC_stop,         -- IN  std_logic;
1164 
 
1165 
      -- downstream MRd Channel
1166 
      dsMRd_Req          => dsMRd_Req,           -- OUT std_logic;
1167 
      dsMRd_RE           => dsMRd_RE,            -- IN  std_logic;
1168 
      dsMRd_Qout         => dsMRd_Qout,          -- OUT std_logic_vector(96 downto 0);
1169 
 
1170 
      -- Upstream MWr/MRd Channel
1171 
      usTlp_Req          => usTlp_Req,           -- OUT std_logic;
1172 
      usTlp_RE           => usTlp_RE,            -- IN  std_logic;
1173 
      usTlp_Qout         => usTlp_Qout,          -- OUT std_logic_vector(96 downto 0);
1174 
      us_FC_stop         => us_FC_stop,          -- IN  std_logic;
1175 
      us_Last_sof        => us_Last_sof,         -- IN  std_logic;
1176 
      us_Last_eof        => us_Last_eof,         -- IN  std_logic;
1177 
 
1178 
      -- Irpt Channel
1179 
      Irpt_Req           => Irpt_Req,            -- OUT std_logic;
1180 
      Irpt_RE            => Irpt_RE,             -- IN  std_logic;
1181 
      Irpt_Qout          => Irpt_Qout,           -- OUT std_logic_vector(96 downto 0);
1182 
 
1183 
 
1184 
      -- Interrupt Interface
1185 
                cfg_interrupt_n         => cfg_interrupt_n         ,  -- OUT std_logic;
1186 
                cfg_interrupt_rdy_n     => cfg_interrupt_rdy_n     ,  -- IN std_logic;
1187 
                cfg_interrupt_mmenable  => cfg_interrupt_mmenable  ,  -- IN std_logic_VECTOR(2 downto 0);
1188 
                cfg_interrupt_msienable => cfg_interrupt_msienable ,  -- IN std_logic;
1189 
                cfg_interrupt_di        => cfg_interrupt_di        ,  -- OUT std_logic_VECTOR(7 downto 0);
1190 
                cfg_interrupt_do        => cfg_interrupt_do        ,  -- IN std_logic_VECTOR(7 downto 0);
1191 
                cfg_interrupt_assert_n  => cfg_interrupt_assert_n  ,  -- OUT std_logic;
1192 
 
1193 
 
1194 
      -- Event Buffer write port
1195 
      eb_FIFO_we          =>  eb_FIFO_we    ,       -- OUT std_logic;
1196 
      eb_FIFO_wsof        =>  eb_FIFO_wsof  ,       -- OUT std_logic;
1197 
      eb_FIFO_weof        =>  eb_FIFO_weof  ,       -- OUT std_logic;
1198 
      eb_FIFO_din         =>  eb_FIFO_din   ,       -- OUT std_logic_vector(C_DBUS_WIDTH-1 downto 0);
1199 
 
1200 
      eb_FIFO_data_count  =>  eb_FIFO_data_count,   -- IN  std_logic_vector(C_FIFO_DC_WIDTH downto 0);
1201 
      eb_FIFO_Empty       =>  eb_FIFO_Empty     ,   -- IN  std_logic;
1202 
      eb_FIFO_Reading     =>  eb_FIFO_RdEn_i    ,   -- IN  std_logic;
1203 
      pio_reading_status  =>  pio_reading_status    ,   -- OUT std_logic;
1204 
 
1205 
      -- Register Write
1206 
      Regs_WrEn0          =>  Regs_WrEnA    ,       -- OUT std_logic;
1207 
      Regs_WrMask0        =>  Regs_WrMaskA  ,       -- OUT std_logic_vector(2-1   downto 0);
1208 
      Regs_WrAddr0        =>  Regs_WrAddrA  ,       -- OUT std_logic_vector(16-1   downto 0);
1209 
      Regs_WrDin0         =>  Regs_WrDinA   ,       -- OUT std_logic_vector(32-1   downto 0);
1210 
 
1211 
      Regs_WrEn1          =>  Regs_WrEnB    ,       -- OUT std_logic;
1212 
      Regs_WrMask1        =>  Regs_WrMaskB  ,       -- OUT std_logic_vector(2-1   downto 0);
1213 
      Regs_WrAddr1        =>  Regs_WrAddrB  ,       -- OUT std_logic_vector(16-1   downto 0);
1214 
      Regs_WrDin1         =>  Regs_WrDinB   ,       -- OUT std_logic_vector(32-1   downto 0);
1215 
 
1216 
      -- Downstream DMA transferred bytes count up
1217 
      ds_DMA_Bytes_Add    =>  ds_DMA_Bytes_Add     ,  -- OUT std_logic;
1218 
      ds_DMA_Bytes        =>  ds_DMA_Bytes         ,  -- OUT std_logic_vector(C_TLP_FLD_WIDTH_OF_LENG+2 downto 0);
1219 
 
1220 
      -- Registers
1221 
                DMA_ds_PA           =>  DMA_ds_PA            ,  -- IN  std_logic_vector(63 downto 0);
1222 
                DMA_ds_HA           =>  DMA_ds_HA            ,  -- IN  std_logic_vector(63 downto 0);
1223 
                DMA_ds_BDA          =>  DMA_ds_BDA           ,  -- IN  std_logic_vector(63 downto 0);
1224 
                DMA_ds_Length       =>  DMA_ds_Length        ,  -- IN  std_logic_vector(31 downto 0);
1225 
                DMA_ds_Control      =>  DMA_ds_Control       ,  -- IN  std_logic_vector(31 downto 0);
1226 
      dsDMA_BDA_eq_Null   =>  dsDMA_BDA_eq_Null    ,  -- IN  std_logic;
1227 
                DMA_ds_Status       =>  DMA_ds_Status        ,  -- OUT std_logic_vector(31 downto 0);
1228 
      DMA_ds_Done         =>  DMA_ds_Done_i        ,  -- OUT std_logic;
1229 
      DMA_ds_Busy         =>  DMA_ds_Busy_i        ,  -- OUT std_logic;
1230 
      DMA_ds_Tout         =>  DMA_ds_Tout          ,  -- OUT std_logic;
1231 
 
1232 
      dsHA_is_64b         =>  dsHA_is_64b          ,  -- IN  std_logic;
1233 
      dsBDA_is_64b        =>  dsBDA_is_64b         ,  -- IN  std_logic;
1234 
 
1235 
      dsLeng_Hi19b_True   =>  dsLeng_Hi19b_True    ,  -- IN  std_logic;
1236 
      dsLeng_Lo7b_True    =>  dsLeng_Lo7b_True     ,  -- IN  std_logic;
1237 
 
1238 
                dsDMA_Start         =>  dsDMA_Start          ,  -- IN  std_logic;
1239 
                dsDMA_Stop          =>  dsDMA_Stop           ,  -- IN  std_logic;
1240 
                dsDMA_Start2        =>  dsDMA_Start2         ,  -- IN  std_logic;
1241 
                dsDMA_Stop2         =>  dsDMA_Stop2          ,  -- IN  std_logic;
1242 
                dsDMA_Channel_Rst   =>  dsDMA_Channel_Rst    ,  -- IN  std_logic;
1243 
      dsDMA_Cmd_Ack       =>  dsDMA_Cmd_Ack        ,  -- OUT std_logic;
1244 
 
1245 
                DMA_us_PA           =>  DMA_us_PA            ,  -- IN  std_logic_vector(63 downto 0);
1246 
                DMA_us_HA           =>  DMA_us_HA            ,  -- IN  std_logic_vector(63 downto 0);
1247 
                DMA_us_BDA          =>  DMA_us_BDA           ,  -- IN  std_logic_vector(63 downto 0);
1248 
                DMA_us_Length       =>  DMA_us_Length        ,  -- IN  std_logic_vector(31 downto 0);
1249 
                DMA_us_Control      =>  DMA_us_Control       ,  -- IN  std_logic_vector(31 downto 0);
1250 
      usDMA_BDA_eq_Null   =>  usDMA_BDA_eq_Null    ,  -- IN  std_logic;
1251 
      us_MWr_Param_Vec    =>  us_MWr_Param_Vec     ,  -- IN  std_logic_vector(6-1   downto 0);
1252 
                DMA_us_Status       =>  DMA_us_Status        ,  -- OUT std_logic_vector(31 downto 0);
1253 
      DMA_us_Done         =>  DMA_us_Done_i        ,  -- OUT std_logic;
1254 
      DMA_us_Busy         =>  DMA_us_Busy_i        ,  -- OUT std_logic;
1255 
      DMA_us_Tout         =>  DMA_us_Tout          ,  -- OUT std_logic;
1256 
 
1257 
      usHA_is_64b         =>  usHA_is_64b          ,  -- IN  std_logic;
1258 
      usBDA_is_64b        =>  usBDA_is_64b         ,  -- IN  std_logic;
1259 
 
1260 
      usLeng_Hi19b_True   =>  usLeng_Hi19b_True    ,  -- IN  std_logic;
1261 
      usLeng_Lo7b_True    =>  usLeng_Lo7b_True     ,  -- IN  std_logic;
1262 
 
1263 
 
1264 
                usDMA_Start         =>  usDMA_Start          ,  -- IN  std_logic;
1265 
                usDMA_Stop          =>  usDMA_Stop           ,  -- IN  std_logic;
1266 
                usDMA_Start2        =>  usDMA_Start2         ,  -- IN  std_logic;
1267 
                usDMA_Stop2         =>  usDMA_Stop2          ,  -- IN  std_logic;
1268 
                usDMA_Channel_Rst   =>  usDMA_Channel_Rst    ,  -- IN  std_logic;
1269 
      usDMA_Cmd_Ack       =>  usDMA_Cmd_Ack        ,  -- OUT std_logic;
1270 
 
1271 
 
1272 
      -- Reset signals
1273 
                MRd_Channel_Rst     =>  MRd_Channel_Rst      ,  -- IN  std_logic;
1274 
 
1275 
      -- to Interrupt module
1276 
      Sys_IRQ             =>  Sys_IRQ              ,  -- IN  std_logic_vector(31 downto 0);
1277 
 
1278 
      IG_Reset            =>  IG_Reset             ,
1279 
      IG_Host_Clear       =>  IG_Host_Clear        ,
1280 
      IG_Latency          =>  IG_Latency           ,
1281 
      IG_Num_Assert       =>  IG_Num_Assert        ,
1282 
      IG_Num_Deassert     =>  IG_Num_Deassert      ,
1283 
      IG_Asserting        =>  IG_Asserting         ,
1284 
 
1285 
 
1286 
      -- DDR write port
1287 
      DDR_wr_sof_A        =>  DDR_wr_sof_A    , -- OUT   std_logic;
1288 
      DDR_wr_eof_A        =>  DDR_wr_eof_A    , -- OUT   std_logic;
1289 
      DDR_wr_v_A          =>  DDR_wr_v_A      , -- OUT   std_logic;
1290 
      DDR_wr_FA_A         =>  DDR_wr_FA_A     , -- OUT   std_logic;
1291 
      DDR_wr_Shift_A      =>  DDR_wr_Shift_A  , -- OUT   std_logic;
1292 
      DDR_wr_Mask_A       =>  DDR_wr_Mask_A   , -- OUT   std_logic_vector(2-1 downto 0);
1293 
      DDR_wr_din_A        =>  DDR_wr_din_A    , -- OUT   std_logic_vector(C_DBUS_WIDTH-1 downto 0);
1294 
 
1295 
      DDR_wr_sof_B        =>  DDR_wr_sof_B    , -- OUT   std_logic;
1296 
      DDR_wr_eof_B        =>  DDR_wr_eof_B    , -- OUT   std_logic;
1297 
      DDR_wr_v_B          =>  DDR_wr_v_B      , -- OUT   std_logic;
1298 
      DDR_wr_FA_B         =>  DDR_wr_FA_B     , -- OUT   std_logic;
1299 
      DDR_wr_Shift_B      =>  DDR_wr_Shift_B  , -- OUT   std_logic;
1300 
      DDR_wr_Mask_B       =>  DDR_wr_Mask_B   , -- OUT   std_logic_vector(2-1 downto 0);
1301 
      DDR_wr_din_B        =>  DDR_wr_din_B    , -- OUT   std_logic_vector(C_DBUS_WIDTH-1 downto 0);
1302 
 
1303 
      DDR_wr_full         =>  DDR_wr_full     , -- IN    std_logic;
1304 
 
1305 
 
1306 
      Link_Buf_full       =>  Link_Buf_full   , -- IN    std_logic;
1307 
 
1308 
 
1309 
      -- Data generator table write
1310 
      tab_we              =>  tab_we          , -- OUT std_logic_vector(2-1 downto 0);
1311 
      tab_wa              =>  tab_wa          , -- OUT std_logic_vector(12-1 downto 0);
1312 
      tab_wd              =>  tab_wd          , -- OUT std_logic_vector(C_DBUS_WIDTH-1 downto 0);
1313 
 
1314 
      -- Additional
1315 
      cfg_dcommand        =>  cfg_dcommand         ,  -- IN  std_logic_vector(15 downto 0)
1316 
      localID             =>  localID                 -- IN  std_logic_vector(15 downto 0)
1317 
    );
1318 
 
1319 
 
1320 
 
1321 
    -- Tx TLP interface
1322 
    tx_Itf:
1323 
    tx_Transact
1324 
    port map(
1325 
      -- Common ports
1326 
      trn_clk             => trn_clk,             -- IN  std_logic,
1327 
      trn_reset_n         => trn_lnk_up_i     , -- trn_reset_n,         -- IN  std_logic,
1328 
      trn_lnk_up_n        => trn_lnk_up_n,        -- IN  std_logic,
1329 
 
1330 
      -- Transaction
1331 
      trn_tsof_n          => trn_tsof_n,          -- OUT std_logic,
1332 
      trn_teof_n          => trn_teof_n,          -- OUT std_logic,
1333 
      trn_td              => trn_td,              -- OUT std_logic_vector(31 downto 0),
1334 
      trn_trem_n          => trn_trem_n,          -- OUT STD_LOGIC_VECTOR (  7 downto 0 );
1335 
      trn_terrfwd_n       => trn_terrfwd_n,       -- OUT std_logic,
1336 
      trn_tsrc_rdy_n      => trn_tsrc_rdy_n,      -- OUT std_logic,
1337 
      trn_tdst_rdy_n      => trn_tdst_rdy_n,      -- IN  std_logic,
1338 
      trn_tsrc_dsc_n      => trn_tsrc_dsc_n,      -- OUT std_logic,
1339 
      trn_tdst_dsc_n      => trn_tdst_dsc_n,      -- IN  std_logic,
1340 
      trn_tbuf_av         => trn_tbuf_av,         -- IN  std_logic_vector(6 downto 0),
1341 
 
1342 
      -- Upstream DMA transferred bytes count up
1343 
      us_DMA_Bytes_Add    => us_DMA_Bytes_Add,    -- OUT std_logic;
1344 
      us_DMA_Bytes        => us_DMA_Bytes,        -- OUT std_logic_vector(C_TLP_FLD_WIDTH_OF_LENG+2 downto 0);
1345 
 
1346 
      -- MRd Channel
1347 
      pioCplD_Req         => pioCplD_Req,         -- IN  std_logic;
1348 
      pioCplD_RE          => pioCplD_RE,          -- OUT std_logic;
1349 
      pioCplD_Qout        => pioCplD_Qout,        -- IN  std_logic_vector(96 downto 0);
1350 
      pio_FC_stop         => pio_FC_stop,         -- OUT std_logic;
1351 
 
1352 
      -- downstream MRd Channel
1353 
      dsMRd_Req           => dsMRd_Req,           -- IN  std_logic;
1354 
      dsMRd_RE            => dsMRd_RE,            -- OUT std_logic;
1355 
      dsMRd_Qout          => dsMRd_Qout,          -- IN  std_logic_vector(96 downto 0);
1356 
 
1357 
      -- Upstream MWr/MRd Channel
1358 
      usTlp_Req           => usTlp_Req,           -- IN  std_logic;
1359 
      usTlp_RE            => usTlp_RE,            -- OUT std_logic;
1360 
      usTlp_Qout          => usTlp_Qout,          -- IN  std_logic_vector(96 downto 0);
1361 
      us_FC_stop          => us_FC_stop,          -- OUT std_logic;
1362 
      us_Last_sof         => us_Last_sof,         -- OUT std_logic;
1363 
      us_Last_eof         => us_Last_eof,         -- OUT std_logic;
1364 
 
1365 
      -- Irpt Channel
1366 
      Irpt_Req            => Irpt_Req,            -- IN  std_logic;
1367 
      Irpt_RE             => Irpt_RE,             -- OUT std_logic;
1368 
      Irpt_Qout           => Irpt_Qout,           -- IN  std_logic_vector(96 downto 0);
1369 
 
1370 
 
1371 
      -- Event Buffer FIFO read port
1372 
      eb_FIFO_re          => eb_FIFO_RdEn_i,      -- OUT std_logic;
1373 
      eb_FIFO_empty       => eb_FIFO_empty ,      -- IN  std_logic;
1374 
      eb_FIFO_qout        => eb_FIFO_qout  ,      -- IN  std_logic_vector(C_DBUS_WIDTH-1 downto 0);
1375 
 
1376 
      -- Registers read
1377 
      Regs_RdAddr         => Regs_RdAddr,         -- OUT std_logic_vector(15 downto 0);
1378 
      Regs_RdQout         => Regs_RdQout,         -- IN  std_logic_vector(31 downto 0);
1379 
 
1380 
      -- Message routing method
1381 
      Msg_Routing         => Msg_Routing,
1382 
 
1383 
      --  DDR read port
1384 
      DDR_rdc_sof         =>  DDR_rdc_sof       ,  -- OUT   std_logic;
1385 
      DDR_rdc_eof         =>  DDR_rdc_eof       ,  -- OUT   std_logic;
1386 
      DDR_rdc_v           =>  DDR_rdc_v         ,  -- OUT   std_logic;
1387 
      DDR_rdc_FA          =>  DDR_rdc_FA        ,  -- OUT   std_logic;
1388 
      DDR_rdc_Shift       =>  DDR_rdc_Shift     ,  -- OUT   std_logic;
1389 
      DDR_rdc_din         =>  DDR_rdc_din       ,  -- OUT   std_logic_vector(C_DBUS_WIDTH-1 downto 0);
1390 
      DDR_rdc_full        =>  DDR_rdc_full      ,  -- IN    std_logic;
1391 
 
1392 
      -- DDR payload FIFO Read Port
1393 
      DDR_FIFO_RdEn       =>  DDR_FIFO_RdEn     ,  -- OUT std_logic;
1394 
      DDR_FIFO_Empty      =>  DDR_FIFO_Empty    ,  -- IN  std_logic;
1395 
      DDR_FIFO_RdQout     =>  DDR_FIFO_RdQout   ,  -- IN  std_logic_vector(C_DBUS_WIDTH-1 downto 0);
1396 
--      DDR_rdD_sof         =>  DDR_rdD_sof       ,  -- IN    std_logic;
1397 
--      DDR_rdD_eof         =>  DDR_rdD_eof       ,  -- IN    std_logic;
1398 
--      DDR_rdDout_V        =>  DDR_rdDout_V      ,  -- IN    std_logic;
1399 
--      DDR_rdDout          =>  DDR_rdDout        ,  -- IN    std_logic_vector(C_DBUS_WIDTH-1 downto 0);
1400 
 
1401 
 
1402 
      -- Additional
1403 
      Tx_TimeOut          => Tx_TimeOut,          -- OUT std_logic;
1404 
      Tx_eb_TimeOut       => Tx_eb_TimeOut,       -- OUT std_logic;
1405 
      Format_Shower       => Format_Shower,       -- OUT std_logic;
1406 
      Tx_Reset            => Tx_Reset,            -- IN  std_logic;
1407 
      mbuf_UserFull       => mbuf_UserFull,       -- IN  std_logic;
1408 
      localID             => localID              -- IN  std_logic_vector(15 downto 0)
1409 
    );
1410 
 
1411 
 
1412 
 
1413 
  -- ------------------------------------------------
1414 
  --   Unified memory space
1415 
  -- ------------------------------------------------
1416 
   Memory_Space:
1417 
   Regs_Group
1418 
   PORT MAP(
1419 
 
1420 
      -- DCB protocol interface
1421 
      protocol_link_act   =>  protocol_link_act    ,  -- IN  std_logic_vector(2-1 downto 0);
1422 
      protocol_rst        =>  protocol_rst         ,  -- OUT std_logic;
1423 
 
1424 
      -- Fabric side: CTL Rx
1425 
      ctl_rv              =>  ctl_rv               ,  -- OUT std_logic;
1426 
      ctl_rd              =>  ctl_rd               ,  -- OUT std_logic_vector(C_DBUS_WIDTH/2-1 downto 0);
1427 
 
1428 
      -- Fabric side: CTL Tx
1429 
      ctl_ttake           =>  ctl_ttake            ,  -- OUT std_logic;
1430 
      ctl_tv              =>  ctl_tv               ,  -- IN  std_logic;
1431 
      ctl_td              =>  ctl_td               ,  -- IN  std_logic_vector(C_DBUS_WIDTH/2-1 downto 0);
1432 
      ctl_tstop           =>  ctl_tstop            ,  -- OUT std_logic;
1433 
 
1434 
      ctl_reset           =>  ctl_reset            ,  -- OUT std_logic;
1435 
      ctl_status          =>  ctl_status           ,  -- IN  std_logic_vector(C_DBUS_WIDTH/2-1 downto 0);
1436 
 
1437 
      -- Fabric side: DLM Rx
1438 
      dlm_tv              =>  dlm_tv               ,  -- OUT std_logic;
1439 
      dlm_td              =>  dlm_td               ,  -- OUT std_logic_vector(C_DBUS_WIDTH/2-1 downto 0);
1440 
 
1441 
      -- Fabric side: DLM Tx
1442 
      dlm_rv              =>  dlm_rv               ,  -- IN  std_logic;
1443 
      dlm_rd              =>  dlm_rd               ,  -- IN  std_logic_vector(C_DBUS_WIDTH/2-1 downto 0);
1444 
 
1445 
      -- Event Buffer status + reset
1446 
      eb_FIFO_Status      =>  eb_FIFO_Status  ,      -- IN  std_logic_vector(C_DBUS_WIDTH-1 downto 0);
1447 
      eb_FIFO_Rst         =>  eb_FIFO_Rst     ,      -- OUT std_logic;
1448 
           H2B_FIFO_Status        => H2B_FIFO_Status  ,
1449 
           B2H_FIFO_Status        => B2H_FIFO_Status  ,
1450 
 
1451 
      -- Registers
1452 
      Regs_WrEnA          =>  Regs_WrEnA      ,      -- IN  std_logic;
1453 
      Regs_WrMaskA        =>  Regs_WrMaskA    ,      -- IN  std_logic_vector(2-1   downto 0);
1454 
      Regs_WrAddrA        =>  Regs_WrAddrA    ,      -- IN  std_logic_vector(16-1   downto 0);
1455 
      Regs_WrDinA         =>  Regs_WrDinA     ,      -- IN  std_logic_vector(32-1   downto 0);
1456 
 
1457 
      Regs_WrEnB          =>  Regs_WrEnB      ,      -- IN  std_logic;
1458 
      Regs_WrMaskB        =>  Regs_WrMaskB    ,      -- IN  std_logic_vector(2-1   downto 0);
1459 
      Regs_WrAddrB        =>  Regs_WrAddrB    ,      -- IN  std_logic_vector(16-1   downto 0);
1460 
      Regs_WrDinB         =>  Regs_WrDinB     ,      -- IN  std_logic_vector(32-1   downto 0);
1461 
 
1462 
 
1463 
      Regs_RdAddr         =>  Regs_RdAddr     ,      -- IN  std_logic_vector(15 downto 0);
1464 
      Regs_RdQout         =>  Regs_RdQout     ,      -- OUT std_logic_vector(31 downto 0);
1465 
 
1466 
      -- Downstream DMA transferred bytes count up
1467 
      ds_DMA_Bytes_Add    =>  ds_DMA_Bytes_Add     , -- IN  std_logic;
1468 
      ds_DMA_Bytes        =>  ds_DMA_Bytes         , -- IN  std_logic_vector(C_TLP_FLD_WIDTH_OF_LENG+2 downto 0);
1469 
 
1470 
      -- Register values
1471 
      DMA_ds_PA           =>  DMA_ds_PA            ,  -- OUT std_logic_vector(63 downto 0);
1472 
      DMA_ds_HA           =>  DMA_ds_HA            ,  -- OUT std_logic_vector(63 downto 0);
1473 
      DMA_ds_BDA          =>  DMA_ds_BDA           ,  -- OUT std_logic_vector(63 downto 0);
1474 
      DMA_ds_Length       =>  DMA_ds_Length        ,  -- OUT std_logic_vector(31 downto 0);
1475 
      DMA_ds_Control      =>  DMA_ds_Control       ,  -- OUT std_logic_vector(31 downto 0);
1476 
      dsDMA_BDA_eq_Null   =>  dsDMA_BDA_eq_Null    ,  -- OUT std_logic;
1477 
      DMA_ds_Status       =>  DMA_ds_Status        ,  -- IN  std_logic_vector(31 downto 0);
1478 
      DMA_ds_Done         =>  DMA_ds_Done_i        ,  -- IN  std_logic;
1479 
      DMA_ds_Tout         =>  DMA_ds_Tout          ,  -- IN  std_logic;
1480 
 
1481 
      dsHA_is_64b         =>  dsHA_is_64b          ,  -- OUT std_logic;
1482 
      dsBDA_is_64b        =>  dsBDA_is_64b         ,  -- OUT std_logic;
1483 
 
1484 
      dsLeng_Hi19b_True   =>  dsLeng_Hi19b_True    ,  -- OUT std_logic;
1485 
      dsLeng_Lo7b_True    =>  dsLeng_Lo7b_True     ,  -- OUT std_logic;
1486 
 
1487 
      dsDMA_Start         =>  dsDMA_Start          ,  -- OUT std_logic;
1488 
      dsDMA_Stop          =>  dsDMA_Stop           ,  -- OUT std_logic;
1489 
      dsDMA_Start2        =>  dsDMA_Start2         ,  -- OUT std_logic;
1490 
      dsDMA_Stop2         =>  dsDMA_Stop2          ,  -- OUT std_logic;
1491 
      dsDMA_Channel_Rst   =>  dsDMA_Channel_Rst    ,  -- OUT std_logic;
1492 
      dsDMA_Cmd_Ack       =>  dsDMA_Cmd_Ack        ,  -- IN  std_logic;
1493 
 
1494 
      -- Upstream DMA transferred bytes count up
1495 
      us_DMA_Bytes_Add    =>  us_DMA_Bytes_Add     ,  -- IN  std_logic;
1496 
      us_DMA_Bytes        =>  us_DMA_Bytes         ,  -- IN  std_logic_vector(C_TLP_FLD_WIDTH_OF_LENG+2 downto 0);
1497 
 
1498 
      DMA_us_PA           =>  DMA_us_PA            ,  -- OUT std_logic_vector(63 downto 0);
1499 
      DMA_us_HA           =>  DMA_us_HA            ,  -- OUT std_logic_vector(63 downto 0);
1500 
      DMA_us_BDA          =>  DMA_us_BDA           ,  -- OUT std_logic_vector(63 downto 0);
1501 
      DMA_us_Length       =>  DMA_us_Length        ,  -- OUT std_logic_vector(31 downto 0);
1502 
      DMA_us_Control      =>  DMA_us_Control       ,  -- OUT std_logic_vector(31 downto 0);
1503 
      usDMA_BDA_eq_Null   =>  usDMA_BDA_eq_Null    ,  -- OUT std_logic;
1504 
      us_MWr_Param_Vec    =>  us_MWr_Param_Vec     ,  -- OUT std_logic_vector(6-1   downto 0);
1505 
      DMA_us_Status       =>  DMA_us_Status        ,  -- IN  std_logic_vector(31 downto 0);
1506 
      DMA_us_Done         =>  DMA_us_Done_i        ,  -- IN  std_logic;
1507 
      DMA_us_Tout         =>  DMA_us_Tout          ,  -- IN  std_logic;
1508 
 
1509 
      usHA_is_64b         =>  usHA_is_64b          ,  -- OUT std_logic;
1510 
      usBDA_is_64b        =>  usBDA_is_64b         ,  -- OUT std_logic;
1511 
 
1512 
      usLeng_Hi19b_True   =>  usLeng_Hi19b_True    ,  -- OUT std_logic;
1513 
      usLeng_Lo7b_True    =>  usLeng_Lo7b_True     ,  -- OUT std_logic;
1514 
 
1515 
 
1516 
      usDMA_Start         =>  usDMA_Start          ,  -- OUT std_logic;
1517 
      usDMA_Stop          =>  usDMA_Stop           ,  -- OUT std_logic;
1518 
      usDMA_Start2        =>  usDMA_Start2         ,  -- OUT std_logic;
1519 
      usDMA_Stop2         =>  usDMA_Stop2          ,  -- OUT std_logic;
1520 
      usDMA_Channel_Rst   =>  usDMA_Channel_Rst    ,  -- OUT std_logic;
1521 
      usDMA_Cmd_Ack       =>  usDMA_Cmd_Ack        ,  -- IN  std_logic;
1522 
 
1523 
      -- Reset signals
1524 
      MRd_Channel_Rst     =>  MRd_Channel_Rst      ,  -- OUT std_logic;
1525 
      Tx_Reset            =>  Tx_Reset             ,  -- OUT std_logic;
1526 
 
1527 
      -- to Interrupt module
1528 
      Sys_IRQ             =>  Sys_IRQ              ,  -- OUT std_logic_vector(31 downto 0);
1529 
      DAQ_irq             =>  DAQ_irq              ,  -- IN  std_logic;
1530 
      CTL_irq             =>  CTL_irq              ,  -- IN  std_logic;
1531 
      DLM_irq             =>  DLM_irq              ,  -- IN  std_logic;
1532 
 
1533 
      -- System error and info
1534 
      eb_FIFO_ow          =>  eb_FIFO_ow           ,
1535 
      Tx_TimeOut          =>  Tx_TimeOut           ,
1536 
      Tx_eb_TimeOut       =>  Tx_eb_TimeOut        ,
1537 
      Msg_Routing         =>  Msg_Routing          ,
1538 
      pcie_link_width     =>  pcie_link_width      ,
1539 
      cfg_dcommand        =>  cfg_dcommand         ,
1540 
 
1541 
      -- Interrupt Generation Signals
1542 
      IG_Reset            =>  IG_Reset             ,
1543 
      IG_Host_Clear       =>  IG_Host_Clear        ,
1544 
      IG_Latency          =>  IG_Latency           ,
1545 
      IG_Num_Assert       =>  IG_Num_Assert        ,
1546 
      IG_Num_Deassert     =>  IG_Num_Deassert      ,
1547 
      IG_Asserting        =>  IG_Asserting         ,
1548 
 
1549 
      -- Data generator control
1550 
      DG_is_Running       =>  DG_is_Running        ,
1551 
      DG_Reset            =>  DG_Reset             ,
1552 
      DG_Mask             =>  DG_Mask              ,
1553 
 
1554 
      -- SIMONE Register: PC-->FPGA
1555 
      reg01_tv                     => reg01_tv,
1556 
      reg01_td                     => reg01_td,
1557 
      reg02_tv                     => reg02_tv,
1558 
      reg02_td                     => reg02_td,
1559 
      reg03_tv                     => reg03_tv,
1560 
      reg03_td                     => reg03_td,
1561 
      reg04_tv                     => reg04_tv,
1562 
      reg04_td                     => reg04_td,
1563 
      reg05_tv                     => reg05_tv,
1564 
      reg05_td                     => reg05_td,
1565 
      reg06_tv                     => reg06_tv,
1566 
      reg06_td                     => reg06_td,
1567 
      reg07_tv                     => reg07_tv,
1568 
      reg07_td                     => reg07_td,
1569 
      reg08_tv                     => reg08_tv,
1570 
      reg08_td                     => reg08_td,
1571 
      reg09_tv                     => reg09_tv,
1572 
      reg09_td                     => reg09_td,
1573 
      reg10_tv                     => reg10_tv,
1574 
      reg10_td                     => reg10_td,
1575 
      reg11_tv                     => reg11_tv,
1576 
      reg11_td                     => reg11_td,
1577 
      reg12_tv                     => reg12_tv,
1578 
      reg12_td                     => reg12_td,
1579 
      reg13_tv                     => reg13_tv,
1580 
      reg13_td                     => reg13_td,
1581 
      reg14_tv                     => reg14_tv,
1582 
      reg14_td                     => reg14_td,
1583 
 
1584 
      -- SIMONE Register: FPGA-->PC
1585 
      reg01_rv                     => reg01_rv,
1586 
      reg01_rd                     => reg01_rd,
1587 
      reg02_rv                     => reg02_rv,
1588 
      reg02_rd                     => reg02_rd,
1589 
      reg03_rv                     => reg03_rv,
1590 
      reg03_rd                     => reg03_rd,
1591 
      reg04_rv                     => reg04_rv,
1592 
      reg04_rd                     => reg04_rd,
1593 
      reg05_rv                     => reg05_rv,
1594 
      reg05_rd                     => reg05_rd,
1595 
      reg06_rv                     => reg06_rv,
1596 
      reg06_rd                     => reg06_rd,
1597 
      reg07_rv                     => reg07_rv,
1598 
      reg07_rd                     => reg07_rd,
1599 
      reg08_rv                     => reg08_rv,
1600 
      reg08_rd                     => reg08_rd,
1601 
      reg09_rv                     => reg09_rv,
1602 
      reg09_rd                     => reg09_rd,
1603 
      reg10_rv                     => reg10_rv,
1604 
      reg10_rd                     => reg10_rd,
1605 
      reg11_rv                     => reg11_rv,
1606 
      reg11_rd                     => reg11_rd,
1607 
      reg12_rv                     => reg12_rv,
1608 
      reg12_rd                     => reg12_rd,
1609 
      reg13_rv                     => reg13_rv,
1610 
      reg13_rd                     => reg13_rd,
1611 
      reg14_rv                     => reg14_rv,
1612 
      reg14_rd                     => reg14_rd,
1613 
 
1614 
                -- SIMONE debug signals
1615 
      debug_in_1i                                                 => debug_in_1i,
1616 
      debug_in_2i                                                 => debug_in_2i,
1617 
      debug_in_3i                                                 => debug_in_3i,
1618 
      debug_in_4i                                                 => debug_in_4i,
1619 
 
1620 
      -- Common
1621 
      trn_clk             =>  trn_clk              ,  -- IN  std_logic;
1622 
      trn_lnk_up_n        =>  trn_lnk_up_n         ,  -- IN  std_logic,
1623 
      trn_reset_n         =>  trn_reset_n             -- IN  std_logic;
1624 
        );
1625 
 
1626 
 
1627 
end architecture Behavioral;

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