OpenCores
URL https://opencores.org/ocsvn/pcie_sg_dma/pcie_sg_dma/trunk

Subversion Repositories pcie_sg_dma

[/] [pcie_sg_dma/] [branches/] [Virtex6/] [ML605_ISE13.3/] [MyUserLogic/] [UserLogic_00/] [synopsis] - Blame information for rev 13

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Line No. Rev Author Line
1 13 barabba
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1372
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1604
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1612
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1620
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1627
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1628
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1629
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1634
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1642
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1643
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1644
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1656
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1658
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1660
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1666
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1668
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1672
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1673
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1674
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1676
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1677
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1680
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1681
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1682
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1683
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1684
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1685
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1688
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1692
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1693
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1698
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1700
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1701
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1702
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1703
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1704
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1705
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1706
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1707
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1708
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1709
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1712
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1714
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1716
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1720
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1721
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1722
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1723
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1724
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1725
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1726
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1728
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1729
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1730
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1731
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1732
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1733
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1736
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1737
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1738
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1739
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1740
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1741
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1742
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1743
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1744
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1745
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1746
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1747
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1748
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1749
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1750
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1751
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1752
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1753
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1754
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1755
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1756
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1757
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1758
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1759
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1760
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1761
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1762
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1763
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1764
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1765
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1766
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1767
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1768
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1769
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1770
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1771
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1772
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1773
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1774
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1776
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1777
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1778
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1779
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1780
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1781
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1782
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1783
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1784
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1785
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1786
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1787
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1788
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1789
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1790
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1791
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1792
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1793
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1794
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1795
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1796
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1797
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1798
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1799
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1800
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1801
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1802
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1803
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1804
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1805
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1806
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1807
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1808
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1809
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1810
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1811
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1812
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1813
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1814
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1815
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1816
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1817
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1818
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1819
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1820
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1821
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1822
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1823
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1824
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1825
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1826
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1827
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1828
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1829
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1830
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1831
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1832
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1833
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1834
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1835
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1836
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1837
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1838
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1839
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1840
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1841
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1842
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1843
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1844
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1845
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1846
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1847
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1848
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1849
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1850
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1851
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1852
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1853
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1854
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1855
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1856
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1911
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1922
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1923
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1929
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1930
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1931
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1935
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2007
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2014
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2015
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2017
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2018
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2019
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2022
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2025
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2026
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2027
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2082
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2083
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2099
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2105
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2106
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2107
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2114
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2122
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2161
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2162
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2163
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2172
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2178
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2266
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2274
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2282
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2323
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2330
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2338
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2346
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2354
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2362
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2369
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2370
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2377
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2378
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2386
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2402
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2403
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2412
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2419
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2420
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2424
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2425
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2426
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2427
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2428
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2433
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2434
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2435
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2436
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2437
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2440
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2441
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2442
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2443
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2445
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2448
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2449
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2450
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2451
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2452
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2453
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2454
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2455
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2456
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2457
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2458
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2459
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2460
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2464
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2465
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2466
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2467
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2468
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2469
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2471
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2482
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2483
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2484
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2491
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2492
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2493
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2498
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2499
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2500
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2501
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2502
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2504
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2505
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2506
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2507
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2508
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2509
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2510
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2512
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2513
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2514
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2515
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2516
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2519
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2520
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2521
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2522
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2523
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2524
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2525
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2526
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2528
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2529
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2530
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2531
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2532
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2533
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2534
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2535
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2536
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2537
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2538
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2539
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2540
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2542
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2544
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2545
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2546
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2547
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2548
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2549
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2550
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2552
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2553
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2554
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2555
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2556
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2558
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2560
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2561
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2562
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2563
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2564
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2565
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2566
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2572
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2573
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2578
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2580
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2588
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2596
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2604
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2612
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2616
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2619
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2620
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2624
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2628
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2636
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2644
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2652
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2708
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2716
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2724
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2732
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2804
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2812
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2820
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2828
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2852
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2858
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2860
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2868
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2876
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2892
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2898
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2899
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2900
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2901
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2902
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2903
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2904
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2905
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2906
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2907
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2908
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2909
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2910
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2912
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2913
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2914
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2915
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2916
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2917
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2920
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2921
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2922
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2923
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2924
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2925
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2928
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2930
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2931
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2932
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2933
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2936
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2937
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2938
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2939
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2940
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2941
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2942
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2944
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2946
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2947
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2948
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2949
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2954
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2955
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2956
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2957
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2960
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2961
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2962
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2963
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2964
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2965
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2967
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2968
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2969
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2970
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2971
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2972
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2973
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2976
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2977
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2978
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2979
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2980
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2981
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2984
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2985
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2986
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2988
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2989
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2991
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2992
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2993
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2994
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2995
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2996
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2997
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2999
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3000
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3001
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3002
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3003
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3004
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3005
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3008
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3009
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3010
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3011
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3012
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3013
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3014
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3016
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3017
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3018
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3019
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3020
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3021
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3022
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3023
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3024
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3025
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3026
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3027
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3028
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3029
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3030
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3031
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3032
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3033
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3034
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3035
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3036
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3037
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3038
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3039
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3040
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3041
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3042
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3043
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3044
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3045
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3046
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3047
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3048
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3049
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3050
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3051
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3052
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3053
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3054
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3055
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3056
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3057
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3058
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3059
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3060
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3061
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3062
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3063
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3064
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3065
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3066
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3067
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3068
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3069
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3070
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3071
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3072
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3073
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3074
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3075
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3076
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3077
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3078
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3079
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3080
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4341
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4342
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4343
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4344
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4345
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4346
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4347
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4348
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4349
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4350
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4351
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4352
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4360
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4361
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4362
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4363
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4364
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4367
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4368
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4369
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4377
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4378
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4379
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4380
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4381
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4382
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4383
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4384
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4385
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4386
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4387
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4388
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4395
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4396
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4397
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4398
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4399
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4400
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4401
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4403
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4404
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4405
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4412
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4413
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4414
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4415
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4416
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4417
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4418
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4419
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4420
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4421
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4422
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4423
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4432
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4434
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4440
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4441
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4450
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4494
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4495
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4502
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4503
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4504
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4505
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4506
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4507
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4508
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4509
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4510
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4512
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4513
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4514
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4530
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4531
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4548
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4556
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4557
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4558
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4559
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4561
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4562
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4563
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4564
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4565
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4566
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4567
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4576
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4577
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4578
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4579
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4584
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4585
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4593
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4594
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4595
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4596
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4597
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4598
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4599
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4600
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4601
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4602
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4603
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4610
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4611
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4612
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4613
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4614
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4615
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4616
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4617
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4618
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4619
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4620
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4621
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4622
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4630
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4631
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4632
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4633
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4634
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4635
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4636
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4637
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4638
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4639
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4640
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4650
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4652
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4653
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4654
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4655
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4656
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4657
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4658
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4664
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4665
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4667
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4668
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4669
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4670
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4671
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4672
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4673
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4674
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4675
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4680
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4682
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4683
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4684
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4685
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4686
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4687
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4688
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4690
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4691
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4692
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4693
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4699
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4700
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4701
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4702
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4703
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4704
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4705
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4706
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4707
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4708
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4709
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4710
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4711
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4712
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4714
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4718
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4719
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4720
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4721
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4722
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4723
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4724
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4725
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4726
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4727
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4728
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4729
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4730
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4731
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4732
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4733
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4734
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4735
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4736
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4737
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4738
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4739
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4740
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4741
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4742
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4743
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4744
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4745
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4746
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4747
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4748
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4749
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4750
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4751
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4752
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4753
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4754
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4757
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4758
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4759
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4760
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4761
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4762
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4763
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4764
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4765
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4766
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4767
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4768
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4769
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4770
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4771
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4772
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4775
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4776
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4777
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4778
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4779
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4780
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4781
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4782
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4783
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4784
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4785
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4786
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4787
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4788
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4789
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4790
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4791
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4792
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4793
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4794
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4795
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4796
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4797
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4798
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4799
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4800
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4801
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4802
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4803
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4804
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4805
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4806
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4807
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4808
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4809
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4810
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4811
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4812
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4813
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4814
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4815
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4816
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4817
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4818
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4819
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4820
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4821
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4822
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4823
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4824
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4825
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4826
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4827
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4829
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4830
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4832
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4833
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4834
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4835
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4836
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4837
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4838
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4840
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4841
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4842
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4843
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4844
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4847
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4850
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4851
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4852
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4853
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4854
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4855
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4856
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4857
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4858
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4859
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4860
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4861
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4862
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4865
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4866
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4868
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4869
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4870
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4871
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4872
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4873
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4874
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4875
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4876
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4877
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4878
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4879
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4880
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4881
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4882
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4883
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4884
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4886
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4887
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4888
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4889
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4890
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4891
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4892
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4893
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4894
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4895
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4896
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4897
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4898
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4899
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4900
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4901
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4902
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4903
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4904
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4905
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4906
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4907
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4908
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4909
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4910
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4911
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4912
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4913
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4914
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4915
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4916
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4917
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4918
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4919
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4920
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4921
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4922
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4923
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4924
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4925
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4926
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4927
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4928
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4929
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4930
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4931
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4932
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4933
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4934
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4935
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4937
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4938
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4940
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4941
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4942
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4943
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4944
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4945
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4946
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4947
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4949
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4950
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4951
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4952
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4956
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4958
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4959
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4960
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4961
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4962
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4963
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4964
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4965
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4966
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4967
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4968
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4969
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4970
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4973
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4974
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4978
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4979
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4980
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4981
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4982
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4983
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4984
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4985
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4986
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4987
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4988
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4991
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4996
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4997
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4998
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4999
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5000
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5001
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5002
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5003
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5004
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5005
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5006
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5007
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5009
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5010
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5012
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5014
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5015
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5016
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5017
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5018
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5019
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5020
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5021
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5022
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5023
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5024
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5025
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5027
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5028
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5030
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5031
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5032
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5033
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5034
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5035
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5036
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5037
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5038
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5039
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5040
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5041
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5042
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5043
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5044
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5045
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5046
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5047
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5048
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5050
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5051
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5052
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5053
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5054
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5055
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5056
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5057
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5058
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5059
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5060
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5061
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5062
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5063
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5064
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5066
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5068
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5069
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5070
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5071
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5072
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5073
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5074
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5075
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5076
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5077
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5078
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5081
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5082
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5084
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5086
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5087
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5088
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5089
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5090
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5091
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5092
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5093
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5094
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5095
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5096
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5098
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5099
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5100
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5101
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5102
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5103
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5104
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5105
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5106
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5107
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5108
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5109
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5110
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5111
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5112
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5113
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5114
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5117
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5118
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5119
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5120
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5122
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5123
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5124
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5125
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5126
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5127
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5128
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5129
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5130
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5131
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5132
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5138
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5140
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5141
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5143
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5144
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5145
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5146
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5147
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5148
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5149
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5150
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5156
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5158
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5159
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5160
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5161
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5162
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5163
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5164
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5165
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5166
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5167
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5168
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5171
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5172
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5174
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5175
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5176
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5177
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5178
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5179
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5180
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5181
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5182
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5183
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5184
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5185
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5186
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5187
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5189
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5190
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5192
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5194
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5195
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5196
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5197
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5198
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5199
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5200
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5201
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5202
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5203
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5204
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5208
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5210
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5211
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5212
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5213
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5214
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5215
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5216
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5217
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5218
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5219
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5220
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5221
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5222
              'inputFile' => 'pcie_userlogic_00_inout_logic_reg07_td.dat',
5223
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5224
              'is_gateway_port' => 1,
5225
              'must_be_hdl_vector' => 1,
5226
              'period' => 1,
5227
              'port_id' => 0,
5228
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/reg07_td/reg07_td',
5229
              'source_block' => 'PCIe_UserLogic_00/INOUT_LOGIC/reg07_td',
5230
              'timingConstraint' => 'none',
5231
              'type' => 'UFix_32_0',
5232
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5233
            'direction' => 'in',
5234
            'hdlType' => 'std_logic_vector(31 downto 0)',
5235
            'width' => 32,
5236
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5237
          'reg07_tv' => {
5238
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5239
              'bin_pt' => 0,
5240
              'inputFile' => 'pcie_userlogic_00_inout_logic_reg07_tv.dat',
5241
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5242
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5243
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5244
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5245
              'port_id' => 0,
5246
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/reg07_tv/reg07_tv',
5247
              'source_block' => 'PCIe_UserLogic_00/INOUT_LOGIC/reg07_tv',
5248
              'timingConstraint' => 'none',
5249
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5250
            },
5251
            'direction' => 'in',
5252
            'hdlType' => 'std_logic',
5253
            'width' => 1,
5254
          },
5255
          'reg08_rd' => {
5256
            'attributes' => {
5257
              'bin_pt' => 0,
5258
              'inputFile' => 'pcie_userlogic_00_inout_logic_reg08_rd.dat',
5259
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5260
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5261
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5262
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5263
              'port_id' => 0,
5264
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/reg08_rd/reg08_rd',
5265
              'source_block' => 'PCIe_UserLogic_00/INOUT_LOGIC/reg08_rd',
5266
              'timingConstraint' => 'none',
5267
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5268
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5269
            'direction' => 'out',
5270
            'hdlType' => 'std_logic_vector(31 downto 0)',
5271
            'width' => 32,
5272
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5273
          'reg08_rv' => {
5274
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5275
              'bin_pt' => 0,
5276
              'inputFile' => 'pcie_userlogic_00_inout_logic_reg08_rv.dat',
5277
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5278
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5279
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5280
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5281
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5282
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/reg08_rv/reg08_rv',
5283
              'source_block' => 'PCIe_UserLogic_00/INOUT_LOGIC/reg08_rv',
5284
              'timingConstraint' => 'none',
5285
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5286
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5287
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5288
            'hdlType' => 'std_logic',
5289
            'width' => 1,
5290
          },
5291
          'reg08_td' => {
5292
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5293
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5294
              'inputFile' => 'pcie_userlogic_00_inout_logic_reg08_td.dat',
5295
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5296
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5297
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5298
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5299
              'port_id' => 0,
5300
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/reg08_td/reg08_td',
5301
              'source_block' => 'PCIe_UserLogic_00/INOUT_LOGIC/reg08_td',
5302
              'timingConstraint' => 'none',
5303
              'type' => 'UFix_32_0',
5304
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5305
            'direction' => 'in',
5306
            'hdlType' => 'std_logic_vector(31 downto 0)',
5307
            'width' => 32,
5308
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5309
          'reg08_tv' => {
5310
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5311
              'bin_pt' => 0,
5312
              'inputFile' => 'pcie_userlogic_00_inout_logic_reg08_tv.dat',
5313
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5314
              'is_gateway_port' => 1,
5315
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5316
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5317
              'port_id' => 0,
5318
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/reg08_tv/reg08_tv',
5319
              'source_block' => 'PCIe_UserLogic_00/INOUT_LOGIC/reg08_tv',
5320
              'timingConstraint' => 'none',
5321
              'type' => 'Bool',
5322
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5323
            'direction' => 'in',
5324
            'hdlType' => 'std_logic',
5325
            'width' => 1,
5326
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5327
          'reg09_rd' => {
5328
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5329
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5330
              'inputFile' => 'pcie_userlogic_00_inout_logic_reg09_rd.dat',
5331
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5332
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5333
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5334
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5335
              'port_id' => 0,
5336
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/reg09_rd/reg09_rd',
5337
              'source_block' => 'PCIe_UserLogic_00/INOUT_LOGIC/reg09_rd',
5338
              'timingConstraint' => 'none',
5339
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5340
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5341
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5342
            'hdlType' => 'std_logic_vector(31 downto 0)',
5343
            'width' => 32,
5344
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5345
          'reg09_rv' => {
5346
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5347
              'bin_pt' => 0,
5348
              'inputFile' => 'pcie_userlogic_00_inout_logic_reg09_rv.dat',
5349
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5350
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5351
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5352
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5353
              'port_id' => 0,
5354
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/reg09_rv/reg09_rv',
5355
              'source_block' => 'PCIe_UserLogic_00/INOUT_LOGIC/reg09_rv',
5356
              'timingConstraint' => 'none',
5357
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5358
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5359
            'direction' => 'out',
5360
            'hdlType' => 'std_logic',
5361
            'width' => 1,
5362
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5363
          'reg09_td' => {
5364
            'attributes' => {
5365
              'bin_pt' => 0,
5366
              'inputFile' => 'pcie_userlogic_00_inout_logic_reg09_td.dat',
5367
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5368
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5369
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5370
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5371
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5372
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/reg09_td/reg09_td',
5373
              'source_block' => 'PCIe_UserLogic_00/INOUT_LOGIC/reg09_td',
5374
              'timingConstraint' => 'none',
5375
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5376
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5377
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5378
            'hdlType' => 'std_logic_vector(31 downto 0)',
5379
            'width' => 32,
5380
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5381
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5382
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5383
              'bin_pt' => 0,
5384
              'inputFile' => 'pcie_userlogic_00_inout_logic_reg09_tv.dat',
5385
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5386
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5387
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5388
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5389
              'port_id' => 0,
5390
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/reg09_tv/reg09_tv',
5391
              'source_block' => 'PCIe_UserLogic_00/INOUT_LOGIC/reg09_tv',
5392
              'timingConstraint' => 'none',
5393
              'type' => 'Bool',
5394
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5395
            'direction' => 'in',
5396
            'hdlType' => 'std_logic',
5397
            'width' => 1,
5398
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5399
          'reg10_rd' => {
5400
            'attributes' => {
5401
              'bin_pt' => 0,
5402
              'inputFile' => 'pcie_userlogic_00_inout_logic_reg10_rd.dat',
5403
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5404
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5405
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5406
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5407
              'port_id' => 0,
5408
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/reg10_rd/reg10_rd',
5409
              'source_block' => 'PCIe_UserLogic_00/INOUT_LOGIC/reg10_rd',
5410
              'timingConstraint' => 'none',
5411
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5412
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5413
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5414
            'hdlType' => 'std_logic_vector(31 downto 0)',
5415
            'width' => 32,
5416
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5417
          'reg10_rv' => {
5418
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5419
              'bin_pt' => 0,
5420
              'inputFile' => 'pcie_userlogic_00_inout_logic_reg10_rv.dat',
5421
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5422
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5423
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5424
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5425
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5426
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/reg10_rv/reg10_rv',
5427
              'source_block' => 'PCIe_UserLogic_00/INOUT_LOGIC/reg10_rv',
5428
              'timingConstraint' => 'none',
5429
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5430
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5431
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5432
            'hdlType' => 'std_logic',
5433
            'width' => 1,
5434
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5435
          'reg10_td' => {
5436
            'attributes' => {
5437
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5438
              'inputFile' => 'pcie_userlogic_00_inout_logic_reg10_td.dat',
5439
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5440
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5441
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5442
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5443
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5444
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/reg10_td/reg10_td',
5445
              'source_block' => 'PCIe_UserLogic_00/INOUT_LOGIC/reg10_td',
5446
              'timingConstraint' => 'none',
5447
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5448
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5449
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5450
            'hdlType' => 'std_logic_vector(31 downto 0)',
5451
            'width' => 32,
5452
          },
5453
          'reg10_tv' => {
5454
            'attributes' => {
5455
              'bin_pt' => 0,
5456
              'inputFile' => 'pcie_userlogic_00_inout_logic_reg10_tv.dat',
5457
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5458
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5459
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5460
              'period' => 1,
5461
              'port_id' => 0,
5462
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/reg10_tv/reg10_tv',
5463
              'source_block' => 'PCIe_UserLogic_00/INOUT_LOGIC/reg10_tv',
5464
              'timingConstraint' => 'none',
5465
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5466
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5467
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5468
            'hdlType' => 'std_logic',
5469
            'width' => 1,
5470
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5471
          'reg11_rd' => {
5472
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5473
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5474
              'inputFile' => 'pcie_userlogic_00_inout_logic_reg11_rd.dat',
5475
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5476
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5477
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5478
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5479
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5480
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/reg11_rd/reg11_rd',
5481
              'source_block' => 'PCIe_UserLogic_00/INOUT_LOGIC/reg11_rd',
5482
              'timingConstraint' => 'none',
5483
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5484
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5485
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5486
            'hdlType' => 'std_logic_vector(31 downto 0)',
5487
            'width' => 32,
5488
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5489
          'reg11_rv' => {
5490
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5491
              'bin_pt' => 0,
5492
              'inputFile' => 'pcie_userlogic_00_inout_logic_reg11_rv.dat',
5493
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5494
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5495
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5496
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5497
              'port_id' => 0,
5498
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/reg11_rv/reg11_rv',
5499
              'source_block' => 'PCIe_UserLogic_00/INOUT_LOGIC/reg11_rv',
5500
              'timingConstraint' => 'none',
5501
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5502
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5503
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5504
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5505
            'width' => 1,
5506
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5507
          'reg11_td' => {
5508
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5509
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5510
              'inputFile' => 'pcie_userlogic_00_inout_logic_reg11_td.dat',
5511
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5512
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5513
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5514
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5515
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5516
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/reg11_td/reg11_td',
5517
              'source_block' => 'PCIe_UserLogic_00/INOUT_LOGIC/reg11_td',
5518
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5519
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5520
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5521
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5522
            'hdlType' => 'std_logic_vector(31 downto 0)',
5523
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5524
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5525
          'reg11_tv' => {
5526
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5527
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5528
              'inputFile' => 'pcie_userlogic_00_inout_logic_reg11_tv.dat',
5529
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5530
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5531
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5532
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5533
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5534
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/reg11_tv/reg11_tv',
5535
              'source_block' => 'PCIe_UserLogic_00/INOUT_LOGIC/reg11_tv',
5536
              'timingConstraint' => 'none',
5537
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5538
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5539
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5540
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5541
            'width' => 1,
5542
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5543
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5544
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5545
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5546
              'inputFile' => 'pcie_userlogic_00_inout_logic_reg12_rd.dat',
5547
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5548
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5549
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5550
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5551
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5552
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/reg12_rd/reg12_rd',
5553
              'source_block' => 'PCIe_UserLogic_00/INOUT_LOGIC/reg12_rd',
5554
              'timingConstraint' => 'none',
5555
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5556
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5557
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5558
            'hdlType' => 'std_logic_vector(31 downto 0)',
5559
            'width' => 32,
5560
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5561
          'reg12_rv' => {
5562
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5563
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5564
              'inputFile' => 'pcie_userlogic_00_inout_logic_reg12_rv.dat',
5565
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5566
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5567
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5568
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5569
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5570
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/reg12_rv/reg12_rv',
5571
              'source_block' => 'PCIe_UserLogic_00/INOUT_LOGIC/reg12_rv',
5572
              'timingConstraint' => 'none',
5573
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5574
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5575
            'direction' => 'out',
5576
            'hdlType' => 'std_logic',
5577
            'width' => 1,
5578
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5579
          'reg12_td' => {
5580
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5581
              'bin_pt' => 0,
5582
              'inputFile' => 'pcie_userlogic_00_inout_logic_reg12_td.dat',
5583
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5584
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5585
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5586
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5587
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5588
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5589
              'source_block' => 'PCIe_UserLogic_00/INOUT_LOGIC/reg12_td',
5590
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5591
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5592
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5593
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5594
            'hdlType' => 'std_logic_vector(31 downto 0)',
5595
            'width' => 32,
5596
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5597
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5598
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5599
              'bin_pt' => 0,
5600
              'inputFile' => 'pcie_userlogic_00_inout_logic_reg12_tv.dat',
5601
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5602
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5603
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5604
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5605
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5606
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/reg12_tv/reg12_tv',
5607
              'source_block' => 'PCIe_UserLogic_00/INOUT_LOGIC/reg12_tv',
5608
              'timingConstraint' => 'none',
5609
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5610
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5611
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5612
            'hdlType' => 'std_logic',
5613
            'width' => 1,
5614
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5615
          'reg13_rd' => {
5616
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5617
              'bin_pt' => 0,
5618
              'inputFile' => 'pcie_userlogic_00_inout_logic_reg13_rd.dat',
5619
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5620
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5621
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5622
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5623
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5624
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/reg13_rd/reg13_rd',
5625
              'source_block' => 'PCIe_UserLogic_00/INOUT_LOGIC/reg13_rd',
5626
              'timingConstraint' => 'none',
5627
              'type' => 'UFix_32_0',
5628
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5629
            'direction' => 'out',
5630
            'hdlType' => 'std_logic_vector(31 downto 0)',
5631
            'width' => 32,
5632
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5633
          'reg13_rv' => {
5634
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5635
              'bin_pt' => 0,
5636
              'inputFile' => 'pcie_userlogic_00_inout_logic_reg13_rv.dat',
5637
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5638
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5639
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5640
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5641
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5642
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/reg13_rv/reg13_rv',
5643
              'source_block' => 'PCIe_UserLogic_00/INOUT_LOGIC/reg13_rv',
5644
              'timingConstraint' => 'none',
5645
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5646
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5647
            'direction' => 'out',
5648
            'hdlType' => 'std_logic',
5649
            'width' => 1,
5650
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5651
          'reg13_td' => {
5652
            'attributes' => {
5653
              'bin_pt' => 0,
5654
              'inputFile' => 'pcie_userlogic_00_inout_logic_reg13_td.dat',
5655
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5656
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5657
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5658
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5659
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5660
              'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/reg13_td/reg13_td',
5661
              'source_block' => 'PCIe_UserLogic_00/INOUT_LOGIC/reg13_td',
5662
              'timingConstraint' => 'none',
5663
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5664
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5665
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5666
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5667
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5669
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5670
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5671
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5672
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5675
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5680
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5681
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5682
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5683
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5684
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5685
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5687
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5688
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5689
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5690
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5698
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5699
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5700
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5701
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5702
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5703
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5705
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5706
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5707
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5708
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5711
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5714
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5716
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5717
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5718
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5719
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5720
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5721
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5722
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5723
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5724
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5725
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5726
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5732
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5734
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5735
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5739
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5740
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5742
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5743
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5750
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5752
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5753
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5754
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5755
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5756
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5757
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5759
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5760
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5761
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5762
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5765
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5768
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5769
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5770
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5771
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5772
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5773
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5774
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5775
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5776
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5777
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5778
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5779
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5780
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5788
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5789
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5790
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5791
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5792
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5795
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5796
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5797
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5798
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5804
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5806
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5807
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5809
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5810
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5811
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5812
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5813
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5814
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5815
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5816
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5822
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5823
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5824
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5825
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5826
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5827
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5828
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5829
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5830
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5831
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5832
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5833
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5834
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5844
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5845
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5846
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5847
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5848
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5849
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5850
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5851
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5852
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5853
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5854
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5855
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5857
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5858
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5859
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5860
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5861
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5862
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5863
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5864
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5865
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5866
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5867
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5869
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5870
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5876
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5877
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5880
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5881
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5882
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5883
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5885
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5887
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5888
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5890
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5895
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5899
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5900
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5901
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5902
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5903
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5904
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5905
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5906
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5907
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5908
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5909
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5910
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5911
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5912
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5913
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5914
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5915
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5916
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5918
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5919
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5920
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5921
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5924
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5929
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5930
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5931
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5932
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5934
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5935
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5936
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5971
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5972
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5973
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5975
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5976
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5977
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5978
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5979
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5981
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5983
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5999
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6000
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6001
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6002
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6003
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6004
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6005
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6006
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6007
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6008
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6009
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6010
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6011
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6012
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6013
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6014
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6015
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6016
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6017
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6018
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6020
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6021
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6023
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6025
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6026
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6027
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6028
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6030
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6031
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6032
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6033
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6064
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6067
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6068
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6069
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6070
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6071
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6073
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6074
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6075
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6076
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6077
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6079
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6080
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6090
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6091
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6092
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6093
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6094
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6095
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6096
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6097
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6098
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6099
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6101
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6130
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6134
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6136
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6138
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6140
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6141
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6142
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6161
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6163
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6165
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6167
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6171
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6176
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6186
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6189
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6191
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6193
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6194
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6210
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6211
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6213
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6214
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6230
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6232
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6233
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6280
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6329
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6330
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6332
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6360
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6364
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6368
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6380
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6383
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6464
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6479
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6579
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6640
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6650
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6752
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6801
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6804
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6810
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6814
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6832
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6833
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6834
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6835
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6836
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6837
              'ce' => 'register02rd_reg_ce',
6838
              'clk' => 'sysgen_dut_to_register2_clk_x0',
6839
              'clr' => 'sysgen_dut_to_register2_clr_x0',
6840
              'i' => 'sysgen_dut_to_register2_data_in_x0',
6841
              'o' => 'from_register5_data_out',
6842
            },
6843
            'entity' => {
6844
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6845
                'entityAlreadyNetlisted' => 1,
6846
                'generics' => [
6847
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6848
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6849
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6850
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6851
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6852
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6853
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6854
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6855
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6856
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6857
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6858
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6859
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6860
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6861
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6862
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6863
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6864
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6865
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6866
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6867
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6868
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6869
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6870
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6871
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6872
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6873
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6874
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6875
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6876
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6877
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6878
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6879
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6880
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6881
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6882
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6883
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6884
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6885
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6886
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6887
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6888
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6889
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6890
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6891
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6892
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6893
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6894
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6895
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6896
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6897
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6898
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6899
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6900
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6901
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6902
              'a' => 'sysgen_dut_to_register2_ce_x0',
6903
              'b' => 'sysgen_dut_to_register2_en_x0',
6904
              'dout' => 'register02rd_reg_ce',
6905
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6906
            'entity' => {
6907
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6908
                'entityAlreadyNetlisted' => 1,
6909
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6910
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6911
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6912
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6913
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6914
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6915
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6916
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6917
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6918
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6919
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6920
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6921
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6922
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6923
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6924
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6925
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6926
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6927
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6928
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6929
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6930
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6931
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6932
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6933
              'ce' => 'register02rv_reg_ce',
6934
              'clk' => 'sysgen_dut_to_register4_clk_x0',
6935
              'clr' => 'sysgen_dut_to_register4_clr_x0',
6936
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6937
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6938
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6939
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6940
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6941
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6942
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6943
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6944
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6945
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6946
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6947
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6948
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6949
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6950
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6951
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6952
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6953
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6954
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6955
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6956
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6957
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6958
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6959
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6960
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6961
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6962
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6963
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6964
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6965
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6966
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6967
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6968
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6969
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6970
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6971
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6972
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6973
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6974
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6975
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6976
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6977
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6978
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6979
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6980
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6981
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6982
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6983
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6984
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6985
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6986
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6987
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6988
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6989
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6990
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6991
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6992
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6993
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6994
            'entityName' => 'synth_reg_w_init',
6995
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6996
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6997
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6998
              'a' => 'sysgen_dut_to_register4_ce_x0',
6999
              'b' => 'sysgen_dut_to_register4_en_x0',
7000
              'dout' => 'register02rv_reg_ce',
7001
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7002
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7003
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7004
                'entityAlreadyNetlisted' => 1,
7005
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7006
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7007
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7008
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7009
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7010
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7011
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7012
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7013
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7014
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7015
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7016
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7017
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7018
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7019
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7020
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7021
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7022
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7023
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7024
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7025
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7026
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7027
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7028
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7029
              'ce' => 'register02td_reg_ce',
7030
              'clk' => 'sysgen_dut_to_register5_clk',
7031
              'clr' => 'sysgen_dut_to_register5_clr',
7032
              'i' => 'sysgen_dut_to_register5_data_in',
7033
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7034
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7035
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7036
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7037
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7038
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7039
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7040
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7041
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7042
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7043
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7044
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7045
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7046
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7047
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7048
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7049
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7050
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7051
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7052
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7053
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7054
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7055
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7056
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7057
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7058
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7059
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7060
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7061
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7062
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7063
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7064
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7065
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7066
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7067
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7068
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7069
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7070
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7071
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7072
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7073
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7074
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7075
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7076
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7077
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7078
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7079
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7080
                  'hdlType' => 'std_logic_vector(31 downto 0)',
7081
                  'width' => 32,
7082
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7083
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7084
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7085
                  'hdlType' => 'std_logic_vector(31 downto 0)',
7086
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7087
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7088
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7089
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7090
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7091
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7092
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7093
            'connections' => {
7094
              'a' => 'sysgen_dut_to_register5_ce',
7095
              'b' => 'sysgen_dut_to_register5_en',
7096
              'dout' => 'register02td_reg_ce',
7097
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7098
            'entity' => {
7099
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7100
                'entityAlreadyNetlisted' => 1,
7101
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7102
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7103
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7104
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7105
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7106
                  'hdlType' => 'std_logic',
7107
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7108
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7109
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7110
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7111
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7112
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7113
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7114
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7115
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7116
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7117
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7118
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7119
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7120
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7121
            'entityName' => 'xland2',
7122
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7123
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7124
            'connections' => {
7125
              'ce' => 'register02tv_reg_ce',
7126
              'clk' => 'sysgen_dut_to_register4_clk',
7127
              'clr' => 'sysgen_dut_to_register4_clr',
7128
              'i' => 'sysgen_dut_to_register4_data_in',
7129
              'o' => 'from_register6_data_out_x0',
7130
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7131
            'entity' => {
7132
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7133
                'entityAlreadyNetlisted' => 1,
7134
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7135
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7136
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7137
                    'integer',
7138
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7139
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7140
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7141
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7142
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7143
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7144
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7145
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7146
                    'init_value',
7147
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7148
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7149
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7150
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7151
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7152
                    'integer',
7153
                    1,
7154
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7155
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7156
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7157
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7158
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7159
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7160
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7161
                  'hdlType' => 'std_logic',
7162
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7163
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7164
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7165
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7166
                  'hdlType' => 'std_logic',
7167
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7168
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7169
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7170
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7171
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7172
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7173
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7174
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7175
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7176
                  'hdlType' => 'std_logic_vector(0 downto 0)',
7177
                  'width' => 1,
7178
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7179
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7180
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7181
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7182
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7183
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7184
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7185
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7186
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7187
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7188
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7189
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7190
              'a' => 'sysgen_dut_to_register4_ce',
7191
              'b' => 'sysgen_dut_to_register4_en',
7192
              'dout' => 'register02tv_reg_ce',
7193
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7194
            'entity' => {
7195
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7196
                'entityAlreadyNetlisted' => 1,
7197
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7198
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7199
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7200
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7201
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7202
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7203
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7204
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7205
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7206
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7207
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7208
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7209
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7210
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7211
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7212
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7213
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7214
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7215
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7216
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7217
            'entityName' => 'xland2',
7218
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7219
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7220
            'connections' => {
7221
              'ce' => 'register03rd_reg_ce',
7222
              'clk' => 'sysgen_dut_to_register3_clk_x0',
7223
              'clr' => 'sysgen_dut_to_register3_clr_x0',
7224
              'i' => 'sysgen_dut_to_register3_data_in_x0',
7225
              'o' => 'from_register7_data_out',
7226
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7227
            'entity' => {
7228
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7229
                'entityAlreadyNetlisted' => 1,
7230
                'generics' => [
7231
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7232
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7233
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7234
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7235
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7236
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7237
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7238
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7239
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7240
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7241
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7242
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7243
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7244
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7245
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7246
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7247
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7248
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7249
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7250
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7251
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7252
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7253
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7254
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7255
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7256
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7257
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7258
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7259
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7260
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7261
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7262
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7263
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7264
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7265
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7266
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7267
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7268
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7269
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7270
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7271
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7272
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7273
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7274
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7275
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7276
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7277
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7278
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7279
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7280
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7281
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7282
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7283
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7284
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7285
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7286
              'a' => 'sysgen_dut_to_register3_ce_x0',
7287
              'b' => 'sysgen_dut_to_register3_en_x0',
7288
              'dout' => 'register03rd_reg_ce',
7289
            },
7290
            'entity' => {
7291
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7292
                'entityAlreadyNetlisted' => 1,
7293
              },
7294
              'entityName' => 'xland2',
7295
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7296
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7297
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7298
                  'hdlType' => 'std_logic',
7299
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7300
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7301
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7302
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7303
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7304
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7305
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7306
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7307
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7308
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7309
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7310
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7311
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7312
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7313
            'entityName' => 'xland2',
7314
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7315
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7316
            'connections' => {
7317
              'ce' => 'register03rv_reg_ce',
7318
              'clk' => 'sysgen_dut_to_register5_clk_x0',
7319
              'clr' => 'sysgen_dut_to_register5_clr_x0',
7320
              'i' => 'sysgen_dut_to_register5_data_in_x0',
7321
              'o' => 'from_register6_data_out',
7322
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7323
            'entity' => {
7324
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7325
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7326
                'generics' => [
7327
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7328
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7329
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7330
                    1,
7331
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7332
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7333
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7334
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7335
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7336
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7337
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7338
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7339
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7340
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7341
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7342
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7343
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7344
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7345
                    1,
7346
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7347
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7348
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7349
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7350
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7351
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7352
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7353
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7354
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7355
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7356
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7357
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7358
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7359
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7360
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7361
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7362
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7363
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7364
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7365
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7366
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7367
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7368
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7369
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7370
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7371
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7372
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7373
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7374
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7375
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7376
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7377
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7378
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7379
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7380
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7381
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7382
              'a' => 'sysgen_dut_to_register5_ce_x0',
7383
              'b' => 'sysgen_dut_to_register5_en_x0',
7384
              'dout' => 'register03rv_reg_ce',
7385
            },
7386
            'entity' => {
7387
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7388
                'entityAlreadyNetlisted' => 1,
7389
              },
7390
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7391
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7392
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7393
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7394
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7395
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7396
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7397
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7398
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7399
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7400
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7401
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7402
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7403
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7404
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7405
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7406
                },
7407
              },
7408
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7409
            'entityName' => 'xland2',
7410
          },
7411
          'register03td' => {
7412
            'connections' => {
7413
              'ce' => 'register03td_reg_ce',
7414
              'clk' => 'sysgen_dut_to_register9_clk',
7415
              'clr' => 'sysgen_dut_to_register9_clr',
7416
              'i' => 'sysgen_dut_to_register9_data_in',
7417
              'o' => 'from_register7_data_out_x0',
7418
            },
7419
            'entity' => {
7420
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7421
                'entityAlreadyNetlisted' => 1,
7422
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7423
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7424
                    'width',
7425
                    'integer',
7426
                    32,
7427
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7428
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7429
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7430
                    'integer',
7431
                    2,
7432
                  ],
7433
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7434
                    'init_value',
7435
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7436
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7437
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7438
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7439
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7440
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7441
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7442
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7443
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7444
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7445
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7446
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7447
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7448
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7449
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7450
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7451
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7452
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7453
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7454
                  'hdlType' => 'std_logic',
7455
                  'width' => 1,
7456
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7457
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7458
                  'direction' => 'in',
7459
                  'hdlType' => 'std_logic',
7460
                  'width' => 1,
7461
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7462
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7463
                  'direction' => 'in',
7464
                  'hdlType' => 'std_logic_vector(31 downto 0)',
7465
                  'width' => 32,
7466
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7467
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7468
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7469
                  'hdlType' => 'std_logic_vector(31 downto 0)',
7470
                  'width' => 32,
7471
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7472
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7473
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7474
            'entityName' => 'synth_reg_w_init',
7475
          },
7476
          'register03td_ce_and2_comp' => {
7477
            'connections' => {
7478
              'a' => 'sysgen_dut_to_register9_ce',
7479
              'b' => 'sysgen_dut_to_register9_en',
7480
              'dout' => 'register03td_reg_ce',
7481
            },
7482
            'entity' => {
7483
              'attributes' => {
7484
                'entityAlreadyNetlisted' => 1,
7485
              },
7486
              'entityName' => 'xland2',
7487
              'ports' => {
7488
                'a' => {
7489
                  'direction' => 'in',
7490
                  'hdlType' => 'std_logic',
7491
                  'width' => 1,
7492
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7493
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7494
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7495
                  'hdlType' => 'std_logic',
7496
                  'width' => 1,
7497
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7498
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7499
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7500
                  'hdlType' => 'std_logic',
7501
                  'width' => 1,
7502
                },
7503
              },
7504
            },
7505
            'entityName' => 'xland2',
7506
          },
7507
          'register03tv' => {
7508
            'connections' => {
7509
              'ce' => 'register03tv_reg_ce',
7510
              'clk' => 'sysgen_dut_to_register8_clk',
7511
              'clr' => 'sysgen_dut_to_register8_clr',
7512
              'i' => 'sysgen_dut_to_register8_data_in',
7513
              'o' => 'from_register8_data_out_x0',
7514
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7515
            'entity' => {
7516
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7517
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7518
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7519
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7520
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7521
                    'integer',
7522
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7523
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7524
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7525
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7526
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7527
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7528
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7529
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7530
                    'init_value',
7531
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7532
                    'b"0"',
7533
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7534
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7535
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7536
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7537
                    1,
7538
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7539
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7540
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7541
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7542
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7543
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7544
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7545
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7546
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7547
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7548
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7549
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7550
                  'hdlType' => 'std_logic',
7551
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7552
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7553
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7554
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7555
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7556
                  'width' => 1,
7557
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7558
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7559
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7560
                  'hdlType' => 'std_logic_vector(0 downto 0)',
7561
                  'width' => 1,
7562
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7563
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7564
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7565
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7566
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7567
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7568
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7569
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7570
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7571
          },
7572
          'register03tv_ce_and2_comp' => {
7573
            'connections' => {
7574
              'a' => 'sysgen_dut_to_register8_ce',
7575
              'b' => 'sysgen_dut_to_register8_en',
7576
              'dout' => 'register03tv_reg_ce',
7577
            },
7578
            'entity' => {
7579
              'attributes' => {
7580
                'entityAlreadyNetlisted' => 1,
7581
              },
7582
              'entityName' => 'xland2',
7583
              'ports' => {
7584
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7585
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7586
                  'hdlType' => 'std_logic',
7587
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7588
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7589
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7590
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7591
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7592
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7593
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7594
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7595
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7596
                  'hdlType' => 'std_logic',
7597
                  'width' => 1,
7598
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7599
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7600
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7601
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7602
          },
7603
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7604
            'connections' => {
7605
              'ce' => 'register04rd_reg_ce',
7606
              'clk' => 'sysgen_dut_to_register6_clk_x0',
7607
              'clr' => 'sysgen_dut_to_register6_clr_x0',
7608
              'i' => 'sysgen_dut_to_register6_data_in_x0',
7609
              'o' => 'from_register8_data_out',
7610
            },
7611
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7612
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7613
                'entityAlreadyNetlisted' => 1,
7614
                'generics' => [
7615
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7616
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7617
                    'integer',
7618
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7619
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7620
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7621
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7622
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7623
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7624
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7625
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7626
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7627
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7628
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7629
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7630
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7631
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7632
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7633
                    1,
7634
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7635
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7636
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7637
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7638
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7639
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7640
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7641
                  'hdlType' => 'std_logic',
7642
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7643
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7644
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7645
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7646
                  'hdlType' => 'std_logic',
7647
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7648
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7649
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7650
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7651
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7652
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7653
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7654
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7655
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7656
                  'hdlType' => 'std_logic_vector(31 downto 0)',
7657
                  'width' => 32,
7658
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7659
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7660
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7661
                  'hdlType' => 'std_logic_vector(31 downto 0)',
7662
                  'width' => 32,
7663
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7664
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7665
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7666
            'entityName' => 'synth_reg_w_init',
7667
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7668
          'register04rd_ce_and2_comp' => {
7669
            'connections' => {
7670
              'a' => 'sysgen_dut_to_register6_ce_x0',
7671
              'b' => 'sysgen_dut_to_register6_en_x0',
7672
              'dout' => 'register04rd_reg_ce',
7673
            },
7674
            'entity' => {
7675
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7676
                'entityAlreadyNetlisted' => 1,
7677
              },
7678
              'entityName' => 'xland2',
7679
              'ports' => {
7680
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7681
                  'direction' => 'in',
7682
                  'hdlType' => 'std_logic',
7683
                  'width' => 1,
7684
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7685
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7686
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7687
                  'hdlType' => 'std_logic',
7688
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7689
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7690
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7691
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7692
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7693
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7694
                },
7695
              },
7696
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7697
            'entityName' => 'xland2',
7698
          },
7699
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7700
            'connections' => {
7701
              'ce' => 'register04rv_reg_ce',
7702
              'clk' => 'sysgen_dut_to_register7_clk_x0',
7703
              'clr' => 'sysgen_dut_to_register7_clr_x0',
7704
              'i' => 'sysgen_dut_to_register7_data_in_x0',
7705
              'o' => 'from_register4_data_out',
7706
            },
7707
            'entity' => {
7708
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7709
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7710
                'generics' => [
7711
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7712
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7713
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7714
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7715
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7716
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7717
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7718
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7719
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7720
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7721
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7722
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7723
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7724
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7725
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7726
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7727
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7728
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7729
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7730
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7731
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7732
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7733
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7734
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7735
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7736
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7737
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7738
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7739
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7740
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7741
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7742
                  'hdlType' => 'std_logic',
7743
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7744
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7745
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7746
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7747
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7748
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7749
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7750
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7751
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7752
                  'hdlType' => 'std_logic_vector(0 downto 0)',
7753
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7754
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7755
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7756
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7757
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7758
                  'width' => 1,
7759
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7760
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7761
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7762
            'entityName' => 'synth_reg_w_init',
7763
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7764
          'register04rv_ce_and2_comp' => {
7765
            'connections' => {
7766
              'a' => 'sysgen_dut_to_register7_ce_x0',
7767
              'b' => 'sysgen_dut_to_register7_en_x0',
7768
              'dout' => 'register04rv_reg_ce',
7769
            },
7770
            'entity' => {
7771
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7772
                'entityAlreadyNetlisted' => 1,
7773
              },
7774
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7775
              'ports' => {
7776
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7777
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7778
                  'hdlType' => 'std_logic',
7779
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7780
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7781
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7782
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7783
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7784
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7785
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7786
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7787
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7788
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7789
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7790
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7791
              },
7792
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7793
            'entityName' => 'xland2',
7794
          },
7795
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7796
            'connections' => {
7797
              'ce' => 'register04td_reg_ce',
7798
              'clk' => 'sysgen_dut_to_register11_clk',
7799
              'clr' => 'sysgen_dut_to_register11_clr',
7800
              'i' => 'sysgen_dut_to_register11_data_in',
7801
              'o' => 'from_register9_data_out_x0',
7802
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7803
            'entity' => {
7804
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7805
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7806
                'generics' => [
7807
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7808
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7809
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7810
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7811
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7812
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7813
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7814
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7815
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7816
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7817
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7818
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7819
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7820
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7821
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7822
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7823
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7824
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7825
                    1,
7826
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7827
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7828
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7829
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7830
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7831
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7832
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7833
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7834
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7835
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7836
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7837
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7838
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7839
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7840
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7841
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7842
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7843
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7844
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7845
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7846
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7847
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7848
                  'hdlType' => 'std_logic_vector(31 downto 0)',
7849
                  'width' => 32,
7850
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7851
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7852
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7853
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7854
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7855
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7856
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7857
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7858
            'entityName' => 'synth_reg_w_init',
7859
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7860
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7861
            'connections' => {
7862
              'a' => 'sysgen_dut_to_register11_ce',
7863
              'b' => 'sysgen_dut_to_register11_en',
7864
              'dout' => 'register04td_reg_ce',
7865
            },
7866
            'entity' => {
7867
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7868
                'entityAlreadyNetlisted' => 1,
7869
              },
7870
              'entityName' => 'xland2',
7871
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7872
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7873
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7874
                  'hdlType' => 'std_logic',
7875
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7876
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7877
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7878
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7879
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7880
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7881
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7882
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7883
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7884
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7885
                  'width' => 1,
7886
                },
7887
              },
7888
            },
7889
            'entityName' => 'xland2',
7890
          },
7891
          'register04tv' => {
7892
            'connections' => {
7893
              'ce' => 'register04tv_reg_ce',
7894
              'clk' => 'sysgen_dut_to_register10_clk',
7895
              'clr' => 'sysgen_dut_to_register10_clr',
7896
              'i' => 'sysgen_dut_to_register10_data_in',
7897
              'o' => 'from_register10_data_out_x0',
7898
            },
7899
            'entity' => {
7900
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7901
                'entityAlreadyNetlisted' => 1,
7902
                'generics' => [
7903
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7904
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7905
                    'integer',
7906
                    1,
7907
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7908
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7909
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7910
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7911
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7912
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7913
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7914
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7915
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7916
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7917
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7918
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7919
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7920
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7921
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7922
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7923
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7924
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7925
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7926
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7927
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7928
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7929
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7930
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7931
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7932
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7933
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7934
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7935
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7936
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7937
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7938
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7939
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7940
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7941
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7942
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7943
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7944
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7945
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7946
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7947
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7948
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7949
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7950
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7951
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7952
              },
7953
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7954
            'entityName' => 'synth_reg_w_init',
7955
          },
7956
          'register04tv_ce_and2_comp' => {
7957
            'connections' => {
7958
              'a' => 'sysgen_dut_to_register10_ce',
7959
              'b' => 'sysgen_dut_to_register10_en',
7960
              'dout' => 'register04tv_reg_ce',
7961
            },
7962
            'entity' => {
7963
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7964
                'entityAlreadyNetlisted' => 1,
7965
              },
7966
              'entityName' => 'xland2',
7967
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7968
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7969
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7970
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7971
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7972
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7973
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7974
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7975
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7976
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7977
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7978
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7979
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7980
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7981
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7982
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7983
              },
7984
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7985
            'entityName' => 'xland2',
7986
          },
7987
          'register05rd' => {
7988
            'connections' => {
7989
              'ce' => 'register05rd_reg_ce',
7990
              'clk' => 'sysgen_dut_to_register8_clk_x0',
7991
              'clr' => 'sysgen_dut_to_register8_clr_x0',
7992
              'i' => 'sysgen_dut_to_register8_data_in_x0',
7993
              'o' => 'from_register10_data_out',
7994
            },
7995
            'entity' => {
7996
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7997
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7998
                'generics' => [
7999
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8000
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8001
                    'integer',
8002
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8003
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8004
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8005
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8006
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8007
                    2,
8008
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8009
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8010
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8011
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8012
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8013
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8014
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8015
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8016
                    'integer',
8017
                    1,
8018
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8019
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8020
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8021
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8022
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8023
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8024
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8025
                  'hdlType' => 'std_logic',
8026
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8027
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8028
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8029
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8030
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8031
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8032
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8033
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8034
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8035
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8036
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8037
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8038
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8039
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8040
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8041
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8042
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8043
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8044
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8045
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8046
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8047
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8048
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8049
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8050
            'entityName' => 'synth_reg_w_init',
8051
          },
8052
          'register05rd_ce_and2_comp' => {
8053
            'connections' => {
8054
              'a' => 'sysgen_dut_to_register8_ce_x0',
8055
              'b' => 'sysgen_dut_to_register8_en_x0',
8056
              'dout' => 'register05rd_reg_ce',
8057
            },
8058
            'entity' => {
8059
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8060
                'entityAlreadyNetlisted' => 1,
8061
              },
8062
              'entityName' => 'xland2',
8063
              'ports' => {
8064
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8065
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8066
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8067
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8068
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8069
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8070
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8071
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8072
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8073
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8074
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8075
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8076
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8077
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8078
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8079
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8080
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8081
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8082
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8083
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8084
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8085
              'ce' => 'register05rv_reg_ce',
8086
              'clk' => 'sysgen_dut_to_register10_clk_x0',
8087
              'clr' => 'sysgen_dut_to_register10_clr_x0',
8088
              'i' => 'sysgen_dut_to_register10_data_in_x0',
8089
              'o' => 'from_register9_data_out',
8090
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8091
            'entity' => {
8092
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8093
                'entityAlreadyNetlisted' => 1,
8094
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8095
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8096
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8097
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8098
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8099
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8100
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8101
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8102
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8103
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8104
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8105
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8106
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8107
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8108
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8109
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8110
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8111
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8112
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8113
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8114
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8115
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8116
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8117
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8118
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8119
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8120
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8121
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8122
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8123
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8124
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8125
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8126
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8127
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8128
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8130
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8131
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8132
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8133
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8134
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8135
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8136
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8137
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8138
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8139
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8140
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8141
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8142
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8143
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8144
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8145
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8146
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8147
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8148
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8149
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8150
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8151
              'b' => 'sysgen_dut_to_register10_en_x0',
8152
              'dout' => 'register05rv_reg_ce',
8153
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8154
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8155
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8156
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8157
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8158
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8160
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8161
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8162
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8163
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8165
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8166
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8167
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8168
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8169
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8170
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8171
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8172
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8173
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8174
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8175
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8176
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8177
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8178
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8179
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8180
            'connections' => {
8181
              'ce' => 'register05td_reg_ce',
8182
              'clk' => 'sysgen_dut_to_register13_clk',
8183
              'clr' => 'sysgen_dut_to_register13_clr',
8184
              'i' => 'sysgen_dut_to_register13_data_in',
8185
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8186
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8187
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8188
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8189
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8190
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8191
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8192
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8193
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8194
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8195
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8196
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8197
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8198
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8199
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8200
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8201
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8202
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8203
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8204
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8205
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8206
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8207
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8208
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8209
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8210
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8211
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8212
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8213
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8214
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8215
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8216
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8217
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8218
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8219
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8220
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8221
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8222
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8223
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8224
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8225
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8226
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8227
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8228
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8229
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8230
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8231
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8232
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8233
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8234
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8235
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8236
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8237
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8238
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8239
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8240
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8241
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8242
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8243
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8244
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8245
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8246
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8247
              'b' => 'sysgen_dut_to_register13_en',
8248
              'dout' => 'register05td_reg_ce',
8249
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8250
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8251
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8252
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8254
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8255
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8256
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8257
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8258
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8259
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8260
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8261
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8262
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8263
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8264
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8266
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8267
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8268
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8269
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8270
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8271
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8272
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8273
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8274
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8275
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8276
            'connections' => {
8277
              'ce' => 'register05tv_reg_ce',
8278
              'clk' => 'sysgen_dut_to_register12_clk',
8279
              'clr' => 'sysgen_dut_to_register12_clr',
8280
              'i' => 'sysgen_dut_to_register12_data_in',
8281
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8282
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8283
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8284
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8285
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8286
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8287
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8288
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8289
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8290
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8291
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8292
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8293
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8294
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8295
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8296
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8297
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8298
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8299
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8300
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8301
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8302
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8303
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8304
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8305
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8306
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8307
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8308
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8309
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8310
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8311
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8312
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8313
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8314
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8315
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8316
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8317
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8318
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8319
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8320
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8321
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8322
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8323
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8324
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8325
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8326
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8327
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8328
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8329
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8330
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8331
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8332
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8333
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8334
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8335
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8336
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8337
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8338
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8339
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8340
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8341
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8342
              'a' => 'sysgen_dut_to_register12_ce',
8343
              'b' => 'sysgen_dut_to_register12_en',
8344
              'dout' => 'register05tv_reg_ce',
8345
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8346
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8347
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8348
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8349
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8350
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8351
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8352
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8353
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8354
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8355
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8356
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8357
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8358
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8359
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8360
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8361
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8362
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8363
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8364
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8365
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8366
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8367
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8368
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8369
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8370
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8371
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8372
            'connections' => {
8373
              'ce' => 'register06rd_reg_ce',
8374
              'clk' => 'sysgen_dut_to_register9_clk_x0',
8375
              'clr' => 'sysgen_dut_to_register9_clr_x0',
8376
              'i' => 'sysgen_dut_to_register9_data_in_x0',
8377
              'o' => 'from_register11_data_out',
8378
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8379
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8380
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8381
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8382
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8383
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8384
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8385
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8386
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8387
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8388
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8389
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8390
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8391
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8392
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8393
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8394
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8395
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8396
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8397
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8398
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8399
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8400
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8401
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8402
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8403
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8404
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8405
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8406
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8407
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8408
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8409
                  'hdlType' => 'std_logic',
8410
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8411
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8412
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8413
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8414
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8415
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8416
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8417
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8418
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8419
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8420
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8421
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8422
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8423
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8424
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8425
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8426
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8427
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8428
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8429
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8430
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8431
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8432
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8433
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8434
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8435
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8436
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8437
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8438
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8439
              'b' => 'sysgen_dut_to_register9_en_x0',
8440
              'dout' => 'register06rd_reg_ce',
8441
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8442
            'entity' => {
8443
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8444
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8445
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8446
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8449
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8450
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8451
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8452
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8453
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8455
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8456
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8457
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8458
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8459
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8460
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8461
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8462
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8463
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8464
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8465
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8466
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8467
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8468
            'connections' => {
8469
              'ce' => 'register06rv_reg_ce',
8470
              'clk' => 'sysgen_dut_to_register11_clk_x0',
8471
              'clr' => 'sysgen_dut_to_register11_clr_x0',
8472
              'i' => 'sysgen_dut_to_register11_data_in_x0',
8473
              'o' => 'from_register12_data_out',
8474
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8475
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8476
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8477
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8478
                'generics' => [
8479
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8480
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8481
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8482
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8483
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8484
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8485
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8486
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8487
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8488
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8489
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8490
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8491
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8492
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8493
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8494
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8495
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8496
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8497
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8498
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8499
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8500
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8501
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8502
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8503
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8504
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8505
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8506
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8507
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8508
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8510
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8511
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8512
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8513
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8514
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8515
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8516
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8517
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8518
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8519
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8520
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8521
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8522
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8523
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8524
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8525
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8526
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8527
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8528
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8529
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8530
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8531
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8532
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8533
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8534
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8535
              'b' => 'sysgen_dut_to_register11_en_x0',
8536
              'dout' => 'register06rv_reg_ce',
8537
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8538
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8539
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8540
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8541
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8542
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8543
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8544
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8545
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8546
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8547
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8548
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8549
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8550
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8551
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8552
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8553
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8554
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8555
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8556
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8557
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8558
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8559
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8560
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8561
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8562
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8563
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8564
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8565
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8566
              'clk' => 'sysgen_dut_to_register15_clk',
8567
              'clr' => 'sysgen_dut_to_register15_clr',
8568
              'i' => 'sysgen_dut_to_register15_data_in',
8569
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8570
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8571
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8572
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8573
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8574
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8575
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8576
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8577
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8578
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8579
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8580
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8581
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8582
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8583
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8584
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8585
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8586
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8587
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8588
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8589
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8590
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8591
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8592
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8593
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8594
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8595
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8596
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8597
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8598
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8599
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8600
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8601
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8602
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8603
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8604
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8605
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8606
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8607
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8608
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8609
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8610
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8611
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8612
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8613
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8614
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8615
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8616
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8617
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8618
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8619
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8620
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8621
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8622
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8623
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8624
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8625
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8626
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8627
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8628
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8629
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8630
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8631
              'b' => 'sysgen_dut_to_register15_en',
8632
              'dout' => 'register06td_reg_ce',
8633
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8634
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8635
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8636
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8637
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8638
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8639
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8640
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8641
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8642
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8643
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8644
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8645
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8646
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8647
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8648
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8649
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8650
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8651
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8652
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8653
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8654
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8655
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8656
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8657
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8658
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8659
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8660
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8661
              'ce' => 'register06tv_reg_ce',
8662
              'clk' => 'sysgen_dut_to_register14_clk',
8663
              'clr' => 'sysgen_dut_to_register14_clr',
8664
              'i' => 'sysgen_dut_to_register14_data_in',
8665
              'o' => 'from_register14_data_out_x0',
8666
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8667
            'entity' => {
8668
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8669
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8670
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8671
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8672
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8673
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8674
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8675
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8676
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8677
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8678
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8679
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8680
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8681
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8682
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8683
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8684
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8685
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8686
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8687
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8688
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8689
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8690
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8712
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8725
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8726
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8728
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8729
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8730
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8731
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8732
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8733
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8734
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8736
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8752
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8753
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8755
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8756
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8757
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8760
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8761
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8763
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8768
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8778
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8781
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8782
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8783
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8813
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8820
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8821
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8822
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8823
              'b' => 'sysgen_dut_to_register13_en_x0',
8824
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8825
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8826
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8827
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8828
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8829
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8830
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8834
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8848
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8849
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8851
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8852
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8853
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8854
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8855
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8856
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8857
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8858
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8859
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8864
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8865
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8866
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8869
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8872
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8874
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8875
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8877
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8879
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8880
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8881
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8883
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8916
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8917
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8920
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8922
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8944
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8945
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8947
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8948
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8949
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8950
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8953
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8954
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8955
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8960
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8963
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8970
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8975
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8977
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8978
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8979
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9016
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9017
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9018
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9020
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9022
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9039
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9040
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9044
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9045
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9047
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9050
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9056
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9064
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9065
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9070
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9071
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9073
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9074
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9075
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9076
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9077
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9101
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9110
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9112
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9113
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9114
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9118
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9136
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9137
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9139
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9140
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9141
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9145
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9147
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9152
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9154
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9155
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9160
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9162
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9163
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9166
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9167
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9171
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9197
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9204
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              'b' => 'sysgen_dut_to_register15_en_x0',
9208
              'dout' => 'register08rd_reg_ce',
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9210
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9211
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9212
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9213
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9214
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9215
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9218
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9224
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9230
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9232
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9233
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9235
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9236
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9237
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9238
              'clk' => 'sysgen_dut_to_register14_clk_x0',
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9240
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9241
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9242
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9243
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9244
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9248
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9249
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9250
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9251
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9252
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9253
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9255
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9256
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9257
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9258
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9259
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9260
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9261
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9262
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9263
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9264
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9265
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9267
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9280
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9281
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9291
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9293
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9295
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9296
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9297
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9298
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9299
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9300
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9301
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9302
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9303
              'b' => 'sysgen_dut_to_register14_en_x0',
9304
              'dout' => 'register08rv_reg_ce',
9305
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9306
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9307
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9308
                'entityAlreadyNetlisted' => 1,
9309
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9310
              'entityName' => 'xland2',
9311
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9312
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9313
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9314
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9315
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9316
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9317
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9318
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9319
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9320
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9322
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9323
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9324
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9325
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9326
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9327
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9328
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9329
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9330
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9331
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9332
            'connections' => {
9333
              'ce' => 'register08td_reg_ce',
9334
              'clk' => 'sysgen_dut_to_register26_clk',
9335
              'clr' => 'sysgen_dut_to_register26_clr',
9336
              'i' => 'sysgen_dut_to_register26_data_in',
9337
              'o' => 'from_register20_data_out_x0',
9338
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9339
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9340
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9341
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9342
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9343
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9344
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9345
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9346
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9347
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9349
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9350
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9351
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9352
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9353
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9354
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9355
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9356
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9357
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9358
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9359
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9360
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9361
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9362
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9363
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9364
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9365
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9366
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9367
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9368
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9369
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9370
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9371
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9372
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9373
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9374
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9375
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9377
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9378
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9379
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9380
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9382
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9383
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9384
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9385
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9386
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9387
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9388
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9389
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9391
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9392
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9393
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9394
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9395
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9396
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9397
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9398
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9399
              'b' => 'sysgen_dut_to_register26_en',
9400
              'dout' => 'register08td_reg_ce',
9401
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9402
            'entity' => {
9403
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9404
                'entityAlreadyNetlisted' => 1,
9405
              },
9406
              'entityName' => 'xland2',
9407
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9408
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9409
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9410
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9411
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9412
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9413
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9414
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9415
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9416
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9417
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9418
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9419
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9420
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9421
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9422
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9423
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9424
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9425
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9426
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9427
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9428
            'connections' => {
9429
              'ce' => 'register08tv_reg_ce',
9430
              'clk' => 'sysgen_dut_to_register25_clk',
9431
              'clr' => 'sysgen_dut_to_register25_clr',
9432
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9433
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9434
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9435
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9436
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9437
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9438
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9439
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9440
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9441
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9442
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9443
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9444
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9445
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9446
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9447
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9448
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9449
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9450
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9451
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9452
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9453
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9454
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9455
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9456
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9457
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9458
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9459
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9460
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9462
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9463
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9464
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9465
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9466
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9467
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9468
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9469
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9470
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9471
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9472
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9473
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9474
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9475
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9476
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9477
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9478
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9479
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9480
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9481
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9482
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9483
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9485
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9486
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9487
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9488
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9489
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9490
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9491
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9492
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9493
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9494
              'a' => 'sysgen_dut_to_register25_ce',
9495
              'b' => 'sysgen_dut_to_register25_en',
9496
              'dout' => 'register08tv_reg_ce',
9497
            },
9498
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9499
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9500
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9501
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9502
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9504
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9505
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9506
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9507
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9509
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9510
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9511
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9512
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9513
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9514
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9515
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9516
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9517
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9518
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9519
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9520
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9521
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9522
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9523
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9524
            'connections' => {
9525
              'ce' => 'register09rd_reg_ce',
9526
              'clk' => 'sysgen_dut_to_register17_clk_x0',
9527
              'clr' => 'sysgen_dut_to_register17_clr_x0',
9528
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9529
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9530
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9531
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9532
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9533
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9534
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9535
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9536
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9537
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9538
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9539
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9540
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9541
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9542
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9543
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9544
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9545
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9546
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9547
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9548
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9549
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9550
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9551
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9552
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9553
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9554
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9555
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9556
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9557
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9558
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9559
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9560
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9561
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9562
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9563
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9564
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9565
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9566
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9567
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9568
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9569
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9570
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9571
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9572
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9573
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9574
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9575
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9576
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9577
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9578
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9579
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9580
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9581
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9582
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9583
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9584
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9585
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9586
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9587
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9588
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9589
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9590
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9591
              'b' => 'sysgen_dut_to_register17_en_x0',
9592
              'dout' => 'register09rd_reg_ce',
9593
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9594
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9595
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9596
                'entityAlreadyNetlisted' => 1,
9597
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9598
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9599
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9600
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9601
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9602
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9603
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9604
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9606
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9607
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9608
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9609
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9610
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9611
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9612
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9613
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9614
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9615
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9616
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9617
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9618
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9619
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9620
            'connections' => {
9621
              'ce' => 'register09rv_reg_ce',
9622
              'clk' => 'sysgen_dut_to_register16_clk_x0',
9623
              'clr' => 'sysgen_dut_to_register16_clr_x0',
9624
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9625
              'o' => 'from_register18_data_out',
9626
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9627
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9628
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9629
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9630
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9631
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9632
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9633
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9634
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9635
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9636
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9637
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9638
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9639
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9640
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9641
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9642
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9643
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9644
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9645
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9646
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9647
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9648
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9649
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9650
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9651
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9652
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9653
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9654
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9655
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9656
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9657
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9658
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9659
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9660
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9662
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9663
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9664
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9665
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9667
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9668
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9669
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9670
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9671
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9672
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9673
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9674
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9675
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9677
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9680
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9681
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9682
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9684
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9685
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9686
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9687
              'b' => 'sysgen_dut_to_register16_en_x0',
9688
              'dout' => 'register09rv_reg_ce',
9689
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9690
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9691
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9692
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9694
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9698
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9699
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9700
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9701
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9703
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9704
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9705
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9706
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9707
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9708
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9709
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9710
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9711
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9712
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9713
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9714
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9715
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9716
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9717
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9718
              'clk' => 'sysgen_dut_to_register22_clk',
9719
              'clr' => 'sysgen_dut_to_register22_clr',
9720
              'i' => 'sysgen_dut_to_register22_data_in',
9721
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9722
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9723
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9724
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9725
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9726
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9727
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9728
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9729
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9730
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9731
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9732
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9733
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9734
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9735
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9736
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9737
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9738
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9739
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9740
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9741
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9742
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9743
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9744
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9745
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9746
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9747
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9748
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9749
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9750
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9752
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9753
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9756
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9758
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9760
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9764
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9765
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9768
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9770
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9773
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9775
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9776
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9777
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9778
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9780
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              'b' => 'sysgen_dut_to_register22_en',
9784
              'dout' => 'register09td_reg_ce',
9785
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9786
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9787
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9788
                'entityAlreadyNetlisted' => 1,
9789
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9790
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9792
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9794
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9795
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9797
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9799
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9800
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9801
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9802
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9803
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9804
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9805
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9806
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9807
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9808
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9809
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9810
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9811
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9812
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9813
              'ce' => 'register09tv_reg_ce',
9814
              'clk' => 'sysgen_dut_to_register21_clk',
9815
              'clr' => 'sysgen_dut_to_register21_clr',
9816
              'i' => 'sysgen_dut_to_register21_data_in',
9817
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9818
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9819
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9820
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9821
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9822
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9823
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9824
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9825
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9826
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9827
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9828
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9829
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9830
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9831
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9832
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9833
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9834
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9835
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9836
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9837
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9838
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9839
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9840
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9841
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9842
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9843
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9844
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9845
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9846
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9847
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9848
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9849
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9850
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9851
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9852
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9853
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9854
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9855
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9856
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9857
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9859
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9860
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9861
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9862
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9863
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9864
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9865
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9866
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9867
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9868
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9869
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9870
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9871
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9872
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9873
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9874
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9875
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9876
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9877
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9878
              'a' => 'sysgen_dut_to_register21_ce',
9879
              'b' => 'sysgen_dut_to_register21_en',
9880
              'dout' => 'register09tv_reg_ce',
9881
            },
9882
            'entity' => {
9883
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9884
                'entityAlreadyNetlisted' => 1,
9885
              },
9886
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9887
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9888
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9889
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9890
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9891
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9893
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9894
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9895
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9896
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9897
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9898
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9899
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9900
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9901
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9902
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9903
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9904
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9905
            'entityName' => 'xland2',
9906
          },
9907
          'register10rd' => {
9908
            'connections' => {
9909
              'ce' => 'register10rd_reg_ce',
9910
              'clk' => 'sysgen_dut_to_register19_clk_x0',
9911
              'clr' => 'sysgen_dut_to_register19_clr_x0',
9912
              'i' => 'sysgen_dut_to_register19_data_in_x0',
9913
              'o' => 'from_register19_data_out',
9914
            },
9915
            'entity' => {
9916
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9917
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9918
                'generics' => [
9919
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9920
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9921
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9922
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9923
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9924
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9925
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9930
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9931
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9932
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9933
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9935
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9936
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9937
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9974
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9976
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9977
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9978
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9979
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9980
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9982
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9984
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9999
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10000
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10001
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10003
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10004
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10005
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10007
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10008
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10009
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10010
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10011
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10012
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10013
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10016
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10021
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10024
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10026
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10027
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10031
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10033
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10035
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10069
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              'b' => 'sysgen_dut_to_register18_en_x0',
10072
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10073
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10074
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10075
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10076
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10077
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10078
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10080
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10095
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10097
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10099
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10100
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10101
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10102
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10103
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10104
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10105
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10106
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10107
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10109
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10110
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10112
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10113
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10114
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10117
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10118
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10119
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10120
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10121
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10122
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10123
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10124
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10125
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10126
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10127
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10128
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10129
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10130
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10131
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10132
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10133
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10134
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10137
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10152
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10157
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10160
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10161
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10162
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10163
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10164
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10165
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10166
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10167
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10168
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10169
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10170
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10171
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10172
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10174
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10189
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10191
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10192
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10193
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10194
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10195
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10196
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10197
              'ce' => 'register10tv_reg_ce',
10198
              'clk' => 'sysgen_dut_to_register23_clk',
10199
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10200
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10201
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10202
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10203
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10208
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10209
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10210
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10211
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10213
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10214
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10215
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10216
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10217
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10218
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10219
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10220
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10222
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10223
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10224
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10225
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10227
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10228
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10229
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10230
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10232
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10233
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10260
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10261
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              'b' => 'sysgen_dut_to_register23_en',
10264
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10265
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10266
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10267
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10270
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10280
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10284
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10287
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10288
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10289
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10291
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10292
            'connections' => {
10293
              'ce' => 'register11rd_reg_ce',
10294
              'clk' => 'sysgen_dut_to_register21_clk_x0',
10295
              'clr' => 'sysgen_dut_to_register21_clr_x0',
10296
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10297
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10298
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10299
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10301
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10303
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10304
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10305
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10307
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10309
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10310
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10311
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10312
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10313
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10314
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10315
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10316
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10318
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10319
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10320
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10321
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10322
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10323
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10324
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10325
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10329
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10332
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10353
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10356
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              'b' => 'sysgen_dut_to_register21_en_x0',
10360
              'dout' => 'register11rd_reg_ce',
10361
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10362
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10363
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10364
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10366
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10378
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10380
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10382
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10383
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10384
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10385
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10387
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10388
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10389
              'ce' => 'register11rv_reg_ce',
10390
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10391
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10392
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10393
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10394
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10395
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10396
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10397
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10399
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10400
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10401
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10402
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10403
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10404
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10405
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10406
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10407
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10408
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10409
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10410
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10411
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10412
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10413
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10414
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10415
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10416
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10417
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10418
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10419
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10420
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10421
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10422
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10424
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10425
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10426
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10428
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10430
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10431
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10432
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10433
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10435
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10436
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10437
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10438
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10440
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10442
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10443
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10445
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10447
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10448
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10449
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10450
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10452
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10453
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10454
              'a' => 'sysgen_dut_to_register20_ce_x0',
10455
              'b' => 'sysgen_dut_to_register20_en_x0',
10456
              'dout' => 'register11rv_reg_ce',
10457
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10458
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10459
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10460
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10461
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10462
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10463
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10464
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10466
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10469
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10472
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10474
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10475
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10477
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10478
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10479
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10480
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10481
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10482
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10483
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10484
            'connections' => {
10485
              'ce' => 'register11td_reg_ce',
10486
              'clk' => 'sysgen_dut_to_register28_clk',
10487
              'clr' => 'sysgen_dut_to_register28_clr',
10488
              'i' => 'sysgen_dut_to_register28_data_in',
10489
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10490
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10491
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10492
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10493
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10494
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10495
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10496
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10497
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10498
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10499
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10500
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10501
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10502
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10503
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10504
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10505
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10506
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10507
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10508
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10509
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10510
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10511
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10512
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10513
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10514
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10515
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10516
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10517
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10518
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10519
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10520
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10521
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10522
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10523
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10524
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10525
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10526
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10527
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10528
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10529
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10530
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10531
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10532
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10533
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10534
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10535
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10536
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10537
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10538
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10539
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10540
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10541
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10542
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10543
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10544
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10545
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10546
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10547
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10548
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10549
            'connections' => {
10550
              'a' => 'sysgen_dut_to_register28_ce',
10551
              'b' => 'sysgen_dut_to_register28_en',
10552
              'dout' => 'register11td_reg_ce',
10553
            },
10554
            'entity' => {
10555
              'attributes' => {
10556
                'entityAlreadyNetlisted' => 1,
10557
              },
10558
              'entityName' => 'xland2',
10559
              'ports' => {
10560
                'a' => {
10561
                  'direction' => 'in',
10562
                  'hdlType' => 'std_logic',
10563
                  'width' => 1,
10564
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10565
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10566
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10567
                  'hdlType' => 'std_logic',
10568
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10569
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10570
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10571
                  'direction' => 'out',
10572
                  'hdlType' => 'std_logic',
10573
                  'width' => 1,
10574
                },
10575
              },
10576
            },
10577
            'entityName' => 'xland2',
10578
          },
10579
          'register11tv' => {
10580
            'connections' => {
10581
              'ce' => 'register11tv_reg_ce',
10582
              'clk' => 'sysgen_dut_to_register27_clk',
10583
              'clr' => 'sysgen_dut_to_register27_clr',
10584
              'i' => 'sysgen_dut_to_register27_data_in',
10585
              'o' => 'from_register27_data_out_x0',
10586
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10587
            'entity' => {
10588
              'attributes' => {
10589
                'entityAlreadyNetlisted' => 1,
10590
                'generics' => [
10591
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10592
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10593
                    'integer',
10594
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10595
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10596
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10597
                    'init_index',
10598
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10599
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10600
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10601
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10602
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10603
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10604
                    'b"0"',
10605
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10606
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10607
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10608
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10609
                    1,
10610
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10611
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10612
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10613
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10614
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10615
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10616
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10617
                  'hdlType' => 'std_logic',
10618
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10619
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10620
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10621
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10622
                  'hdlType' => 'std_logic',
10623
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10624
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10625
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10626
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10627
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10628
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10629
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10630
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10631
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10632
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10633
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10634
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10635
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10636
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10637
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10638
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10639
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10640
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10641
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10642
            'entityName' => 'synth_reg_w_init',
10643
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10644
          'register11tv_ce_and2_comp' => {
10645
            'connections' => {
10646
              'a' => 'sysgen_dut_to_register27_ce',
10647
              'b' => 'sysgen_dut_to_register27_en',
10648
              'dout' => 'register11tv_reg_ce',
10649
            },
10650
            'entity' => {
10651
              'attributes' => {
10652
                'entityAlreadyNetlisted' => 1,
10653
              },
10654
              'entityName' => 'xland2',
10655
              'ports' => {
10656
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10657
                  'direction' => 'in',
10658
                  'hdlType' => 'std_logic',
10659
                  'width' => 1,
10660
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10661
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10662
                  'direction' => 'in',
10663
                  'hdlType' => 'std_logic',
10664
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10665
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10666
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10667
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10668
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10669
                  'width' => 1,
10670
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10671
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10672
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10673
            'entityName' => 'xland2',
10674
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10675
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10676
            'connections' => {
10677
              'ce' => 'register12rd_reg_ce',
10678
              'clk' => 'sysgen_dut_to_register23_clk_x0',
10679
              'clr' => 'sysgen_dut_to_register23_clr_x0',
10680
              'i' => 'sysgen_dut_to_register23_data_in_x0',
10681
              'o' => 'from_register23_data_out',
10682
            },
10683
            'entity' => {
10684
              'attributes' => {
10685
                'entityAlreadyNetlisted' => 1,
10686
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10687
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10688
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10689
                    'integer',
10690
                    32,
10691
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10692
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10693
                    'init_index',
10694
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10695
                    2,
10696
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10697
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10698
                    'init_value',
10699
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10700
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10701
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10702
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10703
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10704
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10705
                    1,
10706
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10707
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10708
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10709
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10710
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10711
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10712
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10713
                  'hdlType' => 'std_logic',
10714
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10715
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10716
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10717
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10718
                  'hdlType' => 'std_logic',
10719
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10720
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10721
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10722
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10723
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10724
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10725
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10726
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10727
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10728
                  'hdlType' => 'std_logic_vector(31 downto 0)',
10729
                  'width' => 32,
10730
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10731
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10732
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10733
                  'hdlType' => 'std_logic_vector(31 downto 0)',
10734
                  'width' => 32,
10735
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10736
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10737
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10738
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10739
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10740
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10741
            'connections' => {
10742
              'a' => 'sysgen_dut_to_register23_ce_x0',
10743
              'b' => 'sysgen_dut_to_register23_en_x0',
10744
              'dout' => 'register12rd_reg_ce',
10745
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10746
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10747
              'attributes' => {
10748
                'entityAlreadyNetlisted' => 1,
10749
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10750
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10751
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10752
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10753
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10754
                  'hdlType' => 'std_logic',
10755
                  'width' => 1,
10756
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10757
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10758
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10759
                  'hdlType' => 'std_logic',
10760
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10761
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10762
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10763
                  'direction' => 'out',
10764
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10765
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10766
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10767
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10768
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10769
            'entityName' => 'xland2',
10770
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10771
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10772
            'connections' => {
10773
              'ce' => 'register12rv_reg_ce',
10774
              'clk' => 'sysgen_dut_to_register22_clk_x0',
10775
              'clr' => 'sysgen_dut_to_register22_clr_x0',
10776
              'i' => 'sysgen_dut_to_register22_data_in_x0',
10777
              'o' => 'from_register24_data_out',
10778
            },
10779
            'entity' => {
10780
              'attributes' => {
10781
                'entityAlreadyNetlisted' => 1,
10782
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10783
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10784
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10785
                    'integer',
10786
                    1,
10787
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10788
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10789
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10790
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10791
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10792
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10793
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10794
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10795
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10796
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10797
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10798
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10799
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10800
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10801
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10802
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10803
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10804
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10805
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10806
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10807
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10808
                  'direction' => 'in',
10809
                  'hdlType' => 'std_logic',
10810
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10811
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10812
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10813
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10814
                  'hdlType' => 'std_logic',
10815
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10816
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10817
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10818
                  'direction' => 'in',
10819
                  'hdlType' => 'std_logic',
10820
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10821
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10822
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10823
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10824
                  'hdlType' => 'std_logic_vector(0 downto 0)',
10825
                  'width' => 1,
10826
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10827
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10828
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10829
                  'hdlType' => 'std_logic_vector(0 downto 0)',
10830
                  'width' => 1,
10831
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10832
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10833
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10834
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10835
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10836
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10837
            'connections' => {
10838
              'a' => 'sysgen_dut_to_register22_ce_x0',
10839
              'b' => 'sysgen_dut_to_register22_en_x0',
10840
              'dout' => 'register12rv_reg_ce',
10841
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10842
            'entity' => {
10843
              'attributes' => {
10844
                'entityAlreadyNetlisted' => 1,
10845
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10846
              'entityName' => 'xland2',
10847
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10848
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10849
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10850
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10851
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10852
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10853
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10854
                  'direction' => 'in',
10855
                  'hdlType' => 'std_logic',
10856
                  'width' => 1,
10857
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10858
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10859
                  'direction' => 'out',
10860
                  'hdlType' => 'std_logic',
10861
                  'width' => 1,
10862
                },
10863
              },
10864
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10865
            'entityName' => 'xland2',
10866
          },
10867
          'register12td' => {
10868
            'connections' => {
10869
              'ce' => 'register12td_reg_ce',
10870
              'clk' => 'sysgen_dut_to_register30_clk',
10871
              'clr' => 'sysgen_dut_to_register30_clr',
10872
              'i' => 'sysgen_dut_to_register30_data_in',
10873
              'o' => 'from_register28_data_out_x0',
10874
            },
10875
            'entity' => {
10876
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10877
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10878
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10879
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10880
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10881
                    'integer',
10882
                    32,
10883
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10884
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10885
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10886
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10887
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10888
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10889
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10890
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10891
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10892
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10893
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10894
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10895
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10896
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10897
                    1,
10898
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10899
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10900
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10901
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10902
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10903
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10904
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10905
                  'hdlType' => 'std_logic',
10906
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10907
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10908
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10909
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10910
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10911
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10912
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10913
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10914
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10915
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10916
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10917
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10918
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10919
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10920
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10921
                  'width' => 32,
10922
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10923
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10924
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10925
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10926
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10927
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10928
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10929
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10930
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10931
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10932
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10933
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10934
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10935
              'b' => 'sysgen_dut_to_register30_en',
10936
              'dout' => 'register12td_reg_ce',
10937
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10938
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10939
              'attributes' => {
10940
                'entityAlreadyNetlisted' => 1,
10941
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10942
              'entityName' => 'xland2',
10943
              'ports' => {
10944
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10945
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10946
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10947
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10948
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10949
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10950
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10951
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10952
                  'width' => 1,
10953
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10954
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10955
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10956
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10957
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10958
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10959
              },
10960
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10961
            'entityName' => 'xland2',
10962
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10963
          'register12tv' => {
10964
            'connections' => {
10965
              'ce' => 'register12tv_reg_ce',
10966
              'clk' => 'sysgen_dut_to_register29_clk',
10967
              'clr' => 'sysgen_dut_to_register29_clr',
10968
              'i' => 'sysgen_dut_to_register29_data_in',
10969
              'o' => 'from_register29_data_out',
10970
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10971
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10972
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10973
                'entityAlreadyNetlisted' => 1,
10974
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10975
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10976
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10977
                    'integer',
10978
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10979
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10980
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10981
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10982
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10983
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10984
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10985
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10986
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10987
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10988
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10989
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10990
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10991
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10992
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10993
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10994
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10995
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10996
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10997
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10998
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10999
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11000
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11001
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11002
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11003
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11004
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11005
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11006
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11007
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11008
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11009
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11010
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11011
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11012
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11013
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11014
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11015
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11016
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11017
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11018
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11019
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11020
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11021
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11022
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11023
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11024
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11025
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11026
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11027
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11028
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11029
            'connections' => {
11030
              'a' => 'sysgen_dut_to_register29_ce',
11031
              'b' => 'sysgen_dut_to_register29_en',
11032
              'dout' => 'register12tv_reg_ce',
11033
            },
11034
            'entity' => {
11035
              'attributes' => {
11036
                'entityAlreadyNetlisted' => 1,
11037
              },
11038
              'entityName' => 'xland2',
11039
              'ports' => {
11040
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11041
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11042
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11043
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11044
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11045
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11046
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11047
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11048
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11049
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11050
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11051
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11052
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11053
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11054
                },
11055
              },
11056
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11057
            'entityName' => 'xland2',
11058
          },
11059
          'register13rd' => {
11060
            'connections' => {
11061
              'ce' => 'register13rd_reg_ce',
11062
              'clk' => 'sysgen_dut_to_register25_clk_x0',
11063
              'clr' => 'sysgen_dut_to_register25_clr_x0',
11064
              'i' => 'sysgen_dut_to_register25_data_in_x0',
11065
              'o' => 'from_register25_data_out',
11066
            },
11067
            'entity' => {
11068
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11069
                'entityAlreadyNetlisted' => 1,
11070
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11071
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11072
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11073
                    'integer',
11074
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11075
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11076
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11077
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11078
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11079
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11080
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11081
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11082
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11083
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11084
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11085
                  ],
11086
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11087
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11088
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11089
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11090
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11091
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11092
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11093
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11094
              'ports' => {
11095
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11096
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11097
                  'hdlType' => 'std_logic',
11098
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11099
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11100
                'clk' => {
11101
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11102
                  'hdlType' => 'std_logic',
11103
                  'width' => 1,
11104
                },
11105
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11106
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11107
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11108
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11109
                },
11110
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11111
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11112
                  'hdlType' => 'std_logic_vector(31 downto 0)',
11113
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11114
                },
11115
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11116
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11117
                  'hdlType' => 'std_logic_vector(31 downto 0)',
11118
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11119
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11120
              },
11121
            },
11122
            'entityName' => 'synth_reg_w_init',
11123
          },
11124
          'register13rd_ce_and2_comp' => {
11125
            'connections' => {
11126
              'a' => 'sysgen_dut_to_register25_ce_x0',
11127
              'b' => 'sysgen_dut_to_register25_en_x0',
11128
              'dout' => 'register13rd_reg_ce',
11129
            },
11130
            'entity' => {
11131
              'attributes' => {
11132
                'entityAlreadyNetlisted' => 1,
11133
              },
11134
              'entityName' => 'xland2',
11135
              'ports' => {
11136
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11137
                  'direction' => 'in',
11138
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11139
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11140
                },
11141
                'b' => {
11142
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11143
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11144
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11145
                },
11146
                'dout' => {
11147
                  'direction' => 'out',
11148
                  'hdlType' => 'std_logic',
11149
                  'width' => 1,
11150
                },
11151
              },
11152
            },
11153
            'entityName' => 'xland2',
11154
          },
11155
          'register13rv' => {
11156
            'connections' => {
11157
              'ce' => 'register13rv_reg_ce',
11158
              'clk' => 'sysgen_dut_to_register24_clk_x0',
11159
              'clr' => 'sysgen_dut_to_register24_clr_x0',
11160
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11165
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11167
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11168
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11173
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11178
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11183
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11222
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11224
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11225
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11227
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11230
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11248
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11249
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11251
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11252
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11253
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11257
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11258
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11264
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11274
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11279
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11281
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11283
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11289
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11292
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11294
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11301
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11309
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11312
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11313
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11314
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11315
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11316
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11317
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11318
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11319
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11320
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11321
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11322
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11323
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11324
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11326
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11330
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11344
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11345
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11347
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11348
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11349
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11350
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11351
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11352
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11353
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11354
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11355
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11357
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11360
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11361
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11362
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11365
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11368
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11370
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11371
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11372
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11374
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11375
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11376
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11377
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11378
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11379
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11380
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11405
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11416
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11417
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11420
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11422
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11440
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11444
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11445
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11456
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11461
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11464
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11466
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11471
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11473
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11474
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11475
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11537
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11540
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11541
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11546
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11547
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11552
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11570
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11571
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11577
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11608
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11610
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11614
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11631
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11633
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11636
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11637
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11648
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11650
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11653
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11658
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11660
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11662
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11663
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11664
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11665
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11667
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11673
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11688
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11696
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11698
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11700
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11701
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11702
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11704
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11705
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11706
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11707
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11708
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11710
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11714
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11725
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11726
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11727
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11728
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11729
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11730
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11731
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11732
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11733
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11734
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11735
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11736
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11737
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11738
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11739
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11744
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11745
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11746
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11747
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11748
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11749
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11750
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11751
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11752
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11753
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11754
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11755
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11756
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11757
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11758
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11759
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11760
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11761
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11762
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11763
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11764
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11765
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11769
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11770
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11772
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11773
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11774
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11775
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11777
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11778
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11779
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11780
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11782
                'i' => {
11783
                  'direction' => 'in',
11784
                  'hdlType' => 'std_logic_vector(0 downto 0)',
11785
                  'width' => 1,
11786
                },
11787
                'o' => {
11788
                  'direction' => 'out',
11789
                  'hdlType' => 'std_logic_vector(0 downto 0)',
11790
                  'width' => 1,
11791
                },
11792
              },
11793
            },
11794
            'entityName' => 'synth_reg_w_init',
11795
          },
11796
          'register14tv_ce_and2_comp' => {
11797
            'connections' => {
11798
              'a' => 'sysgen_dut_to_register33_ce',
11799
              'b' => 'sysgen_dut_to_register33_en',
11800
              'dout' => 'register14tv_reg_ce',
11801
            },
11802
            'entity' => {
11803
              'attributes' => {
11804
                'entityAlreadyNetlisted' => 1,
11805
              },
11806
              'entityName' => 'xland2',
11807
              'ports' => {
11808
                'a' => {
11809
                  'direction' => 'in',
11810
                  'hdlType' => 'std_logic',
11811
                  'width' => 1,
11812
                },
11813
                'b' => {
11814
                  'direction' => 'in',
11815
                  'hdlType' => 'std_logic',
11816
                  'width' => 1,
11817
                },
11818
                'dout' => {
11819
                  'direction' => 'out',
11820
                  'hdlType' => 'std_logic',
11821
                  'width' => 1,
11822
                },
11823
              },
11824
            },
11825
            'entityName' => 'xland2',
11826
          },
11827
          'top_level_0' => {
11828
            'connections' => {
11829
              'ce' => 'x',
11830
              'clk' => 'x_x0',
11831
              'debug_in_1i' => 'x_x1',
11832
              'debug_in_2i' => 'x_x2',
11833
              'debug_in_3i' => 'x_x3',
11834
              'debug_in_4i' => 'x_x4',
11835
              'dma_host2board_busy' => 'x_x5',
11836
              'dma_host2board_done' => 'x_x6',
11837
              'from_register10_data_out' => 'from_register10_data_out',
11838
              'from_register11_data_out' => 'from_register11_data_out',
11839
              'from_register12_data_out' => 'from_register12_data_out',
11840
              'from_register13_data_out' => 'from_register13_data_out',
11841
              'from_register14_data_out' => 'from_register14_data_out',
11842
              'from_register15_data_out' => 'from_register15_data_out',
11843
              'from_register16_data_out' => 'from_register16_data_out',
11844
              'from_register17_data_out' => 'from_register17_data_out',
11845
              'from_register18_data_out' => 'from_register18_data_out',
11846
              'from_register19_data_out' => 'from_register19_data_out',
11847
              'from_register1_data_out' => 'from_register1_data_out',
11848
              'from_register20_data_out' => 'from_register20_data_out',
11849
              'from_register21_data_out' => 'from_register21_data_out',
11850
              'from_register22_data_out' => 'from_register22_data_out',
11851
              'from_register23_data_out' => 'from_register23_data_out',
11852
              'from_register24_data_out' => 'from_register24_data_out',
11853
              'from_register25_data_out' => 'from_register25_data_out',
11854
              'from_register26_data_out' => 'from_register26_data_out',
11855
              'from_register27_data_out' => 'from_register27_data_out',
11856
              'from_register28_data_out' => 'from_register28_data_out',
11857
              'from_register2_data_out' => 'from_register2_data_out',
11858
              'from_register3_data_out' => 'from_register3_data_out',
11859
              'from_register4_data_out' => 'from_register4_data_out',
11860
              'from_register5_data_out' => 'from_register5_data_out',
11861
              'from_register6_data_out' => 'from_register6_data_out',
11862
              'from_register7_data_out' => 'from_register7_data_out',
11863
              'from_register8_data_out' => 'from_register8_data_out',
11864
              'from_register9_data_out' => 'from_register9_data_out',
11865
              'reg01_rd' => 'x_x7',
11866
              'reg01_rv' => 'x_x8',
11867
              'reg01_td' => 'x_x9',
11868
              'reg01_tv' => 'x_x10',
11869
              'reg02_rd' => 'x_x11',
11870
              'reg02_rv' => 'x_x12',
11871
              'reg02_td' => 'x_x13',
11872
              'reg02_tv' => 'x_x14',
11873
              'reg03_rd' => 'x_x15',
11874
              'reg03_rv' => 'x_x16',
11875
              'reg03_td' => 'x_x17',
11876
              'reg03_tv' => 'x_x18',
11877
              'reg04_rd' => 'x_x19',
11878
              'reg04_rv' => 'x_x20',
11879
              'reg04_td' => 'x_x21',
11880
              'reg04_tv' => 'x_x22',
11881
              'reg05_rd' => 'x_x23',
11882
              'reg05_rv' => 'x_x24',
11883
              'reg05_td' => 'x_x25',
11884
              'reg05_tv' => 'x_x26',
11885
              'reg06_rd' => 'x_x27',
11886
              'reg06_rv' => 'x_x28',
11887
              'reg06_td' => 'x_x29',
11888
              'reg06_tv' => 'x_x30',
11889
              'reg07_rd' => 'x_x31',
11890
              'reg07_rv' => 'x_x32',
11891
              'reg07_td' => 'x_x33',
11892
              'reg07_tv' => 'x_x34',
11893
              'reg08_rd' => 'x_x35',
11894
              'reg08_rv' => 'x_x36',
11895
              'reg08_td' => 'x_x37',
11896
              'reg08_tv' => 'x_x38',
11897
              'reg09_rd' => 'x_x39',
11898
              'reg09_rv' => 'x_x40',
11899
              'reg09_td' => 'x_x41',
11900
              'reg09_tv' => 'x_x42',
11901
              'reg10_rd' => 'x_x43',
11902
              'reg10_rv' => 'x_x44',
11903
              'reg10_td' => 'x_x45',
11904
              'reg10_tv' => 'x_x46',
11905
              'reg11_rd' => 'x_x47',
11906
              'reg11_rv' => 'x_x48',
11907
              'reg11_td' => 'x_x49',
11908
              'reg11_tv' => 'x_x50',
11909
              'reg12_rd' => 'x_x51',
11910
              'reg12_rv' => 'x_x52',
11911
              'reg12_td' => 'x_x53',
11912
              'reg12_tv' => 'x_x54',
11913
              'reg13_rd' => 'x_x55',
11914
              'reg13_rv' => 'x_x56',
11915
              'reg13_td' => 'x_x57',
11916
              'reg13_tv' => 'x_x58',
11917
              'reg14_rd' => 'x_x59',
11918
              'reg14_rv' => 'x_x60',
11919
              'reg14_td' => 'x_x61',
11920
              'reg14_tv' => 'x_x62',
11921
              'to_register10_ce' => 'sysgen_dut_to_register10_ce',
11922
              'to_register10_clk' => 'sysgen_dut_to_register10_clk',
11923
              'to_register10_clr' => 'sysgen_dut_to_register10_clr',
11924
              'to_register10_data_in' => 'sysgen_dut_to_register10_data_in',
11925
              'to_register10_dout' => 'from_register10_data_out_x0',
11926
              'to_register10_en' => 'sysgen_dut_to_register10_en',
11927
              'to_register11_ce' => 'sysgen_dut_to_register11_ce',
11928
              'to_register11_clk' => 'sysgen_dut_to_register11_clk',
11929
              'to_register11_clr' => 'sysgen_dut_to_register11_clr',
11930
              'to_register11_data_in' => 'sysgen_dut_to_register11_data_in',
11931
              'to_register11_dout' => 'from_register9_data_out_x0',
11932
              'to_register11_en' => 'sysgen_dut_to_register11_en',
11933
              'to_register12_ce' => 'sysgen_dut_to_register12_ce',
11934
              'to_register12_clk' => 'sysgen_dut_to_register12_clk',
11935
              'to_register12_clr' => 'sysgen_dut_to_register12_clr',
11936
              'to_register12_data_in' => 'sysgen_dut_to_register12_data_in',
11937
              'to_register12_dout' => 'from_register12_data_out_x0',
11938
              'to_register12_en' => 'sysgen_dut_to_register12_en',
11939
              'to_register13_ce' => 'sysgen_dut_to_register13_ce',
11940
              'to_register13_clk' => 'sysgen_dut_to_register13_clk',
11941
              'to_register13_clr' => 'sysgen_dut_to_register13_clr',
11942
              'to_register13_data_in' => 'sysgen_dut_to_register13_data_in',
11943
              'to_register13_dout' => 'from_register11_data_out_x0',
11944
              'to_register13_en' => 'sysgen_dut_to_register13_en',
11945
              'to_register14_ce' => 'sysgen_dut_to_register14_ce',
11946
              'to_register14_clk' => 'sysgen_dut_to_register14_clk',
11947
              'to_register14_clr' => 'sysgen_dut_to_register14_clr',
11948
              'to_register14_data_in' => 'sysgen_dut_to_register14_data_in',
11949
              'to_register14_dout' => 'from_register14_data_out_x0',
11950
              'to_register14_en' => 'sysgen_dut_to_register14_en',
11951
              'to_register15_ce' => 'sysgen_dut_to_register15_ce',
11952
              'to_register15_clk' => 'sysgen_dut_to_register15_clk',
11953
              'to_register15_clr' => 'sysgen_dut_to_register15_clr',
11954
              'to_register15_data_in' => 'sysgen_dut_to_register15_data_in',
11955
              'to_register15_dout' => 'from_register13_data_out_x0',
11956
              'to_register15_en' => 'sysgen_dut_to_register15_en',
11957
              'to_register16_ce' => 'sysgen_dut_to_register16_ce',
11958
              'to_register16_clk' => 'sysgen_dut_to_register16_clk',
11959
              'to_register16_clr' => 'sysgen_dut_to_register16_clr',
11960
              'to_register16_data_in' => 'sysgen_dut_to_register16_data_in',
11961
              'to_register16_dout' => 'from_register18_data_out_x0',
11962
              'to_register16_en' => 'sysgen_dut_to_register16_en',
11963
              'to_register17_ce' => 'sysgen_dut_to_register17_ce',
11964
              'to_register17_clk' => 'sysgen_dut_to_register17_clk',
11965
              'to_register17_clr' => 'sysgen_dut_to_register17_clr',
11966
              'to_register17_data_in' => 'sysgen_dut_to_register17_data_in',
11967
              'to_register17_dout' => 'from_register17_data_out_x0',
11968
              'to_register17_en' => 'sysgen_dut_to_register17_en',
11969
              'to_register18_ce' => 'sysgen_dut_to_register18_ce',
11970
              'to_register18_clk' => 'sysgen_dut_to_register18_clk',
11971
              'to_register18_clr' => 'sysgen_dut_to_register18_clr',
11972
              'to_register18_data_in' => 'sysgen_dut_to_register18_data_in',
11973
              'to_register18_dout' => 'from_register16_data_out_x0',
11974
              'to_register18_en' => 'sysgen_dut_to_register18_en',
11975
              'to_register19_ce' => 'sysgen_dut_to_register19_ce',
11976
              'to_register19_clk' => 'sysgen_dut_to_register19_clk',
11977
              'to_register19_clr' => 'sysgen_dut_to_register19_clr',
11978
              'to_register19_data_in' => 'sysgen_dut_to_register19_data_in',
11979
              'to_register19_dout' => 'from_register15_data_out_x0',
11980
              'to_register19_en' => 'sysgen_dut_to_register19_en',
11981
              'to_register1_ce' => 'sysgen_dut_to_register1_ce',
11982
              'to_register1_clk' => 'sysgen_dut_to_register1_clk',
11983
              'to_register1_clr' => 'sysgen_dut_to_register1_clr',
11984
              'to_register1_data_in' => 'sysgen_dut_to_register1_data_in',
11985
              'to_register1_dout' => 'from_register1_data_out_x0',
11986
              'to_register1_en' => 'sysgen_dut_to_register1_en',
11987
              'to_register20_ce' => 'sysgen_dut_to_register20_ce',
11988
              'to_register20_clk' => 'sysgen_dut_to_register20_clk',
11989
              'to_register20_clr' => 'sysgen_dut_to_register20_clr',
11990
              'to_register20_data_in' => 'sysgen_dut_to_register20_data_in',
11991
              'to_register20_dout' => 'from_register19_data_out_x0',
11992
              'to_register20_en' => 'sysgen_dut_to_register20_en',
11993
              'to_register21_ce' => 'sysgen_dut_to_register21_ce',
11994
              'to_register21_clk' => 'sysgen_dut_to_register21_clk',
11995
              'to_register21_clr' => 'sysgen_dut_to_register21_clr',
11996
              'to_register21_data_in' => 'sysgen_dut_to_register21_data_in',
11997
              'to_register21_dout' => 'from_register23_data_out_x0',
11998
              'to_register21_en' => 'sysgen_dut_to_register21_en',
11999
              'to_register22_ce' => 'sysgen_dut_to_register22_ce',
12000
              'to_register22_clk' => 'sysgen_dut_to_register22_clk',
12001
              'to_register22_clr' => 'sysgen_dut_to_register22_clr',
12002
              'to_register22_data_in' => 'sysgen_dut_to_register22_data_in',
12003
              'to_register22_dout' => 'from_register22_data_out_x0',
12004
              'to_register22_en' => 'sysgen_dut_to_register22_en',
12005
              'to_register23_ce' => 'sysgen_dut_to_register23_ce',
12006
              'to_register23_clk' => 'sysgen_dut_to_register23_clk',
12007
              'to_register23_clr' => 'sysgen_dut_to_register23_clr',
12008
              'to_register23_data_in' => 'sysgen_dut_to_register23_data_in',
12009
              'to_register23_dout' => 'from_register25_data_out_x0',
12010
              'to_register23_en' => 'sysgen_dut_to_register23_en',
12011
              'to_register24_ce' => 'sysgen_dut_to_register24_ce',
12012
              'to_register24_clk' => 'sysgen_dut_to_register24_clk',
12013
              'to_register24_clr' => 'sysgen_dut_to_register24_clr',
12014
              'to_register24_data_in' => 'sysgen_dut_to_register24_data_in',
12015
              'to_register24_dout' => 'from_register24_data_out_x0',
12016
              'to_register24_en' => 'sysgen_dut_to_register24_en',
12017
              'to_register25_ce' => 'sysgen_dut_to_register25_ce',
12018
              'to_register25_clk' => 'sysgen_dut_to_register25_clk',
12019
              'to_register25_clr' => 'sysgen_dut_to_register25_clr',
12020
              'to_register25_data_in' => 'sysgen_dut_to_register25_data_in',
12021
              'to_register25_dout' => 'from_register21_data_out_x0',
12022
              'to_register25_en' => 'sysgen_dut_to_register25_en',
12023
              'to_register26_ce' => 'sysgen_dut_to_register26_ce',
12024
              'to_register26_clk' => 'sysgen_dut_to_register26_clk',
12025
              'to_register26_clr' => 'sysgen_dut_to_register26_clr',
12026
              'to_register26_data_in' => 'sysgen_dut_to_register26_data_in',
12027
              'to_register26_dout' => 'from_register20_data_out_x0',
12028
              'to_register26_en' => 'sysgen_dut_to_register26_en',
12029
              'to_register27_ce' => 'sysgen_dut_to_register27_ce',
12030
              'to_register27_clk' => 'sysgen_dut_to_register27_clk',
12031
              'to_register27_clr' => 'sysgen_dut_to_register27_clr',
12032
              'to_register27_data_in' => 'sysgen_dut_to_register27_data_in',
12033
              'to_register27_dout' => 'from_register27_data_out_x0',
12034
              'to_register27_en' => 'sysgen_dut_to_register27_en',
12035
              'to_register28_ce' => 'sysgen_dut_to_register28_ce',
12036
              'to_register28_clk' => 'sysgen_dut_to_register28_clk',
12037
              'to_register28_clr' => 'sysgen_dut_to_register28_clr',
12038
              'to_register28_data_in' => 'sysgen_dut_to_register28_data_in',
12039
              'to_register28_dout' => 'from_register26_data_out_x0',
12040
              'to_register28_en' => 'sysgen_dut_to_register28_en',
12041
              'to_register29_ce' => 'sysgen_dut_to_register29_ce',
12042
              'to_register29_clk' => 'sysgen_dut_to_register29_clk',
12043
              'to_register29_clr' => 'sysgen_dut_to_register29_clr',
12044
              'to_register29_data_in' => 'sysgen_dut_to_register29_data_in',
12045
              'to_register29_dout' => 'from_register29_data_out',
12046
              'to_register29_en' => 'sysgen_dut_to_register29_en',
12047
              'to_register2_ce' => 'sysgen_dut_to_register2_ce',
12048
              'to_register2_clk' => 'sysgen_dut_to_register2_clk',
12049
              'to_register2_clr' => 'sysgen_dut_to_register2_clr',
12050
              'to_register2_data_in' => 'sysgen_dut_to_register2_data_in',
12051
              'to_register2_dout' => 'from_register2_data_out_x0',
12052
              'to_register2_en' => 'sysgen_dut_to_register2_en',
12053
              'to_register30_ce' => 'sysgen_dut_to_register30_ce',
12054
              'to_register30_clk' => 'sysgen_dut_to_register30_clk',
12055
              'to_register30_clr' => 'sysgen_dut_to_register30_clr',
12056
              'to_register30_data_in' => 'sysgen_dut_to_register30_data_in',
12057
              'to_register30_dout' => 'from_register28_data_out_x0',
12058
              'to_register30_en' => 'sysgen_dut_to_register30_en',
12059
              'to_register31_ce' => 'sysgen_dut_to_register31_ce',
12060
              'to_register31_clk' => 'sysgen_dut_to_register31_clk',
12061
              'to_register31_clr' => 'sysgen_dut_to_register31_clr',
12062
              'to_register31_data_in' => 'sysgen_dut_to_register31_data_in',
12063
              'to_register31_dout' => 'from_register31_data_out',
12064
              'to_register31_en' => 'sysgen_dut_to_register31_en',
12065
              'to_register32_ce' => 'sysgen_dut_to_register32_ce',
12066
              'to_register32_clk' => 'sysgen_dut_to_register32_clk',
12067
              'to_register32_clr' => 'sysgen_dut_to_register32_clr',
12068
              'to_register32_data_in' => 'sysgen_dut_to_register32_data_in',
12069
              'to_register32_dout' => 'from_register30_data_out',
12070
              'to_register32_en' => 'sysgen_dut_to_register32_en',
12071
              'to_register33_ce' => 'sysgen_dut_to_register33_ce',
12072
              'to_register33_clk' => 'sysgen_dut_to_register33_clk',
12073
              'to_register33_clr' => 'sysgen_dut_to_register33_clr',
12074
              'to_register33_data_in' => 'sysgen_dut_to_register33_data_in',
12075
              'to_register33_dout' => 'from_register33_data_out',
12076
              'to_register33_en' => 'sysgen_dut_to_register33_en',
12077
              'to_register34_ce' => 'sysgen_dut_to_register34_ce',
12078
              'to_register34_clk' => 'sysgen_dut_to_register34_clk',
12079
              'to_register34_clr' => 'sysgen_dut_to_register34_clr',
12080
              'to_register34_data_in' => 'sysgen_dut_to_register34_data_in',
12081
              'to_register34_dout' => 'from_register32_data_out',
12082
              'to_register34_en' => 'sysgen_dut_to_register34_en',
12083
              'to_register3_ce' => 'sysgen_dut_to_register3_ce',
12084
              'to_register3_clk' => 'sysgen_dut_to_register3_clk',
12085
              'to_register3_clr' => 'sysgen_dut_to_register3_clr',
12086
              'to_register3_data_in' => 'sysgen_dut_to_register3_data_in',
12087
              'to_register3_dout' => 'from_register4_data_out_x0',
12088
              'to_register3_en' => 'sysgen_dut_to_register3_en',
12089
              'to_register4_ce' => 'sysgen_dut_to_register4_ce',
12090
              'to_register4_clk' => 'sysgen_dut_to_register4_clk',
12091
              'to_register4_clr' => 'sysgen_dut_to_register4_clr',
12092
              'to_register4_data_in' => 'sysgen_dut_to_register4_data_in',
12093
              'to_register4_dout' => 'from_register6_data_out_x0',
12094
              'to_register4_en' => 'sysgen_dut_to_register4_en',
12095
              'to_register5_ce' => 'sysgen_dut_to_register5_ce',
12096
              'to_register5_clk' => 'sysgen_dut_to_register5_clk',
12097
              'to_register5_clr' => 'sysgen_dut_to_register5_clr',
12098
              'to_register5_data_in' => 'sysgen_dut_to_register5_data_in',
12099
              'to_register5_dout' => 'from_register5_data_out_x0',
12100
              'to_register5_en' => 'sysgen_dut_to_register5_en',
12101
              'to_register6_ce' => 'sysgen_dut_to_register6_ce',
12102
              'to_register6_clk' => 'sysgen_dut_to_register6_clk',
12103
              'to_register6_clr' => 'sysgen_dut_to_register6_clr',
12104
              'to_register6_data_in' => 'sysgen_dut_to_register6_data_in',
12105
              'to_register6_dout' => 'from_register_data_out',
12106
              'to_register6_en' => 'sysgen_dut_to_register6_en',
12107
              'to_register7_ce' => 'sysgen_dut_to_register7_ce',
12108
              'to_register7_clk' => 'sysgen_dut_to_register7_clk',
12109
              'to_register7_clr' => 'sysgen_dut_to_register7_clr',
12110
              'to_register7_data_in' => 'sysgen_dut_to_register7_data_in',
12111
              'to_register7_dout' => 'from_register3_data_out_x0',
12112
              'to_register7_en' => 'sysgen_dut_to_register7_en',
12113
              'to_register8_ce' => 'sysgen_dut_to_register8_ce',
12114
              'to_register8_clk' => 'sysgen_dut_to_register8_clk',
12115
              'to_register8_clr' => 'sysgen_dut_to_register8_clr',
12116
              'to_register8_data_in' => 'sysgen_dut_to_register8_data_in',
12117
              'to_register8_dout' => 'from_register8_data_out_x0',
12118
              'to_register8_en' => 'sysgen_dut_to_register8_en',
12119
              'to_register9_ce' => 'sysgen_dut_to_register9_ce',
12120
              'to_register9_clk' => 'sysgen_dut_to_register9_clk',
12121
              'to_register9_clr' => 'sysgen_dut_to_register9_clr',
12122
              'to_register9_data_in' => 'sysgen_dut_to_register9_data_in',
12123
              'to_register9_dout' => 'from_register7_data_out_x0',
12124
              'to_register9_en' => 'sysgen_dut_to_register9_en',
12125
            },
12126
            'entity' => {
12127
              'attributes' => {
12128
                'entityAlreadyNetlisted' => 1,
12129
                'hdlArchAttributes' => [
12130
                ],
12131
                'hdlCompAttributes' => [
12132
                  [
12133
                    'syn_black_box',
12134
                    'boolean',
12135
                    'true',
12136
                  ],
12137
                  [
12138
                    'box_type',
12139
                    'string',
12140
                    '"black_box"',
12141
                  ],
12142
                ],
12143
                'hdlEntityAttributes' => [
12144
                ],
12145
                'isClkWrapper' => 1,
12146
                'needsComponentDeclaration' => 1,
12147
              },
12148
              'connections' => {
12149
                'clk' => 'clkNet',
12150
                'debug_in_1i' => 'debug_in_1i_net',
12151
                'debug_in_2i' => 'debug_in_2i_net',
12152
                'debug_in_3i' => 'debug_in_3i_net',
12153
                'debug_in_4i' => 'debug_in_4i_net',
12154
                'dma_host2board_busy' => 'dma_host2board_busy_net',
12155
                'dma_host2board_done' => 'dma_host2board_done_net',
12156
                'from_register10_data_out' => 'from_register10_data_out_net',
12157
                'from_register11_data_out' => 'from_register11_data_out_net',
12158
                'from_register12_data_out' => 'from_register12_data_out_net',
12159
                'from_register13_data_out' => 'from_register13_data_out_net',
12160
                'from_register14_data_out' => 'from_register14_data_out_net',
12161
                'from_register15_data_out' => 'from_register15_data_out_net',
12162
                'from_register16_data_out' => 'from_register16_data_out_net',
12163
                'from_register17_data_out' => 'from_register17_data_out_net',
12164
                'from_register18_data_out' => 'from_register18_data_out_net',
12165
                'from_register19_data_out' => 'from_register19_data_out_net',
12166
                'from_register1_data_out' => 'from_register1_data_out_net',
12167
                'from_register20_data_out' => 'from_register20_data_out_net',
12168
                'from_register21_data_out' => 'from_register21_data_out_net',
12169
                'from_register22_data_out' => 'from_register22_data_out_net',
12170
                'from_register23_data_out' => 'from_register23_data_out_net',
12171
                'from_register24_data_out' => 'from_register24_data_out_net',
12172
                'from_register25_data_out' => 'from_register25_data_out_net',
12173
                'from_register26_data_out' => 'from_register26_data_out_net',
12174
                'from_register27_data_out' => 'from_register27_data_out_net',
12175
                'from_register28_data_out' => 'from_register28_data_out_net',
12176
                'from_register2_data_out' => 'from_register2_data_out_net',
12177
                'from_register3_data_out' => 'from_register3_data_out_net',
12178
                'from_register4_data_out' => 'from_register4_data_out_net',
12179
                'from_register5_data_out' => 'from_register5_data_out_net',
12180
                'from_register6_data_out' => 'from_register6_data_out_net',
12181
                'from_register7_data_out' => 'from_register7_data_out_net',
12182
                'from_register8_data_out' => 'from_register8_data_out_net',
12183
                'from_register9_data_out' => 'from_register9_data_out_net',
12184
                'reg01_rd' => 'from_register3_data_out_net_x0',
12185
                'reg01_rv' => 'from_register1_data_out_net_x0',
12186
                'reg01_td' => 'reg01_td_net',
12187
                'reg01_tv' => 'reg01_tv_net',
12188
                'reg02_rd' => 'from_register5_data_out_net_x0',
12189
                'reg02_rv' => 'from_register2_data_out_net_x0',
12190
                'reg02_td' => 'reg02_td_net',
12191
                'reg02_tv' => 'reg02_tv_net',
12192
                'reg03_rd' => 'from_register7_data_out_net_x0',
12193
                'reg03_rv' => 'from_register6_data_out_net_x0',
12194
                'reg03_td' => 'reg03_td_net',
12195
                'reg03_tv' => 'reg03_tv_net',
12196
                'reg04_rd' => 'from_register8_data_out_net_x0',
12197
                'reg04_rv' => 'from_register4_data_out_net_x0',
12198
                'reg04_td' => 'reg04_td_net',
12199
                'reg04_tv' => 'reg04_tv_net',
12200
                'reg05_rd' => 'from_register10_data_out_net_x0',
12201
                'reg05_rv' => 'from_register9_data_out_net_x0',
12202
                'reg05_td' => 'reg05_td_net',
12203
                'reg05_tv' => 'reg05_tv_net',
12204
                'reg06_rd' => 'from_register11_data_out_net_x0',
12205
                'reg06_rv' => 'from_register12_data_out_net_x0',
12206
                'reg06_td' => 'reg06_td_net',
12207
                'reg06_tv' => 'reg06_tv_net',
12208
                'reg07_rd' => 'from_register13_data_out_net_x0',
12209
                'reg07_rv' => 'from_register14_data_out_net_x0',
12210
                'reg07_td' => 'reg07_td_net',
12211
                'reg07_tv' => 'reg07_tv_net',
12212
                'reg08_rd' => 'from_register15_data_out_net_x0',
12213
                'reg08_rv' => 'from_register16_data_out_net_x0',
12214
                'reg08_td' => 'reg08_td_net',
12215
                'reg08_tv' => 'reg08_tv_net',
12216
                'reg09_rd' => 'from_register17_data_out_net_x0',
12217
                'reg09_rv' => 'from_register18_data_out_net_x0',
12218
                'reg09_td' => 'reg09_td_net',
12219
                'reg09_tv' => 'reg09_tv_net',
12220
                'reg10_rd' => 'from_register19_data_out_net_x0',
12221
                'reg10_rv' => 'from_register20_data_out_net_x0',
12222
                'reg10_td' => 'reg10_td_net',
12223
                'reg10_tv' => 'reg10_tv_net',
12224
                'reg11_rd' => 'from_register21_data_out_net_x0',
12225
                'reg11_rv' => 'from_register22_data_out_net_x0',
12226
                'reg11_td' => 'reg11_td_net',
12227
                'reg11_tv' => 'reg11_tv_net',
12228
                'reg12_rd' => 'from_register23_data_out_net_x0',
12229
                'reg12_rv' => 'from_register24_data_out_net_x0',
12230
                'reg12_td' => 'reg12_td_net',
12231
                'reg12_tv' => 'reg12_tv_net',
12232
                'reg13_rd' => 'from_register25_data_out_net_x0',
12233
                'reg13_rv' => 'from_register26_data_out_net_x0',
12234
                'reg13_td' => 'reg13_td_net',
12235
                'reg13_tv' => 'reg13_tv_net',
12236
                'reg14_rd' => 'from_register27_data_out_net_x0',
12237
                'reg14_rv' => 'from_register28_data_out_net_x0',
12238
                'reg14_td' => 'reg14_td_net',
12239
                'reg14_tv' => 'reg14_tv_net',
12240
                'to_register10_ce' => 'ce_1_sg',
12241
                'to_register10_clk' => 'clk_1_sg',
12242
                'to_register10_clr' => [
12243
                  'constant',
12244
                  '\'0\'',
12245
                ],
12246
                'to_register10_data_in' => 'reg04_tv_net_x0',
12247
                'to_register10_dout' => 'to_register10_dout_net',
12248
                'to_register10_en' => 'constant5_op_net_x1',
12249
                'to_register11_ce' => 'ce_1_sg',
12250
                'to_register11_clk' => 'clk_1_sg',
12251
                'to_register11_clr' => [
12252
                  'constant',
12253
                  '\'0\'',
12254
                ],
12255
                'to_register11_data_in' => 'reg04_td_net_x0',
12256
                'to_register11_dout' => 'to_register11_dout_net',
12257
                'to_register11_en' => 'constant5_op_net_x2',
12258
                'to_register12_ce' => 'ce_1_sg',
12259
                'to_register12_clk' => 'clk_1_sg',
12260
                'to_register12_clr' => [
12261
                  'constant',
12262
                  '\'0\'',
12263
                ],
12264
                'to_register12_data_in' => 'reg05_tv_net_x0',
12265
                'to_register12_dout' => 'to_register12_dout_net',
12266
                'to_register12_en' => 'constant5_op_net_x3',
12267
                'to_register13_ce' => 'ce_1_sg',
12268
                'to_register13_clk' => 'clk_1_sg',
12269
                'to_register13_clr' => [
12270
                  'constant',
12271
                  '\'0\'',
12272
                ],
12273
                'to_register13_data_in' => 'reg05_td_net_x0',
12274
                'to_register13_dout' => 'to_register13_dout_net',
12275
                'to_register13_en' => 'constant5_op_net_x4',
12276
                'to_register14_ce' => 'ce_1_sg',
12277
                'to_register14_clk' => 'clk_1_sg',
12278
                'to_register14_clr' => [
12279
                  'constant',
12280
                  '\'0\'',
12281
                ],
12282
                'to_register14_data_in' => 'reg06_tv_net_x0',
12283
                'to_register14_dout' => 'to_register14_dout_net',
12284
                'to_register14_en' => 'constant5_op_net_x5',
12285
                'to_register15_ce' => 'ce_1_sg',
12286
                'to_register15_clk' => 'clk_1_sg',
12287
                'to_register15_clr' => [
12288
                  'constant',
12289
                  '\'0\'',
12290
                ],
12291
                'to_register15_data_in' => 'reg06_td_net_x0',
12292
                'to_register15_dout' => 'to_register15_dout_net',
12293
                'to_register15_en' => 'constant5_op_net_x6',
12294
                'to_register16_ce' => 'ce_1_sg',
12295
                'to_register16_clk' => 'clk_1_sg',
12296
                'to_register16_clr' => [
12297
                  'constant',
12298
                  '\'0\'',
12299
                ],
12300
                'to_register16_data_in' => 'reg07_tv_net_x0',
12301
                'to_register16_dout' => 'to_register16_dout_net',
12302
                'to_register16_en' => 'constant5_op_net_x7',
12303
                'to_register17_ce' => 'ce_1_sg',
12304
                'to_register17_clk' => 'clk_1_sg',
12305
                'to_register17_clr' => [
12306
                  'constant',
12307
                  '\'0\'',
12308
                ],
12309
                'to_register17_data_in' => 'reg07_td_net_x0',
12310
                'to_register17_dout' => 'to_register17_dout_net',
12311
                'to_register17_en' => 'constant5_op_net_x8',
12312
                'to_register18_ce' => 'ce_1_sg',
12313
                'to_register18_clk' => 'clk_1_sg',
12314
                'to_register18_clr' => [
12315
                  'constant',
12316
                  '\'0\'',
12317
                ],
12318
                'to_register18_data_in' => 'dma_host2board_busy_net_x0',
12319
                'to_register18_dout' => 'to_register18_dout_net',
12320
                'to_register18_en' => 'constant5_op_net_x9',
12321
                'to_register19_ce' => 'ce_1_sg',
12322
                'to_register19_clk' => 'clk_1_sg',
12323
                'to_register19_clr' => [
12324
                  'constant',
12325
                  '\'0\'',
12326
                ],
12327
                'to_register19_data_in' => 'dma_host2board_done_net_x0',
12328
                'to_register19_dout' => 'to_register19_dout_net',
12329
                'to_register19_en' => 'constant5_op_net_x10',
12330
                'to_register1_ce' => 'ce_1_sg',
12331
                'to_register1_clk' => 'clk_1_sg',
12332
                'to_register1_clr' => [
12333
                  'constant',
12334
                  '\'0\'',
12335
                ],
12336
                'to_register1_data_in' => 'debug_in_2i_net_x0',
12337
                'to_register1_dout' => 'to_register1_dout_net',
12338
                'to_register1_en' => 'constant5_op_net_x0',
12339
                'to_register20_ce' => 'ce_1_sg',
12340
                'to_register20_clk' => 'clk_1_sg',
12341
                'to_register20_clr' => [
12342
                  'constant',
12343
                  '\'0\'',
12344
                ],
12345
                'to_register20_data_in' => 'debug_in_4i_net_x0',
12346
                'to_register20_dout' => 'to_register20_dout_net',
12347
                'to_register20_en' => 'constant5_op_net_x12',
12348
                'to_register21_ce' => 'ce_1_sg',
12349
                'to_register21_clk' => 'clk_1_sg',
12350
                'to_register21_clr' => [
12351
                  'constant',
12352
                  '\'0\'',
12353
                ],
12354
                'to_register21_data_in' => 'reg09_tv_net_x0',
12355
                'to_register21_dout' => 'to_register21_dout_net',
12356
                'to_register21_en' => 'constant1_op_net_x0',
12357
                'to_register22_ce' => 'ce_1_sg',
12358
                'to_register22_clk' => 'clk_1_sg',
12359
                'to_register22_clr' => [
12360
                  'constant',
12361
                  '\'0\'',
12362
                ],
12363
                'to_register22_data_in' => 'reg09_td_net_x0',
12364
                'to_register22_dout' => 'to_register22_dout_net',
12365
                'to_register22_en' => 'constant1_op_net_x1',
12366
                'to_register23_ce' => 'ce_1_sg',
12367
                'to_register23_clk' => 'clk_1_sg',
12368
                'to_register23_clr' => [
12369
                  'constant',
12370
                  '\'0\'',
12371
                ],
12372
                'to_register23_data_in' => 'reg10_tv_net_x0',
12373
                'to_register23_dout' => 'to_register23_dout_net',
12374
                'to_register23_en' => 'constant1_op_net_x2',
12375
                'to_register24_ce' => 'ce_1_sg',
12376
                'to_register24_clk' => 'clk_1_sg',
12377
                'to_register24_clr' => [
12378
                  'constant',
12379
                  '\'0\'',
12380
                ],
12381
                'to_register24_data_in' => 'reg10_td_net_x0',
12382
                'to_register24_dout' => 'to_register24_dout_net',
12383
                'to_register24_en' => 'constant1_op_net_x3',
12384
                'to_register25_ce' => 'ce_1_sg',
12385
                'to_register25_clk' => 'clk_1_sg',
12386
                'to_register25_clr' => [
12387
                  'constant',
12388
                  '\'0\'',
12389
                ],
12390
                'to_register25_data_in' => 'reg08_tv_net_x0',
12391
                'to_register25_dout' => 'to_register25_dout_net',
12392
                'to_register25_en' => 'constant1_op_net_x4',
12393
                'to_register26_ce' => 'ce_1_sg',
12394
                'to_register26_clk' => 'clk_1_sg',
12395
                'to_register26_clr' => [
12396
                  'constant',
12397
                  '\'0\'',
12398
                ],
12399
                'to_register26_data_in' => 'reg08_td_net_x0',
12400
                'to_register26_dout' => 'to_register26_dout_net',
12401
                'to_register26_en' => 'constant1_op_net_x5',
12402
                'to_register27_ce' => 'ce_1_sg',
12403
                'to_register27_clk' => 'clk_1_sg',
12404
                'to_register27_clr' => [
12405
                  'constant',
12406
                  '\'0\'',
12407
                ],
12408
                'to_register27_data_in' => 'reg11_tv_net_x0',
12409
                'to_register27_dout' => 'to_register27_dout_net',
12410
                'to_register27_en' => 'constant1_op_net_x6',
12411
                'to_register28_ce' => 'ce_1_sg',
12412
                'to_register28_clk' => 'clk_1_sg',
12413
                'to_register28_clr' => [
12414
                  'constant',
12415
                  '\'0\'',
12416
                ],
12417
                'to_register28_data_in' => 'reg11_td_net_x0',
12418
                'to_register28_dout' => 'to_register28_dout_net',
12419
                'to_register28_en' => 'constant1_op_net_x7',
12420
                'to_register29_ce' => 'ce_1_sg',
12421
                'to_register29_clk' => 'clk_1_sg',
12422
                'to_register29_clr' => [
12423
                  'constant',
12424
                  '\'0\'',
12425
                ],
12426
                'to_register29_data_in' => 'reg12_tv_net_x0',
12427
                'to_register29_dout' => 'to_register29_dout_net',
12428
                'to_register29_en' => 'constant1_op_net_x8',
12429
                'to_register2_ce' => 'ce_1_sg',
12430
                'to_register2_clk' => 'clk_1_sg',
12431
                'to_register2_clr' => [
12432
                  'constant',
12433
                  '\'0\'',
12434
                ],
12435
                'to_register2_data_in' => 'debug_in_3i_net_x0',
12436
                'to_register2_dout' => 'to_register2_dout_net',
12437
                'to_register2_en' => 'constant5_op_net_x11',
12438
                'to_register30_ce' => 'ce_1_sg',
12439
                'to_register30_clk' => 'clk_1_sg',
12440
                'to_register30_clr' => [
12441
                  'constant',
12442
                  '\'0\'',
12443
                ],
12444
                'to_register30_data_in' => 'reg12_td_net_x0',
12445
                'to_register30_dout' => 'to_register30_dout_net',
12446
                'to_register30_en' => 'constant1_op_net_x9',
12447
                'to_register31_ce' => 'ce_1_sg',
12448
                'to_register31_clk' => 'clk_1_sg',
12449
                'to_register31_clr' => [
12450
                  'constant',
12451
                  '\'0\'',
12452
                ],
12453
                'to_register31_data_in' => 'reg13_tv_net_x0',
12454
                'to_register31_dout' => 'to_register31_dout_net',
12455
                'to_register31_en' => 'constant1_op_net_x10',
12456
                'to_register32_ce' => 'ce_1_sg',
12457
                'to_register32_clk' => 'clk_1_sg',
12458
                'to_register32_clr' => [
12459
                  'constant',
12460
                  '\'0\'',
12461
                ],
12462
                'to_register32_data_in' => 'reg13_td_net_x0',
12463
                'to_register32_dout' => 'to_register32_dout_net',
12464
                'to_register32_en' => 'constant1_op_net_x11',
12465
                'to_register33_ce' => 'ce_1_sg',
12466
                'to_register33_clk' => 'clk_1_sg',
12467
                'to_register33_clr' => [
12468
                  'constant',
12469
                  '\'0\'',
12470
                ],
12471
                'to_register33_data_in' => 'reg14_tv_net_x0',
12472
                'to_register33_dout' => 'to_register33_dout_net',
12473
                'to_register33_en' => 'constant1_op_net_x12',
12474
                'to_register34_ce' => 'ce_1_sg',
12475
                'to_register34_clk' => 'clk_1_sg',
12476
                'to_register34_clr' => [
12477
                  'constant',
12478
                  '\'0\'',
12479
                ],
12480
                'to_register34_data_in' => 'reg14_td_net_x0',
12481
                'to_register34_dout' => 'to_register34_dout_net',
12482
                'to_register34_en' => 'constant1_op_net_x13',
12483
                'to_register3_ce' => 'ce_1_sg',
12484
                'to_register3_clk' => 'clk_1_sg',
12485
                'to_register3_clr' => [
12486
                  'constant',
12487
                  '\'0\'',
12488
                ],
12489
                'to_register3_data_in' => 'reg01_tv_net_x0',
12490
                'to_register3_dout' => 'to_register3_dout_net',
12491
                'to_register3_en' => 'constant5_op_net_x13',
12492
                'to_register4_ce' => 'ce_1_sg',
12493
                'to_register4_clk' => 'clk_1_sg',
12494
                'to_register4_clr' => [
12495
                  'constant',
12496
                  '\'0\'',
12497
                ],
12498
                'to_register4_data_in' => 'reg02_tv_net_x0',
12499
                'to_register4_dout' => 'to_register4_dout_net',
12500
                'to_register4_en' => 'constant5_op_net_x14',
12501
                'to_register5_ce' => 'ce_1_sg',
12502
                'to_register5_clk' => 'clk_1_sg',
12503
                'to_register5_clr' => [
12504
                  'constant',
12505
                  '\'0\'',
12506
                ],
12507
                'to_register5_data_in' => 'reg02_td_net_x0',
12508
                'to_register5_dout' => 'to_register5_dout_net',
12509
                'to_register5_en' => 'constant5_op_net_x15',
12510
                'to_register6_ce' => 'ce_1_sg',
12511
                'to_register6_clk' => 'clk_1_sg',
12512
                'to_register6_clr' => [
12513
                  'constant',
12514
                  '\'0\'',
12515
                ],
12516
                'to_register6_data_in' => 'debug_in_1i_net_x0',
12517
                'to_register6_dout' => 'to_register6_dout_net',
12518
                'to_register6_en' => 'constant5_op_net_x16',
12519
                'to_register7_ce' => 'ce_1_sg',
12520
                'to_register7_clk' => 'clk_1_sg',
12521
                'to_register7_clr' => [
12522
                  'constant',
12523
                  '\'0\'',
12524
                ],
12525
                'to_register7_data_in' => 'reg01_td_net_x0',
12526
                'to_register7_dout' => 'to_register7_dout_net',
12527
                'to_register7_en' => 'constant5_op_net_x17',
12528
                'to_register8_ce' => 'ce_1_sg',
12529
                'to_register8_clk' => 'clk_1_sg',
12530
                'to_register8_clr' => [
12531
                  'constant',
12532
                  '\'0\'',
12533
                ],
12534
                'to_register8_data_in' => 'reg03_tv_net_x0',
12535
                'to_register8_dout' => 'to_register8_dout_net',
12536
                'to_register8_en' => 'constant5_op_net_x18',
12537
                'to_register9_ce' => 'ce_1_sg',
12538
                'to_register9_clk' => 'clk_1_sg',
12539
                'to_register9_clr' => [
12540
                  'constant',
12541
                  '\'0\'',
12542
                ],
12543
                'to_register9_data_in' => 'reg03_td_net_x0',
12544
                'to_register9_dout' => 'to_register9_dout_net',
12545
                'to_register9_en' => 'constant5_op_net_x19',
12546
              },
12547
              'entityName' => 'inout_logic_cw',
12548
              'nets' => {
12549
                'ce_1_sg' => {
12550
                  'attributes' => {
12551
                    'hdlNetAttributes' => [
12552
                      [
12553
                        'MAX_FANOUT',
12554
                        'string',
12555
                        '"REDUCE"',
12556
                      ],
12557
                    ],
12558
                  },
12559
                  'hdlType' => 'std_logic',
12560
                  'width' => 1,
12561
                },
12562
                'clkNet' => {
12563
                  'attributes' => {
12564
                    'hdlNetAttributes' => [
12565
                    ],
12566
                  },
12567
                  'hdlType' => 'std_logic',
12568
                  'width' => 1,
12569
                },
12570
                'clk_1_sg' => {
12571
                  'attributes' => {
12572
                    'hdlNetAttributes' => [
12573
                    ],
12574
                  },
12575
                  'hdlType' => 'std_logic',
12576
                  'width' => 1,
12577
                },
12578
                'constant1_op_net_x0' => {
12579
                  'attributes' => {
12580
                    'hdlNetAttributes' => [
12581
                    ],
12582
                  },
12583
                  'hdlType' => 'std_logic',
12584
                  'width' => 1,
12585
                },
12586
                'constant1_op_net_x1' => {
12587
                  'attributes' => {
12588
                    'hdlNetAttributes' => [
12589
                    ],
12590
                  },
12591
                  'hdlType' => 'std_logic',
12592
                  'width' => 1,
12593
                },
12594
                'constant1_op_net_x10' => {
12595
                  'attributes' => {
12596
                    'hdlNetAttributes' => [
12597
                    ],
12598
                  },
12599
                  'hdlType' => 'std_logic',
12600
                  'width' => 1,
12601
                },
12602
                'constant1_op_net_x11' => {
12603
                  'attributes' => {
12604
                    'hdlNetAttributes' => [
12605
                    ],
12606
                  },
12607
                  'hdlType' => 'std_logic',
12608
                  'width' => 1,
12609
                },
12610
                'constant1_op_net_x12' => {
12611
                  'attributes' => {
12612
                    'hdlNetAttributes' => [
12613
                    ],
12614
                  },
12615
                  'hdlType' => 'std_logic',
12616
                  'width' => 1,
12617
                },
12618
                'constant1_op_net_x13' => {
12619
                  'attributes' => {
12620
                    'hdlNetAttributes' => [
12621
                    ],
12622
                  },
12623
                  'hdlType' => 'std_logic',
12624
                  'width' => 1,
12625
                },
12626
                'constant1_op_net_x2' => {
12627
                  'attributes' => {
12628
                    'hdlNetAttributes' => [
12629
                    ],
12630
                  },
12631
                  'hdlType' => 'std_logic',
12632
                  'width' => 1,
12633
                },
12634
                'constant1_op_net_x3' => {
12635
                  'attributes' => {
12636
                    'hdlNetAttributes' => [
12637
                    ],
12638
                  },
12639
                  'hdlType' => 'std_logic',
12640
                  'width' => 1,
12641
                },
12642
                'constant1_op_net_x4' => {
12643
                  'attributes' => {
12644
                    'hdlNetAttributes' => [
12645
                    ],
12646
                  },
12647
                  'hdlType' => 'std_logic',
12648
                  'width' => 1,
12649
                },
12650
                'constant1_op_net_x5' => {
12651
                  'attributes' => {
12652
                    'hdlNetAttributes' => [
12653
                    ],
12654
                  },
12655
                  'hdlType' => 'std_logic',
12656
                  'width' => 1,
12657
                },
12658
                'constant1_op_net_x6' => {
12659
                  'attributes' => {
12660
                    'hdlNetAttributes' => [
12661
                    ],
12662
                  },
12663
                  'hdlType' => 'std_logic',
12664
                  'width' => 1,
12665
                },
12666
                'constant1_op_net_x7' => {
12667
                  'attributes' => {
12668
                    'hdlNetAttributes' => [
12669
                    ],
12670
                  },
12671
                  'hdlType' => 'std_logic',
12672
                  'width' => 1,
12673
                },
12674
                'constant1_op_net_x8' => {
12675
                  'attributes' => {
12676
                    'hdlNetAttributes' => [
12677
                    ],
12678
                  },
12679
                  'hdlType' => 'std_logic',
12680
                  'width' => 1,
12681
                },
12682
                'constant1_op_net_x9' => {
12683
                  'attributes' => {
12684
                    'hdlNetAttributes' => [
12685
                    ],
12686
                  },
12687
                  'hdlType' => 'std_logic',
12688
                  'width' => 1,
12689
                },
12690
                'constant5_op_net_x0' => {
12691
                  'attributes' => {
12692
                    'hdlNetAttributes' => [
12693
                    ],
12694
                  },
12695
                  'hdlType' => 'std_logic',
12696
                  'width' => 1,
12697
                },
12698
                'constant5_op_net_x1' => {
12699
                  'attributes' => {
12700
                    'hdlNetAttributes' => [
12701
                    ],
12702
                  },
12703
                  'hdlType' => 'std_logic',
12704
                  'width' => 1,
12705
                },
12706
                'constant5_op_net_x10' => {
12707
                  'attributes' => {
12708
                    'hdlNetAttributes' => [
12709
                    ],
12710
                  },
12711
                  'hdlType' => 'std_logic',
12712
                  'width' => 1,
12713
                },
12714
                'constant5_op_net_x11' => {
12715
                  'attributes' => {
12716
                    'hdlNetAttributes' => [
12717
                    ],
12718
                  },
12719
                  'hdlType' => 'std_logic',
12720
                  'width' => 1,
12721
                },
12722
                'constant5_op_net_x12' => {
12723
                  'attributes' => {
12724
                    'hdlNetAttributes' => [
12725
                    ],
12726
                  },
12727
                  'hdlType' => 'std_logic',
12728
                  'width' => 1,
12729
                },
12730
                'constant5_op_net_x13' => {
12731
                  'attributes' => {
12732
                    'hdlNetAttributes' => [
12733
                    ],
12734
                  },
12735
                  'hdlType' => 'std_logic',
12736
                  'width' => 1,
12737
                },
12738
                'constant5_op_net_x14' => {
12739
                  'attributes' => {
12740
                    'hdlNetAttributes' => [
12741
                    ],
12742
                  },
12743
                  'hdlType' => 'std_logic',
12744
                  'width' => 1,
12745
                },
12746
                'constant5_op_net_x15' => {
12747
                  'attributes' => {
12748
                    'hdlNetAttributes' => [
12749
                    ],
12750
                  },
12751
                  'hdlType' => 'std_logic',
12752
                  'width' => 1,
12753
                },
12754
                'constant5_op_net_x16' => {
12755
                  'attributes' => {
12756
                    'hdlNetAttributes' => [
12757
                    ],
12758
                  },
12759
                  'hdlType' => 'std_logic',
12760
                  'width' => 1,
12761
                },
12762
                'constant5_op_net_x17' => {
12763
                  'attributes' => {
12764
                    'hdlNetAttributes' => [
12765
                    ],
12766
                  },
12767
                  'hdlType' => 'std_logic',
12768
                  'width' => 1,
12769
                },
12770
                'constant5_op_net_x18' => {
12771
                  'attributes' => {
12772
                    'hdlNetAttributes' => [
12773
                    ],
12774
                  },
12775
                  'hdlType' => 'std_logic',
12776
                  'width' => 1,
12777
                },
12778
                'constant5_op_net_x19' => {
12779
                  'attributes' => {
12780
                    'hdlNetAttributes' => [
12781
                    ],
12782
                  },
12783
                  'hdlType' => 'std_logic',
12784
                  'width' => 1,
12785
                },
12786
                'constant5_op_net_x2' => {
12787
                  'attributes' => {
12788
                    'hdlNetAttributes' => [
12789
                    ],
12790
                  },
12791
                  'hdlType' => 'std_logic',
12792
                  'width' => 1,
12793
                },
12794
                'constant5_op_net_x3' => {
12795
                  'attributes' => {
12796
                    'hdlNetAttributes' => [
12797
                    ],
12798
                  },
12799
                  'hdlType' => 'std_logic',
12800
                  'width' => 1,
12801
                },
12802
                'constant5_op_net_x4' => {
12803
                  'attributes' => {
12804
                    'hdlNetAttributes' => [
12805
                    ],
12806
                  },
12807
                  'hdlType' => 'std_logic',
12808
                  'width' => 1,
12809
                },
12810
                'constant5_op_net_x5' => {
12811
                  'attributes' => {
12812
                    'hdlNetAttributes' => [
12813
                    ],
12814
                  },
12815
                  'hdlType' => 'std_logic',
12816
                  'width' => 1,
12817
                },
12818
                'constant5_op_net_x6' => {
12819
                  'attributes' => {
12820
                    'hdlNetAttributes' => [
12821
                    ],
12822
                  },
12823
                  'hdlType' => 'std_logic',
12824
                  'width' => 1,
12825
                },
12826
                'constant5_op_net_x7' => {
12827
                  'attributes' => {
12828
                    'hdlNetAttributes' => [
12829
                    ],
12830
                  },
12831
                  'hdlType' => 'std_logic',
12832
                  'width' => 1,
12833
                },
12834
                'constant5_op_net_x8' => {
12835
                  'attributes' => {
12836
                    'hdlNetAttributes' => [
12837
                    ],
12838
                  },
12839
                  'hdlType' => 'std_logic',
12840
                  'width' => 1,
12841
                },
12842
                'constant5_op_net_x9' => {
12843
                  'attributes' => {
12844
                    'hdlNetAttributes' => [
12845
                    ],
12846
                  },
12847
                  'hdlType' => 'std_logic',
12848
                  'width' => 1,
12849
                },
12850
                'debug_in_1i_net' => {
12851
                  'attributes' => {
12852
                    'hdlNetAttributes' => [
12853
                    ],
12854
                  },
12855
                  'hdlType' => 'std_logic_vector(31 downto 0)',
12856
                  'width' => 32,
12857
                },
12858
                'debug_in_1i_net_x0' => {
12859
                  'attributes' => {
12860
                    'hdlNetAttributes' => [
12861
                    ],
12862
                  },
12863
                  'hdlType' => 'std_logic_vector(31 downto 0)',
12864
                  'width' => 32,
12865
                },
12866
                'debug_in_2i_net' => {
12867
                  'attributes' => {
12868
                    'hdlNetAttributes' => [
12869
                    ],
12870
                  },
12871
                  'hdlType' => 'std_logic_vector(31 downto 0)',
12872
                  'width' => 32,
12873
                },
12874
                'debug_in_2i_net_x0' => {
12875
                  'attributes' => {
12876
                    'hdlNetAttributes' => [
12877
                    ],
12878
                  },
12879
                  'hdlType' => 'std_logic_vector(31 downto 0)',
12880
                  'width' => 32,
12881
                },
12882
                'debug_in_3i_net' => {
12883
                  'attributes' => {
12884
                    'hdlNetAttributes' => [
12885
                    ],
12886
                  },
12887
                  'hdlType' => 'std_logic_vector(31 downto 0)',
12888
                  'width' => 32,
12889
                },
12890
                'debug_in_3i_net_x0' => {
12891
                  'attributes' => {
12892
                    'hdlNetAttributes' => [
12893
                    ],
12894
                  },
12895
                  'hdlType' => 'std_logic_vector(31 downto 0)',
12896
                  'width' => 32,
12897
                },
12898
                'debug_in_4i_net' => {
12899
                  'attributes' => {
12900
                    'hdlNetAttributes' => [
12901
                    ],
12902
                  },
12903
                  'hdlType' => 'std_logic_vector(31 downto 0)',
12904
                  'width' => 32,
12905
                },
12906
                'debug_in_4i_net_x0' => {
12907
                  'attributes' => {
12908
                    'hdlNetAttributes' => [
12909
                    ],
12910
                  },
12911
                  'hdlType' => 'std_logic_vector(31 downto 0)',
12912
                  'width' => 32,
12913
                },
12914
                'dma_host2board_busy_net' => {
12915
                  'attributes' => {
12916
                    'hdlNetAttributes' => [
12917
                    ],
12918
                  },
12919
                  'hdlType' => 'std_logic',
12920
                  'width' => 1,
12921
                },
12922
                'dma_host2board_busy_net_x0' => {
12923
                  'attributes' => {
12924
                    'hdlNetAttributes' => [
12925
                    ],
12926
                  },
12927
                  'hdlType' => 'std_logic',
12928
                  'width' => 1,
12929
                },
12930
                'dma_host2board_done_net' => {
12931
                  'attributes' => {
12932
                    'hdlNetAttributes' => [
12933
                    ],
12934
                  },
12935
                  'hdlType' => 'std_logic',
12936
                  'width' => 1,
12937
                },
12938
                'dma_host2board_done_net_x0' => {
12939
                  'attributes' => {
12940
                    'hdlNetAttributes' => [
12941
                    ],
12942
                  },
12943
                  'hdlType' => 'std_logic',
12944
                  'width' => 1,
12945
                },
12946
                'from_register10_data_out_net' => {
12947
                  'attributes' => {
12948
                    'hdlNetAttributes' => [
12949
                    ],
12950
                  },
12951
                  'hdlType' => 'std_logic_vector(31 downto 0)',
12952
                  'width' => 32,
12953
                },
12954
                'from_register10_data_out_net_x0' => {
12955
                  'attributes' => {
12956
                    'hdlNetAttributes' => [
12957
                    ],
12958
                  },
12959
                  'hdlType' => 'std_logic_vector(31 downto 0)',
12960
                  'width' => 32,
12961
                },
12962
                'from_register11_data_out_net' => {
12963
                  'attributes' => {
12964
                    'hdlNetAttributes' => [
12965
                    ],
12966
                  },
12967
                  'hdlType' => 'std_logic_vector(31 downto 0)',
12968
                  'width' => 32,
12969
                },
12970
                'from_register11_data_out_net_x0' => {
12971
                  'attributes' => {
12972
                    'hdlNetAttributes' => [
12973
                    ],
12974
                  },
12975
                  'hdlType' => 'std_logic_vector(31 downto 0)',
12976
                  'width' => 32,
12977
                },
12978
                'from_register12_data_out_net' => {
12979
                  'attributes' => {
12980
                    'hdlNetAttributes' => [
12981
                    ],
12982
                  },
12983
                  'hdlType' => 'std_logic',
12984
                  'width' => 1,
12985
                },
12986
                'from_register12_data_out_net_x0' => {
12987
                  'attributes' => {
12988
                    'hdlNetAttributes' => [
12989
                    ],
12990
                  },
12991
                  'hdlType' => 'std_logic',
12992
                  'width' => 1,
12993
                },
12994
                'from_register13_data_out_net' => {
12995
                  'attributes' => {
12996
                    'hdlNetAttributes' => [
12997
                    ],
12998
                  },
12999
                  'hdlType' => 'std_logic_vector(31 downto 0)',
13000
                  'width' => 32,
13001
                },
13002
                'from_register13_data_out_net_x0' => {
13003
                  'attributes' => {
13004
                    'hdlNetAttributes' => [
13005
                    ],
13006
                  },
13007
                  'hdlType' => 'std_logic_vector(31 downto 0)',
13008
                  'width' => 32,
13009
                },
13010
                'from_register14_data_out_net' => {
13011
                  'attributes' => {
13012
                    'hdlNetAttributes' => [
13013
                    ],
13014
                  },
13015
                  'hdlType' => 'std_logic',
13016
                  'width' => 1,
13017
                },
13018
                'from_register14_data_out_net_x0' => {
13019
                  'attributes' => {
13020
                    'hdlNetAttributes' => [
13021
                    ],
13022
                  },
13023
                  'hdlType' => 'std_logic',
13024
                  'width' => 1,
13025
                },
13026
                'from_register15_data_out_net' => {
13027
                  'attributes' => {
13028
                    'hdlNetAttributes' => [
13029
                    ],
13030
                  },
13031
                  'hdlType' => 'std_logic_vector(31 downto 0)',
13032
                  'width' => 32,
13033
                },
13034
                'from_register15_data_out_net_x0' => {
13035
                  'attributes' => {
13036
                    'hdlNetAttributes' => [
13037
                    ],
13038
                  },
13039
                  'hdlType' => 'std_logic_vector(31 downto 0)',
13040
                  'width' => 32,
13041
                },
13042
                'from_register16_data_out_net' => {
13043
                  'attributes' => {
13044
                    'hdlNetAttributes' => [
13045
                    ],
13046
                  },
13047
                  'hdlType' => 'std_logic',
13048
                  'width' => 1,
13049
                },
13050
                'from_register16_data_out_net_x0' => {
13051
                  'attributes' => {
13052
                    'hdlNetAttributes' => [
13053
                    ],
13054
                  },
13055
                  'hdlType' => 'std_logic',
13056
                  'width' => 1,
13057
                },
13058
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13059
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13060
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13061
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13062
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13063
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13064
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13065
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13066
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13067
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13068
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13069
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13070
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13071
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13072
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13073
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13074
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13075
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13076
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13077
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13078
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13079
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13080
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13081
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13082
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13083
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13084
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13085
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13086
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13087
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13088
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13089
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13090
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13091
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13092
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13093
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13094
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13095
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13096
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13097
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13098
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13099
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13100
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13101
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13102
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13103
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13104
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13105
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13106
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13107
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13108
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13109
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13110
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13111
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13112
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13113
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13114
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13115
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13116
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13117
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13118
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13119
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13120
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13121
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13122
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13123
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13124
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13125
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13126
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13127
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13128
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13129
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13130
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13131
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13132
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13133
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13134
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13135
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13136
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13137
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13138
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13139
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13140
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13141
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13142
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13143
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13144
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13145
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13146
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13147
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13148
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13149
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13150
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13151
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13152
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13153
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13154
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13155
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13156
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13157
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13158
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13159
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13160
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13161
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13162
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13163
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13164
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13165
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13166
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13167
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13168
                  'width' => 1,
13169
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13170
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13171
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13172
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13173
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13174
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13175
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13176
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13177
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13178
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13179
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13180
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13181
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13182
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13183
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13184
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13185
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13186
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13187
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13188
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13189
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13190
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13191
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13192
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13193
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13194
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13195
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13196
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13197
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13198
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13199
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13200
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13201
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13202
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13203
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13204
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13205
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13206
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13207
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13208
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13209
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13210
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13211
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13212
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13213
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13214
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13215
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13216
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13217
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13218
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13219
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13220
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13221
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13222
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13223
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13224
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13225
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13226
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13227
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13228
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13229
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13230
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13231
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13232
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13233
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13234
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13235
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13236
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13237
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13238
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13239
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13240
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13241
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13242
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13243
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13244
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13245
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13246
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13247
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13248
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13249
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13250
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13251
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13252
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13253
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13254
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13255
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13256
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13257
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13258
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13259
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13260
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13261
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13262
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13263
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13264
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13265
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13266
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13267
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13268
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13269
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13270
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13271
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13272
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13273
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13274
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13275
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13276
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13277
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13278
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13279
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13280
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13281
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13282
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13283
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13284
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13285
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13286
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13287
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13288
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13289
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13290
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13291
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13292
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13293
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13294
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13295
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13296
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13297
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13298
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13299
                  'attributes' => {
13300
                    'hdlNetAttributes' => [
13301
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13302
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13303
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13304
                  'width' => 1,
13305
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13306
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13307
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13308
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13309
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13310
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13311
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13312
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13313
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13314
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13315
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13316
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13317
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13318
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13319
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13320
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13321
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13322
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13323
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13324
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13325
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13326
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13327
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13328
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13329
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13330
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13331
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13332
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13333
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13334
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13335
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13336
                  'width' => 1,
13337
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13338
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13339
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13340
                    'hdlNetAttributes' => [
13341
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13342
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13343
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13344
                  'width' => 1,
13345
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13346
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13347
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13348
                    'hdlNetAttributes' => [
13349
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13350
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13351
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13352
                  'width' => 32,
13353
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13354
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13355
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13356
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13357
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13358
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13359
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13360
                  'width' => 32,
13361
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13362
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13363
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13364
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13365
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13366
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13367
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13368
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13369
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13370
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13371
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13372
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13373
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13374
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13375
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13376
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13377
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13378
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13379
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13380
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13381
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13382
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13383
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13384
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13385
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13386
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13387
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13388
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13389
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13390
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13391
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13392
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13393
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13394
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13395
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13396
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13397
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13398
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13399
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13400
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13401
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13402
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13403
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13404
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13405
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13406
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13407
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13408
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13409
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13410
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13411
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13412
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13413
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13414
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13415
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13416
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13417
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13418
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13419
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13420
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13421
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13422
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13423
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13424
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13425
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13426
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13427
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13428
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13429
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13430
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13431
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13432
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13433
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13434
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13435
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13436
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13437
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13438
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13439
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13440
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13441
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13442
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13443
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13444
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13445
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13446
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13447
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13448
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13449
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13450
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13451
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13452
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13453
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13454
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13455
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13456
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13457
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13458
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13459
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13460
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13461
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13462
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13463
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13464
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13465
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13466
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13467
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13468
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13469
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13470
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13471
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13472
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13473
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13474
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13475
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13476
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13477
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13478
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13479
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13480
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13481
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13482
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13483
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13484
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13485
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13486
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13487
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13488
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13489
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13490
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13491
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13492
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13493
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13494
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13495
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13496
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13497
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13498
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13499
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13500
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13501
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13502
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13503
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13504
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13505
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13506
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13507
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13508
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13509
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13510
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13511
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13512
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13513
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13514
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13515
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13516
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13517
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13518
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13519
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13520
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13521
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13522
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13523
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13524
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13525
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13526
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13527
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13528
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13529
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13530
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13531
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13532
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13533
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13534
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13535
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13536
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13537
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13538
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13539
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13540
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13541
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13542
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13543
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13544
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13545
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13546
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13547
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13548
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13549
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13550
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13551
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13552
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13553
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13554
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13555
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13556
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13557
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13558
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13559
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13560
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13561
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13562
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13563
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13564
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13565
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13566
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13567
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13568
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13569
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13570
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13571
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13572
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13573
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13574
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13575
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13576
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13577
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13578
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13579
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13580
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13581
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13582
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13583
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13584
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13585
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13586
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13587
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13588
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13589
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13590
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13591
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13592
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13593
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13594
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13595
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13596
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13597
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13598
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13599
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13600
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13601
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13602
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13603
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13604
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13605
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13606
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13607
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13608
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13609
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13610
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13611
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13612
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13613
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13614
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13615
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13616
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13617
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13618
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13619
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13620
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13621
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13622
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13623
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13624
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13625
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13626
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13627
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13628
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13629
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13630
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13631
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13632
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13633
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13634
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13635
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13636
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13637
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13638
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13639
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13640
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13641
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13642
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13643
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13644
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13645
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13646
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13647
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13648
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13649
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13650
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13651
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13652
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13653
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13654
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13655
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13656
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13657
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13658
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13659
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13660
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13661
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13662
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13663
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13664
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13665
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13666
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13667
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13668
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13669
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13670
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13671
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13672
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13673
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13674
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13675
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13676
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13677
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13678
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13730
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13818
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13826
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13850
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13875
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13877
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13890
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13894
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13895
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13898
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13899
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13900
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13901
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13904
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13905
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13906
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13907
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13909
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13910
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13911
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13912
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13913
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13914
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13915
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13916
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13917
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13918
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13919
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13920
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13921
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13922
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13923
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13925
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13926
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13927
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13928
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13929
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13930
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13931
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13932
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13933
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13934
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13935
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13936
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13937
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13938
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13939
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13940
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13941
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13942
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13943
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13945
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13946
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13947
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13948
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13949
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13950
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13951
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13952
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13953
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13954
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13955
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13957
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13958
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13959
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13960
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13961
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13962
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13963
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13964
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13965
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13966
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13967
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13968
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13969
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13970
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13971
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13972
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13973
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13974
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13975
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13976
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13977
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13978
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13979
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13980
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13981
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13982
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13983
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13985
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13986
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13987
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13989
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13990
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13991
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13993
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13994
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13995
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13998
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13999
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14000
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14001
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14003
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14004
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14005
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14006
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14007
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14008
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14009
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14010
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14011
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14012
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14013
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14014
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14015
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14016
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14017
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14018
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14019
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14020
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14021
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14022
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14023
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14024
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14025
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14026
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14027
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14028
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14029
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14030
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14031
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14032
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14033
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14034
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14035
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14036
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14037
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14038
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14039
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14040
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14041
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14042
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14043
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14044
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14045
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14046
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14047
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14049
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14050
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14051
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14052
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14054
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14055
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14057
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14058
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14059
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14060
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14061
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14062
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14063
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14064
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14065
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14066
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14067
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14068
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14069
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14070
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14071
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14072
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14073
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14074
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14075
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14076
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14077
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14078
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14079
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14080
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14081
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14082
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14083
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14084
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14085
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14086
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14087
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14089
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14090
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14091
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14092
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14093
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14094
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14095
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14096
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14097
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14098
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14099
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14100
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14101
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14102
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14103
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14104
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14105
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14106
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14107
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14108
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14109
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14110
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14111
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14112
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14113
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14114
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14115
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14116
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14117
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14118
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14119
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14120
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14121
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14122
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14123
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14124
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14125
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14126
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14127
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14128
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14129
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14130
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14131
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14132
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14133
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14134
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14135
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14136
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14137
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14138
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14139
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14140
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14141
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14142
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14143
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14144
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14145
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14146
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14147
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14148
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14149
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14150
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14151
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14152
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14153
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14154
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14155
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14156
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14157
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14158
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14159
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14160
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14161
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14162
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14163
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14164
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14165
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14166
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14175
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14176
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14177
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14178
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14179
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14180
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14181
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14182
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14183
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14184
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14186
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14187
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14188
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14189
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14190
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14191
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14192
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14193
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14194
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14195
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14196
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14197
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14198
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14199
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14200
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14201
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14202
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14203
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14204
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14205
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14206
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14207
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14208
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14209
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14210
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14211
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14212
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14213
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14214
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14215
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14216
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14217
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14218
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14219
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14220
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14221
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14222
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14223
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14224
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14225
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14226
                    'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/debug_in_4i/debug_in_4i',
14227
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14228
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14229
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14230
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14231
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14232
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14233
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14234
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14235
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14236
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14237
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14238
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14239
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14240
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14241
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14242
                    'period' => 1,
14243
                    'port_id' => 0,
14244
                    'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/DMA_Host2Board_Busy/DMA_Host2Board_Busy',
14245
                    'source_block' => 'PCIe_UserLogic_00/INOUT_LOGIC/DMA_Host2Board_Busy',
14246
                    'timingConstraint' => 'none',
14247
                    'type' => 'UFix_1_0',
14248
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14249
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14250
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14251
                  'width' => 1,
14252
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14253
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14254
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14255
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14256
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14257
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14258
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14259
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14260
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14261
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14262
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14263
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14264
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14265
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14266
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14267
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14268
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14269
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14270
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14271
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14272
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14273
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14274
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14275
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14276
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14277
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14278
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14279
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14280
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14281
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14282
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14283
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14284
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14285
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14286
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14287
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14288
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14289
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14290
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14291
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14292
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14293
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14294
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14295
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14296
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14297
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14298
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14299
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14300
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14301
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14302
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14303
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14304
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14305
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14306
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14307
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14308
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14309
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14310
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14311
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14312
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14313
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14314
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14315
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14316
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14317
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14318
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14319
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14320
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14321
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14322
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14323
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14324
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14325
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14326
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14327
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14328
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14329
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14330
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14331
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14332
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14333
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14334
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14335
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14336
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14337
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14338
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14339
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14340
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14341
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14342
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14343
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14344
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14345
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14346
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14347
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14348
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14349
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14350
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14351
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14352
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14353
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14354
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14355
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14356
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14357
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14358
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14359
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14360
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14361
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14362
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14363
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14364
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14365
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14366
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14367
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14368
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14369
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14370
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14371
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14372
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14373
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14374
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14375
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14376
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14377
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14378
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14379
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14380
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14381
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14382
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14383
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14384
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14385
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14386
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14387
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14388
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14389
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14390
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14391
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14392
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14393
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14394
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14395
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14396
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14397
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14398
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14399
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14400
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14401
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14402
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14403
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14404
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14405
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14406
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14407
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14408
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14409
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14410
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14411
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14412
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14413
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14414
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14415
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14416
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14417
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14418
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14419
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14420
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14421
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14422
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14423
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14424
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14425
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14426
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14427
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14428
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14429
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14430
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14431
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14432
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14433
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14434
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14435
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14436
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14437
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14438
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14439
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14440
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14441
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14442
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14443
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14444
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14445
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14446
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14447
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14448
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14449
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14450
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14451
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14452
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14453
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14454
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14455
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14456
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14457
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14458
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14459
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14460
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14461
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14462
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14463
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14464
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14465
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14466
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14467
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14468
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14469
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14470
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14471
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14472
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14473
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14474
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14475
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14476
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14477
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14478
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14479
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14480
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14481
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14482
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14483
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14484
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14485
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14486
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14487
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14488
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14489
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14490
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14491
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14492
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14493
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14494
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14495
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14496
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14497
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14498
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14499
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14500
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14501
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14502
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14503
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14504
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14505
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14506
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14507
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14508
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14509
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14510
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14511
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14512
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14513
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14514
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14515
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14516
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14517
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14518
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14519
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14520
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14521
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14522
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14523
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14524
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14525
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14526
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14527
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14528
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14529
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14530
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14531
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14532
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14533
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14534
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14535
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14536
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14537
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14538
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14539
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14540
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14541
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14542
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14543
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14544
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14545
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14546
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14547
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14548
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14549
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14550
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14551
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14552
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14553
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14554
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14555
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14556
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14557
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14558
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14559
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14560
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14561
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14562
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14563
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14564
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14565
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14566
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14567
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14568
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14569
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14570
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14571
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14572
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14573
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14574
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14575
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14576
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14577
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14578
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14579
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14580
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14581
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14582
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14583
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14584
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14585
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14586
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14587
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14588
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14589
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14590
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14591
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14592
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14593
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14594
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14595
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14596
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14597
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14598
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14599
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14600
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14601
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14602
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14603
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14604
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14605
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14606
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14607
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14608
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14609
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14610
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14611
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14612
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14613
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14614
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14615
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14616
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14617
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14618
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14619
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14620
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14621
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14622
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14623
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14624
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14625
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14626
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14627
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14628
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14629
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14630
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14631
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14632
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14633
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14634
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14635
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14636
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14637
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14638
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14639
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14640
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14641
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14642
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14643
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14644
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14645
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14646
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14647
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14648
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14649
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14650
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14651
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14652
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14653
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14654
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14655
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14656
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14657
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14658
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14659
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14660
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14661
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14662
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14663
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14664
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14665
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14666
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14667
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14668
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14669
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14670
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14671
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14672
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14673
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14674
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14675
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14676
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14677
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14678
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14679
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14680
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14681
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14682
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14683
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14684
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14685
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14686
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14687
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14688
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14689
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14690
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14691
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14692
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14693
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14694
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14695
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14696
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14697
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14698
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14699
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14700
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14701
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14702
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14703
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14704
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14705
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14706
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14707
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14708
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14709
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14710
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14711
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14712
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14713
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14714
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14715
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14716
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14717
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14718
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14719
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14720
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14721
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14722
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14723
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14724
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14725
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14726
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14727
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14728
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14729
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14730
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14731
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14732
                  'hdlType' => 'std_logic',
14733
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14734
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14735
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14736
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14737
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14738
                    'inputFile' => 'pcie_userlogic_00_inout_logic_reg02_rd.dat',
14739
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14740
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14741
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14742
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14743
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14744
                    'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/reg02_rd/reg02_rd',
14745
                    'source_block' => 'PCIe_UserLogic_00/INOUT_LOGIC/reg02_rd',
14746
                    'timingConstraint' => 'none',
14747
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14748
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14749
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14750
                  'hdlType' => 'std_logic_vector(31 downto 0)',
14751
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14752
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14753
                'reg02_rv' => {
14754
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14755
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14756
                    'inputFile' => 'pcie_userlogic_00_inout_logic_reg02_rv.dat',
14757
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14758
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14759
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14760
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14761
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14762
                    'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/reg02_rv/reg02_rv',
14763
                    'source_block' => 'PCIe_UserLogic_00/INOUT_LOGIC/reg02_rv',
14764
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14765
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14766
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14767
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14768
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14769
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14770
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14771
                'reg02_td' => {
14772
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14773
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14774
                    'inputFile' => 'pcie_userlogic_00_inout_logic_reg02_td.dat',
14775
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14776
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14777
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14778
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14779
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14780
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14781
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14782
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14783
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14784
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14785
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14786
                  'hdlType' => 'std_logic_vector(31 downto 0)',
14787
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14788
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14789
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14790
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14791
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14792
                    'inputFile' => 'pcie_userlogic_00_inout_logic_reg02_tv.dat',
14793
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14794
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14795
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14796
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14797
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14798
                    'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/reg02_tv/reg02_tv',
14799
                    'source_block' => 'PCIe_UserLogic_00/INOUT_LOGIC/reg02_tv',
14800
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14801
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14802
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14803
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14804
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14805
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14806
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14807
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14808
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14809
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14810
                    'inputFile' => 'pcie_userlogic_00_inout_logic_reg03_rd.dat',
14811
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14812
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14813
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14814
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14815
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14816
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14817
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14818
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14819
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14820
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14821
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14822
                  'hdlType' => 'std_logic_vector(31 downto 0)',
14823
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14824
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14825
                'reg03_rv' => {
14826
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14827
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14828
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14829
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14830
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14831
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14832
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14833
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14834
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14835
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14836
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14837
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14838
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14839
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14840
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14841
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14842
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14843
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14844
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14845
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14846
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14847
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14848
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14849
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14850
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14851
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14852
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14853
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14854
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14855
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14856
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14857
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14858
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14859
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14860
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14861
                'reg03_tv' => {
14862
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14863
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14864
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14865
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14866
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14867
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14868
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14869
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14870
                    'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/reg03_tv/reg03_tv',
14871
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14872
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14873
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14874
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14875
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14876
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14877
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14878
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14879
                'reg04_rd' => {
14880
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14881
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14882
                    'inputFile' => 'pcie_userlogic_00_inout_logic_reg04_rd.dat',
14883
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14884
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14885
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14886
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14887
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14888
                    'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/reg04_rd/reg04_rd',
14889
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14890
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14891
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14892
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14893
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14894
                  'hdlType' => 'std_logic_vector(31 downto 0)',
14895
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14896
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14897
                'reg04_rv' => {
14898
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14899
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14900
                    'inputFile' => 'pcie_userlogic_00_inout_logic_reg04_rv.dat',
14901
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14902
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14903
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14904
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14905
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14906
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14907
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14908
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14909
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14910
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14911
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14912
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14913
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14914
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14915
                'reg04_td' => {
14916
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14917
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14918
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14919
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14920
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14921
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14922
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14923
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14924
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14925
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14926
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14927
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14928
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14929
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14930
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14931
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14932
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14933
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14934
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14935
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14936
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14937
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14938
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14939
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14940
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14941
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14942
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14943
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14944
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14945
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14946
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14947
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14948
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14949
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14950
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14951
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14952
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14953
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14954
                    'inputFile' => 'pcie_userlogic_00_inout_logic_reg05_rd.dat',
14955
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14956
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14957
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14958
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14959
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14960
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14961
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14962
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14963
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14964
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14965
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14966
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14967
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14968
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14969
                'reg05_rv' => {
14970
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14971
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14972
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14973
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14974
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14975
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14976
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14977
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14978
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14979
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14980
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14981
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14982
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14983
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14984
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14985
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14986
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14987
                'reg05_td' => {
14988
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14989
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14990
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14991
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14992
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14993
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14994
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14995
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14996
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14997
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14998
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14999
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15000
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15001
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15002
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15003
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15004
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15005
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15006
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15007
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15008
                    'inputFile' => 'pcie_userlogic_00_inout_logic_reg05_tv.dat',
15009
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15010
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15011
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15012
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15013
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15014
                    'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/reg05_tv/reg05_tv',
15015
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15016
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15017
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15018
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15019
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15020
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15021
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15022
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15023
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15024
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15025
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15026
                    'inputFile' => 'pcie_userlogic_00_inout_logic_reg06_rd.dat',
15027
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15028
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15029
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15030
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15031
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15032
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15033
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15034
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15035
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15036
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15037
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15038
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15039
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15040
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15041
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15042
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15043
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15044
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15045
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15046
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15047
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15048
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15049
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15050
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15051
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15052
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15053
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15054
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15055
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15056
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15057
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15058
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15059
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15060
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15061
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15062
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15063
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15064
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15065
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15066
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15067
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15068
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15069
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15070
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15071
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15072
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15073
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15074
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15075
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15076
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15077
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15078
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15079
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15080
                    'inputFile' => 'pcie_userlogic_00_inout_logic_reg06_tv.dat',
15081
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15082
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15083
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15084
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15085
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15086
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15087
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15088
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15089
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15090
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15091
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15092
                  'hdlType' => 'std_logic',
15093
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15094
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15095
                'reg07_rd' => {
15096
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15097
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15098
                    'inputFile' => 'pcie_userlogic_00_inout_logic_reg07_rd.dat',
15099
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15100
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15101
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15102
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15103
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15104
                    'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/reg07_rd/reg07_rd',
15105
                    'source_block' => 'PCIe_UserLogic_00/INOUT_LOGIC/reg07_rd',
15106
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15107
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15108
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15109
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15110
                  'hdlType' => 'std_logic_vector(31 downto 0)',
15111
                  'width' => 32,
15112
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15113
                'reg07_rv' => {
15114
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15115
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15116
                    'inputFile' => 'pcie_userlogic_00_inout_logic_reg07_rv.dat',
15117
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15118
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15119
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15120
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15121
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15122
                    'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/reg07_rv/reg07_rv',
15123
                    'source_block' => 'PCIe_UserLogic_00/INOUT_LOGIC/reg07_rv',
15124
                    'timingConstraint' => 'none',
15125
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15126
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15127
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15128
                  'hdlType' => 'std_logic',
15129
                  'width' => 1,
15130
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15131
                'reg07_td' => {
15132
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15133
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15134
                    'inputFile' => 'pcie_userlogic_00_inout_logic_reg07_td.dat',
15135
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15136
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15137
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15138
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15139
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15140
                    'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/reg07_td/reg07_td',
15141
                    'source_block' => 'PCIe_UserLogic_00/INOUT_LOGIC/reg07_td',
15142
                    'timingConstraint' => 'none',
15143
                    'type' => 'UFix_32_0',
15144
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15145
                  'direction' => 'in',
15146
                  'hdlType' => 'std_logic_vector(31 downto 0)',
15147
                  'width' => 32,
15148
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15149
                'reg07_tv' => {
15150
                  'attributes' => {
15151
                    'bin_pt' => 0,
15152
                    'inputFile' => 'pcie_userlogic_00_inout_logic_reg07_tv.dat',
15153
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15154
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15155
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15156
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15157
                    'port_id' => 0,
15158
                    'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/reg07_tv/reg07_tv',
15159
                    'source_block' => 'PCIe_UserLogic_00/INOUT_LOGIC/reg07_tv',
15160
                    'timingConstraint' => 'none',
15161
                    'type' => 'Bool',
15162
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15163
                  'direction' => 'in',
15164
                  'hdlType' => 'std_logic',
15165
                  'width' => 1,
15166
                },
15167
                'reg08_rd' => {
15168
                  'attributes' => {
15169
                    'bin_pt' => 0,
15170
                    'inputFile' => 'pcie_userlogic_00_inout_logic_reg08_rd.dat',
15171
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15172
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15173
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15174
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15175
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15176
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15177
                    'source_block' => 'PCIe_UserLogic_00/INOUT_LOGIC/reg08_rd',
15178
                    'timingConstraint' => 'none',
15179
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15180
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15181
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15182
                  'hdlType' => 'std_logic_vector(31 downto 0)',
15183
                  'width' => 32,
15184
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15185
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15186
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15187
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15188
                    'inputFile' => 'pcie_userlogic_00_inout_logic_reg08_rv.dat',
15189
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15190
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15191
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15192
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15193
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15194
                    'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/reg08_rv/reg08_rv',
15195
                    'source_block' => 'PCIe_UserLogic_00/INOUT_LOGIC/reg08_rv',
15196
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15197
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15198
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15199
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15200
                  'hdlType' => 'std_logic',
15201
                  'width' => 1,
15202
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15203
                'reg08_td' => {
15204
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15205
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15206
                    'inputFile' => 'pcie_userlogic_00_inout_logic_reg08_td.dat',
15207
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15208
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15209
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15210
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15211
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15212
                    'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/reg08_td/reg08_td',
15213
                    'source_block' => 'PCIe_UserLogic_00/INOUT_LOGIC/reg08_td',
15214
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15215
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15216
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15217
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15218
                  'hdlType' => 'std_logic_vector(31 downto 0)',
15219
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15220
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15221
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15222
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15223
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15224
                    'inputFile' => 'pcie_userlogic_00_inout_logic_reg08_tv.dat',
15225
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15226
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15227
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15228
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15229
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15230
                    'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/reg08_tv/reg08_tv',
15231
                    'source_block' => 'PCIe_UserLogic_00/INOUT_LOGIC/reg08_tv',
15232
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15233
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15234
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15235
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15236
                  'hdlType' => 'std_logic',
15237
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15238
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15239
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15240
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15241
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15242
                    'inputFile' => 'pcie_userlogic_00_inout_logic_reg09_rd.dat',
15243
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15244
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15245
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15246
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15247
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15248
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15249
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15250
                    'timingConstraint' => 'none',
15251
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15252
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15253
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15254
                  'hdlType' => 'std_logic_vector(31 downto 0)',
15255
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15256
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15257
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15258
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15259
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15260
                    'inputFile' => 'pcie_userlogic_00_inout_logic_reg09_rv.dat',
15261
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15262
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15263
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15264
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15265
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15266
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15267
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15268
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15269
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15270
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15271
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15272
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15273
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15274
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15275
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15276
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15277
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15278
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15279
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15280
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15281
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15282
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15283
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15284
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15285
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15286
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15287
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15288
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15289
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15290
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15291
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15292
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15293
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15294
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15295
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15296
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15297
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15298
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15299
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15300
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15301
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15302
                    'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/reg09_tv/reg09_tv',
15303
                    'source_block' => 'PCIe_UserLogic_00/INOUT_LOGIC/reg09_tv',
15304
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15305
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15306
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15307
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15308
                  'hdlType' => 'std_logic',
15309
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15310
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15311
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15312
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15313
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15314
                    'inputFile' => 'pcie_userlogic_00_inout_logic_reg10_rd.dat',
15315
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15316
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15317
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15318
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15319
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15320
                    'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/reg10_rd/reg10_rd',
15321
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15322
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15323
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15324
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15325
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15326
                  'hdlType' => 'std_logic_vector(31 downto 0)',
15327
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15328
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15329
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15330
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15331
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15332
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15333
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15334
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15335
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15336
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15337
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15338
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15339
                    'source_block' => 'PCIe_UserLogic_00/INOUT_LOGIC/reg10_rv',
15340
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15341
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15342
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15343
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15344
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15345
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15346
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15347
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15348
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15349
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15350
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15351
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15352
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15353
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15354
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15355
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15356
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15357
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15358
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15359
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15360
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15361
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15362
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15363
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15364
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15365
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15366
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15367
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15368
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15369
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15370
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15371
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15372
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15373
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15374
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15375
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15376
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15377
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15378
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15379
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15380
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15381
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15382
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15383
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15384
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15385
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15386
                    'inputFile' => 'pcie_userlogic_00_inout_logic_reg11_rd.dat',
15387
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15388
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15389
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15390
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15391
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15392
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15393
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15394
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15395
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15396
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15397
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15398
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15399
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15400
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15401
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15402
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15403
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15404
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15405
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15406
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15407
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15408
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15409
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15410
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15411
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15412
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15413
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15414
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15415
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15416
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15417
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15418
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15419
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15420
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15421
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15422
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15423
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15424
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15425
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15426
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15427
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15428
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15429
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15430
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15431
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15432
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15433
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15434
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15435
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15436
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15437
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15438
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15439
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15440
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15441
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15442
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15443
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15444
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15445
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15446
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15447
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15448
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15449
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15450
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15451
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15452
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15453
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15454
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15455
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15456
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15457
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15458
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15459
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15460
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15461
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15462
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15463
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15464
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15465
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15466
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15467
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15468
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15469
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15470
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15471
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15472
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15473
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15474
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15475
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15476
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15477
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15478
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15479
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15480
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15481
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15482
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15483
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15484
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15485
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15486
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15487
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15488
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15489
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15490
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15491
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15492
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15493
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15494
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15495
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15496
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15497
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15498
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15499
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15500
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15501
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15502
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15503
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15504
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15505
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15506
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15507
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15508
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15509
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15510
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15511
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15512
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15513
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15514
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15515
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15516
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15517
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15518
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15519
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15520
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15521
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15522
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15523
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15524
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15525
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15526
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15527
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15528
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15529
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15530
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15531
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15532
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15533
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15534
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15535
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15536
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15537
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15538
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15539
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15540
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15541
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15542
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15543
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15544
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15545
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15546
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15547
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15548
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15549
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15550
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15551
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15552
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15553
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15554
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15555
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15556
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15557
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15558
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15559
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15560
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15561
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15562
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15563
                'reg13_td' => {
15564
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15565
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15566
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15567
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15568
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15569
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15570
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15571
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15572
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15573
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15574
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15575
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15576
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15577
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15578
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15579
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15580
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15581
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15582
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15583
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15584
                    'inputFile' => 'pcie_userlogic_00_inout_logic_reg13_tv.dat',
15585
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15586
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15587
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15588
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15589
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15590
                    'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/reg13_tv/reg13_tv',
15591
                    'source_block' => 'PCIe_UserLogic_00/INOUT_LOGIC/reg13_tv',
15592
                    'timingConstraint' => 'none',
15593
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15594
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15595
                  'direction' => 'in',
15596
                  'hdlType' => 'std_logic',
15597
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15598
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15599
                'reg14_rd' => {
15600
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15601
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15602
                    'inputFile' => 'pcie_userlogic_00_inout_logic_reg14_rd.dat',
15603
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15604
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15605
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15606
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15607
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15608
                    'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/reg14_rd/reg14_rd',
15609
                    'source_block' => 'PCIe_UserLogic_00/INOUT_LOGIC/reg14_rd',
15610
                    'timingConstraint' => 'none',
15611
                    'type' => 'UFix_32_0',
15612
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15613
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15614
                  'hdlType' => 'std_logic_vector(31 downto 0)',
15615
                  'width' => 32,
15616
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15617
                'reg14_rv' => {
15618
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15619
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15620
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15699
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15712
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15750
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15755
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15760
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15764
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15768
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15775
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15780
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15781
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15786
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15789
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15790
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15795
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15819
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15822
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15831
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15832
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15836
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15837
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15839
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15850
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15863
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15864
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15877
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15890
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15904
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15905
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15915
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15916
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15918
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15919
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15920
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15932
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15935
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15936
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15937
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15939
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15942
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15944
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15945
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15949
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15950
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15953
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15954
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15957
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15958
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15959
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15960
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15961
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15962
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15972
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15973
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15974
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15975
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15981
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15983
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15985
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15986
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15987
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15988
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15989
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15995
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15998
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15999
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16000
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16001
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16008
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16013
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16014
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16015
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16016
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16019
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16020
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16021
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16022
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16023
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16024
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16025
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16026
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16027
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16028
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16029
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16030
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16031
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16032
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16035
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16036
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16037
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16038
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16039
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16040
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16041
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16042
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16049
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16050
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16051
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16052
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16053
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16054
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16055
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16056
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16060
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16063
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16064
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16065
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16066
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16067
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16068
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16069
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16070
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                    'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/To Register14/en',
16075
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16077
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16078
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16079
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16080
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16081
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16082
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16083
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16084
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16085
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16086
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16087
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16088
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16089
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16090
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16092
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16093
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16094
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16095
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16096
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16097
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16098
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16099
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16100
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16101
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16102
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16103
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16104
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16105
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16106
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16107
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16108
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16109
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16110
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16111
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16112
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16113
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16114
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16115
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16116
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16117
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16118
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16119
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16120
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16121
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16122
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16123
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16124
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16125
                    'must_be_hdl_vector' => 1,
16126
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16127
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16128
                    'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/To Register15/data_in',
16129
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16130
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16131
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16132
                  'hdlType' => 'std_logic_vector(31 downto 0)',
16133
                  'width' => 32,
16134
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16135
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16136
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16137
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16138
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16139
                    'must_be_hdl_vector' => 1,
16140
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16141
                    'port_id' => 0,
16142
                    'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/To Register15/dout',
16143
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16144
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16145
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16146
                  'hdlType' => 'std_logic_vector(31 downto 0)',
16147
                  'width' => 32,
16148
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16149
                'to_register15_en' => {
16150
                  'attributes' => {
16151
                    'bin_pt' => 0,
16152
                    'is_floating_block' => 1,
16153
                    'must_be_hdl_vector' => 1,
16154
                    'period' => 1,
16155
                    'port_id' => 1,
16156
                    'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/To Register15/en',
16157
                    'type' => 'Bool',
16158
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16159
                  'direction' => 'out',
16160
                  'hdlType' => 'std_logic_vector(0 downto 0)',
16161
                  'width' => 1,
16162
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16163
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16164
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16165
                    'domain' => '',
16166
                    'group' => 1,
16167
                    'isCe' => 1,
16168
                    'is_floating_block' => 1,
16169
                    'period' => 1,
16170
                    'type' => 'logic',
16171
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16172
                  'direction' => 'out',
16173
                  'hdlType' => 'std_logic',
16174
                  'width' => 1,
16175
                },
16176
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16177
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16178
                    'domain' => '',
16179
                    'group' => 1,
16180
                    'isClk' => 1,
16181
                    'is_floating_block' => 1,
16182
                    'period' => 1,
16183
                    'type' => 'logic',
16184
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16185
                  'direction' => 'out',
16186
                  'hdlType' => 'std_logic',
16187
                  'width' => 1,
16188
                },
16189
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16190
                  'attributes' => {
16191
                    'domain' => '',
16192
                    'group' => 1,
16193
                    'isClr' => 1,
16194
                    'is_floating_block' => 1,
16195
                    'period' => 1,
16196
                    'type' => 'logic',
16197
                    'valid_bit_used' => 0,
16198
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16199
                  'direction' => 'out',
16200
                  'hdlType' => 'std_logic',
16201
                  'width' => 1,
16202
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16203
                'to_register16_data_in' => {
16204
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16205
                    'bin_pt' => 0,
16206
                    'is_floating_block' => 1,
16207
                    'must_be_hdl_vector' => 1,
16208
                    'period' => 1,
16209
                    'port_id' => 0,
16210
                    'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/To Register16/data_in',
16211
                    'type' => 'Bool',
16212
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16213
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16214
                  'hdlType' => 'std_logic_vector(0 downto 0)',
16215
                  'width' => 1,
16216
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16217
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16218
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16219
                    'bin_pt' => 0,
16220
                    'is_floating_block' => 1,
16221
                    'must_be_hdl_vector' => 1,
16222
                    'period' => 1,
16223
                    'port_id' => 0,
16224
                    'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/To Register16/dout',
16225
                    'type' => 'Bool',
16226
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16227
                  'direction' => 'in',
16228
                  'hdlType' => 'std_logic_vector(0 downto 0)',
16229
                  'width' => 1,
16230
                },
16231
                'to_register16_en' => {
16232
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16233
                    'bin_pt' => 0,
16234
                    'is_floating_block' => 1,
16235
                    'must_be_hdl_vector' => 1,
16236
                    'period' => 1,
16237
                    'port_id' => 1,
16238
                    'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/To Register16/en',
16239
                    'type' => 'Bool',
16240
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16241
                  'direction' => 'out',
16242
                  'hdlType' => 'std_logic_vector(0 downto 0)',
16243
                  'width' => 1,
16244
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16245
                'to_register17_ce' => {
16246
                  'attributes' => {
16247
                    'domain' => '',
16248
                    'group' => 1,
16249
                    'isCe' => 1,
16250
                    'is_floating_block' => 1,
16251
                    'period' => 1,
16252
                    'type' => 'logic',
16253
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16254
                  'direction' => 'out',
16255
                  'hdlType' => 'std_logic',
16256
                  'width' => 1,
16257
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16258
                'to_register17_clk' => {
16259
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16260
                    'domain' => '',
16261
                    'group' => 1,
16262
                    'isClk' => 1,
16263
                    'is_floating_block' => 1,
16264
                    'period' => 1,
16265
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16266
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16267
                  'direction' => 'out',
16268
                  'hdlType' => 'std_logic',
16269
                  'width' => 1,
16270
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16271
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16272
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16273
                    'domain' => '',
16274
                    'group' => 1,
16275
                    'isClr' => 1,
16276
                    'is_floating_block' => 1,
16277
                    'period' => 1,
16278
                    'type' => 'logic',
16279
                    'valid_bit_used' => 0,
16280
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16281
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16282
                  'hdlType' => 'std_logic',
16283
                  'width' => 1,
16284
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16285
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16286
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16287
                    'bin_pt' => 0,
16288
                    'is_floating_block' => 1,
16289
                    'must_be_hdl_vector' => 1,
16290
                    'period' => 1,
16291
                    'port_id' => 0,
16292
                    'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/To Register17/data_in',
16293
                    'type' => 'UFix_32_0',
16294
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16295
                  'direction' => 'out',
16296
                  'hdlType' => 'std_logic_vector(31 downto 0)',
16297
                  'width' => 32,
16298
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16299
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16300
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16301
                    'bin_pt' => 0,
16302
                    'is_floating_block' => 1,
16303
                    'must_be_hdl_vector' => 1,
16304
                    'period' => 1,
16305
                    'port_id' => 0,
16306
                    'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/To Register17/dout',
16307
                    'type' => 'UFix_32_0',
16308
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16309
                  'direction' => 'in',
16310
                  'hdlType' => 'std_logic_vector(31 downto 0)',
16311
                  'width' => 32,
16312
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16313
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16314
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16315
                    'bin_pt' => 0,
16316
                    'is_floating_block' => 1,
16317
                    'must_be_hdl_vector' => 1,
16318
                    'period' => 1,
16319
                    'port_id' => 1,
16320
                    'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/To Register17/en',
16321
                    'type' => 'Bool',
16322
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16323
                  'direction' => 'out',
16324
                  'hdlType' => 'std_logic_vector(0 downto 0)',
16325
                  'width' => 1,
16326
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16327
                'to_register18_ce' => {
16328
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16329
                    'domain' => '',
16330
                    'group' => 1,
16331
                    'isCe' => 1,
16332
                    'is_floating_block' => 1,
16333
                    'period' => 1,
16334
                    'type' => 'logic',
16335
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16336
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16337
                  'hdlType' => 'std_logic',
16338
                  'width' => 1,
16339
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16340
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16341
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16342
                    'domain' => '',
16343
                    'group' => 1,
16344
                    'isClk' => 1,
16345
                    'is_floating_block' => 1,
16346
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16347
                    'type' => 'logic',
16348
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16349
                  'direction' => 'out',
16350
                  'hdlType' => 'std_logic',
16351
                  'width' => 1,
16352
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16353
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16354
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16355
                    'domain' => '',
16356
                    'group' => 1,
16357
                    'isClr' => 1,
16358
                    'is_floating_block' => 1,
16359
                    'period' => 1,
16360
                    'type' => 'logic',
16361
                    'valid_bit_used' => 0,
16362
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16363
                  'direction' => 'out',
16364
                  'hdlType' => 'std_logic',
16365
                  'width' => 1,
16366
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16367
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16368
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16369
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16370
                    'is_floating_block' => 1,
16371
                    'must_be_hdl_vector' => 1,
16372
                    'period' => 1,
16373
                    'port_id' => 0,
16374
                    'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/To Register18/data_in',
16375
                    'type' => 'UFix_1_0',
16376
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16377
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16378
                  'hdlType' => 'std_logic_vector(0 downto 0)',
16379
                  'width' => 1,
16380
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16381
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16382
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16383
                    'bin_pt' => 0,
16384
                    'is_floating_block' => 1,
16385
                    'must_be_hdl_vector' => 1,
16386
                    'period' => 1,
16387
                    'port_id' => 0,
16388
                    'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/To Register18/dout',
16389
                    'type' => 'UFix_1_0',
16390
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16391
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16392
                  'hdlType' => 'std_logic_vector(0 downto 0)',
16393
                  'width' => 1,
16394
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16395
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16396
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16397
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16398
                    'is_floating_block' => 1,
16399
                    'must_be_hdl_vector' => 1,
16400
                    'period' => 1,
16401
                    'port_id' => 1,
16402
                    'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/To Register18/en',
16403
                    'type' => 'Bool',
16404
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16405
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16406
                  'hdlType' => 'std_logic_vector(0 downto 0)',
16407
                  'width' => 1,
16408
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16409
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16410
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16411
                    'domain' => '',
16412
                    'group' => 1,
16413
                    'isCe' => 1,
16414
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16415
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16416
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16417
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16418
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16419
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16420
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16421
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16422
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16423
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16424
                    'domain' => '',
16425
                    'group' => 1,
16426
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16427
                    'is_floating_block' => 1,
16428
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16429
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16430
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16431
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16432
                  'hdlType' => 'std_logic',
16433
                  'width' => 1,
16434
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16435
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16436
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16437
                    'domain' => '',
16438
                    'group' => 1,
16439
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16440
                    'is_floating_block' => 1,
16441
                    'period' => 1,
16442
                    'type' => 'logic',
16443
                    'valid_bit_used' => 0,
16444
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16445
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16446
                  'hdlType' => 'std_logic',
16447
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16448
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16449
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16450
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16451
                    'bin_pt' => 0,
16452
                    'is_floating_block' => 1,
16453
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16454
                    'period' => 1,
16455
                    'port_id' => 0,
16456
                    'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/To Register19/data_in',
16457
                    'type' => 'UFix_1_0',
16458
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16459
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16460
                  'hdlType' => 'std_logic_vector(0 downto 0)',
16461
                  'width' => 1,
16462
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16463
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16464
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16465
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16466
                    'is_floating_block' => 1,
16467
                    'must_be_hdl_vector' => 1,
16468
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16469
                    'port_id' => 0,
16470
                    'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/To Register19/dout',
16471
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16472
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16473
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16474
                  'hdlType' => 'std_logic_vector(0 downto 0)',
16475
                  'width' => 1,
16476
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16477
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16478
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16479
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16480
                    'is_floating_block' => 1,
16481
                    'must_be_hdl_vector' => 1,
16482
                    'period' => 1,
16483
                    'port_id' => 1,
16484
                    'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/To Register19/en',
16485
                    'type' => 'Bool',
16486
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16487
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16488
                  'hdlType' => 'std_logic_vector(0 downto 0)',
16489
                  'width' => 1,
16490
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16491
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16492
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16493
                    'domain' => '',
16494
                    'group' => 1,
16495
                    'isCe' => 1,
16496
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16497
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16498
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16499
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16500
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16501
                  'hdlType' => 'std_logic',
16502
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16503
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16504
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16505
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16506
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16507
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16508
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16509
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16510
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16511
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16512
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16513
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16514
                  'hdlType' => 'std_logic',
16515
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16516
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16517
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16518
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16519
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16520
                    'group' => 1,
16521
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16522
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16523
                    'period' => 1,
16524
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16525
                    'valid_bit_used' => 0,
16526
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16527
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16528
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16529
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16530
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16531
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16532
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16533
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16534
                    'is_floating_block' => 1,
16535
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16536
                    'period' => 1,
16537
                    'port_id' => 0,
16538
                    'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/To Register1/data_in',
16539
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16540
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16541
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16542
                  'hdlType' => 'std_logic_vector(31 downto 0)',
16543
                  'width' => 32,
16544
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16545
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16546
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16547
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16548
                    'is_floating_block' => 1,
16549
                    'must_be_hdl_vector' => 1,
16550
                    'period' => 1,
16551
                    'port_id' => 0,
16552
                    'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/To Register1/dout',
16553
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16554
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16555
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16556
                  'hdlType' => 'std_logic_vector(31 downto 0)',
16557
                  'width' => 32,
16558
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16559
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16560
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16561
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16562
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16563
                    'must_be_hdl_vector' => 1,
16564
                    'period' => 1,
16565
                    'port_id' => 1,
16566
                    'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/To Register1/en',
16567
                    'type' => 'Bool',
16568
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16569
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16570
                  'hdlType' => 'std_logic_vector(0 downto 0)',
16571
                  'width' => 1,
16572
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16573
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16574
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16575
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16576
                    'group' => 1,
16577
                    'isCe' => 1,
16578
                    'is_floating_block' => 1,
16579
                    'period' => 1,
16580
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16581
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16582
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16583
                  'hdlType' => 'std_logic',
16584
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16585
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16586
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16587
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16588
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16589
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16590
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16591
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16592
                    'period' => 1,
16593
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16594
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16595
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16596
                  'hdlType' => 'std_logic',
16597
                  'width' => 1,
16598
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16599
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16600
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16601
                    'domain' => '',
16602
                    'group' => 1,
16603
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16604
                    'is_floating_block' => 1,
16605
                    'period' => 1,
16606
                    'type' => 'logic',
16607
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16608
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16609
                  'direction' => 'out',
16610
                  'hdlType' => 'std_logic',
16611
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16612
                },
16613
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16614
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16615
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16616
                    'is_floating_block' => 1,
16617
                    'must_be_hdl_vector' => 1,
16618
                    'period' => 1,
16619
                    'port_id' => 0,
16620
                    'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/To Register20/data_in',
16621
                    'type' => 'UFix_32_0',
16622
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16623
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16624
                  'hdlType' => 'std_logic_vector(31 downto 0)',
16625
                  'width' => 32,
16626
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16627
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16628
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16629
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16630
                    'is_floating_block' => 1,
16631
                    'must_be_hdl_vector' => 1,
16632
                    'period' => 1,
16633
                    'port_id' => 0,
16634
                    'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/To Register20/dout',
16635
                    'type' => 'UFix_32_0',
16636
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16637
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16638
                  'hdlType' => 'std_logic_vector(31 downto 0)',
16639
                  'width' => 32,
16640
                },
16641
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16642
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16643
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16644
                    'is_floating_block' => 1,
16645
                    'must_be_hdl_vector' => 1,
16646
                    'period' => 1,
16647
                    'port_id' => 1,
16648
                    'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/To Register20/en',
16649
                    'type' => 'Bool',
16650
                  },
16651
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16652
                  'hdlType' => 'std_logic_vector(0 downto 0)',
16653
                  'width' => 1,
16654
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16655
                'to_register21_ce' => {
16656
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16657
                    'domain' => '',
16658
                    'group' => 1,
16659
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16660
                    'is_floating_block' => 1,
16661
                    'period' => 1,
16662
                    'type' => 'logic',
16663
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16664
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16665
                  'hdlType' => 'std_logic',
16666
                  'width' => 1,
16667
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16668
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16669
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16670
                    'domain' => '',
16671
                    'group' => 1,
16672
                    'isClk' => 1,
16673
                    'is_floating_block' => 1,
16674
                    'period' => 1,
16675
                    'type' => 'logic',
16676
                  },
16677
                  'direction' => 'out',
16678
                  'hdlType' => 'std_logic',
16679
                  'width' => 1,
16680
                },
16681
                'to_register21_clr' => {
16682
                  'attributes' => {
16683
                    'domain' => '',
16684
                    'group' => 1,
16685
                    'isClr' => 1,
16686
                    'is_floating_block' => 1,
16687
                    'period' => 1,
16688
                    'type' => 'logic',
16689
                    'valid_bit_used' => 0,
16690
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16691
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16696
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16699
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16705
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16710
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16711
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16713
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16716
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16717
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16720
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16721
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16723
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16724
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16725
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16726
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16727
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16729
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16730
                    'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/To Register21/en',
16731
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16733
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16734
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16735
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16736
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16739
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16741
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16743
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16744
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16746
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16748
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16749
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16750
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16751
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16752
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16753
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16754
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16755
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16756
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16757
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16759
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16760
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16764
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16765
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16766
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16767
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16768
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16769
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16770
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16773
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16774
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16775
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16776
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16777
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16778
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16779
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16780
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16781
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16784
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16786
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16787
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16788
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16789
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16790
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16792
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16793
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16794
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16795
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16798
                    'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/To Register22/dout',
16799
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16801
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16803
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16804
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16806
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16807
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16808
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16809
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16810
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16811
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16812
                    'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/To Register22/en',
16813
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16814
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16815
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16816
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16817
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16818
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16819
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16820
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16821
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16822
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16823
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16824
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16826
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16828
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16830
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16831
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16833
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16834
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16835
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16836
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16837
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16838
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16839
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16840
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16841
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16842
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16843
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16844
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16845
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16846
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16847
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16848
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16849
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16850
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16851
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16852
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16853
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16854
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16855
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16856
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16857
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16858
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16859
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16860
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16861
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16862
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16863
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16864
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16865
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16866
                    'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/To Register23/data_in',
16867
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16868
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16869
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16870
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16871
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16872
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16873
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16874
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16875
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16876
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16877
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16878
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16879
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16880
                    'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/To Register23/dout',
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16885
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16888
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16889
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16890
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16891
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16892
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16894
                    'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/To Register23/en',
16895
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16899
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16900
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16901
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16903
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16904
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16905
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16906
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16910
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16911
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16912
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16913
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16914
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16915
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16916
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16917
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16918
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16919
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16920
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16921
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16923
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16924
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16925
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16926
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16928
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16929
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16930
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16931
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16932
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16933
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16934
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16937
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16938
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16940
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16941
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16942
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16943
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16944
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16945
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16946
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16948
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16950
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16951
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16952
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16953
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16954
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16955
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16956
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16957
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16958
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16959
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16960
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16961
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16962
                    'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/To Register24/dout',
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16968
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16969
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16970
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16971
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16972
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16973
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16974
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16975
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16976
                    'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/To Register24/en',
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16979
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16980
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16981
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16982
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16983
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16984
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16985
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16986
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16987
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16988
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16989
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16990
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16992
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16993
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16994
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16995
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16997
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16998
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16999
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17000
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17001
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17002
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17003
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17005
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17006
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17007
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17008
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17009
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17010
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17011
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17012
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17013
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17014
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17015
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17016
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17018
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17019
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17020
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17021
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17022
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17023
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17024
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17025
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17026
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17027
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17028
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17029
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17030
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17031
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17033
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17034
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17035
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17036
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17037
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17038
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17039
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17040
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17041
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17044
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17049
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17050
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17051
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17052
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17053
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17054
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17055
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17056
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17057
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17058
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17059
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17060
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17061
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17062
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17063
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17064
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17065
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17066
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17067
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17068
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17069
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17070
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17071
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17072
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17074
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17075
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17076
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17077
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17079
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17080
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17081
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17082
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17083
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17084
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17085
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17086
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17087
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17088
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17089
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17090
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17092
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17093
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17094
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17095
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17096
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17097
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17098
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17099
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17101
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17102
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17103
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17104
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17105
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17106
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17107
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17108
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17109
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17110
                    'period' => 1,
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17112
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17115
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17116
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17117
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17118
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17119
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17120
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17121
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17122
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17123
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17124
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17125
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17126
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17130
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17131
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17132
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17133
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17134
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17135
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17136
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17137
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17139
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17140
                    'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/To Register26/en',
17141
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17144
                  'hdlType' => 'std_logic_vector(0 downto 0)',
17145
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17146
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17147
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17148
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17149
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17150
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17151
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17152
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17154
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17156
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17158
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17159
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17160
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17161
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17162
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17163
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17164
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17165
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17166
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17167
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17169
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17170
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17171
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17172
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17173
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17174
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17175
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17176
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17177
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17178
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17179
                    'period' => 1,
17180
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17181
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17182
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17183
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17184
                  'hdlType' => 'std_logic',
17185
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17186
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17187
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17188
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17189
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17190
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17191
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                    'port_id' => 0,
17194
                    'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/To Register27/data_in',
17195
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17196
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17197
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17198
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17199
                  'width' => 1,
17200
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17201
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17202
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17203
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17204
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17205
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17206
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17207
                    'port_id' => 0,
17208
                    'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/To Register27/dout',
17209
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17211
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17212
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17213
                  'width' => 1,
17214
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17215
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17216
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17217
                    'bin_pt' => 0,
17218
                    'is_floating_block' => 1,
17219
                    'must_be_hdl_vector' => 1,
17220
                    'period' => 1,
17221
                    'port_id' => 1,
17222
                    'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/To Register27/en',
17223
                    'type' => 'Bool',
17224
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17225
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17226
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17227
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17760
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17913
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17927
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17995
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18064
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18077
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18079
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18085
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18090
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18104
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18105
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18119
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18133
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18146
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18150
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18155
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18158
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18159
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18160
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18167
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18172
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18173
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18184
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18186
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18187
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18200
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18201
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18213
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18214
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18215
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18216
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18218
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18219
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18222
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18228
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18235
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18238
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18239
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18240
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18241
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18243
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18244
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18249
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18250
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18251
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18252
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18253
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18254
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18255
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18256
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18260
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18264
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18265
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18266
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18267
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18271
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18281
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18282
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18283
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18292
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18294
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18295
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18296
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18297
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18298
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18299
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18300
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18301
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18304
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18306
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18307
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18308
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18309
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18310
                    'domain' => '',
18311
                    'group' => 1,
18312
                    'isClk' => 1,
18313
                    'is_floating_block' => 1,
18314
                    'period' => 1,
18315
                    'type' => 'logic',
18316
                  },
18317
                  'direction' => 'out',
18318
                  'hdlType' => 'std_logic',
18319
                  'width' => 1,
18320
                },
18321
                'to_register8_clr' => {
18322
                  'attributes' => {
18323
                    'domain' => '',
18324
                    'group' => 1,
18325
                    'isClr' => 1,
18326
                    'is_floating_block' => 1,
18327
                    'period' => 1,
18328
                    'type' => 'logic',
18329
                    'valid_bit_used' => 0,
18330
                  },
18331
                  'direction' => 'out',
18332
                  'hdlType' => 'std_logic',
18333
                  'width' => 1,
18334
                },
18335
                'to_register8_data_in' => {
18336
                  'attributes' => {
18337
                    'bin_pt' => 0,
18338
                    'is_floating_block' => 1,
18339
                    'must_be_hdl_vector' => 1,
18340
                    'period' => 1,
18341
                    'port_id' => 0,
18342
                    'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/To Register8/data_in',
18343
                    'type' => 'Bool',
18344
                  },
18345
                  'direction' => 'out',
18346
                  'hdlType' => 'std_logic_vector(0 downto 0)',
18347
                  'width' => 1,
18348
                },
18349
                'to_register8_dout' => {
18350
                  'attributes' => {
18351
                    'bin_pt' => 0,
18352
                    'is_floating_block' => 1,
18353
                    'must_be_hdl_vector' => 1,
18354
                    'period' => 1,
18355
                    'port_id' => 0,
18356
                    'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/To Register8/dout',
18357
                    'type' => 'Bool',
18358
                  },
18359
                  'direction' => 'in',
18360
                  'hdlType' => 'std_logic_vector(0 downto 0)',
18361
                  'width' => 1,
18362
                },
18363
                'to_register8_en' => {
18364
                  'attributes' => {
18365
                    'bin_pt' => 0,
18366
                    'is_floating_block' => 1,
18367
                    'must_be_hdl_vector' => 1,
18368
                    'period' => 1,
18369
                    'port_id' => 1,
18370
                    'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/To Register8/en',
18371
                    'type' => 'Bool',
18372
                  },
18373
                  'direction' => 'out',
18374
                  'hdlType' => 'std_logic_vector(0 downto 0)',
18375
                  'width' => 1,
18376
                },
18377
                'to_register9_ce' => {
18378
                  'attributes' => {
18379
                    'domain' => '',
18380
                    'group' => 1,
18381
                    'isCe' => 1,
18382
                    'is_floating_block' => 1,
18383
                    'period' => 1,
18384
                    'type' => 'logic',
18385
                  },
18386
                  'direction' => 'out',
18387
                  'hdlType' => 'std_logic',
18388
                  'width' => 1,
18389
                },
18390
                'to_register9_clk' => {
18391
                  'attributes' => {
18392
                    'domain' => '',
18393
                    'group' => 1,
18394
                    'isClk' => 1,
18395
                    'is_floating_block' => 1,
18396
                    'period' => 1,
18397
                    'type' => 'logic',
18398
                  },
18399
                  'direction' => 'out',
18400
                  'hdlType' => 'std_logic',
18401
                  'width' => 1,
18402
                },
18403
                'to_register9_clr' => {
18404
                  'attributes' => {
18405
                    'domain' => '',
18406
                    'group' => 1,
18407
                    'isClr' => 1,
18408
                    'is_floating_block' => 1,
18409
                    'period' => 1,
18410
                    'type' => 'logic',
18411
                    'valid_bit_used' => 0,
18412
                  },
18413
                  'direction' => 'out',
18414
                  'hdlType' => 'std_logic',
18415
                  'width' => 1,
18416
                },
18417
                'to_register9_data_in' => {
18418
                  'attributes' => {
18419
                    'bin_pt' => 0,
18420
                    'is_floating_block' => 1,
18421
                    'must_be_hdl_vector' => 1,
18422
                    'period' => 1,
18423
                    'port_id' => 0,
18424
                    'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/To Register9/data_in',
18425
                    'type' => 'UFix_32_0',
18426
                  },
18427
                  'direction' => 'out',
18428
                  'hdlType' => 'std_logic_vector(31 downto 0)',
18429
                  'width' => 32,
18430
                },
18431
                'to_register9_dout' => {
18432
                  'attributes' => {
18433
                    'bin_pt' => 0,
18434
                    'is_floating_block' => 1,
18435
                    'must_be_hdl_vector' => 1,
18436
                    'period' => 1,
18437
                    'port_id' => 0,
18438
                    'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/To Register9/dout',
18439
                    'type' => 'UFix_32_0',
18440
                  },
18441
                  'direction' => 'in',
18442
                  'hdlType' => 'std_logic_vector(31 downto 0)',
18443
                  'width' => 32,
18444
                },
18445
                'to_register9_en' => {
18446
                  'attributes' => {
18447
                    'bin_pt' => 0,
18448
                    'is_floating_block' => 1,
18449
                    'must_be_hdl_vector' => 1,
18450
                    'period' => 1,
18451
                    'port_id' => 1,
18452
                    'simulinkName' => 'PCIe_UserLogic_00/INOUT_LOGIC/To Register9/en',
18453
                    'type' => 'Bool',
18454
                  },
18455
                  'direction' => 'out',
18456
                  'hdlType' => 'std_logic_vector(0 downto 0)',
18457
                  'width' => 1,
18458
                },
18459
              },
18460
              'subblocks' => {
18461
                'default_clock_driver_x0' => {
18462
                  'connections' => {
18463
                    'ce_1' => 'ce_1_sg',
18464
                    'clk_1' => 'clk_1_sg',
18465
                    'sysce' => [
18466
                      'constant',
18467
                      '\'1\'',
18468
                    ],
18469
                    'sysce_clr' => [
18470
                      'constant',
18471
                      '\'0\'',
18472
                    ],
18473
                    'sysclk' => 'clkNet',
18474
                  },
18475
                  'entity' => {
18476
                    'attributes' => {
18477
                      'domain' => 'default',
18478
                      'hdlArchAttributes' => [
18479
                        [
18480
                          'syn_noprune',
18481
                          'boolean',
18482
                          'true',
18483
                        ],
18484
                        [
18485
                          'optimize_primitives',
18486
                          'boolean',
18487
                          'false',
18488
                        ],
18489
                        [
18490
                          'dont_touch',
18491
                          'boolean',
18492
                          'true',
18493
                        ],
18494
                      ],
18495
                      'hdlEntityAttributes' => [
18496
                      ],
18497
                      'isClkDriver' => 1,
18498
                    },
18499
                    'entityName' => 'default_clock_driver',
18500
                    'ports' => {
18501
                      'ce_1' => {
18502
                        'attributes' => {
18503
                          'domain' => 'default',
18504
                          'group' => 1,
18505
                          'isCe' => 1,
18506
                          'period' => 1,
18507
                          'type' => 'logic',
18508
                        },
18509
                        'direction' => 'out',
18510
                        'hdlType' => 'std_logic',
18511
                        'width' => 1,
18512
                      },
18513
                      'clk_1' => {
18514
                        'attributes' => {
18515
                          'domain' => 'default',
18516
                          'group' => 1,
18517
                          'isClk' => 1,
18518
                          'period' => 1,
18519
                          'type' => 'logic',
18520
                        },
18521
                        'direction' => 'out',
18522
                        'hdlType' => 'std_logic',
18523
                        'width' => 1,
18524
                      },
18525
                      'sysce' => {
18526
                        'attributes' => {
18527
                          'group' => 4,
18528
                          'isCe' => 1,
18529
                          'period' => 1,
18530
                        },
18531
                        'direction' => 'in',
18532
                        'hdlType' => 'std_logic',
18533
                        'width' => 1,
18534
                      },
18535
                      'sysce_clr' => {
18536
                        'attributes' => {
18537
                          'group' => 4,
18538
                          'isClr' => 1,
18539
                          'period' => 1,
18540
                        },
18541
                        'direction' => 'in',
18542
                        'hdlType' => 'std_logic',
18543
                        'width' => 1,
18544
                      },
18545
                      'sysclk' => {
18546
                        'attributes' => {
18547
                          'group' => 4,
18548
                          'isClk' => 1,
18549
                          'period' => 1,
18550
                        },
18551
                        'direction' => 'in',
18552
                        'hdlType' => 'std_logic',
18553
                        'width' => 1,
18554
                      },
18555
                    },
18556
                  },
18557
                  'entityName' => 'default_clock_driver',
18558
                },
18559
                'inout_logic_x0' => {
18560
                  'connections' => {
18561
                    'data_in' => 'debug_in_2i_net_x0',
18562
                    'data_in_x0' => 'reg04_tv_net_x0',
18563
                    'data_in_x1' => 'reg04_td_net_x0',
18564
                    'data_in_x10' => 'debug_in_3i_net_x0',
18565
                    'data_in_x11' => 'debug_in_4i_net_x0',
18566
                    'data_in_x12' => 'reg09_tv_net_x0',
18567
                    'data_in_x13' => 'reg09_td_net_x0',
18568
                    'data_in_x14' => 'reg10_tv_net_x0',
18569
                    'data_in_x15' => 'reg10_td_net_x0',
18570
                    'data_in_x16' => 'reg08_tv_net_x0',
18571
                    'data_in_x17' => 'reg08_td_net_x0',
18572
                    'data_in_x18' => 'reg11_tv_net_x0',
18573
                    'data_in_x19' => 'reg11_td_net_x0',
18574
                    'data_in_x2' => 'reg05_tv_net_x0',
18575
                    'data_in_x20' => 'reg12_tv_net_x0',
18576
                    'data_in_x21' => 'reg01_tv_net_x0',
18577
                    'data_in_x22' => 'reg12_td_net_x0',
18578
                    'data_in_x23' => 'reg13_tv_net_x0',
18579
                    'data_in_x24' => 'reg13_td_net_x0',
18580
                    'data_in_x25' => 'reg14_tv_net_x0',
18581
                    'data_in_x26' => 'reg14_td_net_x0',
18582
                    'data_in_x27' => 'reg02_tv_net_x0',
18583
                    'data_in_x28' => 'reg02_td_net_x0',
18584
                    'data_in_x29' => 'debug_in_1i_net_x0',
18585
                    'data_in_x3' => 'reg05_td_net_x0',
18586
                    'data_in_x30' => 'reg01_td_net_x0',
18587
                    'data_in_x31' => 'reg03_tv_net_x0',
18588
                    'data_in_x32' => 'reg03_td_net_x0',
18589
                    'data_in_x4' => 'reg06_tv_net_x0',
18590
                    'data_in_x5' => 'reg06_td_net_x0',
18591
                    'data_in_x6' => 'reg07_tv_net_x0',
18592
                    'data_in_x7' => 'reg07_td_net_x0',
18593
                    'data_in_x8' => 'dma_host2board_busy_net_x0',
18594
                    'data_in_x9' => 'dma_host2board_done_net_x0',
18595
                    'data_out' => 'from_register1_data_out_net',
18596
                    'data_out_x0' => 'from_register10_data_out_net',
18597
                    'data_out_x1' => 'from_register11_data_out_net',
18598
                    'data_out_x10' => 'from_register2_data_out_net',
18599
                    'data_out_x11' => 'from_register20_data_out_net',
18600
                    'data_out_x12' => 'from_register21_data_out_net',
18601
                    'data_out_x13' => 'from_register22_data_out_net',
18602
                    'data_out_x14' => 'from_register23_data_out_net',
18603
                    'data_out_x15' => 'from_register24_data_out_net',
18604
                    'data_out_x16' => 'from_register25_data_out_net',
18605
                    'data_out_x17' => 'from_register26_data_out_net',
18606
                    'data_out_x18' => 'from_register27_data_out_net',
18607
                    'data_out_x19' => 'from_register28_data_out_net',
18608
                    'data_out_x2' => 'from_register12_data_out_net',
18609
                    'data_out_x20' => 'from_register3_data_out_net',
18610
                    'data_out_x21' => 'from_register4_data_out_net',
18611
                    'data_out_x22' => 'from_register5_data_out_net',
18612
                    'data_out_x23' => 'from_register6_data_out_net',
18613
                    'data_out_x24' => 'from_register7_data_out_net',
18614
                    'data_out_x25' => 'from_register8_data_out_net',
18615
                    'data_out_x26' => 'from_register9_data_out_net',
18616
                    'data_out_x3' => 'from_register13_data_out_net',
18617
                    'data_out_x4' => 'from_register14_data_out_net',
18618
                    'data_out_x5' => 'from_register15_data_out_net',
18619
                    'data_out_x6' => 'from_register16_data_out_net',
18620
                    'data_out_x7' => 'from_register17_data_out_net',
18621
                    'data_out_x8' => 'from_register18_data_out_net',
18622
                    'data_out_x9' => 'from_register19_data_out_net',
18623
                    'debug_in_1i' => 'debug_in_1i_net',
18624
                    'debug_in_2i' => 'debug_in_2i_net',
18625
                    'debug_in_3i' => 'debug_in_3i_net',
18626
                    'debug_in_4i' => 'debug_in_4i_net',
18627
                    'dma_host2board_busy' => 'dma_host2board_busy_net',
18628
                    'dma_host2board_done' => 'dma_host2board_done_net',
18629
                    'en' => 'constant5_op_net_x0',
18630
                    'en_x0' => 'constant5_op_net_x1',
18631
                    'en_x1' => 'constant5_op_net_x2',
18632
                    'en_x10' => 'constant5_op_net_x11',
18633
                    'en_x11' => 'constant5_op_net_x12',
18634
                    'en_x12' => 'constant1_op_net_x0',
18635
                    'en_x13' => 'constant1_op_net_x1',
18636
                    'en_x14' => 'constant1_op_net_x2',
18637
                    'en_x15' => 'constant1_op_net_x3',
18638
                    'en_x16' => 'constant1_op_net_x4',
18639
                    'en_x17' => 'constant1_op_net_x5',
18640
                    'en_x18' => 'constant1_op_net_x6',
18641
                    'en_x19' => 'constant1_op_net_x7',
18642
                    'en_x2' => 'constant5_op_net_x3',
18643
                    'en_x20' => 'constant1_op_net_x8',
18644
                    'en_x21' => 'constant5_op_net_x13',
18645
                    'en_x22' => 'constant1_op_net_x9',
18646
                    'en_x23' => 'constant1_op_net_x10',
18647
                    'en_x24' => 'constant1_op_net_x11',
18648
                    'en_x25' => 'constant1_op_net_x12',
18649
                    'en_x26' => 'constant1_op_net_x13',
18650
                    'en_x27' => 'constant5_op_net_x14',
18651
                    'en_x28' => 'constant5_op_net_x15',
18652
                    'en_x29' => 'constant5_op_net_x16',
18653
                    'en_x3' => 'constant5_op_net_x4',
18654
                    'en_x30' => 'constant5_op_net_x17',
18655
                    'en_x31' => 'constant5_op_net_x18',
18656
                    'en_x32' => 'constant5_op_net_x19',
18657
                    'en_x4' => 'constant5_op_net_x5',
18658
                    'en_x5' => 'constant5_op_net_x6',
18659
                    'en_x6' => 'constant5_op_net_x7',
18660
                    'en_x7' => 'constant5_op_net_x8',
18661
                    'en_x8' => 'constant5_op_net_x9',
18662
                    'en_x9' => 'constant5_op_net_x10',
18663
                    'reg01_rd' => 'from_register3_data_out_net_x0',
18664
                    'reg01_rv' => 'from_register1_data_out_net_x0',
18665
                    'reg01_td' => 'reg01_td_net',
18666
                    'reg01_tv' => 'reg01_tv_net',
18667
                    'reg02_rd' => 'from_register5_data_out_net_x0',
18668
                    'reg02_rv' => 'from_register2_data_out_net_x0',
18669
                    'reg02_td' => 'reg02_td_net',
18670
                    'reg02_tv' => 'reg02_tv_net',
18671
                    'reg03_rd' => 'from_register7_data_out_net_x0',
18672
                    'reg03_rv' => 'from_register6_data_out_net_x0',
18673
                    'reg03_td' => 'reg03_td_net',
18674
                    'reg03_tv' => 'reg03_tv_net',
18675
                    'reg04_rd' => 'from_register8_data_out_net_x0',
18676
                    'reg04_rv' => 'from_register4_data_out_net_x0',
18677
                    'reg04_td' => 'reg04_td_net',
18678
                    'reg04_tv' => 'reg04_tv_net',
18679
                    'reg05_rd' => 'from_register10_data_out_net_x0',
18680
                    'reg05_rv' => 'from_register9_data_out_net_x0',
18681
                    'reg05_td' => 'reg05_td_net',
18682
                    'reg05_tv' => 'reg05_tv_net',
18683
                    'reg06_rd' => 'from_register11_data_out_net_x0',
18684
                    'reg06_rv' => 'from_register12_data_out_net_x0',
18685
                    'reg06_td' => 'reg06_td_net',
18686
                    'reg06_tv' => 'reg06_tv_net',
18687
                    'reg07_rd' => 'from_register13_data_out_net_x0',
18688
                    'reg07_rv' => 'from_register14_data_out_net_x0',
18689
                    'reg07_td' => 'reg07_td_net',
18690
                    'reg07_tv' => 'reg07_tv_net',
18691
                    'reg08_rd' => 'from_register15_data_out_net_x0',
18692
                    'reg08_rv' => 'from_register16_data_out_net_x0',
18693
                    'reg08_td' => 'reg08_td_net',
18694
                    'reg08_tv' => 'reg08_tv_net',
18695
                    'reg09_rd' => 'from_register17_data_out_net_x0',
18696
                    'reg09_rv' => 'from_register18_data_out_net_x0',
18697
                    'reg09_td' => 'reg09_td_net',
18698
                    'reg09_tv' => 'reg09_tv_net',
18699
                    'reg10_rd' => 'from_register19_data_out_net_x0',
18700
                    'reg10_rv' => 'from_register20_data_out_net_x0',
18701
                    'reg10_td' => 'reg10_td_net',
18702
                    'reg10_tv' => 'reg10_tv_net',
18703
                    'reg11_rd' => 'from_register21_data_out_net_x0',
18704
                    'reg11_rv' => 'from_register22_data_out_net_x0',
18705
                    'reg11_td' => 'reg11_td_net',
18706
                    'reg11_tv' => 'reg11_tv_net',
18707
                    'reg12_rd' => 'from_register23_data_out_net_x0',
18708
                    'reg12_rv' => 'from_register24_data_out_net_x0',
18709
                    'reg12_td' => 'reg12_td_net',
18710
                    'reg12_tv' => 'reg12_tv_net',
18711
                    'reg13_rd' => 'from_register25_data_out_net_x0',
18712
                    'reg13_rv' => 'from_register26_data_out_net_x0',
18713
                    'reg13_td' => 'reg13_td_net',
18714
                    'reg13_tv' => 'reg13_tv_net',
18715
                    'reg14_rd' => 'from_register27_data_out_net_x0',
18716
                    'reg14_rv' => 'from_register28_data_out_net_x0',
18717
                    'reg14_td' => 'reg14_td_net',
18718
                    'reg14_tv' => 'reg14_tv_net',
18719
                  },
18720
                  'entity' => {
18721
                    'attributes' => {
18722
                      'entityAlreadyNetlisted' => 1,
18723
                      'hdlKind' => 'vhdl',
18724
                      'isDesign' => 1,
18725
                      'simulinkName' => 'INOUT_LOGIC',
18726
                    },
18727
                    'entityName' => 'inout_logic',
18728
                    'ports' => {
18729
                      'data_in' => {
18730
                        'attributes' => {
18731
                          'bin_pt' => 0,
18732
                          'is_floating_block' => 1,
18733
                          'must_be_hdl_vector' => 1,
18734
                          'period' => 1,
18735
                          'port_id' => 0,
18736
                          'simulinkName' => 'INOUT_LOGIC/data_in',
18737
                          'type' => 'UFix_32_0',
18738
                        },
18739
                        'direction' => 'out',
18740
                        'hdlType' => 'std_logic_vector(31 downto 0)',
18741
                        'width' => 32,
18742
                      },
18743
                      'data_in_x0' => {
18744
                        'attributes' => {
18745
                          'bin_pt' => 0,
18746
                          'is_floating_block' => 1,
18747
                          'must_be_hdl_vector' => 1,
18748
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18749
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20750
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20830
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20866
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20895
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20900
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20904
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20974
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21011
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21028
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21029
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21030
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21064
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21079
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21082
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21101
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21110
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21111
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21112
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21113
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21114
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21115
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21119
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21130
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21134
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21136
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21137
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21154
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21155
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21185
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21186
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21188
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21189
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21190
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21191
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21192
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21193
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21194
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21195
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21196
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21197
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21198
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21199
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21200
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21201
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21202
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21203
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21204
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21205
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21206
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21207
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21208
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21209
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21210
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21211
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21212
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21213
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21214
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21215
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21216
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21217
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21218
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21219
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21220
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21221
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21222
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21223
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21224
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21225
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21226
                        'hdlType' => 'std_logic',
21227
                        'width' => 1,
21228
                      },
21229
                      'q' => {
21230
                        'direction' => 'out',
21231
                        'hdlType' => 'std_logic',
21232
                        'width' => 1,
21233
                      },
21234
                    },
21235
                  },
21236
                  'entityName' => 'xlpersistentdff',
21237
                },
21238
              },
21239
            },
21240
            'entityName' => 'inout_logic_cw',
21241
          },
21242
          'top_level_1' => {
21243
            'connections' => {
21244
              'bram_rd_addr' => 'x_x63',
21245
              'bram_rd_dout' => 'x_x64',
21246
              'bram_wr_addr' => 'x_x65',
21247
              'bram_wr_din' => 'x_x66',
21248
              'bram_wr_en' => 'x_x67',
21249
              'ce' => 'x_x68',
21250
              'clk' => 'x_x69',
21251
              'fifo_rd_count' => 'x_x70',
21252
              'fifo_rd_dout' => 'x_x71',
21253
              'fifo_rd_empty' => 'x_x72',
21254
              'fifo_rd_en' => 'x_x73',
21255
              'fifo_rd_pempty' => 'x_x74',
21256
              'fifo_rd_valid' => 'x_x75',
21257
              'fifo_wr_count' => 'x_x76',
21258
              'fifo_wr_din' => 'x_x77',
21259
              'fifo_wr_en' => 'x_x78',
21260
              'fifo_wr_full' => 'x_x79',
21261
              'fifo_wr_pfull' => 'x_x80',
21262
              'from_register10_data_out' => 'from_register10_data_out_x0',
21263
              'from_register11_data_out' => 'from_register11_data_out_x0',
21264
              'from_register12_data_out' => 'from_register12_data_out_x0',
21265
              'from_register13_data_out' => 'from_register13_data_out_x0',
21266
              'from_register14_data_out' => 'from_register14_data_out_x0',
21267
              'from_register15_data_out' => 'from_register15_data_out_x0',
21268
              'from_register16_data_out' => 'from_register16_data_out_x0',
21269
              'from_register17_data_out' => 'from_register17_data_out_x0',
21270
              'from_register18_data_out' => 'from_register18_data_out_x0',
21271
              'from_register19_data_out' => 'from_register19_data_out_x0',
21272
              'from_register1_data_out' => 'from_register1_data_out_x0',
21273
              'from_register20_data_out' => 'from_register20_data_out_x0',
21274
              'from_register21_data_out' => 'from_register21_data_out_x0',
21275
              'from_register22_data_out' => 'from_register22_data_out_x0',
21276
              'from_register23_data_out' => 'from_register23_data_out_x0',
21277
              'from_register24_data_out' => 'from_register24_data_out_x0',
21278
              'from_register25_data_out' => 'from_register25_data_out_x0',
21279
              'from_register26_data_out' => 'from_register26_data_out_x0',
21280
              'from_register27_data_out' => 'from_register27_data_out_x0',
21281
              'from_register28_data_out' => 'from_register28_data_out_x0',
21282
              'from_register29_data_out' => 'from_register29_data_out',
21283
              'from_register2_data_out' => 'from_register2_data_out_x0',
21284
              'from_register30_data_out' => 'from_register30_data_out',
21285
              'from_register31_data_out' => 'from_register31_data_out',
21286
              'from_register32_data_out' => 'from_register32_data_out',
21287
              'from_register33_data_out' => 'from_register33_data_out',
21288
              'from_register3_data_out' => 'from_register3_data_out_x0',
21289
              'from_register4_data_out' => 'from_register4_data_out_x0',
21290
              'from_register5_data_out' => 'from_register5_data_out_x0',
21291
              'from_register6_data_out' => 'from_register6_data_out_x0',
21292
              'from_register7_data_out' => 'from_register7_data_out_x0',
21293
              'from_register8_data_out' => 'from_register8_data_out_x0',
21294
              'from_register9_data_out' => 'from_register9_data_out_x0',
21295
              'from_register_data_out' => 'from_register_data_out',
21296
              'rst_i' => 'x_x81',
21297
              'rst_o' => 'x_x82',
21298
              'to_register10_ce' => 'sysgen_dut_to_register10_ce_x0',
21299
              'to_register10_clk' => 'sysgen_dut_to_register10_clk_x0',
21300
              'to_register10_clr' => 'sysgen_dut_to_register10_clr_x0',
21301
              'to_register10_data_in' => 'sysgen_dut_to_register10_data_in_x0',
21302
              'to_register10_dout' => 'from_register9_data_out',
21303
              'to_register10_en' => 'sysgen_dut_to_register10_en_x0',
21304
              'to_register11_ce' => 'sysgen_dut_to_register11_ce_x0',
21305
              'to_register11_clk' => 'sysgen_dut_to_register11_clk_x0',
21306
              'to_register11_clr' => 'sysgen_dut_to_register11_clr_x0',
21307
              'to_register11_data_in' => 'sysgen_dut_to_register11_data_in_x0',
21308
              'to_register11_dout' => 'from_register12_data_out',
21309
              'to_register11_en' => 'sysgen_dut_to_register11_en_x0',
21310
              'to_register12_ce' => 'sysgen_dut_to_register12_ce_x0',
21311
              'to_register12_clk' => 'sysgen_dut_to_register12_clk_x0',
21312
              'to_register12_clr' => 'sysgen_dut_to_register12_clr_x0',
21313
              'to_register12_data_in' => 'sysgen_dut_to_register12_data_in_x0',
21314
              'to_register12_dout' => 'from_register14_data_out',
21315
              'to_register12_en' => 'sysgen_dut_to_register12_en_x0',
21316
              'to_register13_ce' => 'sysgen_dut_to_register13_ce_x0',
21317
              'to_register13_clk' => 'sysgen_dut_to_register13_clk_x0',
21318
              'to_register13_clr' => 'sysgen_dut_to_register13_clr_x0',
21319
              'to_register13_data_in' => 'sysgen_dut_to_register13_data_in_x0',
21320
              'to_register13_dout' => 'from_register13_data_out',
21321
              'to_register13_en' => 'sysgen_dut_to_register13_en_x0',
21322
              'to_register14_ce' => 'sysgen_dut_to_register14_ce_x0',
21323
              'to_register14_clk' => 'sysgen_dut_to_register14_clk_x0',
21324
              'to_register14_clr' => 'sysgen_dut_to_register14_clr_x0',
21325
              'to_register14_data_in' => 'sysgen_dut_to_register14_data_in_x0',
21326
              'to_register14_dout' => 'from_register16_data_out',
21327
              'to_register14_en' => 'sysgen_dut_to_register14_en_x0',
21328
              'to_register15_ce' => 'sysgen_dut_to_register15_ce_x0',
21329
              'to_register15_clk' => 'sysgen_dut_to_register15_clk_x0',
21330
              'to_register15_clr' => 'sysgen_dut_to_register15_clr_x0',
21331
              'to_register15_data_in' => 'sysgen_dut_to_register15_data_in_x0',
21332
              'to_register15_dout' => 'from_register15_data_out',
21333
              'to_register15_en' => 'sysgen_dut_to_register15_en_x0',
21334
              'to_register16_ce' => 'sysgen_dut_to_register16_ce_x0',
21335
              'to_register16_clk' => 'sysgen_dut_to_register16_clk_x0',
21336
              'to_register16_clr' => 'sysgen_dut_to_register16_clr_x0',
21337
              'to_register16_data_in' => 'sysgen_dut_to_register16_data_in_x0',
21338
              'to_register16_dout' => 'from_register18_data_out',
21339
              'to_register16_en' => 'sysgen_dut_to_register16_en_x0',
21340
              'to_register17_ce' => 'sysgen_dut_to_register17_ce_x0',
21341
              'to_register17_clk' => 'sysgen_dut_to_register17_clk_x0',
21342
              'to_register17_clr' => 'sysgen_dut_to_register17_clr_x0',
21343
              'to_register17_data_in' => 'sysgen_dut_to_register17_data_in_x0',
21344
              'to_register17_dout' => 'from_register17_data_out',
21345
              'to_register17_en' => 'sysgen_dut_to_register17_en_x0',
21346
              'to_register18_ce' => 'sysgen_dut_to_register18_ce_x0',
21347
              'to_register18_clk' => 'sysgen_dut_to_register18_clk_x0',
21348
              'to_register18_clr' => 'sysgen_dut_to_register18_clr_x0',
21349
              'to_register18_data_in' => 'sysgen_dut_to_register18_data_in_x0',
21350
              'to_register18_dout' => 'from_register20_data_out',
21351
              'to_register18_en' => 'sysgen_dut_to_register18_en_x0',
21352
              'to_register19_ce' => 'sysgen_dut_to_register19_ce_x0',
21353
              'to_register19_clk' => 'sysgen_dut_to_register19_clk_x0',
21354
              'to_register19_clr' => 'sysgen_dut_to_register19_clr_x0',
21355
              'to_register19_data_in' => 'sysgen_dut_to_register19_data_in_x0',
21356
              'to_register19_dout' => 'from_register19_data_out',
21357
              'to_register19_en' => 'sysgen_dut_to_register19_en_x0',
21358
              'to_register1_ce' => 'sysgen_dut_to_register1_ce_x0',
21359
              'to_register1_clk' => 'sysgen_dut_to_register1_clk_x0',
21360
              'to_register1_clr' => 'sysgen_dut_to_register1_clr_x0',
21361
              'to_register1_data_in' => 'sysgen_dut_to_register1_data_in_x0',
21362
              'to_register1_dout' => 'from_register1_data_out',
21363
              'to_register1_en' => 'sysgen_dut_to_register1_en_x0',
21364
              'to_register20_ce' => 'sysgen_dut_to_register20_ce_x0',
21365
              'to_register20_clk' => 'sysgen_dut_to_register20_clk_x0',
21366
              'to_register20_clr' => 'sysgen_dut_to_register20_clr_x0',
21367
              'to_register20_data_in' => 'sysgen_dut_to_register20_data_in_x0',
21368
              'to_register20_dout' => 'from_register22_data_out',
21369
              'to_register20_en' => 'sysgen_dut_to_register20_en_x0',
21370
              'to_register21_ce' => 'sysgen_dut_to_register21_ce_x0',
21371
              'to_register21_clk' => 'sysgen_dut_to_register21_clk_x0',
21372
              'to_register21_clr' => 'sysgen_dut_to_register21_clr_x0',
21373
              'to_register21_data_in' => 'sysgen_dut_to_register21_data_in_x0',
21374
              'to_register21_dout' => 'from_register21_data_out',
21375
              'to_register21_en' => 'sysgen_dut_to_register21_en_x0',
21376
              'to_register22_ce' => 'sysgen_dut_to_register22_ce_x0',
21377
              'to_register22_clk' => 'sysgen_dut_to_register22_clk_x0',
21378
              'to_register22_clr' => 'sysgen_dut_to_register22_clr_x0',
21379
              'to_register22_data_in' => 'sysgen_dut_to_register22_data_in_x0',
21380
              'to_register22_dout' => 'from_register24_data_out',
21381
              'to_register22_en' => 'sysgen_dut_to_register22_en_x0',
21382
              'to_register23_ce' => 'sysgen_dut_to_register23_ce_x0',
21383
              'to_register23_clk' => 'sysgen_dut_to_register23_clk_x0',
21384
              'to_register23_clr' => 'sysgen_dut_to_register23_clr_x0',
21385
              'to_register23_data_in' => 'sysgen_dut_to_register23_data_in_x0',
21386
              'to_register23_dout' => 'from_register23_data_out',
21387
              'to_register23_en' => 'sysgen_dut_to_register23_en_x0',
21388
              'to_register24_ce' => 'sysgen_dut_to_register24_ce_x0',
21389
              'to_register24_clk' => 'sysgen_dut_to_register24_clk_x0',
21390
              'to_register24_clr' => 'sysgen_dut_to_register24_clr_x0',
21391
              'to_register24_data_in' => 'sysgen_dut_to_register24_data_in_x0',
21392
              'to_register24_dout' => 'from_register26_data_out',
21393
              'to_register24_en' => 'sysgen_dut_to_register24_en_x0',
21394
              'to_register25_ce' => 'sysgen_dut_to_register25_ce_x0',
21395
              'to_register25_clk' => 'sysgen_dut_to_register25_clk_x0',
21396
              'to_register25_clr' => 'sysgen_dut_to_register25_clr_x0',
21397
              'to_register25_data_in' => 'sysgen_dut_to_register25_data_in_x0',
21398
              'to_register25_dout' => 'from_register25_data_out',
21399
              'to_register25_en' => 'sysgen_dut_to_register25_en_x0',
21400
              'to_register26_ce' => 'sysgen_dut_to_register26_ce_x0',
21401
              'to_register26_clk' => 'sysgen_dut_to_register26_clk_x0',
21402
              'to_register26_clr' => 'sysgen_dut_to_register26_clr_x0',
21403
              'to_register26_data_in' => 'sysgen_dut_to_register26_data_in_x0',
21404
              'to_register26_dout' => 'from_register28_data_out',
21405
              'to_register26_en' => 'sysgen_dut_to_register26_en_x0',
21406
              'to_register27_ce' => 'sysgen_dut_to_register27_ce_x0',
21407
              'to_register27_clk' => 'sysgen_dut_to_register27_clk_x0',
21408
              'to_register27_clr' => 'sysgen_dut_to_register27_clr_x0',
21409
              'to_register27_data_in' => 'sysgen_dut_to_register27_data_in_x0',
21410
              'to_register27_dout' => 'from_register27_data_out',
21411
              'to_register27_en' => 'sysgen_dut_to_register27_en_x0',
21412
              'to_register2_ce' => 'sysgen_dut_to_register2_ce_x0',
21413
              'to_register2_clk' => 'sysgen_dut_to_register2_clk_x0',
21414
              'to_register2_clr' => 'sysgen_dut_to_register2_clr_x0',
21415
              'to_register2_data_in' => 'sysgen_dut_to_register2_data_in_x0',
21416
              'to_register2_dout' => 'from_register5_data_out',
21417
              'to_register2_en' => 'sysgen_dut_to_register2_en_x0',
21418
              'to_register3_ce' => 'sysgen_dut_to_register3_ce_x0',
21419
              'to_register3_clk' => 'sysgen_dut_to_register3_clk_x0',
21420
              'to_register3_clr' => 'sysgen_dut_to_register3_clr_x0',
21421
              'to_register3_data_in' => 'sysgen_dut_to_register3_data_in_x0',
21422
              'to_register3_dout' => 'from_register7_data_out',
21423
              'to_register3_en' => 'sysgen_dut_to_register3_en_x0',
21424
              'to_register4_ce' => 'sysgen_dut_to_register4_ce_x0',
21425
              'to_register4_clk' => 'sysgen_dut_to_register4_clk_x0',
21426
              'to_register4_clr' => 'sysgen_dut_to_register4_clr_x0',
21427
              'to_register4_data_in' => 'sysgen_dut_to_register4_data_in_x0',
21428
              'to_register4_dout' => 'from_register2_data_out',
21429
              'to_register4_en' => 'sysgen_dut_to_register4_en_x0',
21430
              'to_register5_ce' => 'sysgen_dut_to_register5_ce_x0',
21431
              'to_register5_clk' => 'sysgen_dut_to_register5_clk_x0',
21432
              'to_register5_clr' => 'sysgen_dut_to_register5_clr_x0',
21433
              'to_register5_data_in' => 'sysgen_dut_to_register5_data_in_x0',
21434
              'to_register5_dout' => 'from_register6_data_out',
21435
              'to_register5_en' => 'sysgen_dut_to_register5_en_x0',
21436
              'to_register6_ce' => 'sysgen_dut_to_register6_ce_x0',
21437
              'to_register6_clk' => 'sysgen_dut_to_register6_clk_x0',
21438
              'to_register6_clr' => 'sysgen_dut_to_register6_clr_x0',
21439
              'to_register6_data_in' => 'sysgen_dut_to_register6_data_in_x0',
21440
              'to_register6_dout' => 'from_register8_data_out',
21441
              'to_register6_en' => 'sysgen_dut_to_register6_en_x0',
21442
              'to_register7_ce' => 'sysgen_dut_to_register7_ce_x0',
21443
              'to_register7_clk' => 'sysgen_dut_to_register7_clk_x0',
21444
              'to_register7_clr' => 'sysgen_dut_to_register7_clr_x0',
21445
              'to_register7_data_in' => 'sysgen_dut_to_register7_data_in_x0',
21446
              'to_register7_dout' => 'from_register4_data_out',
21447
              'to_register7_en' => 'sysgen_dut_to_register7_en_x0',
21448
              'to_register8_ce' => 'sysgen_dut_to_register8_ce_x0',
21449
              'to_register8_clk' => 'sysgen_dut_to_register8_clk_x0',
21450
              'to_register8_clr' => 'sysgen_dut_to_register8_clr_x0',
21451
              'to_register8_data_in' => 'sysgen_dut_to_register8_data_in_x0',
21452
              'to_register8_dout' => 'from_register10_data_out',
21453
              'to_register8_en' => 'sysgen_dut_to_register8_en_x0',
21454
              'to_register9_ce' => 'sysgen_dut_to_register9_ce_x0',
21455
              'to_register9_clk' => 'sysgen_dut_to_register9_clk_x0',
21456
              'to_register9_clr' => 'sysgen_dut_to_register9_clr_x0',
21457
              'to_register9_data_in' => 'sysgen_dut_to_register9_data_in_x0',
21458
              'to_register9_dout' => 'from_register11_data_out',
21459
              'to_register9_en' => 'sysgen_dut_to_register9_en_x0',
21460
              'to_register_ce' => 'sysgen_dut_to_register_ce',
21461
              'to_register_clk' => 'sysgen_dut_to_register_clk',
21462
              'to_register_clr' => 'sysgen_dut_to_register_clr',
21463
              'to_register_data_in' => 'sysgen_dut_to_register_data_in',
21464
              'to_register_dout' => 'from_register3_data_out',
21465
              'to_register_en' => 'sysgen_dut_to_register_en',
21466
              'user_int_1o' => 'x_x83',
21467
              'user_int_2o' => 'x_x84',
21468
              'user_int_3o' => 'x_x85',
21469
            },
21470
            'entity' => {
21471
              'attributes' => {
21472
                'entityAlreadyNetlisted' => 1,
21473
                'hdlArchAttributes' => [
21474
                ],
21475
                'hdlCompAttributes' => [
21476
                  [
21477
                    'syn_black_box',
21478
                    'boolean',
21479
                    'true',
21480
                  ],
21481
                  [
21482
                    'box_type',
21483
                    'string',
21484
                    '"black_box"',
21485
                  ],
21486
                ],
21487
                'hdlEntityAttributes' => [
21488
                ],
21489
                'isClkWrapper' => 1,
21490
                'needsComponentDeclaration' => 1,
21491
              },
21492
              'connections' => {
21493
                'bram_rd_addr' => 'bram_rd_addr_net',
21494
                'bram_rd_dout' => 'bram_rd_dout_net',
21495
                'bram_wr_addr' => 'bram_wr_addr_net',
21496
                'bram_wr_din' => 'bram_wr_din_net',
21497
                'bram_wr_en' => 'bram_wr_en_net',
21498
                'clk' => 'clkNet',
21499
                'fifo_rd_count' => 'fifo_rd_count_net',
21500
                'fifo_rd_dout' => 'fifo_rd_dout_net',
21501
                'fifo_rd_empty' => 'fifo_rd_empty_net',
21502
                'fifo_rd_en' => 'fifo_rd_en_net',
21503
                'fifo_rd_pempty' => 'fifo_rd_pempty_net',
21504
                'fifo_rd_valid' => 'fifo_rd_valid_net',
21505
                'fifo_wr_count' => 'fifo_wr_count_net',
21506
                'fifo_wr_din' => 'fifo_wr_din_net',
21507
                'fifo_wr_en' => 'fifo_wr_en_net',
21508
                'fifo_wr_full' => 'fifo_wr_full_net',
21509
                'fifo_wr_pfull' => 'fifo_wr_pfull_net',
21510
                'from_register10_data_out' => 'data_out_x1_net',
21511
                'from_register11_data_out' => 'data_out_x2_net',
21512
                'from_register12_data_out' => 'data_out_x3_net',
21513
                'from_register13_data_out' => 'data_out_x4_net',
21514
                'from_register14_data_out' => 'data_out_x5_net',
21515
                'from_register15_data_out' => 'from_register15_data_out_net',
21516
                'from_register16_data_out' => 'from_register16_data_out_net',
21517
                'from_register17_data_out' => 'data_out_x8_net',
21518
                'from_register18_data_out' => 'data_out_x9_net',
21519
                'from_register19_data_out' => 'from_register19_data_out_net',
21520
                'from_register1_data_out' => 'from_register1_data_out_net',
21521
                'from_register20_data_out' => 'data_out_x12_net',
21522
                'from_register21_data_out' => 'data_out_x13_net',
21523
                'from_register22_data_out' => 'data_out_x14_net',
21524
                'from_register23_data_out' => 'data_out_x15_net',
21525
                'from_register24_data_out' => 'data_out_x16_net',
21526
                'from_register25_data_out' => 'data_out_x17_net',
21527
                'from_register26_data_out' => 'data_out_x18_net',
21528
                'from_register27_data_out' => 'data_out_x19_net',
21529
                'from_register28_data_out' => 'data_out_x20_net',
21530
                'from_register29_data_out' => 'data_out_x21_net',
21531
                'from_register2_data_out' => 'from_register2_data_out_net',
21532
                'from_register30_data_out' => 'data_out_x23_net',
21533
                'from_register31_data_out' => 'data_out_x24_net',
21534
                'from_register32_data_out' => 'data_out_x25_net',
21535
                'from_register33_data_out' => 'data_out_x26_net',
21536
                'from_register3_data_out' => 'data_out_x22_net',
21537
                'from_register4_data_out' => 'data_out_x27_net',
21538
                'from_register5_data_out' => 'data_out_x28_net',
21539
                'from_register6_data_out' => 'data_out_x29_net',
21540
                'from_register7_data_out' => 'data_out_x30_net',
21541
                'from_register8_data_out' => 'data_out_x31_net',
21542
                'from_register9_data_out' => 'data_out_x32_net',
21543
                'from_register_data_out' => 'from_register_data_out_net',
21544
                'rst_i' => 'rst_i_net',
21545
                'rst_o' => 'rst_o_net',
21546
                'to_register10_ce' => 'ce_1_sg_x0',
21547
                'to_register10_clk' => 'clk_1_sg_x0',
21548
                'to_register10_clr' => [
21549
                  'constant',
21550
                  '\'0\'',
21551
                ],
21552
                'to_register10_data_in' => 'data_in_x1_net',
21553
                'to_register10_dout' => 'to_register10_dout_net',
21554
                'to_register10_en' => 'constant6_op_net_x2',
21555
                'to_register11_ce' => 'ce_1_sg_x0',
21556
                'to_register11_clk' => 'clk_1_sg_x0',
21557
                'to_register11_clr' => [
21558
                  'constant',
21559
                  '\'0\'',
21560
                ],
21561
                'to_register11_data_in' => 'data_in_x2_net',
21562
                'to_register11_dout' => 'to_register11_dout_net',
21563
                'to_register11_en' => 'constant6_op_net_x3',
21564
                'to_register12_ce' => 'ce_1_sg_x0',
21565
                'to_register12_clk' => 'clk_1_sg_x0',
21566
                'to_register12_clr' => [
21567
                  'constant',
21568
                  '\'0\'',
21569
                ],
21570
                'to_register12_data_in' => 'data_in_x3_net',
21571
                'to_register12_dout' => 'to_register12_dout_net',
21572
                'to_register12_en' => 'constant6_op_net_x4',
21573
                'to_register13_ce' => 'ce_1_sg_x0',
21574
                'to_register13_clk' => 'clk_1_sg_x0',
21575
                'to_register13_clr' => [
21576
                  'constant',
21577
                  '\'0\'',
21578
                ],
21579
                'to_register13_data_in' => 'data_in_x4_net',
21580
                'to_register13_dout' => 'to_register13_dout_net',
21581
                'to_register13_en' => 'constant6_op_net_x5',
21582
                'to_register14_ce' => 'ce_1_sg_x0',
21583
                'to_register14_clk' => 'clk_1_sg_x0',
21584
                'to_register14_clr' => [
21585
                  'constant',
21586
                  '\'0\'',
21587
                ],
21588
                'to_register14_data_in' => 'data_in_x5_net',
21589
                'to_register14_dout' => 'to_register14_dout_net',
21590
                'to_register14_en' => 'constant6_op_net_x6',
21591
                'to_register15_ce' => 'ce_1_sg_x0',
21592
                'to_register15_clk' => 'clk_1_sg_x0',
21593
                'to_register15_clr' => [
21594
                  'constant',
21595
                  '\'0\'',
21596
                ],
21597
                'to_register15_data_in' => 'data_in_x6_net',
21598
                'to_register15_dout' => 'to_register15_dout_net',
21599
                'to_register15_en' => 'constant6_op_net_x7',
21600
                'to_register16_ce' => 'ce_1_sg_x0',
21601
                'to_register16_clk' => 'clk_1_sg_x0',
21602
                'to_register16_clr' => [
21603
                  'constant',
21604
                  '\'0\'',
21605
                ],
21606
                'to_register16_data_in' => 'data_in_x7_net',
21607
                'to_register16_dout' => 'to_register16_dout_net',
21608
                'to_register16_en' => 'constant6_op_net_x8',
21609
                'to_register17_ce' => 'ce_1_sg_x0',
21610
                'to_register17_clk' => 'clk_1_sg_x0',
21611
                'to_register17_clr' => [
21612
                  'constant',
21613
                  '\'0\'',
21614
                ],
21615
                'to_register17_data_in' => 'data_in_x8_net',
21616
                'to_register17_dout' => 'to_register17_dout_net',
21617
                'to_register17_en' => 'constant6_op_net_x9',
21618
                'to_register18_ce' => 'ce_1_sg_x0',
21619
                'to_register18_clk' => 'clk_1_sg_x0',
21620
                'to_register18_clr' => [
21621
                  'constant',
21622
                  '\'0\'',
21623
                ],
21624
                'to_register18_data_in' => 'data_in_x9_net',
21625
                'to_register18_dout' => 'to_register18_dout_net',
21626
                'to_register18_en' => 'constant6_op_net_x10',
21627
                'to_register19_ce' => 'ce_1_sg_x0',
21628
                'to_register19_clk' => 'clk_1_sg_x0',
21629
                'to_register19_clr' => [
21630
                  'constant',
21631
                  '\'0\'',
21632
                ],
21633
                'to_register19_data_in' => 'data_in_x10_net',
21634
                'to_register19_dout' => 'to_register19_dout_net',
21635
                'to_register19_en' => 'constant6_op_net_x11',
21636
                'to_register1_ce' => 'ce_1_sg_x0',
21637
                'to_register1_clk' => 'clk_1_sg_x0',
21638
                'to_register1_clr' => [
21639
                  'constant',
21640
                  '\'0\'',
21641
                ],
21642
                'to_register1_data_in' => 'data_in_x0_net',
21643
                'to_register1_dout' => 'to_register1_dout_net',
21644
                'to_register1_en' => 'constant6_op_net_x1',
21645
                'to_register20_ce' => 'ce_1_sg_x0',
21646
                'to_register20_clk' => 'clk_1_sg_x0',
21647
                'to_register20_clr' => [
21648
                  'constant',
21649
                  '\'0\'',
21650
                ],
21651
                'to_register20_data_in' => 'data_in_x12_net',
21652
                'to_register20_dout' => 'to_register20_dout_net',
21653
                'to_register20_en' => 'constant6_op_net_x13',
21654
                'to_register21_ce' => 'ce_1_sg_x0',
21655
                'to_register21_clk' => 'clk_1_sg_x0',
21656
                'to_register21_clr' => [
21657
                  'constant',
21658
                  '\'0\'',
21659
                ],
21660
                'to_register21_data_in' => 'data_in_x13_net',
21661
                'to_register21_dout' => 'to_register21_dout_net',
21662
                'to_register21_en' => 'constant6_op_net_x14',
21663
                'to_register22_ce' => 'ce_1_sg_x0',
21664
                'to_register22_clk' => 'clk_1_sg_x0',
21665
                'to_register22_clr' => [
21666
                  'constant',
21667
                  '\'0\'',
21668
                ],
21669
                'to_register22_data_in' => 'data_in_x14_net',
21670
                'to_register22_dout' => 'to_register22_dout_net',
21671
                'to_register22_en' => 'constant6_op_net_x15',
21672
                'to_register23_ce' => 'ce_1_sg_x0',
21673
                'to_register23_clk' => 'clk_1_sg_x0',
21674
                'to_register23_clr' => [
21675
                  'constant',
21676
                  '\'0\'',
21677
                ],
21678
                'to_register23_data_in' => 'data_in_x15_net',
21679
                'to_register23_dout' => 'to_register23_dout_net',
21680
                'to_register23_en' => 'constant6_op_net_x16',
21681
                'to_register24_ce' => 'ce_1_sg_x0',
21682
                'to_register24_clk' => 'clk_1_sg_x0',
21683
                'to_register24_clr' => [
21684
                  'constant',
21685
                  '\'0\'',
21686
                ],
21687
                'to_register24_data_in' => 'data_in_x16_net',
21688
                'to_register24_dout' => 'to_register24_dout_net',
21689
                'to_register24_en' => 'constant6_op_net_x17',
21690
                'to_register25_ce' => 'ce_1_sg_x0',
21691
                'to_register25_clk' => 'clk_1_sg_x0',
21692
                'to_register25_clr' => [
21693
                  'constant',
21694
                  '\'0\'',
21695
                ],
21696
                'to_register25_data_in' => 'data_in_x17_net',
21697
                'to_register25_dout' => 'to_register25_dout_net',
21698
                'to_register25_en' => 'constant6_op_net_x18',
21699
                'to_register26_ce' => 'ce_1_sg_x0',
21700
                'to_register26_clk' => 'clk_1_sg_x0',
21701
                'to_register26_clr' => [
21702
                  'constant',
21703
                  '\'0\'',
21704
                ],
21705
                'to_register26_data_in' => 'data_in_x18_net',
21706
                'to_register26_dout' => 'to_register26_dout_net',
21707
                'to_register26_en' => 'constant6_op_net_x19',
21708
                'to_register27_ce' => 'ce_1_sg_x0',
21709
                'to_register27_clk' => 'clk_1_sg_x0',
21710
                'to_register27_clr' => [
21711
                  'constant',
21712
                  '\'0\'',
21713
                ],
21714
                'to_register27_data_in' => 'data_in_x19_net',
21715
                'to_register27_dout' => 'to_register27_dout_net',
21716
                'to_register27_en' => 'constant6_op_net_x20',
21717
                'to_register2_ce' => 'ce_1_sg_x0',
21718
                'to_register2_clk' => 'clk_1_sg_x0',
21719
                'to_register2_clr' => [
21720
                  'constant',
21721
                  '\'0\'',
21722
                ],
21723
                'to_register2_data_in' => 'data_in_x11_net',
21724
                'to_register2_dout' => 'to_register2_dout_net',
21725
                'to_register2_en' => 'constant6_op_net_x12',
21726
                'to_register3_ce' => 'ce_1_sg_x0',
21727
                'to_register3_clk' => 'clk_1_sg_x0',
21728
                'to_register3_clr' => [
21729
                  'constant',
21730
                  '\'0\'',
21731
                ],
21732
                'to_register3_data_in' => 'data_in_x20_net',
21733
                'to_register3_dout' => 'to_register3_dout_net',
21734
                'to_register3_en' => 'constant6_op_net_x21',
21735
                'to_register4_ce' => 'ce_1_sg_x0',
21736
                'to_register4_clk' => 'clk_1_sg_x0',
21737
                'to_register4_clr' => [
21738
                  'constant',
21739
                  '\'0\'',
21740
                ],
21741
                'to_register4_data_in' => 'data_in_x21_net',
21742
                'to_register4_dout' => 'to_register4_dout_net',
21743
                'to_register4_en' => 'constant6_op_net_x22',
21744
                'to_register5_ce' => 'ce_1_sg_x0',
21745
                'to_register5_clk' => 'clk_1_sg_x0',
21746
                'to_register5_clr' => [
21747
                  'constant',
21748
                  '\'0\'',
21749
                ],
21750
                'to_register5_data_in' => 'data_in_x22_net',
21751
                'to_register5_dout' => 'to_register5_dout_net',
21752
                'to_register5_en' => 'constant6_op_net_x23',
21753
                'to_register6_ce' => 'ce_1_sg_x0',
21754
                'to_register6_clk' => 'clk_1_sg_x0',
21755
                'to_register6_clr' => [
21756
                  'constant',
21757
                  '\'0\'',
21758
                ],
21759
                'to_register6_data_in' => 'data_in_x23_net',
21760
                'to_register6_dout' => 'to_register6_dout_net',
21761
                'to_register6_en' => 'constant6_op_net_x24',
21762
                'to_register7_ce' => 'ce_1_sg_x0',
21763
                'to_register7_clk' => 'clk_1_sg_x0',
21764
                'to_register7_clr' => [
21765
                  'constant',
21766
                  '\'0\'',
21767
                ],
21768
                'to_register7_data_in' => 'data_in_x24_net',
21769
                'to_register7_dout' => 'to_register7_dout_net',
21770
                'to_register7_en' => 'constant6_op_net_x25',
21771
                'to_register8_ce' => 'ce_1_sg_x0',
21772
                'to_register8_clk' => 'clk_1_sg_x0',
21773
                'to_register8_clr' => [
21774
                  'constant',
21775
                  '\'0\'',
21776
                ],
21777
                'to_register8_data_in' => 'data_in_x25_net',
21778
                'to_register8_dout' => 'to_register8_dout_net',
21779
                'to_register8_en' => 'constant6_op_net_x26',
21780
                'to_register9_ce' => 'ce_1_sg_x0',
21781
                'to_register9_clk' => 'clk_1_sg_x0',
21782
                'to_register9_clr' => [
21783
                  'constant',
21784
                  '\'0\'',
21785
                ],
21786
                'to_register9_data_in' => 'data_in_x26_net',
21787
                'to_register9_dout' => 'to_register9_dout_net',
21788
                'to_register9_en' => 'constant6_op_net_x27',
21789
                'to_register_ce' => 'ce_1_sg_x0',
21790
                'to_register_clk' => 'clk_1_sg_x0',
21791
                'to_register_clr' => [
21792
                  'constant',
21793
                  '\'0\'',
21794
                ],
21795
                'to_register_data_in' => 'data_in_net',
21796
                'to_register_dout' => 'to_register_dout_net',
21797
                'to_register_en' => 'constant6_op_net_x0',
21798
                'user_int_1o' => 'user_int_1o_net',
21799
                'user_int_2o' => 'user_int_2o_net',
21800
                'user_int_3o' => 'user_int_3o_net',
21801
              },
21802
              'entityName' => 'user_logic_cw',
21803
              'nets' => {
21804
                'bram_rd_addr_net' => {
21805
                  'attributes' => {
21806
                    'hdlNetAttributes' => [
21807
                    ],
21808
                  },
21809
                  'hdlType' => 'std_logic_vector(11 downto 0)',
21810
                  'width' => 12,
21811
                },
21812
                'bram_rd_dout_net' => {
21813
                  'attributes' => {
21814
                    'hdlNetAttributes' => [
21815
                    ],
21816
                  },
21817
                  'hdlType' => 'std_logic_vector(63 downto 0)',
21818
                  'width' => 64,
21819
                },
21820
                'bram_wr_addr_net' => {
21821
                  'attributes' => {
21822
                    'hdlNetAttributes' => [
21823
                    ],
21824
                  },
21825
                  'hdlType' => 'std_logic_vector(11 downto 0)',
21826
                  'width' => 12,
21827
                },
21828
                'bram_wr_din_net' => {
21829
                  'attributes' => {
21830
                    'hdlNetAttributes' => [
21831
                    ],
21832
                  },
21833
                  'hdlType' => 'std_logic_vector(63 downto 0)',
21834
                  'width' => 64,
21835
                },
21836
                'bram_wr_en_net' => {
21837
                  'attributes' => {
21838
                    'hdlNetAttributes' => [
21839
                    ],
21840
                  },
21841
                  'hdlType' => 'std_logic_vector(7 downto 0)',
21842
                  'width' => 8,
21843
                },
21844
                'ce_1_sg_x0' => {
21845
                  'attributes' => {
21846
                    'hdlNetAttributes' => [
21847
                      [
21848
                        'MAX_FANOUT',
21849
                        'string',
21850
                        '"REDUCE"',
21851
                      ],
21852
                    ],
21853
                  },
21854
                  'hdlType' => 'std_logic',
21855
                  'width' => 1,
21856
                },
21857
                'clkNet' => {
21858
                  'attributes' => {
21859
                    'hdlNetAttributes' => [
21860
                    ],
21861
                  },
21862
                  'hdlType' => 'std_logic',
21863
                  'width' => 1,
21864
                },
21865
                'clk_1_sg_x0' => {
21866
                  'attributes' => {
21867
                    'hdlNetAttributes' => [
21868
                    ],
21869
                  },
21870
                  'hdlType' => 'std_logic',
21871
                  'width' => 1,
21872
                },
21873
                'constant6_op_net_x0' => {
21874
                  'attributes' => {
21875
                    'hdlNetAttributes' => [
21876
                    ],
21877
                  },
21878
                  'hdlType' => 'std_logic',
21879
                  'width' => 1,
21880
                },
21881
                'constant6_op_net_x1' => {
21882
                  'attributes' => {
21883
                    'hdlNetAttributes' => [
21884
                    ],
21885
                  },
21886
                  'hdlType' => 'std_logic',
21887
                  'width' => 1,
21888
                },
21889
                'constant6_op_net_x10' => {
21890
                  'attributes' => {
21891
                    'hdlNetAttributes' => [
21892
                    ],
21893
                  },
21894
                  'hdlType' => 'std_logic',
21895
                  'width' => 1,
21896
                },
21897
                'constant6_op_net_x11' => {
21898
                  'attributes' => {
21899
                    'hdlNetAttributes' => [
21900
                    ],
21901
                  },
21902
                  'hdlType' => 'std_logic',
21903
                  'width' => 1,
21904
                },
21905
                'constant6_op_net_x12' => {
21906
                  'attributes' => {
21907
                    'hdlNetAttributes' => [
21908
                    ],
21909
                  },
21910
                  'hdlType' => 'std_logic',
21911
                  'width' => 1,
21912
                },
21913
                'constant6_op_net_x13' => {
21914
                  'attributes' => {
21915
                    'hdlNetAttributes' => [
21916
                    ],
21917
                  },
21918
                  'hdlType' => 'std_logic',
21919
                  'width' => 1,
21920
                },
21921
                'constant6_op_net_x14' => {
21922
                  'attributes' => {
21923
                    'hdlNetAttributes' => [
21924
                    ],
21925
                  },
21926
                  'hdlType' => 'std_logic',
21927
                  'width' => 1,
21928
                },
21929
                'constant6_op_net_x15' => {
21930
                  'attributes' => {
21931
                    'hdlNetAttributes' => [
21932
                    ],
21933
                  },
21934
                  'hdlType' => 'std_logic',
21935
                  'width' => 1,
21936
                },
21937
                'constant6_op_net_x16' => {
21938
                  'attributes' => {
21939
                    'hdlNetAttributes' => [
21940
                    ],
21941
                  },
21942
                  'hdlType' => 'std_logic',
21943
                  'width' => 1,
21944
                },
21945
                'constant6_op_net_x17' => {
21946
                  'attributes' => {
21947
                    'hdlNetAttributes' => [
21948
                    ],
21949
                  },
21950
                  'hdlType' => 'std_logic',
21951
                  'width' => 1,
21952
                },
21953
                'constant6_op_net_x18' => {
21954
                  'attributes' => {
21955
                    'hdlNetAttributes' => [
21956
                    ],
21957
                  },
21958
                  'hdlType' => 'std_logic',
21959
                  'width' => 1,
21960
                },
21961
                'constant6_op_net_x19' => {
21962
                  'attributes' => {
21963
                    'hdlNetAttributes' => [
21964
                    ],
21965
                  },
21966
                  'hdlType' => 'std_logic',
21967
                  'width' => 1,
21968
                },
21969
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21970
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21971
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21972
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21973
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21974
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21975
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21976
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21977
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21978
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21979
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21980
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21981
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21982
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21983
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21984
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21985
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21986
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21987
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21988
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21989
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21990
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21991
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21992
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21993
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21994
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21995
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21996
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21997
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21998
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21999
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22000
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22001
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22002
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22003
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22004
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22005
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22006
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22007
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22008
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22010
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22011
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22012
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22013
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22014
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22015
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22016
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22017
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22018
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22019
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22020
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22021
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22022
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22023
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22024
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22025
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22026
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22027
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22028
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22029
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22030
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22031
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22032
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22033
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22034
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22035
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22036
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22037
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22038
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22039
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22040
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22041
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22042
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22043
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22044
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22045
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22046
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22047
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22048
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22049
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22050
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22051
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22052
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22053
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22054
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22055
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22056
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22057
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22058
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22059
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22060
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22061
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22062
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22063
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22064
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22065
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22066
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22067
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22068
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22069
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22070
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22071
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22072
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22073
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22074
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22075
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22076
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22077
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22078
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22079
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22080
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22081
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22082
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22083
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22084
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22085
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22086
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22087
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22088
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22089
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22090
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22091
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22092
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22093
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22094
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22095
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22096
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22097
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22098
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22099
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22100
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22101
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22102
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22103
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22104
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22105
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22106
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22107
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22108
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22109
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22110
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22111
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22112
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22113
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22114
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22115
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22116
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22117
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22118
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22119
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22120
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22121
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22122
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22123
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22124
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22125
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22126
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22127
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22128
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22129
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22130
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22131
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22132
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22133
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22134
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22135
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22136
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22137
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22138
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22139
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22140
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22141
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22142
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22143
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22144
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22145
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22146
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22147
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22148
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22149
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22150
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22151
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22152
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22153
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22154
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22155
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22156
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22157
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22158
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22159
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22160
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22161
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22162
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22163
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22164
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22165
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22166
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22167
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22168
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22169
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22170
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22171
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22172
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22173
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22174
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22175
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22176
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22177
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22178
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22179
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22180
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22181
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22182
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22183
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22184
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22185
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22186
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22187
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22188
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22189
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22190
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22191
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22192
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22193
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22194
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22195
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22196
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22197
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22198
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22199
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22200
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22201
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22202
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22203
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22204
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22205
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22206
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22207
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22208
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22209
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22210
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22211
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22212
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22213
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22214
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22215
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22216
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22217
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22218
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22219
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22220
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22221
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22222
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22223
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22224
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22225
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22226
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22227
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22228
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22229
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22230
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22231
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22232
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22233
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22234
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22235
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22236
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22237
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22238
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22239
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22240
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22241
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22242
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22243
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22244
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22245
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22246
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22247
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22248
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22249
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22250
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22251
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22252
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22253
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22254
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22255
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22256
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22257
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22258
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22259
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22260
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22261
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22262
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22263
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22264
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22265
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22266
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22267
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22268
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22269
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22270
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22271
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22272
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22273
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22274
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22275
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22276
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22277
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22278
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22279
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22280
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22281
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22282
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22283
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22284
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22285
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22286
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22287
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22288
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22289
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22290
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22291
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22292
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22293
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22294
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22295
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22296
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22297
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22298
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22299
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22300
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22301
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22302
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22303
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22304
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22305
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22306
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22307
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22308
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22309
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22310
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22311
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22312
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22313
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22314
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22315
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22316
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22317
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22318
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22319
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22320
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22321
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22322
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22323
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22324
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22325
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22326
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22327
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22328
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22329
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22330
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22331
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22332
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22333
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22334
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22335
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22336
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22337
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22338
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22339
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22340
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22341
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22342
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22343
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22344
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22345
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22346
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22347
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22348
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22349
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22350
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22351
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22352
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22353
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22354
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22355
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22356
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22357
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22358
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22359
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22360
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22361
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22362
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22363
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22364
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22365
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22366
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22367
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22368
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22369
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22370
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22371
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22372
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22373
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22374
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22375
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22376
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22377
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22378
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22379
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22380
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22381
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22382
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22383
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22384
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22385
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22386
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22387
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22388
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22389
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22390
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22391
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22392
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22393
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22394
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22395
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22396
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22397
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22398
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22399
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22400
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22401
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22402
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22403
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22404
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22405
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22406
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22407
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22408
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22409
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22410
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22411
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22412
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22413
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22414
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22415
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22416
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22417
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22418
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22419
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22420
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22421
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22422
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22423
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22424
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22425
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22426
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22427
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22428
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22429
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22430
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22431
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22432
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22433
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22434
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22435
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22436
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22437
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22438
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22439
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22440
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22441
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22442
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22443
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22444
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22445
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22446
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22447
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22448
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22449
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22450
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22451
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22452
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22453
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22454
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22455
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22456
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22457
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22458
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22459
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22460
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22461
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22462
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22463
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22464
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22465
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22466
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22467
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22468
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22469
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22470
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22471
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22472
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22473
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22474
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22475
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22476
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22477
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22478
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22479
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22480
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22481
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22482
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22483
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22484
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22485
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22486
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22487
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22488
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22489
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22490
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22491
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22492
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22493
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22494
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22495
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22496
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22497
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22498
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22499
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22500
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22501
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22502
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22503
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22504
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22505
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22506
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22507
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22508
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22509
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22510
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22511
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22512
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22513
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22514
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22515
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22516
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22517
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22518
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22519
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22520
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22521
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22522
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22523
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22524
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22525
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22526
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22527
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22528
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22529
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22530
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22531
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22532
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22533
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22534
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22535
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22536
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22537
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22538
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22539
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22540
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22541
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22542
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22543
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22544
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22545
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22546
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22547
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22548
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22549
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22550
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22551
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22552
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22553
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22554
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22555
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22556
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22557
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22558
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22559
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22560
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22561
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22562
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22563
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22566
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22567
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22568
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22569
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22570
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22571
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22573
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22574
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22577
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22579
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22581
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22582
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22583
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22585
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22586
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22587
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22589
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22590
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22591
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22592
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22593
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22594
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22595
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22597
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22598
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22599
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22600
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22601
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22602
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22603
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22604
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22605
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22606
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22607
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22608
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22609
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22610
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22611
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22612
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22613
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22614
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22615
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22616
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22617
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22618
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22619
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22620
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22621
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22622
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22623
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22624
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22625
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22626
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22627
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22628
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22629
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22630
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22631
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22632
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22633
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22634
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22635
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22636
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22637
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22638
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22639
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22640
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22641
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22642
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22643
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22644
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22645
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22646
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22647
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22648
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22649
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22650
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22651
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22652
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22653
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22654
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22655
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22656
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22657
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22658
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22659
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22660
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22661
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22662
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22663
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22664
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22665
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22666
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22667
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22668
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22669
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22670
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22671
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22672
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22673
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22674
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22675
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22676
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22677
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22678
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22679
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22680
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22681
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22682
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22683
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22684
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22685
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22686
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22687
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22688
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22690
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22691
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22692
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22693
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22694
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22695
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22696
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22697
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22699
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22700
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22701
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22702
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22704
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22705
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22706
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22709
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22710
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22711
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22712
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22713
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22714
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22715
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22716
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22717
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22718
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22720
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22721
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22722
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22723
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22724
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22725
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22726
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22727
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22728
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22729
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22730
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22731
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22732
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22733
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22734
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22735
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22736
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22737
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22738
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22739
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22740
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22741
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22742
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22743
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22744
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22745
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22746
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22747
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22748
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22749
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22750
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22751
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22752
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22753
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22754
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22755
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22756
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22757
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22758
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22760
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22761
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22762
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22764
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22765
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22766
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22767
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22768
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22769
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22770
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22771
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22772
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22773
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22774
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22775
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22777
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22778
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22779
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22780
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22781
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22782
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22783
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22784
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22785
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22786
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22787
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22788
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22789
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22790
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22792
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22793
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22794
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22795
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22796
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22797
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22798
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22799
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22800
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22801
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22802
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22803
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22804
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22805
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22806
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22807
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22808
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22809
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22810
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22811
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22812
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22813
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22814
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22815
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22816
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22817
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22818
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22819
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22820
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22821
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22822
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22823
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22824
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22825
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22826
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22827
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22828
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22829
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22830
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22831
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22832
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22833
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22834
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22835
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22836
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22837
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22838
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22839
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22840
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22841
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22842
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22843
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22844
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22845
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22846
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22847
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22848
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22849
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22850
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22851
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22852
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22853
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22854
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22855
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22856
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22857
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22858
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22859
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22860
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22861
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22862
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22863
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22864
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22865
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22866
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22867
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22868
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22869
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22870
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22871
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22872
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22873
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22874
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22875
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22876
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22877
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22878
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22879
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22880
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22881
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22882
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22883
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22884
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22885
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22886
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22887
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22888
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22889
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22890
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22891
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22892
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22893
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22894
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22895
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22896
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22897
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22898
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22899
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22900
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22901
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22902
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22903
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22904
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22905
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22906
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22907
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22908
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22909
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22910
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22911
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22912
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22913
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22914
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22915
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22916
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22917
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22918
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22919
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22920
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22921
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22922
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22923
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22924
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22925
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22926
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22927
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22928
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22929
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22930
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22931
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22932
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22933
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22934
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22935
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22936
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22937
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22938
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22939
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22940
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22941
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22942
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22943
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22944
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22945
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22946
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22947
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22948
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22949
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22950
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22951
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22952
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22953
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22954
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22955
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22956
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22957
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22958
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22959
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22960
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22961
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22962
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22963
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22964
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22965
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22966
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22967
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22968
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22969
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22970
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22971
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22972
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22973
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22974
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22975
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22976
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22977
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22978
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22979
                    'simulinkName' => 'PCIe_UserLogic_00/USER_LOGIC/BRAM_rd_addr/BRAM_rd_addr',
22980
                    'source_block' => 'PCIe_UserLogic_00/USER_LOGIC/BRAM_rd_addr',
22981
                    'timingConstraint' => 'none',
22982
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22983
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22984
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22985
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22986
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22987
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22988
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22989
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22990
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22991
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22992
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22993
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22994
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22995
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22996
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22997
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22998
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22999
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23000
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23001
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23002
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23003
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23004
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23005
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23006
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23007
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23008
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23009
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23010
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23011
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23012
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23013
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23014
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23015
                    'simulinkName' => 'PCIe_UserLogic_00/USER_LOGIC/BRAM_wr_addr/BRAM_wr_addr',
23016
                    'source_block' => 'PCIe_UserLogic_00/USER_LOGIC/BRAM_wr_addr',
23017
                    'timingConstraint' => 'none',
23018
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23019
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23020
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23021
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23022
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23023
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23024
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23025
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23026
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23027
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23028
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23029
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23030
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23031
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23032
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23033
                    'simulinkName' => 'PCIe_UserLogic_00/USER_LOGIC/BRAM_wr_din/BRAM_wr_din',
23034
                    'source_block' => 'PCIe_UserLogic_00/USER_LOGIC/BRAM_wr_din',
23035
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23036
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23037
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23038
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23039
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23040
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23041
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23042
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23043
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23044
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23045
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23046
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23047
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23048
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23049
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23050
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23051
                    'simulinkName' => 'PCIe_UserLogic_00/USER_LOGIC/BRAM_wr_en/BRAM_wr_en',
23052
                    'source_block' => 'PCIe_UserLogic_00/USER_LOGIC/BRAM_wr_en',
23053
                    'timingConstraint' => 'none',
23054
                    'type' => 'UFix_8_0',
23055
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23056
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23057
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23058
                  'width' => 8,
23059
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23060
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23061
                  'attributes' => {
23062
                    'defaultHdlValue' => '\'1\'',
23063
                    'domain' => 'default',
23064
                    'group' => 6,
23065
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23066
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23067
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23068
                  'direction' => 'in',
23069
                  'hdlType' => 'std_logic',
23070
                  'width' => 1,
23071
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23072
                'clk' => {
23073
                  'attributes' => {
23074
                    'domain' => 'default',
23075
                    'group' => 6,
23076
                    'isClk' => 1,
23077
                    'period' => 1,
23078
                    'type' => 'logic',
23079
                  },
23080
                  'direction' => 'in',
23081
                  'hdlType' => 'std_logic',
23082
                  'width' => 1,
23083
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23084
                'fifo_rd_count' => {
23085
                  'attributes' => {
23086
                    'bin_pt' => 0,
23087
                    'inputFile' => 'pcie_userlogic_00_user_logic_fifo_rd_count.dat',
23088
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23089
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23090
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23091
                    'period' => 1,
23092
                    'port_id' => 0,
23093
                    'simulinkName' => 'PCIe_UserLogic_00/USER_LOGIC/FIFO_rd_count/FIFO_rd_count',
23094
                    'source_block' => 'PCIe_UserLogic_00/USER_LOGIC/FIFO_rd_count',
23095
                    'timingConstraint' => 'none',
23096
                    'type' => 'UFix_15_0',
23097
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23098
                  'direction' => 'in',
23099
                  'hdlType' => 'std_logic_vector(14 downto 0)',
23100
                  'width' => 15,
23101
                },
23102
                'fifo_rd_dout' => {
23103
                  'attributes' => {
23104
                    'bin_pt' => 0,
23105
                    'inputFile' => 'pcie_userlogic_00_user_logic_fifo_rd_dout.dat',
23106
                    'is_floating_block' => 1,
23107
                    'is_gateway_port' => 1,
23108
                    'must_be_hdl_vector' => 1,
23109
                    'period' => 1,
23110
                    'port_id' => 0,
23111
                    'simulinkName' => 'PCIe_UserLogic_00/USER_LOGIC/FIFO_rd_dout/FIFO_rd_dout',
23112
                    'source_block' => 'PCIe_UserLogic_00/USER_LOGIC/FIFO_rd_dout',
23113
                    'timingConstraint' => 'none',
23114
                    'type' => 'UFix_72_0',
23115
                  },
23116
                  'direction' => 'in',
23117
                  'hdlType' => 'std_logic_vector(71 downto 0)',
23118
                  'width' => 72,
23119
                },
23120
                'fifo_rd_empty' => {
23121
                  'attributes' => {
23122
                    'bin_pt' => 0,
23123
                    'inputFile' => 'pcie_userlogic_00_user_logic_fifo_rd_empty.dat',
23124
                    'is_floating_block' => 1,
23125
                    'is_gateway_port' => 1,
23126
                    'must_be_hdl_vector' => 1,
23127
                    'period' => 1,
23128
                    'port_id' => 0,
23129
                    'simulinkName' => 'PCIe_UserLogic_00/USER_LOGIC/FIFO_rd_empty/FIFO_rd_empty',
23130
                    'source_block' => 'PCIe_UserLogic_00/USER_LOGIC/FIFO_rd_empty',
23131
                    'timingConstraint' => 'none',
23132
                    'type' => 'Bool',
23133
                  },
23134
                  'direction' => 'in',
23135
                  'hdlType' => 'std_logic',
23136
                  'width' => 1,
23137
                },
23138
                'fifo_rd_en' => {
23139
                  'attributes' => {
23140
                    'bin_pt' => 0,
23141
                    'inputFile' => 'pcie_userlogic_00_user_logic_fifo_rd_en.dat',
23142
                    'is_floating_block' => 1,
23143
                    'is_gateway_port' => 1,
23144
                    'must_be_hdl_vector' => 1,
23145
                    'period' => 1,
23146
                    'port_id' => 0,
23147
                    'simulinkName' => 'PCIe_UserLogic_00/USER_LOGIC/FIFO_rd_en/FIFO_rd_en',
23148
                    'source_block' => 'PCIe_UserLogic_00/USER_LOGIC/FIFO_rd_en',
23149
                    'timingConstraint' => 'none',
23150
                    'type' => 'Bool',
23151
                  },
23152
                  'direction' => 'out',
23153
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23154
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23155
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23156
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23157
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23158
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23159
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23160
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23161
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23162
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23163
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23165
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23166
                    'source_block' => 'PCIe_UserLogic_00/USER_LOGIC/FIFO_rd_pempty',
23167
                    'timingConstraint' => 'none',
23168
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23169
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23170
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23171
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23172
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23173
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23174
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23175
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23176
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23177
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23183
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23184
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23185
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23186
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23187
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23188
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23189
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23190
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23191
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23192
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23193
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23194
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23195
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23199
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23200
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23201
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23202
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23203
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23204
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23205
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23206
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23207
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23208
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23209
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23210
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23211
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23212
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23213
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23214
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23215
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23216
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23217
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23218
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23219
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23220
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23221
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23222
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23223
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23224
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23225
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23226
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23227
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23228
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23229
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23230
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23231
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23232
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23233
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23234
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23235
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23236
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23237
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23238
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23239
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23240
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23241
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23242
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23243
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23244
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23245
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23246
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23247
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23248
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23249
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23250
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23251
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23252
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23253
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23254
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23255
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23256
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23257
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23258
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23259
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23260
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23261
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23262
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23263
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23264
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23265
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23266
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23267
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23268
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23269
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23270
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23271
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23272
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23273
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23274
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23275
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23276
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23277
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23278
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23279
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23280
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23281
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23282
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23283
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23284
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23285
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23286
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23287
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23288
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23289
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23290
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23291
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23292
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23293
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23294
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23295
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23296
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23297
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23298
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23299
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23300
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23301
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23302
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23303
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23304
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23305
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23306
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23307
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23308
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23309
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23310
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23311
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23312
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23313
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23314
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23315
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23316
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23317
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23318
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23319
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23320
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23321
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23322
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23323
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23324
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23325
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23326
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23327
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23329
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23330
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23331
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23332
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23333
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23334
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23335
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23336
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23337
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23338
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23339
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23340
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23341
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23342
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23343
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23345
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23346
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23347
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23348
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23349
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23350
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23351
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23352
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23353
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23354
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23355
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23356
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23357
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23358
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23359
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23360
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23361
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23362
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23363
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23364
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23365
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23366
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23367
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23368
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23369
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23371
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23373
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23374
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23375
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23376
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23377
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23378
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23379
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23380
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23381
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23382
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23383
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23384
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23385
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23387
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23388
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23389
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23390
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23391
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23392
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23393
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23394
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23395
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23396
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23397
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23399
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23401
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23402
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23403
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23404
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23405
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23406
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23407
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23408
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23409
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23410
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23411
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23412
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23413
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23414
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23415
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23416
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23417
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23418
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23419
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23420
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23421
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23422
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23423
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23424
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23425
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23426
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23427
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23428
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23429
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23430
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23431
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23432
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23433
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23434
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23435
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23436
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23437
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23438
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23439
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23440
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23441
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23442
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23443
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23444
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23445
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23446
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23447
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23448
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23449
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23450
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23451
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23452
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23453
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23454
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23455
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23456
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23457
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23458
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23459
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23460
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23461
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23462
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23463
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23464
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23465
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23466
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23467
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23468
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23469
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23470
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23471
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23472
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23473
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23474
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23475
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23476
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23477
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23478
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23479
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23480
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23481
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23482
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23483
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23484
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23485
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23486
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23487
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23488
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23489
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23490
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23491
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23492
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23493
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23494
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23495
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23496
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23497
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23498
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23499
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23500
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23501
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23502
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23503
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23504
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23505
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23506
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23507
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23508
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23509
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23510
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23511
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23512
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23513
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23514
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23515
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23516
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23517
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23518
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23519
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23520
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23521
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23522
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23523
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23524
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23525
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23526
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23527
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23528
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23529
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23530
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23531
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23532
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23533
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23534
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23535
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23536
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23537
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23538
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23539
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23540
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23541
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23542
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23543
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23544
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23545
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23546
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23547
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23548
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23549
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23550
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23551
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23552
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23553
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23554
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23555
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23556
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23557
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23558
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23559
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23560
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23561
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23562
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23563
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23564
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23565
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23566
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23567
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23568
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23569
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23570
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23571
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23572
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23573
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23574
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23575
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23576
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23577
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23578
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23579
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23580
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23581
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23582
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23583
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23584
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23585
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23586
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23587
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23588
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23589
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23590
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23591
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23592
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23593
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23594
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23595
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23596
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23597
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23598
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23599
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23600
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23601
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23602
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23603
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23604
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23605
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23606
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23607
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23608
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23609
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23610
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23611
                    'simulinkName' => 'PCIe_UserLogic_00/USER_LOGIC/From Register31/data_out',
23612
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23613
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23614
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23615
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23616
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23617
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23618
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23619
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23620
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23621
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23622
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23623
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23624
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23625
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24095
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24110
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24119
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24121
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24122
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24123
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24124
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24137
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24140
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24141
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24143
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24144
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24146
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24147
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24560
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24650
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24684
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24688
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24705
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24723
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24724
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24732
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24737
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24743
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24780
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24787
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24795
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24801
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24806
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24810
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24811
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24812
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24814
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24815
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24816
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24817
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24818
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24819
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24820
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24821
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24823
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24825
                    'simulinkName' => 'PCIe_UserLogic_00/USER_LOGIC/To Register21/data_in',
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24828
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24829
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24830
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24831
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24833
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24834
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24835
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24836
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24839
                    'simulinkName' => 'PCIe_UserLogic_00/USER_LOGIC/To Register21/dout',
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24844
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24845
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24847
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24848
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24850
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                    'port_id' => 1,
24853
                    'simulinkName' => 'PCIe_UserLogic_00/USER_LOGIC/To Register21/en',
24854
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24856
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                  'hdlType' => 'std_logic_vector(0 downto 0)',
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24860
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24862
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24864
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24865
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24869
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24870
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24874
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24875
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24876
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24877
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24878
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24880
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24882
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24884
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24887
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24888
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24889
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24890
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24892
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24893
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24894
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24895
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24896
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24898
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24899
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24900
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24901
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24902
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24903
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24904
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24905
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24907
                    'simulinkName' => 'PCIe_UserLogic_00/USER_LOGIC/To Register22/data_in',
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24910
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24911
                  'hdlType' => 'std_logic_vector(0 downto 0)',
24912
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24913
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24914
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24915
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24916
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24917
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24918
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24919
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24920
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24921
                    'simulinkName' => 'PCIe_UserLogic_00/USER_LOGIC/To Register22/dout',
24922
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24924
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24925
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24926
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24927
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24928
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24929
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24930
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24931
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24932
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24933
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24934
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                    'simulinkName' => 'PCIe_UserLogic_00/USER_LOGIC/To Register22/en',
24936
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24938
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24939
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24940
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24941
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24942
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24943
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24944
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24946
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24947
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24948
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24949
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24950
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24951
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24953
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24956
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24957
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24960
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24961
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24962
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24963
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24964
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24965
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24966
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24967
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24968
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24969
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24970
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24971
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24972
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24973
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24974
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24975
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24977
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24978
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24979
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24980
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24981
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24982
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24983
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24984
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24985
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24986
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24987
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24989
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24992
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24993
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24994
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24995
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24996
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24997
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24998
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24999
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25000
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25001
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25003
                    'simulinkName' => 'PCIe_UserLogic_00/USER_LOGIC/To Register23/dout',
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25008
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25009
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25010
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25011
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25012
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                    'simulinkName' => 'PCIe_UserLogic_00/USER_LOGIC/To Register23/en',
25018
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25019
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25020
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25021
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25022
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25023
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25024
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25025
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25026
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25027
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25028
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25029
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25030
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25031
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25032
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25033
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25034
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25035
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25036
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25037
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25038
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25039
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25040
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25041
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25042
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25043
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25044
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25045
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25046
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25047
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25048
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25049
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25050
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25051
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25052
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25053
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25054
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25055
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25056
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25057
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25058
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25059
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25060
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25061
                  'hdlType' => 'std_logic',
25062
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25063
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25064
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25065
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25066
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25067
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25068
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25069
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25070
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25071
                    'simulinkName' => 'PCIe_UserLogic_00/USER_LOGIC/To Register24/data_in',
25072
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25073
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25074
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25075
                  'hdlType' => 'std_logic_vector(0 downto 0)',
25076
                  'width' => 1,
25077
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25078
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25079
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25080
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25081
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25082
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25083
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25084
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25085
                    'simulinkName' => 'PCIe_UserLogic_00/USER_LOGIC/To Register24/dout',
25086
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25087
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25088
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25089
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25090
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25091
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25092
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25093
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25094
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25095
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25096
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25097
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25098
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25099
                    'simulinkName' => 'PCIe_UserLogic_00/USER_LOGIC/To Register24/en',
25100
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25103
                  'hdlType' => 'std_logic_vector(0 downto 0)',
25104
                  'width' => 1,
25105
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25106
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25107
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25108
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25109
                    'group' => 1,
25110
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25111
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25112
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25113
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25114
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25115
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25116
                  'hdlType' => 'std_logic',
25117
                  'width' => 1,
25118
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25119
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25120
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25121
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25122
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25123
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25124
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25125
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25126
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25127
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25128
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25129
                  'hdlType' => 'std_logic',
25130
                  'width' => 1,
25131
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25132
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25133
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25134
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25135
                    'group' => 1,
25136
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25137
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25138
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25139
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25140
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25141
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25142
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25143
                  'hdlType' => 'std_logic',
25144
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25145
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25146
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25147
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25148
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25149
                    'is_floating_block' => 1,
25150
                    'must_be_hdl_vector' => 1,
25151
                    'period' => 1,
25152
                    'port_id' => 0,
25153
                    'simulinkName' => 'PCIe_UserLogic_00/USER_LOGIC/To Register25/data_in',
25154
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25155
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25156
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25157
                  'hdlType' => 'std_logic_vector(31 downto 0)',
25158
                  'width' => 32,
25159
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25160
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25161
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25162
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25163
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25164
                    'must_be_hdl_vector' => 1,
25165
                    'period' => 1,
25166
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25167
                    'simulinkName' => 'PCIe_UserLogic_00/USER_LOGIC/To Register25/dout',
25168
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25169
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25170
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25171
                  'hdlType' => 'std_logic_vector(31 downto 0)',
25172
                  'width' => 32,
25173
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25174
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25175
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25176
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25177
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25178
                    'must_be_hdl_vector' => 1,
25179
                    'period' => 1,
25180
                    'port_id' => 1,
25181
                    'simulinkName' => 'PCIe_UserLogic_00/USER_LOGIC/To Register25/en',
25182
                    'type' => 'Bool',
25183
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25184
                  'direction' => 'out',
25185
                  'hdlType' => 'std_logic_vector(0 downto 0)',
25186
                  'width' => 1,
25187
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25188
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25189
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25190
                    'domain' => '',
25191
                    'group' => 1,
25192
                    'isCe' => 1,
25193
                    'is_floating_block' => 1,
25194
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25195
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25196
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25197
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25198
                  'hdlType' => 'std_logic',
25199
                  'width' => 1,
25200
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25201
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25202
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25203
                    'domain' => '',
25204
                    'group' => 1,
25205
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25206
                    'is_floating_block' => 1,
25207
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25208
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25209
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25210
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25211
                  'hdlType' => 'std_logic',
25212
                  'width' => 1,
25213
                },
25214
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25215
                  'attributes' => {
25216
                    'domain' => '',
25217
                    'group' => 1,
25218
                    'isClr' => 1,
25219
                    'is_floating_block' => 1,
25220
                    'period' => 1,
25221
                    'type' => 'logic',
25222
                    'valid_bit_used' => 0,
25223
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25224
                  'direction' => 'out',
25225
                  'hdlType' => 'std_logic',
25226
                  'width' => 1,
25227
                },
25228
                'to_register26_data_in' => {
25229
                  'attributes' => {
25230
                    'bin_pt' => 0,
25231
                    'is_floating_block' => 1,
25232
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25233
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25234
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25235
                    'simulinkName' => 'PCIe_UserLogic_00/USER_LOGIC/To Register26/data_in',
25236
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25237
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25238
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25239
                  'hdlType' => 'std_logic_vector(0 downto 0)',
25240
                  'width' => 1,
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25242
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25243
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25244
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25245
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25246
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25248
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25249
                    'simulinkName' => 'PCIe_UserLogic_00/USER_LOGIC/To Register26/dout',
25250
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25251
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25252
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25253
                  'hdlType' => 'std_logic_vector(0 downto 0)',
25254
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25257
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25258
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25259
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25260
                    'must_be_hdl_vector' => 1,
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25262
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25263
                    'simulinkName' => 'PCIe_UserLogic_00/USER_LOGIC/To Register26/en',
25264
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25265
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25266
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25267
                  'hdlType' => 'std_logic_vector(0 downto 0)',
25268
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25270
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25271
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25272
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25273
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25274
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25275
                    'is_floating_block' => 1,
25276
                    'period' => 1,
25277
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25278
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25279
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25280
                  'hdlType' => 'std_logic',
25281
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25282
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25283
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25284
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25285
                    'domain' => '',
25286
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25287
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25288
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25289
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25290
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25291
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25292
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25293
                  'hdlType' => 'std_logic',
25294
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25295
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25296
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25297
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25298
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25299
                    'group' => 1,
25300
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25301
                    'is_floating_block' => 1,
25302
                    'period' => 1,
25303
                    'type' => 'logic',
25304
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25305
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25306
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25307
                  'hdlType' => 'std_logic',
25308
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25309
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25310
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25311
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25312
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25313
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25314
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25315
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25316
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25317
                    'simulinkName' => 'PCIe_UserLogic_00/USER_LOGIC/To Register27/data_in',
25318
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25319
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25320
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25321
                  'hdlType' => 'std_logic_vector(31 downto 0)',
25322
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25323
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25324
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25325
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25326
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25327
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25328
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25330
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25331
                    'simulinkName' => 'PCIe_UserLogic_00/USER_LOGIC/To Register27/dout',
25332
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25334
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25335
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25336
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25337
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25338
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25339
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25340
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25341
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25342
                    'must_be_hdl_vector' => 1,
25343
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25344
                    'port_id' => 1,
25345
                    'simulinkName' => 'PCIe_UserLogic_00/USER_LOGIC/To Register27/en',
25346
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25347
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25348
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25349
                  'hdlType' => 'std_logic_vector(0 downto 0)',
25350
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25351
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25352
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25353
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25354
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25355
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25356
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25357
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25358
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25359
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25360
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25361
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25362
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25363
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25364
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25365
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25366
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25367
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25368
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25369
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25370
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25371
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25372
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25373
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25374
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25375
                  'hdlType' => 'std_logic',
25376
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25377
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25378
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25379
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25380
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25381
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25382
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25383
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25384
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25385
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25386
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25387
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25388
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25389
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25390
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25391
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25392
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25393
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25394
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25395
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25396
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25397
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25398
                    'port_id' => 0,
25399
                    'simulinkName' => 'PCIe_UserLogic_00/USER_LOGIC/To Register2/data_in',
25400
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25401
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25402
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25403
                  'hdlType' => 'std_logic_vector(31 downto 0)',
25404
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25405
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25406
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25407
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25408
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25409
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25410
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25411
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25412
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25413
                    'simulinkName' => 'PCIe_UserLogic_00/USER_LOGIC/To Register2/dout',
25414
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25415
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25416
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25417
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25418
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25419
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25420
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25421
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25422
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25423
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25424
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25425
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25426
                    'port_id' => 1,
25427
                    'simulinkName' => 'PCIe_UserLogic_00/USER_LOGIC/To Register2/en',
25428
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25429
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25430
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25431
                  'hdlType' => 'std_logic_vector(0 downto 0)',
25432
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25433
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25434
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25435
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25436
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25437
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25438
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25439
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25440
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25441
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25442
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25443
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25444
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25445
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25446
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25447
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25448
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25449
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25450
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25451
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25452
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25453
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25454
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25455
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25456
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25457
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25458
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25459
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25460
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25461
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25462
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25463
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25464
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25465
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25466
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25467
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25468
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25469
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25470
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25471
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25472
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25473
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25474
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25475
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25476
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25477
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25478
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25479
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25480
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25481
                    'simulinkName' => 'PCIe_UserLogic_00/USER_LOGIC/To Register3/data_in',
25482
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25483
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25484
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25485
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25486
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25487
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25488
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25489
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25490
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25491
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25492
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25493
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25494
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25495
                    'simulinkName' => 'PCIe_UserLogic_00/USER_LOGIC/To Register3/dout',
25496
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25497
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25498
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25499
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25500
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25501
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25502
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25503
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25504
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25505
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25506
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25507
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25508
                    'port_id' => 1,
25509
                    'simulinkName' => 'PCIe_UserLogic_00/USER_LOGIC/To Register3/en',
25510
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25511
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25512
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25513
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25514
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25515
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25516
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25517
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25518
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25519
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25520
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25521
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25522
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25523
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25524
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25525
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25526
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25527
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25528
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25529
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25530
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25531
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25532
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25533
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25534
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25535
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25536
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25537
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25538
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25539
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25540
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25541
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25542
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25543
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25544
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25545
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25546
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25547
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25548
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25549
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25550
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25551
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25552
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25553
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25554
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25555
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25556
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25557
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25558
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25559
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25560
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25561
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25562
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25563
                    'simulinkName' => 'PCIe_UserLogic_00/USER_LOGIC/To Register4/data_in',
25564
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25565
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25566
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25567
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25568
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25569
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25570
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25571
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25572
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25573
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25574
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25575
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25576
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25577
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25578
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25579
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25580
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25581
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25582
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25583
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25584
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25585
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25586
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25587
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25588
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25589
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25590
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25591
                    'simulinkName' => 'PCIe_UserLogic_00/USER_LOGIC/To Register4/en',
25592
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25593
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25594
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25595
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25596
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25597
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25598
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25599
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25600
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25601
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25602
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25603
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25604
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25605
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25606
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25607
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25608
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25609
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25610
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25611
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25612
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25613
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25614
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25615
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25616
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25617
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25618
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25619
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25620
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25621
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25622
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25623
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25624
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25625
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25626
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25627
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25628
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25629
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25630
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25631
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25632
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25633
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25634
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25635
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25636
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25637
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25638
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25639
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25640
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25641
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25642
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25643
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25644
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25645
                    'simulinkName' => 'PCIe_UserLogic_00/USER_LOGIC/To Register5/data_in',
25646
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25647
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25648
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25649
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25650
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25651
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25652
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25653
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25654
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25655
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25656
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25657
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25658
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25659
                    'simulinkName' => 'PCIe_UserLogic_00/USER_LOGIC/To Register5/dout',
25660
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25661
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25662
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25663
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25664
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25665
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25666
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25667
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25668
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25669
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25670
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25671
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25672
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25673
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25674
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25675
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25676
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25677
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25678
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25679
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25680
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25681
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25682
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25683
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25684
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25685
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25686
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25687
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25688
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25689
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25690
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25691
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25692
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25693
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25694
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25695
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25696
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25697
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25698
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25699
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25700
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25701
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25702
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25703
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25704
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25705
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25706
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25707
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25708
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25709
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25710
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25711
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25712
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25713
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25714
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25715
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25716
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25717
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25718
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25719
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25720
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25721
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25722
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25723
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25724
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25725
                    'period' => 1,
25726
                    'port_id' => 0,
25727
                    'simulinkName' => 'PCIe_UserLogic_00/USER_LOGIC/To Register6/data_in',
25728
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25729
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25730
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25731
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25732
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25733
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25734
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25735
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25736
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25737
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25738
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25739
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25740
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25741
                    'simulinkName' => 'PCIe_UserLogic_00/USER_LOGIC/To Register6/dout',
25742
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25743
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25744
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25745
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25746
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25747
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25748
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25749
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25750
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25751
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25752
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25753
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25754
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25755
                    'simulinkName' => 'PCIe_UserLogic_00/USER_LOGIC/To Register6/en',
25756
                    'type' => 'Bool',
25757
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25758
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25759
                  'hdlType' => 'std_logic_vector(0 downto 0)',
25760
                  'width' => 1,
25761
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25762
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25763
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25764
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25765
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25766
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25767
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25768
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25769
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25770
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25771
                  'direction' => 'out',
25772
                  'hdlType' => 'std_logic',
25773
                  'width' => 1,
25774
                },
25775
                'to_register7_clk' => {
25776
                  'attributes' => {
25777
                    'domain' => '',
25778
                    'group' => 1,
25779
                    'isClk' => 1,
25780
                    'is_floating_block' => 1,
25781
                    'period' => 1,
25782
                    'type' => 'logic',
25783
                  },
25784
                  'direction' => 'out',
25785
                  'hdlType' => 'std_logic',
25786
                  'width' => 1,
25787
                },
25788
                'to_register7_clr' => {
25789
                  'attributes' => {
25790
                    'domain' => '',
25791
                    'group' => 1,
25792
                    'isClr' => 1,
25793
                    'is_floating_block' => 1,
25794
                    'period' => 1,
25795
                    'type' => 'logic',
25796
                    'valid_bit_used' => 0,
25797
                  },
25798
                  'direction' => 'out',
25799
                  'hdlType' => 'std_logic',
25800
                  'width' => 1,
25801
                },
25802
                'to_register7_data_in' => {
25803
                  'attributes' => {
25804
                    'bin_pt' => 0,
25805
                    'is_floating_block' => 1,
25806
                    'must_be_hdl_vector' => 1,
25807
                    'period' => 1,
25808
                    'port_id' => 0,
25809
                    'simulinkName' => 'PCIe_UserLogic_00/USER_LOGIC/To Register7/data_in',
25810
                    'type' => 'Bool',
25811
                  },
25812
                  'direction' => 'out',
25813
                  'hdlType' => 'std_logic_vector(0 downto 0)',
25814
                  'width' => 1,
25815
                },
25816
                'to_register7_dout' => {
25817
                  'attributes' => {
25818
                    'bin_pt' => 0,
25819
                    'is_floating_block' => 1,
25820
                    'must_be_hdl_vector' => 1,
25821
                    'period' => 1,
25822
                    'port_id' => 0,
25823
                    'simulinkName' => 'PCIe_UserLogic_00/USER_LOGIC/To Register7/dout',
25824
                    'type' => 'Bool',
25825
                  },
25826
                  'direction' => 'in',
25827
                  'hdlType' => 'std_logic_vector(0 downto 0)',
25828
                  'width' => 1,
25829
                },
25830
                'to_register7_en' => {
25831
                  'attributes' => {
25832
                    'bin_pt' => 0,
25833
                    'is_floating_block' => 1,
25834
                    'must_be_hdl_vector' => 1,
25835
                    'period' => 1,
25836
                    'port_id' => 1,
25837
                    'simulinkName' => 'PCIe_UserLogic_00/USER_LOGIC/To Register7/en',
25838
                    'type' => 'Bool',
25839
                  },
25840
                  'direction' => 'out',
25841
                  'hdlType' => 'std_logic_vector(0 downto 0)',
25842
                  'width' => 1,
25843
                },
25844
                'to_register8_ce' => {
25845
                  'attributes' => {
25846
                    'domain' => '',
25847
                    'group' => 1,
25848
                    'isCe' => 1,
25849
                    'is_floating_block' => 1,
25850
                    'period' => 1,
25851
                    'type' => 'logic',
25852
                  },
25853
                  'direction' => 'out',
25854
                  'hdlType' => 'std_logic',
25855
                  'width' => 1,
25856
                },
25857
                'to_register8_clk' => {
25858
                  'attributes' => {
25859
                    'domain' => '',
25860
                    'group' => 1,
25861
                    'isClk' => 1,
25862
                    'is_floating_block' => 1,
25863
                    'period' => 1,
25864
                    'type' => 'logic',
25865
                  },
25866
                  'direction' => 'out',
25867
                  'hdlType' => 'std_logic',
25868
                  'width' => 1,
25869
                },
25870
                'to_register8_clr' => {
25871
                  'attributes' => {
25872
                    'domain' => '',
25873
                    'group' => 1,
25874
                    'isClr' => 1,
25875
                    'is_floating_block' => 1,
25876
                    'period' => 1,
25877
                    'type' => 'logic',
25878
                    'valid_bit_used' => 0,
25879
                  },
25880
                  'direction' => 'out',
25881
                  'hdlType' => 'std_logic',
25882
                  'width' => 1,
25883
                },
25884
                'to_register8_data_in' => {
25885
                  'attributes' => {
25886
                    'bin_pt' => 0,
25887
                    'is_floating_block' => 1,
25888
                    'must_be_hdl_vector' => 1,
25889
                    'period' => 1,
25890
                    'port_id' => 0,
25891
                    'simulinkName' => 'PCIe_UserLogic_00/USER_LOGIC/To Register8/data_in',
25892
                    'type' => 'UFix_32_0',
25893
                  },
25894
                  'direction' => 'out',
25895
                  'hdlType' => 'std_logic_vector(31 downto 0)',
25896
                  'width' => 32,
25897
                },
25898
                'to_register8_dout' => {
25899
                  'attributes' => {
25900
                    'bin_pt' => 0,
25901
                    'is_floating_block' => 1,
25902
                    'must_be_hdl_vector' => 1,
25903
                    'period' => 1,
25904
                    'port_id' => 0,
25905
                    'simulinkName' => 'PCIe_UserLogic_00/USER_LOGIC/To Register8/dout',
25906
                    'type' => 'UFix_32_0',
25907
                  },
25908
                  'direction' => 'in',
25909
                  'hdlType' => 'std_logic_vector(31 downto 0)',
25910
                  'width' => 32,
25911
                },
25912
                'to_register8_en' => {
25913
                  'attributes' => {
25914
                    'bin_pt' => 0,
25915
                    'is_floating_block' => 1,
25916
                    'must_be_hdl_vector' => 1,
25917
                    'period' => 1,
25918
                    'port_id' => 1,
25919
                    'simulinkName' => 'PCIe_UserLogic_00/USER_LOGIC/To Register8/en',
25920
                    'type' => 'Bool',
25921
                  },
25922
                  'direction' => 'out',
25923
                  'hdlType' => 'std_logic_vector(0 downto 0)',
25924
                  'width' => 1,
25925
                },
25926
                'to_register9_ce' => {
25927
                  'attributes' => {
25928
                    'domain' => '',
25929
                    'group' => 1,
25930
                    'isCe' => 1,
25931
                    'is_floating_block' => 1,
25932
                    'period' => 1,
25933
                    'type' => 'logic',
25934
                  },
25935
                  'direction' => 'out',
25936
                  'hdlType' => 'std_logic',
25937
                  'width' => 1,
25938
                },
25939
                'to_register9_clk' => {
25940
                  'attributes' => {
25941
                    'domain' => '',
25942
                    'group' => 1,
25943
                    'isClk' => 1,
25944
                    'is_floating_block' => 1,
25945
                    'period' => 1,
25946
                    'type' => 'logic',
25947
                  },
25948
                  'direction' => 'out',
25949
                  'hdlType' => 'std_logic',
25950
                  'width' => 1,
25951
                },
25952
                'to_register9_clr' => {
25953
                  'attributes' => {
25954
                    'domain' => '',
25955
                    'group' => 1,
25956
                    'isClr' => 1,
25957
                    'is_floating_block' => 1,
25958
                    'period' => 1,
25959
                    'type' => 'logic',
25960
                    'valid_bit_used' => 0,
25961
                  },
25962
                  'direction' => 'out',
25963
                  'hdlType' => 'std_logic',
25964
                  'width' => 1,
25965
                },
25966
                'to_register9_data_in' => {
25967
                  'attributes' => {
25968
                    'bin_pt' => 0,
25969
                    'is_floating_block' => 1,
25970
                    'must_be_hdl_vector' => 1,
25971
                    'period' => 1,
25972
                    'port_id' => 0,
25973
                    'simulinkName' => 'PCIe_UserLogic_00/USER_LOGIC/To Register9/data_in',
25974
                    'type' => 'UFix_32_0',
25975
                  },
25976
                  'direction' => 'out',
25977
                  'hdlType' => 'std_logic_vector(31 downto 0)',
25978
                  'width' => 32,
25979
                },
25980
                'to_register9_dout' => {
25981
                  'attributes' => {
25982
                    'bin_pt' => 0,
25983
                    'is_floating_block' => 1,
25984
                    'must_be_hdl_vector' => 1,
25985
                    'period' => 1,
25986
                    'port_id' => 0,
25987
                    'simulinkName' => 'PCIe_UserLogic_00/USER_LOGIC/To Register9/dout',
25988
                    'type' => 'UFix_32_0',
25989
                  },
25990
                  'direction' => 'in',
25991
                  'hdlType' => 'std_logic_vector(31 downto 0)',
25992
                  'width' => 32,
25993
                },
25994
                'to_register9_en' => {
25995
                  'attributes' => {
25996
                    'bin_pt' => 0,
25997
                    'is_floating_block' => 1,
25998
                    'must_be_hdl_vector' => 1,
25999
                    'period' => 1,
26000
                    'port_id' => 1,
26001
                    'simulinkName' => 'PCIe_UserLogic_00/USER_LOGIC/To Register9/en',
26002
                    'type' => 'Bool',
26003
                  },
26004
                  'direction' => 'out',
26005
                  'hdlType' => 'std_logic_vector(0 downto 0)',
26006
                  'width' => 1,
26007
                },
26008
                'to_register_ce' => {
26009
                  'attributes' => {
26010
                    'domain' => '',
26011
                    'group' => 1,
26012
                    'isCe' => 1,
26013
                    'is_floating_block' => 1,
26014
                    'period' => 1,
26015
                    'type' => 'logic',
26016
                  },
26017
                  'direction' => 'out',
26018
                  'hdlType' => 'std_logic',
26019
                  'width' => 1,
26020
                },
26021
                'to_register_clk' => {
26022
                  'attributes' => {
26023
                    'domain' => '',
26024
                    'group' => 1,
26025
                    'isClk' => 1,
26026
                    'is_floating_block' => 1,
26027
                    'period' => 1,
26028
                    'type' => 'logic',
26029
                  },
26030
                  'direction' => 'out',
26031
                  'hdlType' => 'std_logic',
26032
                  'width' => 1,
26033
                },
26034
                'to_register_clr' => {
26035
                  'attributes' => {
26036
                    'domain' => '',
26037
                    'group' => 1,
26038
                    'isClr' => 1,
26039
                    'is_floating_block' => 1,
26040
                    'period' => 1,
26041
                    'type' => 'logic',
26042
                    'valid_bit_used' => 0,
26043
                  },
26044
                  'direction' => 'out',
26045
                  'hdlType' => 'std_logic',
26046
                  'width' => 1,
26047
                },
26048
                'to_register_data_in' => {
26049
                  'attributes' => {
26050
                    'bin_pt' => 0,
26051
                    'is_floating_block' => 1,
26052
                    'must_be_hdl_vector' => 1,
26053
                    'period' => 1,
26054
                    'port_id' => 0,
26055
                    'simulinkName' => 'PCIe_UserLogic_00/USER_LOGIC/To Register/data_in',
26056
                    'type' => 'UFix_32_0',
26057
                  },
26058
                  'direction' => 'out',
26059
                  'hdlType' => 'std_logic_vector(31 downto 0)',
26060
                  'width' => 32,
26061
                },
26062
                'to_register_dout' => {
26063
                  'attributes' => {
26064
                    'bin_pt' => 0,
26065
                    'is_floating_block' => 1,
26066
                    'must_be_hdl_vector' => 1,
26067
                    'period' => 1,
26068
                    'port_id' => 0,
26069
                    'simulinkName' => 'PCIe_UserLogic_00/USER_LOGIC/To Register/dout',
26070
                    'type' => 'UFix_32_0',
26071
                  },
26072
                  'direction' => 'in',
26073
                  'hdlType' => 'std_logic_vector(31 downto 0)',
26074
                  'width' => 32,
26075
                },
26076
                'to_register_en' => {
26077
                  'attributes' => {
26078
                    'bin_pt' => 0,
26079
                    'is_floating_block' => 1,
26080
                    'must_be_hdl_vector' => 1,
26081
                    'period' => 1,
26082
                    'port_id' => 1,
26083
                    'simulinkName' => 'PCIe_UserLogic_00/USER_LOGIC/To Register/en',
26084
                    'type' => 'Bool',
26085
                  },
26086
                  'direction' => 'out',
26087
                  'hdlType' => 'std_logic_vector(0 downto 0)',
26088
                  'width' => 1,
26089
                },
26090
                'user_int_1o' => {
26091
                  'attributes' => {
26092
                    'bin_pt' => 0,
26093
                    'inputFile' => 'pcie_userlogic_00_user_logic_user_int_1o.dat',
26094
                    'is_floating_block' => 1,
26095
                    'is_gateway_port' => 1,
26096
                    'must_be_hdl_vector' => 1,
26097
                    'period' => 1,
26098
                    'port_id' => 0,
26099
                    'simulinkName' => 'PCIe_UserLogic_00/USER_LOGIC/user_int_1o/user_int_1o',
26100
                    'source_block' => 'PCIe_UserLogic_00/USER_LOGIC/user_int_1o',
26101
                    'timingConstraint' => 'none',
26102
                    'type' => 'Bool',
26103
                  },
26104
                  'direction' => 'out',
26105
                  'hdlType' => 'std_logic',
26106
                  'width' => 1,
26107
                },
26108
                'user_int_2o' => {
26109
                  'attributes' => {
26110
                    'bin_pt' => 0,
26111
                    'inputFile' => 'pcie_userlogic_00_user_logic_user_int_2o.dat',
26112
                    'is_floating_block' => 1,
26113
                    'is_gateway_port' => 1,
26114
                    'must_be_hdl_vector' => 1,
26115
                    'period' => 1,
26116
                    'port_id' => 0,
26117
                    'simulinkName' => 'PCIe_UserLogic_00/USER_LOGIC/user_int_2o/user_int_2o',
26118
                    'source_block' => 'PCIe_UserLogic_00/USER_LOGIC/user_int_2o',
26119
                    'timingConstraint' => 'none',
26120
                    'type' => 'Bool',
26121
                  },
26122
                  'direction' => 'out',
26123
                  'hdlType' => 'std_logic',
26124
                  'width' => 1,
26125
                },
26126
                'user_int_3o' => {
26127
                  'attributes' => {
26128
                    'bin_pt' => 0,
26129
                    'inputFile' => 'pcie_userlogic_00_user_logic_user_int_3o.dat',
26130
                    'is_floating_block' => 1,
26131
                    'is_gateway_port' => 1,
26132
                    'must_be_hdl_vector' => 1,
26133
                    'period' => 1,
26134
                    'port_id' => 0,
26135
                    'simulinkName' => 'PCIe_UserLogic_00/USER_LOGIC/user_int_3o/user_int_3o',
26136
                    'source_block' => 'PCIe_UserLogic_00/USER_LOGIC/user_int_3o',
26137
                    'timingConstraint' => 'none',
26138
                    'type' => 'Bool',
26139
                  },
26140
                  'direction' => 'out',
26141
                  'hdlType' => 'std_logic',
26142
                  'width' => 1,
26143
                },
26144
              },
26145
              'subblocks' => {
26146
                'default_clock_driver_x0' => {
26147
                  'connections' => {
26148
                    'ce_1' => 'ce_1_sg_x0',
26149
                    'clk_1' => 'clk_1_sg_x0',
26150
                    'sysce' => [
26151
                      'constant',
26152
                      '\'1\'',
26153
                    ],
26154
                    'sysce_clr' => [
26155
                      'constant',
26156
                      '\'0\'',
26157
                    ],
26158
                    'sysclk' => 'clkNet',
26159
                  },
26160
                  'entity' => {
26161
                    'attributes' => {
26162
                      'domain' => 'default',
26163
                      'hdlArchAttributes' => [
26164
                        [
26165
                          'syn_noprune',
26166
                          'boolean',
26167
                          'true',
26168
                        ],
26169
                        [
26170
                          'optimize_primitives',
26171
                          'boolean',
26172
                          'false',
26173
                        ],
26174
                        [
26175
                          'dont_touch',
26176
                          'boolean',
26177
                          'true',
26178
                        ],
26179
                      ],
26180
                      'hdlEntityAttributes' => [
26181
                      ],
26182
                      'isClkDriver' => 1,
26183
                    },
26184
                    'entityName' => 'default_clock_driver',
26185
                    'ports' => {
26186
                      'ce_1' => {
26187
                        'attributes' => {
26188
                          'domain' => 'default',
26189
                          'group' => 1,
26190
                          'isCe' => 1,
26191
                          'period' => 1,
26192
                          'type' => 'logic',
26193
                        },
26194
                        'direction' => 'out',
26195
                        'hdlType' => 'std_logic',
26196
                        'width' => 1,
26197
                      },
26198
                      'clk_1' => {
26199
                        'attributes' => {
26200
                          'domain' => 'default',
26201
                          'group' => 1,
26202
                          'isClk' => 1,
26203
                          'period' => 1,
26204
                          'type' => 'logic',
26205
                        },
26206
                        'direction' => 'out',
26207
                        'hdlType' => 'std_logic',
26208
                        'width' => 1,
26209
                      },
26210
                      'sysce' => {
26211
                        'attributes' => {
26212
                          'group' => 6,
26213
                          'isCe' => 1,
26214
                          'period' => 1,
26215
                        },
26216
                        'direction' => 'in',
26217
                        'hdlType' => 'std_logic',
26218
                        'width' => 1,
26219
                      },
26220
                      'sysce_clr' => {
26221
                        'attributes' => {
26222
                          'group' => 6,
26223
                          'isClr' => 1,
26224
                          'period' => 1,
26225
                        },
26226
                        'direction' => 'in',
26227
                        'hdlType' => 'std_logic',
26228
                        'width' => 1,
26229
                      },
26230
                      'sysclk' => {
26231
                        'attributes' => {
26232
                          'group' => 6,
26233
                          'isClk' => 1,
26234
                          'period' => 1,
26235
                        },
26236
                        'direction' => 'in',
26237
                        'hdlType' => 'std_logic',
26238
                        'width' => 1,
26239
                      },
26240
                    },
26241
                  },
26242
                  'entityName' => 'default_clock_driver',
26243
                },
26244
                'persistentdff_inst' => {
26245
                  'connections' => {
26246
                    'clk' => 'clkNet',
26247
                    'd' => 'persistentdff_inst_q',
26248
                    'q' => 'persistentdff_inst_q',
26249
                  },
26250
                  'entity' => {
26251
                    'attributes' => {
26252
                      'entityAlreadyNetlisted' => 1,
26253
                      'hdlCompAttributes' => [
26254
                        [
26255
                          'syn_black_box',
26256
                          'boolean',
26257
                          'true',
26258
                        ],
26259
                        [
26260
                          'box_type',
26261
                          'string',
26262
                          '"black_box"',
26263
                        ],
26264
                      ],
26265
                      'is_persistent_dff' => 1,
26266
                      'needsComponentDeclaration' => 1,
26267
                    },
26268
                    'entityName' => 'xlpersistentdff',
26269
                    'ports' => {
26270
                      'clk' => {
26271
                        'direction' => 'in',
26272
                        'hdlType' => 'std_logic',
26273
                        'width' => 1,
26274
                      },
26275
                      'd' => {
26276
                        'direction' => 'in',
26277
                        'hdlType' => 'std_logic',
26278
                        'width' => 1,
26279
                      },
26280
                      'q' => {
26281
                        'direction' => 'out',
26282
                        'hdlType' => 'std_logic',
26283
                        'width' => 1,
26284
                      },
26285
                    },
26286
                  },
26287
                  'entityName' => 'xlpersistentdff',
26288
                },
26289
                'user_logic_x0' => {
26290
                  'connections' => {
26291
                    'bram_rd_addr' => 'bram_rd_addr_net',
26292
                    'bram_rd_dout' => 'bram_rd_dout_net',
26293
                    'bram_wr_addr' => 'bram_wr_addr_net',
26294
                    'bram_wr_din' => 'bram_wr_din_net',
26295
                    'bram_wr_en' => 'bram_wr_en_net',
26296
                    'ce_1' => 'ce_1_sg_x0',
26297
                    'clk_1' => 'clk_1_sg_x0',
26298
                    'data_in' => 'data_in_net',
26299
                    'data_in_x0' => 'data_in_x0_net',
26300
                    'data_in_x1' => 'data_in_x1_net',
26301
                    'data_in_x10' => 'data_in_x10_net',
26302
                    'data_in_x11' => 'data_in_x11_net',
26303
                    'data_in_x12' => 'data_in_x12_net',
26304
                    'data_in_x13' => 'data_in_x13_net',
26305
                    'data_in_x14' => 'data_in_x14_net',
26306
                    'data_in_x15' => 'data_in_x15_net',
26307
                    'data_in_x16' => 'data_in_x16_net',
26308
                    'data_in_x17' => 'data_in_x17_net',
26309
                    'data_in_x18' => 'data_in_x18_net',
26310
                    'data_in_x19' => 'data_in_x19_net',
26311
                    'data_in_x2' => 'data_in_x2_net',
26312
                    'data_in_x20' => 'data_in_x20_net',
26313
                    'data_in_x21' => 'data_in_x21_net',
26314
                    'data_in_x22' => 'data_in_x22_net',
26315
                    'data_in_x23' => 'data_in_x23_net',
26316
                    'data_in_x24' => 'data_in_x24_net',
26317
                    'data_in_x25' => 'data_in_x25_net',
26318
                    'data_in_x26' => 'data_in_x26_net',
26319
                    'data_in_x3' => 'data_in_x3_net',
26320
                    'data_in_x4' => 'data_in_x4_net',
26321
                    'data_in_x5' => 'data_in_x5_net',
26322
                    'data_in_x6' => 'data_in_x6_net',
26323
                    'data_in_x7' => 'data_in_x7_net',
26324
                    'data_in_x8' => 'data_in_x8_net',
26325
                    'data_in_x9' => 'data_in_x9_net',
26326
                    'data_out_x1' => 'data_out_x1_net',
26327
                    'data_out_x12' => 'data_out_x12_net',
26328
                    'data_out_x13' => 'data_out_x13_net',
26329
                    'data_out_x14' => 'data_out_x14_net',
26330
                    'data_out_x15' => 'data_out_x15_net',
26331
                    'data_out_x16' => 'data_out_x16_net',
26332
                    'data_out_x17' => 'data_out_x17_net',
26333
                    'data_out_x18' => 'data_out_x18_net',
26334
                    'data_out_x19' => 'data_out_x19_net',
26335
                    'data_out_x2' => 'data_out_x2_net',
26336
                    'data_out_x20' => 'data_out_x20_net',
26337
                    'data_out_x21' => 'data_out_x21_net',
26338
                    'data_out_x22' => 'data_out_x22_net',
26339
                    'data_out_x23' => 'data_out_x23_net',
26340
                    'data_out_x24' => 'data_out_x24_net',
26341
                    'data_out_x25' => 'data_out_x25_net',
26342
                    'data_out_x26' => 'data_out_x26_net',
26343
                    'data_out_x27' => 'data_out_x27_net',
26344
                    'data_out_x28' => 'data_out_x28_net',
26345
                    'data_out_x29' => 'data_out_x29_net',
26346
                    'data_out_x3' => 'data_out_x3_net',
26347
                    'data_out_x30' => 'data_out_x30_net',
26348
                    'data_out_x31' => 'data_out_x31_net',
26349
                    'data_out_x32' => 'data_out_x32_net',
26350
                    'data_out_x4' => 'data_out_x4_net',
26351
                    'data_out_x5' => 'data_out_x5_net',
26352
                    'data_out_x8' => 'data_out_x8_net',
26353
                    'data_out_x9' => 'data_out_x9_net',
26354
                    'en' => 'constant6_op_net_x0',
26355
                    'en_x0' => 'constant6_op_net_x1',
26356
                    'en_x1' => 'constant6_op_net_x2',
26357
                    'en_x10' => 'constant6_op_net_x11',
26358
                    'en_x11' => 'constant6_op_net_x12',
26359
                    'en_x12' => 'constant6_op_net_x13',
26360
                    'en_x13' => 'constant6_op_net_x14',
26361
                    'en_x14' => 'constant6_op_net_x15',
26362
                    'en_x15' => 'constant6_op_net_x16',
26363
                    'en_x16' => 'constant6_op_net_x17',
26364
                    'en_x17' => 'constant6_op_net_x18',
26365
                    'en_x18' => 'constant6_op_net_x19',
26366
                    'en_x19' => 'constant6_op_net_x20',
26367
                    'en_x2' => 'constant6_op_net_x3',
26368
                    'en_x20' => 'constant6_op_net_x21',
26369
                    'en_x21' => 'constant6_op_net_x22',
26370
                    'en_x22' => 'constant6_op_net_x23',
26371
                    'en_x23' => 'constant6_op_net_x24',
26372
                    'en_x24' => 'constant6_op_net_x25',
26373
                    'en_x25' => 'constant6_op_net_x26',
26374
                    'en_x26' => 'constant6_op_net_x27',
26375
                    'en_x3' => 'constant6_op_net_x4',
26376
                    'en_x4' => 'constant6_op_net_x5',
26377
                    'en_x5' => 'constant6_op_net_x6',
26378
                    'en_x6' => 'constant6_op_net_x7',
26379
                    'en_x7' => 'constant6_op_net_x8',
26380
                    'en_x8' => 'constant6_op_net_x9',
26381
                    'en_x9' => 'constant6_op_net_x10',
26382
                    'fifo_rd_count_x0' => 'fifo_rd_count_net',
26383
                    'fifo_rd_dout' => 'fifo_rd_dout_net',
26384
                    'fifo_rd_empty' => 'fifo_rd_empty_net',
26385
                    'fifo_rd_en_x1' => 'fifo_rd_en_net',
26386
                    'fifo_rd_pempty_x0' => 'fifo_rd_pempty_net',
26387
                    'fifo_rd_valid' => 'fifo_rd_valid_net',
26388
                    'fifo_wr_count_x0' => 'fifo_wr_count_net',
26389
                    'fifo_wr_din' => 'fifo_wr_din_net',
26390
                    'fifo_wr_en_x0' => 'fifo_wr_en_net',
26391
                    'fifo_wr_full_x0' => 'fifo_wr_full_net',
26392
                    'fifo_wr_pfull_x0' => 'fifo_wr_pfull_net',
26393
                    'rst_i' => 'rst_i_net',
26394
                    'rst_o' => 'rst_o_net',
26395
                    'user_int_1o' => 'user_int_1o_net',
26396
                    'user_int_2o' => 'user_int_2o_net',
26397
                    'user_int_3o' => 'user_int_3o_net',
26398
                  },
26399
                  'entity' => {
26400
                    'attributes' => {
26401
                      'entityAlreadyNetlisted' => 1,
26402
                      'hdlKind' => 'vhdl',
26403
                      'isDesign' => 1,
26404
                      'simulinkName' => 'USER_LOGIC',
26405
                    },
26406
                    'entityName' => 'user_logic',
26407
                    'ports' => {
26408
                      'bram_rd_addr' => {
26409
                        'attributes' => {
26410
                          'bin_pt' => 0,
26411
                          'inputFile' => 'pcie_userlogic_00_user_logic_bram_rd_addr.dat',
26412
                          'is_floating_block' => 1,
26413
                          'is_gateway_port' => 1,
26414
                          'must_be_hdl_vector' => 1,
26415
                          'period' => 1,
26416
                          'port_id' => 15,
26417
                          'simulinkName' => 'USER_LOGIC/BRAM_rd_addr',
26418
                          'source_block' => 'USER_LOGIC',
26419
                          'timingConstraint' => 'none',
26420
                          'type' => 'UFix_12_0',
26421
                        },
26422
                        'direction' => 'out',
26423
                        'hdlType' => 'std_logic_vector(11 downto 0)',
26424
                        'width' => 12,
26425
                      },
26426
                      'bram_rd_dout' => {
26427
                        'attributes' => {
26428
                          'bin_pt' => 0,
26429
                          'inputFile' => 'pcie_userlogic_00_user_logic_bram_rd_dout.dat',
26430
                          'is_floating_block' => 1,
26431
                          'is_gateway_port' => 1,
26432
                          'must_be_hdl_vector' => 1,
26433
                          'period' => 1,
26434
                          'port_id' => 0,
26435
                          'simulinkName' => 'USER_LOGIC/BRAM_rd_dout',
26436
                          'source_block' => 'USER_LOGIC',
26437
                          'timingConstraint' => 'none',
26438
                          'type' => 'UFix_64_0',
26439
                        },
26440
                        'direction' => 'in',
26441
                        'hdlType' => 'std_logic_vector(63 downto 0)',
26442
                        'width' => 64,
26443
                      },
26444
                      'bram_wr_addr' => {
26445
                        'attributes' => {
26446
                          'bin_pt' => 0,
26447
                          'inputFile' => 'pcie_userlogic_00_user_logic_bram_wr_addr.dat',
26448
                          'is_floating_block' => 1,
26449
                          'is_gateway_port' => 1,
26450
                          'must_be_hdl_vector' => 1,
26451
                          'period' => 1,
26452
                          'port_id' => 16,
26453
                          'simulinkName' => 'USER_LOGIC/BRAM_wr_addr',
26454
                          'source_block' => 'USER_LOGIC',
26455
                          'timingConstraint' => 'none',
26456
                          'type' => 'UFix_12_0',
26457
                        },
26458
                        'direction' => 'out',
26459
                        'hdlType' => 'std_logic_vector(11 downto 0)',
26460
                        'width' => 12,
26461
                      },
26462
                      'bram_wr_din' => {
26463
                        'attributes' => {
26464
                          'bin_pt' => 0,
26465
                          'inputFile' => 'pcie_userlogic_00_user_logic_bram_wr_din.dat',
26466
                          'is_floating_block' => 1,
26467
                          'is_gateway_port' => 1,
26468
                          'must_be_hdl_vector' => 1,
26469
                          'period' => 1,
26470
                          'port_id' => 18,
26471
                          'simulinkName' => 'USER_LOGIC/BRAM_wr_din',
26472
                          'source_block' => 'USER_LOGIC',
26473
                          'timingConstraint' => 'none',
26474
                          'type' => 'UFix_64_0',
26475
                        },
26476
                        'direction' => 'out',
26477
                        'hdlType' => 'std_logic_vector(63 downto 0)',
26478
                        'width' => 64,
26479
                      },
26480
                      'bram_wr_en' => {
26481
                        'attributes' => {
26482
                          'bin_pt' => 0,
26483
                          'inputFile' => 'pcie_userlogic_00_user_logic_bram_wr_en.dat',
26484
                          'is_floating_block' => 1,
26485
                          'is_gateway_port' => 1,
26486
                          'must_be_hdl_vector' => 1,
26487
                          'period' => 1,
26488
                          'port_id' => 23,
26489
                          'simulinkName' => 'USER_LOGIC/BRAM_wr_en',
26490
                          'source_block' => 'USER_LOGIC',
26491
                          'timingConstraint' => 'none',
26492
                          'type' => 'UFix_8_0',
26493
                        },
26494
                        'direction' => 'out',
26495
                        'hdlType' => 'std_logic_vector(7 downto 0)',
26496
                        'width' => 8,
26497
                      },
26498
                      'ce_1' => {
26499
                        'attributes' => {
26500
                          'domain' => '',
26501
                          'group' => 1,
26502
                          'isCe' => 1,
26503
                          'is_subsys_port' => 1,
26504
                          'period' => 1,
26505
                          'subsys_port_index' => 0,
26506
                          'type' => 'logic',
26507
                        },
26508
                        'direction' => 'in',
26509
                        'hdlType' => 'std_logic',
26510
                        'width' => 1,
26511
                      },
26512
                      'clk_1' => {
26513
                        'attributes' => {
26514
                          'domain' => '',
26515
                          'group' => 1,
26516
                          'isClk' => 1,
26517
                          'is_subsys_port' => 1,
26518
                          'period' => 1,
26519
                          'subsys_port_index' => 0,
26520
                          'type' => 'logic',
26521
                        },
26522
                        'direction' => 'in',
26523
                        'hdlType' => 'std_logic',
26524
                        'width' => 1,
26525
                      },
26526
                      'data_in' => {
26527
                        'attributes' => {
26528
                          'bin_pt' => 0,
26529
                          'is_floating_block' => 1,
26530
                          'must_be_hdl_vector' => 1,
26531
                          'period' => 1,
26532
                          'port_id' => 17,
26533
                          'simulinkName' => 'USER_LOGIC/tx_en_in2',
26534
                          'type' => 'UFix_32_0',
26535
                        },
26536
                        'direction' => 'out',
26537
                        'hdlType' => 'std_logic_vector(31 downto 0)',
26538
                        'width' => 32,
26539
                      },
26540
                      'data_in_x0' => {
26541
                        'attributes' => {
26542
                          'bin_pt' => 0,
26543
                          'is_floating_block' => 1,
26544
                          'must_be_hdl_vector' => 1,
26545
                          'period' => 1,
26546
                          'port_id' => 1,
26547
                          'simulinkName' => 'USER_LOGIC/tx_en_in1',
26548
                          'type' => 'Bool',
26549
                        },
26550
                        'direction' => 'out',
26551
                        'hdlType' => 'std_logic',
26552
                        'width' => 1,
26553
                      },
26554
                      'data_in_x1' => {
26555
                        'attributes' => {
26556
                          'bin_pt' => 0,
26557
                          'is_floating_block' => 1,
26558
                          'must_be_hdl_vector' => 1,
26559
                          'period' => 1,
26560
                          'port_id' => 36,
26561
                          'simulinkName' => 'USER_LOGIC/tx_en_in96',
26562
                          'type' => 'Bool',
26563
                        },
26564
                        'direction' => 'out',
26565
                        'hdlType' => 'std_logic',
26566
                        'width' => 1,
26567
                      },
26568
                      'data_in_x10' => {
26569
                        'attributes' => {
26570
                          'bin_pt' => 0,
26571
                          'is_floating_block' => 1,
26572
                          'must_be_hdl_vector' => 1,
26573
                          'period' => 1,
26574
                          'port_id' => 33,
26575
                          'simulinkName' => 'USER_LOGIC/tx_en_in91',
26576
                          'type' => 'UFix_32_0',
26577
                        },
26578
                        'direction' => 'out',
26579
                        'hdlType' => 'std_logic_vector(31 downto 0)',
26580
                        'width' => 32,
26581
                      },
26582
                      'data_in_x11' => {
26583
                        'attributes' => {
26584
                          'bin_pt' => 0,
26585
                          'is_floating_block' => 1,
26586
                          'must_be_hdl_vector' => 1,
26587
                          'period' => 1,
26588
                          'port_id' => 21,
26589
                          'simulinkName' => 'USER_LOGIC/tx_en_in33',
26590
                          'type' => 'UFix_32_0',
26591
                        },
26592
                        'direction' => 'out',
26593
                        'hdlType' => 'std_logic_vector(31 downto 0)',
26594
                        'width' => 32,
26595
                      },
26596
                      'data_in_x12' => {
26597
                        'attributes' => {
26598
                          'bin_pt' => 0,
26599
                          'is_floating_block' => 1,
26600
                          'must_be_hdl_vector' => 1,
26601
                          'period' => 1,
26602
                          'port_id' => 6,
26603
                          'simulinkName' => 'USER_LOGIC/tx_en_in113',
26604
                          'type' => 'Bool',
26605
                        },
26606
                        'direction' => 'out',
26607
                        'hdlType' => 'std_logic',
26608
                        'width' => 1,
26609
                      },
26610
                      'data_in_x13' => {
26611
                        'attributes' => {
26612
                          'bin_pt' => 0,
26613
                          'is_floating_block' => 1,
26614
                          'must_be_hdl_vector' => 1,
26615
                          'period' => 1,
26616
                          'port_id' => 8,
26617
                          'simulinkName' => 'USER_LOGIC/tx_en_in115',
26618
                          'type' => 'UFix_32_0',
26619
                        },
26620
                        'direction' => 'out',
26621
                        'hdlType' => 'std_logic_vector(31 downto 0)',
26622
                        'width' => 32,
26623
                      },
26624
                      'data_in_x14' => {
26625
                        'attributes' => {
26626
                          'bin_pt' => 0,
26627
                          'is_floating_block' => 1,
26628
                          'must_be_hdl_vector' => 1,
26629
                          'period' => 1,
26630
                          'port_id' => 7,
26631
                          'simulinkName' => 'USER_LOGIC/tx_en_in114',
26632
                          'type' => 'Bool',
26633
                        },
26634
                        'direction' => 'out',
26635
                        'hdlType' => 'std_logic',
26636
                        'width' => 1,
26637
                      },
26638
                      'data_in_x15' => {
26639
                        'attributes' => {
26640
                          'bin_pt' => 0,
26641
                          'is_floating_block' => 1,
26642
                          'must_be_hdl_vector' => 1,
26643
                          'period' => 1,
26644
                          'port_id' => 9,
26645
                          'simulinkName' => 'USER_LOGIC/tx_en_in118',
26646
                          'type' => 'UFix_32_0',
26647
                        },
26648
                        'direction' => 'out',
26649
                        'hdlType' => 'std_logic_vector(31 downto 0)',
26650
                        'width' => 32,
26651
                      },
26652
                      'data_in_x16' => {
26653
                        'attributes' => {
26654
                          'bin_pt' => 0,
26655
                          'is_floating_block' => 1,
26656
                          'must_be_hdl_vector' => 1,
26657
                          'period' => 1,
26658
                          'port_id' => 10,
26659
                          'simulinkName' => 'USER_LOGIC/tx_en_in121',
26660
                          'type' => 'Bool',
26661
                        },
26662
                        'direction' => 'out',
26663
                        'hdlType' => 'std_logic',
26664
                        'width' => 1,
26665
                      },
26666
                      'data_in_x17' => {
26667
                        'attributes' => {
26668
                          'bin_pt' => 0,
26669
                          'is_floating_block' => 1,
26670
                          'must_be_hdl_vector' => 1,
26671
                          'period' => 1,
26672
                          'port_id' => 11,
26673
                          'simulinkName' => 'USER_LOGIC/tx_en_in122',
26674
                          'type' => 'UFix_32_0',
26675
                        },
26676
                        'direction' => 'out',
26677
                        'hdlType' => 'std_logic_vector(31 downto 0)',
26678
                        'width' => 32,
26679
                      },
26680
                      'data_in_x18' => {
26681
                        'attributes' => {
26682
                          'bin_pt' => 0,
26683
                          'is_floating_block' => 1,
26684
                          'must_be_hdl_vector' => 1,
26685
                          'period' => 1,
26686
                          'port_id' => 12,
26687
                          'simulinkName' => 'USER_LOGIC/tx_en_in125',
26688
                          'type' => 'Bool',
26689
                        },
26690
                        'direction' => 'out',
26691
                        'hdlType' => 'std_logic',
26692
                        'width' => 1,
26693
                      },
26694
                      'data_in_x19' => {
26695
                        'attributes' => {
26696
                          'bin_pt' => 0,
26697
                          'is_floating_block' => 1,
26698
                          'must_be_hdl_vector' => 1,
26699
                          'period' => 1,
26700
                          'port_id' => 13,
26701
                          'simulinkName' => 'USER_LOGIC/tx_en_in126',
26702
                          'type' => 'UFix_32_0',
26703
                        },
26704
                        'direction' => 'out',
26705
                        'hdlType' => 'std_logic_vector(31 downto 0)',
26706
                        'width' => 32,
26707
                      },
26708
                      'data_in_x2' => {
26709
                        'attributes' => {
26710
                          'bin_pt' => 0,
26711
                          'is_floating_block' => 1,
26712
                          'must_be_hdl_vector' => 1,
26713
                          'period' => 1,
26714
                          'port_id' => 37,
26715
                          'simulinkName' => 'USER_LOGIC/tx_en_in97',
26716
                          'type' => 'Bool',
26717
                        },
26718
                        'direction' => 'out',
26719
                        'hdlType' => 'std_logic',
26720
                        'width' => 1,
26721
                      },
26722
                      'data_in_x20' => {
26723
                        'attributes' => {
26724
                          'bin_pt' => 0,
26725
                          'is_floating_block' => 1,
26726
                          'must_be_hdl_vector' => 1,
26727
                          'period' => 1,
26728
                          'port_id' => 2,
26729
                          'simulinkName' => 'USER_LOGIC/tx_en_in10',
26730
                          'type' => 'UFix_32_0',
26731
                        },
26732
                        'direction' => 'out',
26733
                        'hdlType' => 'std_logic_vector(31 downto 0)',
26734
                        'width' => 32,
26735
                      },
26736
                      'data_in_x21' => {
26737
                        'attributes' => {
26738
                          'bin_pt' => 0,
26739
                          'is_floating_block' => 1,
26740
                          'must_be_hdl_vector' => 1,
26741
                          'period' => 1,
26742
                          'port_id' => 34,
26743
                          'simulinkName' => 'USER_LOGIC/tx_en_in94',
26744
                          'type' => 'Bool',
26745
                        },
26746
                        'direction' => 'out',
26747
                        'hdlType' => 'std_logic',
26748
                        'width' => 1,
26749
                      },
26750
                      'data_in_x22' => {
26751
                        'attributes' => {
26752
                          'bin_pt' => 0,
26753
                          'is_floating_block' => 1,
26754
                          'must_be_hdl_vector' => 1,
26755
                          'period' => 1,
26756
                          'port_id' => 29,
26757
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                        'hdlType' => 'std_logic',
27790
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27791
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27792
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27793
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27794
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27795
                          'inputFile' => 'pcie_userlogic_00_user_logic_fifo_rd_valid.dat',
27796
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27797
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27798
                          'must_be_hdl_vector' => 1,
27799
                          'period' => 1,
27800
                          'port_id' => 5,
27801
                          'simulinkName' => 'USER_LOGIC/FIFO_rd_valid',
27802
                          'source_block' => 'USER_LOGIC',
27803
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27804
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27805
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27806
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27807
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27808
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27809
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27810
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27811
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27812
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27813
                          'inputFile' => 'pcie_userlogic_00_user_logic_fifo_wr_count.dat',
27814
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27815
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27816
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27817
                          'period' => 1,
27818
                          'port_id' => 6,
27819
                          'simulinkName' => 'USER_LOGIC/FIFO_wr_count',
27820
                          'source_block' => 'USER_LOGIC',
27821
                          'timingConstraint' => 'none',
27822
                          'type' => 'UFix_15_0',
27823
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27824
                        'direction' => 'in',
27825
                        'hdlType' => 'std_logic_vector(14 downto 0)',
27826
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27827
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27828
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27829
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27830
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27831
                          'inputFile' => 'pcie_userlogic_00_user_logic_fifo_wr_din.dat',
27832
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27833
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27834
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27835
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27836
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27837
                          'simulinkName' => 'USER_LOGIC/FIFO_wr_din',
27838
                          'source_block' => 'USER_LOGIC',
27839
                          'timingConstraint' => 'none',
27840
                          'type' => 'UFix_72_0',
27841
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27842
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27843
                        'hdlType' => 'std_logic_vector(71 downto 0)',
27844
                        'width' => 72,
27845
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27846
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27847
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27848
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27849
                          'inputFile' => 'pcie_userlogic_00_user_logic_fifo_wr_en.dat',
27850
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27851
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27852
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27853
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27854
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27855
                          'simulinkName' => 'USER_LOGIC/FIFO_wr_en',
27856
                          'source_block' => 'USER_LOGIC',
27857
                          'timingConstraint' => 'none',
27858
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27859
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27860
                        'direction' => 'out',
27861
                        'hdlType' => 'std_logic',
27862
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27863
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27864
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27865
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27866
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27867
                          'inputFile' => 'pcie_userlogic_00_user_logic_fifo_wr_full.dat',
27868
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27869
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27870
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27871
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27872
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27873
                          'simulinkName' => 'USER_LOGIC/FIFO_wr_full',
27874
                          'source_block' => 'USER_LOGIC',
27875
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27876
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27877
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27878
                        'direction' => 'in',
27879
                        'hdlType' => 'std_logic',
27880
                        'width' => 1,
27881
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27882
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27883
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27884
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27885
                          'inputFile' => 'pcie_userlogic_00_user_logic_fifo_wr_pfull.dat',
27886
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27887
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27888
                          'must_be_hdl_vector' => 1,
27889
                          'period' => 1,
27890
                          'port_id' => 8,
27891
                          'simulinkName' => 'USER_LOGIC/FIFO_wr_pfull',
27892
                          'source_block' => 'USER_LOGIC',
27893
                          'timingConstraint' => 'none',
27894
                          'type' => 'Bool',
27895
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27896
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27897
                        'hdlType' => 'std_logic',
27898
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27899
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27900
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27901
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27902
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27903
                          'inputFile' => 'pcie_userlogic_00_user_logic_rst_i.dat',
27904
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27905
                          'is_gateway_port' => 1,
27906
                          'must_be_hdl_vector' => 1,
27907
                          'period' => 1,
27908
                          'port_id' => 37,
27909
                          'simulinkName' => 'USER_LOGIC/rst_i',
27910
                          'source_block' => 'USER_LOGIC',
27911
                          'timingConstraint' => 'none',
27912
                          'type' => 'Bool',
27913
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27914
                        'direction' => 'in',
27915
                        'hdlType' => 'std_logic',
27916
                        'width' => 1,
27917
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27918
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27919
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27920
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27921
                          'inputFile' => 'pcie_userlogic_00_user_logic_rst_o.dat',
27922
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27923
                          'is_gateway_port' => 1,
27924
                          'must_be_hdl_vector' => 1,
27925
                          'period' => 1,
27926
                          'port_id' => 19,
27927
                          'simulinkName' => 'USER_LOGIC/rst_o',
27928
                          'source_block' => 'USER_LOGIC',
27929
                          'timingConstraint' => 'none',
27930
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27931
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27932
                        'direction' => 'out',
27933
                        'hdlType' => 'std_logic',
27934
                        'width' => 1,
27935
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27936
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27937
                        'attributes' => {
27938
                          'bin_pt' => 0,
27939
                          'inputFile' => 'pcie_userlogic_00_user_logic_user_int_1o.dat',
27940
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27941
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27942
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27943
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27944
                          'port_id' => 20,
27945
                          'simulinkName' => 'USER_LOGIC/user_int_1o',
27946
                          'source_block' => 'USER_LOGIC',
27947
                          'timingConstraint' => 'none',
27948
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27949
                        },
27950
                        'direction' => 'out',
27951
                        'hdlType' => 'std_logic',
27952
                        'width' => 1,
27953
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27954
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27955
                        'attributes' => {
27956
                          'bin_pt' => 0,
27957
                          'inputFile' => 'pcie_userlogic_00_user_logic_user_int_2o.dat',
27958
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27959
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27960
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27961
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27962
                          'port_id' => 30,
27963
                          'simulinkName' => 'USER_LOGIC/user_int_2o',
27964
                          'source_block' => 'USER_LOGIC',
27965
                          'timingConstraint' => 'none',
27966
                          'type' => 'Bool',
27967
                        },
27968
                        'direction' => 'out',
27969
                        'hdlType' => 'std_logic',
27970
                        'width' => 1,
27971
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27972
                      'user_int_3o' => {
27973
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27974
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27975
                          'inputFile' => 'pcie_userlogic_00_user_logic_user_int_3o.dat',
27976
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27977
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27978
                          'must_be_hdl_vector' => 1,
27979
                          'period' => 1,
27980
                          'port_id' => 25,
27981
                          'simulinkName' => 'USER_LOGIC/user_int_3o',
27982
                          'source_block' => 'USER_LOGIC',
27983
                          'timingConstraint' => 'none',
27984
                          'type' => 'Bool',
27985
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27986
                        'direction' => 'out',
27987
                        'hdlType' => 'std_logic',
27988
                        'width' => 1,
27989
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27990
                    },
27991
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27992
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27993
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27994
              },
27995
            },
27996
            'entityName' => 'user_logic_cw',
27997
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27998
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27999
      },
28000
      'entityName' => 'PCIe_UserLogic_00',
28001
    },
28002
  },
28003
}

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