1 |
13 |
barabba |
|
2 |
|
|
-------------------------------------------------------------------
|
3 |
|
|
-- System Generator version 13.2 VHDL source file.
|
4 |
|
|
--
|
5 |
|
|
-- Copyright(C) 2011 by Xilinx, Inc. All rights reserved. This
|
6 |
|
|
-- text/file contains proprietary, confidential information of Xilinx,
|
7 |
|
|
-- Inc., is distributed under license from Xilinx, Inc., and may be used,
|
8 |
|
|
-- copied and/or disclosed only pursuant to the terms of a valid license
|
9 |
|
|
-- agreement with Xilinx, Inc. Xilinx hereby grants you a license to use
|
10 |
|
|
-- this text/file solely for design, simulation, implementation and
|
11 |
|
|
-- creation of design files limited to Xilinx devices or technologies.
|
12 |
|
|
-- Use with non-Xilinx devices or technologies is expressly prohibited
|
13 |
|
|
-- and immediately terminates your license unless covered by a separate
|
14 |
|
|
-- agreement.
|
15 |
|
|
--
|
16 |
|
|
-- Xilinx is providing this design, code, or information "as is" solely
|
17 |
|
|
-- for use in developing programs and solutions for Xilinx devices. By
|
18 |
|
|
-- providing this design, code, or information as one possible
|
19 |
|
|
-- implementation of this feature, application or standard, Xilinx is
|
20 |
|
|
-- making no representation that this implementation is free from any
|
21 |
|
|
-- claims of infringement. You are responsible for obtaining any rights
|
22 |
|
|
-- you may require for your implementation. Xilinx expressly disclaims
|
23 |
|
|
-- any warranty whatsoever with respect to the adequacy of the
|
24 |
|
|
-- implementation, including but not limited to warranties of
|
25 |
|
|
-- merchantability or fitness for a particular purpose.
|
26 |
|
|
--
|
27 |
|
|
-- Xilinx products are not intended for use in life support appliances,
|
28 |
|
|
-- devices, or systems. Use in such applications is expressly prohibited.
|
29 |
|
|
--
|
30 |
|
|
-- Any modifications that are made to the source code are done at the user's
|
31 |
|
|
-- sole risk and will be unsupported.
|
32 |
|
|
--
|
33 |
|
|
-- This copyright and support notice must be retained as part of this
|
34 |
|
|
-- text at all times. (c) Copyright 1995-2011 Xilinx, Inc. All rights
|
35 |
|
|
-- reserved.
|
36 |
|
|
-------------------------------------------------------------------
|
37 |
|
|
-- The following code must appear in the VHDL architecture header:
|
38 |
|
|
|
39 |
|
|
------------- Begin Cut here for COMPONENT Declaration ------ COMP_TAG
|
40 |
|
|
component inout_logic_cw port (
|
41 |
|
|
ce: in std_logic := '1';
|
42 |
|
|
clk: in std_logic; -- clock period = 5.0 ns (200.0 Mhz)
|
43 |
|
|
debug_in_1i: in std_logic_vector(31 downto 0);
|
44 |
|
|
debug_in_2i: in std_logic_vector(31 downto 0);
|
45 |
|
|
debug_in_3i: in std_logic_vector(31 downto 0);
|
46 |
|
|
debug_in_4i: in std_logic_vector(31 downto 0);
|
47 |
|
|
dma_host2board_busy: in std_logic;
|
48 |
|
|
dma_host2board_done: in std_logic;
|
49 |
|
|
from_register10_data_out: in std_logic_vector(31 downto 0);
|
50 |
|
|
from_register11_data_out: in std_logic_vector(31 downto 0);
|
51 |
|
|
from_register12_data_out: in std_logic_vector(0 downto 0);
|
52 |
|
|
from_register13_data_out: in std_logic_vector(31 downto 0);
|
53 |
|
|
from_register14_data_out: in std_logic_vector(0 downto 0);
|
54 |
|
|
from_register15_data_out: in std_logic_vector(31 downto 0);
|
55 |
|
|
from_register16_data_out: in std_logic_vector(0 downto 0);
|
56 |
|
|
from_register17_data_out: in std_logic_vector(31 downto 0);
|
57 |
|
|
from_register18_data_out: in std_logic_vector(0 downto 0);
|
58 |
|
|
from_register19_data_out: in std_logic_vector(31 downto 0);
|
59 |
|
|
from_register1_data_out: in std_logic_vector(0 downto 0);
|
60 |
|
|
from_register20_data_out: in std_logic_vector(0 downto 0);
|
61 |
|
|
from_register21_data_out: in std_logic_vector(31 downto 0);
|
62 |
|
|
from_register22_data_out: in std_logic_vector(0 downto 0);
|
63 |
|
|
from_register23_data_out: in std_logic_vector(31 downto 0);
|
64 |
|
|
from_register24_data_out: in std_logic_vector(0 downto 0);
|
65 |
|
|
from_register25_data_out: in std_logic_vector(31 downto 0);
|
66 |
|
|
from_register26_data_out: in std_logic_vector(0 downto 0);
|
67 |
|
|
from_register27_data_out: in std_logic_vector(31 downto 0);
|
68 |
|
|
from_register28_data_out: in std_logic_vector(0 downto 0);
|
69 |
|
|
from_register2_data_out: in std_logic_vector(0 downto 0);
|
70 |
|
|
from_register3_data_out: in std_logic_vector(31 downto 0);
|
71 |
|
|
from_register4_data_out: in std_logic_vector(0 downto 0);
|
72 |
|
|
from_register5_data_out: in std_logic_vector(31 downto 0);
|
73 |
|
|
from_register6_data_out: in std_logic_vector(0 downto 0);
|
74 |
|
|
from_register7_data_out: in std_logic_vector(31 downto 0);
|
75 |
|
|
from_register8_data_out: in std_logic_vector(31 downto 0);
|
76 |
|
|
from_register9_data_out: in std_logic_vector(0 downto 0);
|
77 |
|
|
reg01_td: in std_logic_vector(31 downto 0);
|
78 |
|
|
reg01_tv: in std_logic;
|
79 |
|
|
reg02_td: in std_logic_vector(31 downto 0);
|
80 |
|
|
reg02_tv: in std_logic;
|
81 |
|
|
reg03_td: in std_logic_vector(31 downto 0);
|
82 |
|
|
reg03_tv: in std_logic;
|
83 |
|
|
reg04_td: in std_logic_vector(31 downto 0);
|
84 |
|
|
reg04_tv: in std_logic;
|
85 |
|
|
reg05_td: in std_logic_vector(31 downto 0);
|
86 |
|
|
reg05_tv: in std_logic;
|
87 |
|
|
reg06_td: in std_logic_vector(31 downto 0);
|
88 |
|
|
reg06_tv: in std_logic;
|
89 |
|
|
reg07_td: in std_logic_vector(31 downto 0);
|
90 |
|
|
reg07_tv: in std_logic;
|
91 |
|
|
reg08_td: in std_logic_vector(31 downto 0);
|
92 |
|
|
reg08_tv: in std_logic;
|
93 |
|
|
reg09_td: in std_logic_vector(31 downto 0);
|
94 |
|
|
reg09_tv: in std_logic;
|
95 |
|
|
reg10_td: in std_logic_vector(31 downto 0);
|
96 |
|
|
reg10_tv: in std_logic;
|
97 |
|
|
reg11_td: in std_logic_vector(31 downto 0);
|
98 |
|
|
reg11_tv: in std_logic;
|
99 |
|
|
reg12_td: in std_logic_vector(31 downto 0);
|
100 |
|
|
reg12_tv: in std_logic;
|
101 |
|
|
reg13_td: in std_logic_vector(31 downto 0);
|
102 |
|
|
reg13_tv: in std_logic;
|
103 |
|
|
reg14_td: in std_logic_vector(31 downto 0);
|
104 |
|
|
reg14_tv: in std_logic;
|
105 |
|
|
to_register10_dout: in std_logic_vector(0 downto 0);
|
106 |
|
|
to_register11_dout: in std_logic_vector(31 downto 0);
|
107 |
|
|
to_register12_dout: in std_logic_vector(0 downto 0);
|
108 |
|
|
to_register13_dout: in std_logic_vector(31 downto 0);
|
109 |
|
|
to_register14_dout: in std_logic_vector(0 downto 0);
|
110 |
|
|
to_register15_dout: in std_logic_vector(31 downto 0);
|
111 |
|
|
to_register16_dout: in std_logic_vector(0 downto 0);
|
112 |
|
|
to_register17_dout: in std_logic_vector(31 downto 0);
|
113 |
|
|
to_register18_dout: in std_logic_vector(0 downto 0);
|
114 |
|
|
to_register19_dout: in std_logic_vector(0 downto 0);
|
115 |
|
|
to_register1_dout: in std_logic_vector(31 downto 0);
|
116 |
|
|
to_register20_dout: in std_logic_vector(31 downto 0);
|
117 |
|
|
to_register21_dout: in std_logic_vector(0 downto 0);
|
118 |
|
|
to_register22_dout: in std_logic_vector(31 downto 0);
|
119 |
|
|
to_register23_dout: in std_logic_vector(0 downto 0);
|
120 |
|
|
to_register24_dout: in std_logic_vector(31 downto 0);
|
121 |
|
|
to_register25_dout: in std_logic_vector(0 downto 0);
|
122 |
|
|
to_register26_dout: in std_logic_vector(31 downto 0);
|
123 |
|
|
to_register27_dout: in std_logic_vector(0 downto 0);
|
124 |
|
|
to_register28_dout: in std_logic_vector(31 downto 0);
|
125 |
|
|
to_register29_dout: in std_logic_vector(0 downto 0);
|
126 |
|
|
to_register2_dout: in std_logic_vector(31 downto 0);
|
127 |
|
|
to_register30_dout: in std_logic_vector(31 downto 0);
|
128 |
|
|
to_register31_dout: in std_logic_vector(0 downto 0);
|
129 |
|
|
to_register32_dout: in std_logic_vector(31 downto 0);
|
130 |
|
|
to_register33_dout: in std_logic_vector(0 downto 0);
|
131 |
|
|
to_register34_dout: in std_logic_vector(31 downto 0);
|
132 |
|
|
to_register3_dout: in std_logic_vector(0 downto 0);
|
133 |
|
|
to_register4_dout: in std_logic_vector(0 downto 0);
|
134 |
|
|
to_register5_dout: in std_logic_vector(31 downto 0);
|
135 |
|
|
to_register6_dout: in std_logic_vector(31 downto 0);
|
136 |
|
|
to_register7_dout: in std_logic_vector(31 downto 0);
|
137 |
|
|
to_register8_dout: in std_logic_vector(0 downto 0);
|
138 |
|
|
to_register9_dout: in std_logic_vector(31 downto 0);
|
139 |
|
|
reg01_rd: out std_logic_vector(31 downto 0);
|
140 |
|
|
reg01_rv: out std_logic;
|
141 |
|
|
reg02_rd: out std_logic_vector(31 downto 0);
|
142 |
|
|
reg02_rv: out std_logic;
|
143 |
|
|
reg03_rd: out std_logic_vector(31 downto 0);
|
144 |
|
|
reg03_rv: out std_logic;
|
145 |
|
|
reg04_rd: out std_logic_vector(31 downto 0);
|
146 |
|
|
reg04_rv: out std_logic;
|
147 |
|
|
reg05_rd: out std_logic_vector(31 downto 0);
|
148 |
|
|
reg05_rv: out std_logic;
|
149 |
|
|
reg06_rd: out std_logic_vector(31 downto 0);
|
150 |
|
|
reg06_rv: out std_logic;
|
151 |
|
|
reg07_rd: out std_logic_vector(31 downto 0);
|
152 |
|
|
reg07_rv: out std_logic;
|
153 |
|
|
reg08_rd: out std_logic_vector(31 downto 0);
|
154 |
|
|
reg08_rv: out std_logic;
|
155 |
|
|
reg09_rd: out std_logic_vector(31 downto 0);
|
156 |
|
|
reg09_rv: out std_logic;
|
157 |
|
|
reg10_rd: out std_logic_vector(31 downto 0);
|
158 |
|
|
reg10_rv: out std_logic;
|
159 |
|
|
reg11_rd: out std_logic_vector(31 downto 0);
|
160 |
|
|
reg11_rv: out std_logic;
|
161 |
|
|
reg12_rd: out std_logic_vector(31 downto 0);
|
162 |
|
|
reg12_rv: out std_logic;
|
163 |
|
|
reg13_rd: out std_logic_vector(31 downto 0);
|
164 |
|
|
reg13_rv: out std_logic;
|
165 |
|
|
reg14_rd: out std_logic_vector(31 downto 0);
|
166 |
|
|
reg14_rv: out std_logic;
|
167 |
|
|
to_register10_ce: out std_logic;
|
168 |
|
|
to_register10_clk: out std_logic; -- clock period = 5.0 ns (200.0 Mhz)
|
169 |
|
|
to_register10_clr: out std_logic;
|
170 |
|
|
to_register10_data_in: out std_logic_vector(0 downto 0);
|
171 |
|
|
to_register10_en: out std_logic_vector(0 downto 0);
|
172 |
|
|
to_register11_ce: out std_logic;
|
173 |
|
|
to_register11_clk: out std_logic; -- clock period = 5.0 ns (200.0 Mhz)
|
174 |
|
|
to_register11_clr: out std_logic;
|
175 |
|
|
to_register11_data_in: out std_logic_vector(31 downto 0);
|
176 |
|
|
to_register11_en: out std_logic_vector(0 downto 0);
|
177 |
|
|
to_register12_ce: out std_logic;
|
178 |
|
|
to_register12_clk: out std_logic; -- clock period = 5.0 ns (200.0 Mhz)
|
179 |
|
|
to_register12_clr: out std_logic;
|
180 |
|
|
to_register12_data_in: out std_logic_vector(0 downto 0);
|
181 |
|
|
to_register12_en: out std_logic_vector(0 downto 0);
|
182 |
|
|
to_register13_ce: out std_logic;
|
183 |
|
|
to_register13_clk: out std_logic; -- clock period = 5.0 ns (200.0 Mhz)
|
184 |
|
|
to_register13_clr: out std_logic;
|
185 |
|
|
to_register13_data_in: out std_logic_vector(31 downto 0);
|
186 |
|
|
to_register13_en: out std_logic_vector(0 downto 0);
|
187 |
|
|
to_register14_ce: out std_logic;
|
188 |
|
|
to_register14_clk: out std_logic; -- clock period = 5.0 ns (200.0 Mhz)
|
189 |
|
|
to_register14_clr: out std_logic;
|
190 |
|
|
to_register14_data_in: out std_logic_vector(0 downto 0);
|
191 |
|
|
to_register14_en: out std_logic_vector(0 downto 0);
|
192 |
|
|
to_register15_ce: out std_logic;
|
193 |
|
|
to_register15_clk: out std_logic; -- clock period = 5.0 ns (200.0 Mhz)
|
194 |
|
|
to_register15_clr: out std_logic;
|
195 |
|
|
to_register15_data_in: out std_logic_vector(31 downto 0);
|
196 |
|
|
to_register15_en: out std_logic_vector(0 downto 0);
|
197 |
|
|
to_register16_ce: out std_logic;
|
198 |
|
|
to_register16_clk: out std_logic; -- clock period = 5.0 ns (200.0 Mhz)
|
199 |
|
|
to_register16_clr: out std_logic;
|
200 |
|
|
to_register16_data_in: out std_logic_vector(0 downto 0);
|
201 |
|
|
to_register16_en: out std_logic_vector(0 downto 0);
|
202 |
|
|
to_register17_ce: out std_logic;
|
203 |
|
|
to_register17_clk: out std_logic; -- clock period = 5.0 ns (200.0 Mhz)
|
204 |
|
|
to_register17_clr: out std_logic;
|
205 |
|
|
to_register17_data_in: out std_logic_vector(31 downto 0);
|
206 |
|
|
to_register17_en: out std_logic_vector(0 downto 0);
|
207 |
|
|
to_register18_ce: out std_logic;
|
208 |
|
|
to_register18_clk: out std_logic; -- clock period = 5.0 ns (200.0 Mhz)
|
209 |
|
|
to_register18_clr: out std_logic;
|
210 |
|
|
to_register18_data_in: out std_logic_vector(0 downto 0);
|
211 |
|
|
to_register18_en: out std_logic_vector(0 downto 0);
|
212 |
|
|
to_register19_ce: out std_logic;
|
213 |
|
|
to_register19_clk: out std_logic; -- clock period = 5.0 ns (200.0 Mhz)
|
214 |
|
|
to_register19_clr: out std_logic;
|
215 |
|
|
to_register19_data_in: out std_logic_vector(0 downto 0);
|
216 |
|
|
to_register19_en: out std_logic_vector(0 downto 0);
|
217 |
|
|
to_register1_ce: out std_logic;
|
218 |
|
|
to_register1_clk: out std_logic; -- clock period = 5.0 ns (200.0 Mhz)
|
219 |
|
|
to_register1_clr: out std_logic;
|
220 |
|
|
to_register1_data_in: out std_logic_vector(31 downto 0);
|
221 |
|
|
to_register1_en: out std_logic_vector(0 downto 0);
|
222 |
|
|
to_register20_ce: out std_logic;
|
223 |
|
|
to_register20_clk: out std_logic; -- clock period = 5.0 ns (200.0 Mhz)
|
224 |
|
|
to_register20_clr: out std_logic;
|
225 |
|
|
to_register20_data_in: out std_logic_vector(31 downto 0);
|
226 |
|
|
to_register20_en: out std_logic_vector(0 downto 0);
|
227 |
|
|
to_register21_ce: out std_logic;
|
228 |
|
|
to_register21_clk: out std_logic; -- clock period = 5.0 ns (200.0 Mhz)
|
229 |
|
|
to_register21_clr: out std_logic;
|
230 |
|
|
to_register21_data_in: out std_logic_vector(0 downto 0);
|
231 |
|
|
to_register21_en: out std_logic_vector(0 downto 0);
|
232 |
|
|
to_register22_ce: out std_logic;
|
233 |
|
|
to_register22_clk: out std_logic; -- clock period = 5.0 ns (200.0 Mhz)
|
234 |
|
|
to_register22_clr: out std_logic;
|
235 |
|
|
to_register22_data_in: out std_logic_vector(31 downto 0);
|
236 |
|
|
to_register22_en: out std_logic_vector(0 downto 0);
|
237 |
|
|
to_register23_ce: out std_logic;
|
238 |
|
|
to_register23_clk: out std_logic; -- clock period = 5.0 ns (200.0 Mhz)
|
239 |
|
|
to_register23_clr: out std_logic;
|
240 |
|
|
to_register23_data_in: out std_logic_vector(0 downto 0);
|
241 |
|
|
to_register23_en: out std_logic_vector(0 downto 0);
|
242 |
|
|
to_register24_ce: out std_logic;
|
243 |
|
|
to_register24_clk: out std_logic; -- clock period = 5.0 ns (200.0 Mhz)
|
244 |
|
|
to_register24_clr: out std_logic;
|
245 |
|
|
to_register24_data_in: out std_logic_vector(31 downto 0);
|
246 |
|
|
to_register24_en: out std_logic_vector(0 downto 0);
|
247 |
|
|
to_register25_ce: out std_logic;
|
248 |
|
|
to_register25_clk: out std_logic; -- clock period = 5.0 ns (200.0 Mhz)
|
249 |
|
|
to_register25_clr: out std_logic;
|
250 |
|
|
to_register25_data_in: out std_logic_vector(0 downto 0);
|
251 |
|
|
to_register25_en: out std_logic_vector(0 downto 0);
|
252 |
|
|
to_register26_ce: out std_logic;
|
253 |
|
|
to_register26_clk: out std_logic; -- clock period = 5.0 ns (200.0 Mhz)
|
254 |
|
|
to_register26_clr: out std_logic;
|
255 |
|
|
to_register26_data_in: out std_logic_vector(31 downto 0);
|
256 |
|
|
to_register26_en: out std_logic_vector(0 downto 0);
|
257 |
|
|
to_register27_ce: out std_logic;
|
258 |
|
|
to_register27_clk: out std_logic; -- clock period = 5.0 ns (200.0 Mhz)
|
259 |
|
|
to_register27_clr: out std_logic;
|
260 |
|
|
to_register27_data_in: out std_logic_vector(0 downto 0);
|
261 |
|
|
to_register27_en: out std_logic_vector(0 downto 0);
|
262 |
|
|
to_register28_ce: out std_logic;
|
263 |
|
|
to_register28_clk: out std_logic; -- clock period = 5.0 ns (200.0 Mhz)
|
264 |
|
|
to_register28_clr: out std_logic;
|
265 |
|
|
to_register28_data_in: out std_logic_vector(31 downto 0);
|
266 |
|
|
to_register28_en: out std_logic_vector(0 downto 0);
|
267 |
|
|
to_register29_ce: out std_logic;
|
268 |
|
|
to_register29_clk: out std_logic; -- clock period = 5.0 ns (200.0 Mhz)
|
269 |
|
|
to_register29_clr: out std_logic;
|
270 |
|
|
to_register29_data_in: out std_logic_vector(0 downto 0);
|
271 |
|
|
to_register29_en: out std_logic_vector(0 downto 0);
|
272 |
|
|
to_register2_ce: out std_logic;
|
273 |
|
|
to_register2_clk: out std_logic; -- clock period = 5.0 ns (200.0 Mhz)
|
274 |
|
|
to_register2_clr: out std_logic;
|
275 |
|
|
to_register2_data_in: out std_logic_vector(31 downto 0);
|
276 |
|
|
to_register2_en: out std_logic_vector(0 downto 0);
|
277 |
|
|
to_register30_ce: out std_logic;
|
278 |
|
|
to_register30_clk: out std_logic; -- clock period = 5.0 ns (200.0 Mhz)
|
279 |
|
|
to_register30_clr: out std_logic;
|
280 |
|
|
to_register30_data_in: out std_logic_vector(31 downto 0);
|
281 |
|
|
to_register30_en: out std_logic_vector(0 downto 0);
|
282 |
|
|
to_register31_ce: out std_logic;
|
283 |
|
|
to_register31_clk: out std_logic; -- clock period = 5.0 ns (200.0 Mhz)
|
284 |
|
|
to_register31_clr: out std_logic;
|
285 |
|
|
to_register31_data_in: out std_logic_vector(0 downto 0);
|
286 |
|
|
to_register31_en: out std_logic_vector(0 downto 0);
|
287 |
|
|
to_register32_ce: out std_logic;
|
288 |
|
|
to_register32_clk: out std_logic; -- clock period = 5.0 ns (200.0 Mhz)
|
289 |
|
|
to_register32_clr: out std_logic;
|
290 |
|
|
to_register32_data_in: out std_logic_vector(31 downto 0);
|
291 |
|
|
to_register32_en: out std_logic_vector(0 downto 0);
|
292 |
|
|
to_register33_ce: out std_logic;
|
293 |
|
|
to_register33_clk: out std_logic; -- clock period = 5.0 ns (200.0 Mhz)
|
294 |
|
|
to_register33_clr: out std_logic;
|
295 |
|
|
to_register33_data_in: out std_logic_vector(0 downto 0);
|
296 |
|
|
to_register33_en: out std_logic_vector(0 downto 0);
|
297 |
|
|
to_register34_ce: out std_logic;
|
298 |
|
|
to_register34_clk: out std_logic; -- clock period = 5.0 ns (200.0 Mhz)
|
299 |
|
|
to_register34_clr: out std_logic;
|
300 |
|
|
to_register34_data_in: out std_logic_vector(31 downto 0);
|
301 |
|
|
to_register34_en: out std_logic_vector(0 downto 0);
|
302 |
|
|
to_register3_ce: out std_logic;
|
303 |
|
|
to_register3_clk: out std_logic; -- clock period = 5.0 ns (200.0 Mhz)
|
304 |
|
|
to_register3_clr: out std_logic;
|
305 |
|
|
to_register3_data_in: out std_logic_vector(0 downto 0);
|
306 |
|
|
to_register3_en: out std_logic_vector(0 downto 0);
|
307 |
|
|
to_register4_ce: out std_logic;
|
308 |
|
|
to_register4_clk: out std_logic; -- clock period = 5.0 ns (200.0 Mhz)
|
309 |
|
|
to_register4_clr: out std_logic;
|
310 |
|
|
to_register4_data_in: out std_logic_vector(0 downto 0);
|
311 |
|
|
to_register4_en: out std_logic_vector(0 downto 0);
|
312 |
|
|
to_register5_ce: out std_logic;
|
313 |
|
|
to_register5_clk: out std_logic; -- clock period = 5.0 ns (200.0 Mhz)
|
314 |
|
|
to_register5_clr: out std_logic;
|
315 |
|
|
to_register5_data_in: out std_logic_vector(31 downto 0);
|
316 |
|
|
to_register5_en: out std_logic_vector(0 downto 0);
|
317 |
|
|
to_register6_ce: out std_logic;
|
318 |
|
|
to_register6_clk: out std_logic; -- clock period = 5.0 ns (200.0 Mhz)
|
319 |
|
|
to_register6_clr: out std_logic;
|
320 |
|
|
to_register6_data_in: out std_logic_vector(31 downto 0);
|
321 |
|
|
to_register6_en: out std_logic_vector(0 downto 0);
|
322 |
|
|
to_register7_ce: out std_logic;
|
323 |
|
|
to_register7_clk: out std_logic; -- clock period = 5.0 ns (200.0 Mhz)
|
324 |
|
|
to_register7_clr: out std_logic;
|
325 |
|
|
to_register7_data_in: out std_logic_vector(31 downto 0);
|
326 |
|
|
to_register7_en: out std_logic_vector(0 downto 0);
|
327 |
|
|
to_register8_ce: out std_logic;
|
328 |
|
|
to_register8_clk: out std_logic; -- clock period = 5.0 ns (200.0 Mhz)
|
329 |
|
|
to_register8_clr: out std_logic;
|
330 |
|
|
to_register8_data_in: out std_logic_vector(0 downto 0);
|
331 |
|
|
to_register8_en: out std_logic_vector(0 downto 0);
|
332 |
|
|
to_register9_ce: out std_logic;
|
333 |
|
|
to_register9_clk: out std_logic; -- clock period = 5.0 ns (200.0 Mhz)
|
334 |
|
|
to_register9_clr: out std_logic;
|
335 |
|
|
to_register9_data_in: out std_logic_vector(31 downto 0);
|
336 |
|
|
to_register9_en: out std_logic_vector(0 downto 0)
|
337 |
|
|
);
|
338 |
|
|
end component;
|
339 |
|
|
-- COMP_TAG_END ------ End COMPONENT Declaration ------------
|
340 |
|
|
|
341 |
|
|
-- The following code must appear in the VHDL architecture
|
342 |
|
|
-- body. Substitute your own instance name and net names.
|
343 |
|
|
|
344 |
|
|
------------- Begin Cut here for INSTANTIATION Template ----- INST_TAG
|
345 |
|
|
your_instance_name : inout_logic_cw
|
346 |
|
|
port map (
|
347 |
|
|
ce => ce,
|
348 |
|
|
clk => clk,
|
349 |
|
|
debug_in_1i => debug_in_1i,
|
350 |
|
|
debug_in_2i => debug_in_2i,
|
351 |
|
|
debug_in_3i => debug_in_3i,
|
352 |
|
|
debug_in_4i => debug_in_4i,
|
353 |
|
|
dma_host2board_busy => dma_host2board_busy,
|
354 |
|
|
dma_host2board_done => dma_host2board_done,
|
355 |
|
|
from_register10_data_out => from_register10_data_out,
|
356 |
|
|
from_register11_data_out => from_register11_data_out,
|
357 |
|
|
from_register12_data_out => from_register12_data_out,
|
358 |
|
|
from_register13_data_out => from_register13_data_out,
|
359 |
|
|
from_register14_data_out => from_register14_data_out,
|
360 |
|
|
from_register15_data_out => from_register15_data_out,
|
361 |
|
|
from_register16_data_out => from_register16_data_out,
|
362 |
|
|
from_register17_data_out => from_register17_data_out,
|
363 |
|
|
from_register18_data_out => from_register18_data_out,
|
364 |
|
|
from_register19_data_out => from_register19_data_out,
|
365 |
|
|
from_register1_data_out => from_register1_data_out,
|
366 |
|
|
from_register20_data_out => from_register20_data_out,
|
367 |
|
|
from_register21_data_out => from_register21_data_out,
|
368 |
|
|
from_register22_data_out => from_register22_data_out,
|
369 |
|
|
from_register23_data_out => from_register23_data_out,
|
370 |
|
|
from_register24_data_out => from_register24_data_out,
|
371 |
|
|
from_register25_data_out => from_register25_data_out,
|
372 |
|
|
from_register26_data_out => from_register26_data_out,
|
373 |
|
|
from_register27_data_out => from_register27_data_out,
|
374 |
|
|
from_register28_data_out => from_register28_data_out,
|
375 |
|
|
from_register2_data_out => from_register2_data_out,
|
376 |
|
|
from_register3_data_out => from_register3_data_out,
|
377 |
|
|
from_register4_data_out => from_register4_data_out,
|
378 |
|
|
from_register5_data_out => from_register5_data_out,
|
379 |
|
|
from_register6_data_out => from_register6_data_out,
|
380 |
|
|
from_register7_data_out => from_register7_data_out,
|
381 |
|
|
from_register8_data_out => from_register8_data_out,
|
382 |
|
|
from_register9_data_out => from_register9_data_out,
|
383 |
|
|
reg01_td => reg01_td,
|
384 |
|
|
reg01_tv => reg01_tv,
|
385 |
|
|
reg02_td => reg02_td,
|
386 |
|
|
reg02_tv => reg02_tv,
|
387 |
|
|
reg03_td => reg03_td,
|
388 |
|
|
reg03_tv => reg03_tv,
|
389 |
|
|
reg04_td => reg04_td,
|
390 |
|
|
reg04_tv => reg04_tv,
|
391 |
|
|
reg05_td => reg05_td,
|
392 |
|
|
reg05_tv => reg05_tv,
|
393 |
|
|
reg06_td => reg06_td,
|
394 |
|
|
reg06_tv => reg06_tv,
|
395 |
|
|
reg07_td => reg07_td,
|
396 |
|
|
reg07_tv => reg07_tv,
|
397 |
|
|
reg08_td => reg08_td,
|
398 |
|
|
reg08_tv => reg08_tv,
|
399 |
|
|
reg09_td => reg09_td,
|
400 |
|
|
reg09_tv => reg09_tv,
|
401 |
|
|
reg10_td => reg10_td,
|
402 |
|
|
reg10_tv => reg10_tv,
|
403 |
|
|
reg11_td => reg11_td,
|
404 |
|
|
reg11_tv => reg11_tv,
|
405 |
|
|
reg12_td => reg12_td,
|
406 |
|
|
reg12_tv => reg12_tv,
|
407 |
|
|
reg13_td => reg13_td,
|
408 |
|
|
reg13_tv => reg13_tv,
|
409 |
|
|
reg14_td => reg14_td,
|
410 |
|
|
reg14_tv => reg14_tv,
|
411 |
|
|
to_register10_dout => to_register10_dout,
|
412 |
|
|
to_register11_dout => to_register11_dout,
|
413 |
|
|
to_register12_dout => to_register12_dout,
|
414 |
|
|
to_register13_dout => to_register13_dout,
|
415 |
|
|
to_register14_dout => to_register14_dout,
|
416 |
|
|
to_register15_dout => to_register15_dout,
|
417 |
|
|
to_register16_dout => to_register16_dout,
|
418 |
|
|
to_register17_dout => to_register17_dout,
|
419 |
|
|
to_register18_dout => to_register18_dout,
|
420 |
|
|
to_register19_dout => to_register19_dout,
|
421 |
|
|
to_register1_dout => to_register1_dout,
|
422 |
|
|
to_register20_dout => to_register20_dout,
|
423 |
|
|
to_register21_dout => to_register21_dout,
|
424 |
|
|
to_register22_dout => to_register22_dout,
|
425 |
|
|
to_register23_dout => to_register23_dout,
|
426 |
|
|
to_register24_dout => to_register24_dout,
|
427 |
|
|
to_register25_dout => to_register25_dout,
|
428 |
|
|
to_register26_dout => to_register26_dout,
|
429 |
|
|
to_register27_dout => to_register27_dout,
|
430 |
|
|
to_register28_dout => to_register28_dout,
|
431 |
|
|
to_register29_dout => to_register29_dout,
|
432 |
|
|
to_register2_dout => to_register2_dout,
|
433 |
|
|
to_register30_dout => to_register30_dout,
|
434 |
|
|
to_register31_dout => to_register31_dout,
|
435 |
|
|
to_register32_dout => to_register32_dout,
|
436 |
|
|
to_register33_dout => to_register33_dout,
|
437 |
|
|
to_register34_dout => to_register34_dout,
|
438 |
|
|
to_register3_dout => to_register3_dout,
|
439 |
|
|
to_register4_dout => to_register4_dout,
|
440 |
|
|
to_register5_dout => to_register5_dout,
|
441 |
|
|
to_register6_dout => to_register6_dout,
|
442 |
|
|
to_register7_dout => to_register7_dout,
|
443 |
|
|
to_register8_dout => to_register8_dout,
|
444 |
|
|
to_register9_dout => to_register9_dout,
|
445 |
|
|
reg01_rd => reg01_rd,
|
446 |
|
|
reg01_rv => reg01_rv,
|
447 |
|
|
reg02_rd => reg02_rd,
|
448 |
|
|
reg02_rv => reg02_rv,
|
449 |
|
|
reg03_rd => reg03_rd,
|
450 |
|
|
reg03_rv => reg03_rv,
|
451 |
|
|
reg04_rd => reg04_rd,
|
452 |
|
|
reg04_rv => reg04_rv,
|
453 |
|
|
reg05_rd => reg05_rd,
|
454 |
|
|
reg05_rv => reg05_rv,
|
455 |
|
|
reg06_rd => reg06_rd,
|
456 |
|
|
reg06_rv => reg06_rv,
|
457 |
|
|
reg07_rd => reg07_rd,
|
458 |
|
|
reg07_rv => reg07_rv,
|
459 |
|
|
reg08_rd => reg08_rd,
|
460 |
|
|
reg08_rv => reg08_rv,
|
461 |
|
|
reg09_rd => reg09_rd,
|
462 |
|
|
reg09_rv => reg09_rv,
|
463 |
|
|
reg10_rd => reg10_rd,
|
464 |
|
|
reg10_rv => reg10_rv,
|
465 |
|
|
reg11_rd => reg11_rd,
|
466 |
|
|
reg11_rv => reg11_rv,
|
467 |
|
|
reg12_rd => reg12_rd,
|
468 |
|
|
reg12_rv => reg12_rv,
|
469 |
|
|
reg13_rd => reg13_rd,
|
470 |
|
|
reg13_rv => reg13_rv,
|
471 |
|
|
reg14_rd => reg14_rd,
|
472 |
|
|
reg14_rv => reg14_rv,
|
473 |
|
|
to_register10_ce => to_register10_ce,
|
474 |
|
|
to_register10_clk => to_register10_clk,
|
475 |
|
|
to_register10_clr => to_register10_clr,
|
476 |
|
|
to_register10_data_in => to_register10_data_in,
|
477 |
|
|
to_register10_en => to_register10_en,
|
478 |
|
|
to_register11_ce => to_register11_ce,
|
479 |
|
|
to_register11_clk => to_register11_clk,
|
480 |
|
|
to_register11_clr => to_register11_clr,
|
481 |
|
|
to_register11_data_in => to_register11_data_in,
|
482 |
|
|
to_register11_en => to_register11_en,
|
483 |
|
|
to_register12_ce => to_register12_ce,
|
484 |
|
|
to_register12_clk => to_register12_clk,
|
485 |
|
|
to_register12_clr => to_register12_clr,
|
486 |
|
|
to_register12_data_in => to_register12_data_in,
|
487 |
|
|
to_register12_en => to_register12_en,
|
488 |
|
|
to_register13_ce => to_register13_ce,
|
489 |
|
|
to_register13_clk => to_register13_clk,
|
490 |
|
|
to_register13_clr => to_register13_clr,
|
491 |
|
|
to_register13_data_in => to_register13_data_in,
|
492 |
|
|
to_register13_en => to_register13_en,
|
493 |
|
|
to_register14_ce => to_register14_ce,
|
494 |
|
|
to_register14_clk => to_register14_clk,
|
495 |
|
|
to_register14_clr => to_register14_clr,
|
496 |
|
|
to_register14_data_in => to_register14_data_in,
|
497 |
|
|
to_register14_en => to_register14_en,
|
498 |
|
|
to_register15_ce => to_register15_ce,
|
499 |
|
|
to_register15_clk => to_register15_clk,
|
500 |
|
|
to_register15_clr => to_register15_clr,
|
501 |
|
|
to_register15_data_in => to_register15_data_in,
|
502 |
|
|
to_register15_en => to_register15_en,
|
503 |
|
|
to_register16_ce => to_register16_ce,
|
504 |
|
|
to_register16_clk => to_register16_clk,
|
505 |
|
|
to_register16_clr => to_register16_clr,
|
506 |
|
|
to_register16_data_in => to_register16_data_in,
|
507 |
|
|
to_register16_en => to_register16_en,
|
508 |
|
|
to_register17_ce => to_register17_ce,
|
509 |
|
|
to_register17_clk => to_register17_clk,
|
510 |
|
|
to_register17_clr => to_register17_clr,
|
511 |
|
|
to_register17_data_in => to_register17_data_in,
|
512 |
|
|
to_register17_en => to_register17_en,
|
513 |
|
|
to_register18_ce => to_register18_ce,
|
514 |
|
|
to_register18_clk => to_register18_clk,
|
515 |
|
|
to_register18_clr => to_register18_clr,
|
516 |
|
|
to_register18_data_in => to_register18_data_in,
|
517 |
|
|
to_register18_en => to_register18_en,
|
518 |
|
|
to_register19_ce => to_register19_ce,
|
519 |
|
|
to_register19_clk => to_register19_clk,
|
520 |
|
|
to_register19_clr => to_register19_clr,
|
521 |
|
|
to_register19_data_in => to_register19_data_in,
|
522 |
|
|
to_register19_en => to_register19_en,
|
523 |
|
|
to_register1_ce => to_register1_ce,
|
524 |
|
|
to_register1_clk => to_register1_clk,
|
525 |
|
|
to_register1_clr => to_register1_clr,
|
526 |
|
|
to_register1_data_in => to_register1_data_in,
|
527 |
|
|
to_register1_en => to_register1_en,
|
528 |
|
|
to_register20_ce => to_register20_ce,
|
529 |
|
|
to_register20_clk => to_register20_clk,
|
530 |
|
|
to_register20_clr => to_register20_clr,
|
531 |
|
|
to_register20_data_in => to_register20_data_in,
|
532 |
|
|
to_register20_en => to_register20_en,
|
533 |
|
|
to_register21_ce => to_register21_ce,
|
534 |
|
|
to_register21_clk => to_register21_clk,
|
535 |
|
|
to_register21_clr => to_register21_clr,
|
536 |
|
|
to_register21_data_in => to_register21_data_in,
|
537 |
|
|
to_register21_en => to_register21_en,
|
538 |
|
|
to_register22_ce => to_register22_ce,
|
539 |
|
|
to_register22_clk => to_register22_clk,
|
540 |
|
|
to_register22_clr => to_register22_clr,
|
541 |
|
|
to_register22_data_in => to_register22_data_in,
|
542 |
|
|
to_register22_en => to_register22_en,
|
543 |
|
|
to_register23_ce => to_register23_ce,
|
544 |
|
|
to_register23_clk => to_register23_clk,
|
545 |
|
|
to_register23_clr => to_register23_clr,
|
546 |
|
|
to_register23_data_in => to_register23_data_in,
|
547 |
|
|
to_register23_en => to_register23_en,
|
548 |
|
|
to_register24_ce => to_register24_ce,
|
549 |
|
|
to_register24_clk => to_register24_clk,
|
550 |
|
|
to_register24_clr => to_register24_clr,
|
551 |
|
|
to_register24_data_in => to_register24_data_in,
|
552 |
|
|
to_register24_en => to_register24_en,
|
553 |
|
|
to_register25_ce => to_register25_ce,
|
554 |
|
|
to_register25_clk => to_register25_clk,
|
555 |
|
|
to_register25_clr => to_register25_clr,
|
556 |
|
|
to_register25_data_in => to_register25_data_in,
|
557 |
|
|
to_register25_en => to_register25_en,
|
558 |
|
|
to_register26_ce => to_register26_ce,
|
559 |
|
|
to_register26_clk => to_register26_clk,
|
560 |
|
|
to_register26_clr => to_register26_clr,
|
561 |
|
|
to_register26_data_in => to_register26_data_in,
|
562 |
|
|
to_register26_en => to_register26_en,
|
563 |
|
|
to_register27_ce => to_register27_ce,
|
564 |
|
|
to_register27_clk => to_register27_clk,
|
565 |
|
|
to_register27_clr => to_register27_clr,
|
566 |
|
|
to_register27_data_in => to_register27_data_in,
|
567 |
|
|
to_register27_en => to_register27_en,
|
568 |
|
|
to_register28_ce => to_register28_ce,
|
569 |
|
|
to_register28_clk => to_register28_clk,
|
570 |
|
|
to_register28_clr => to_register28_clr,
|
571 |
|
|
to_register28_data_in => to_register28_data_in,
|
572 |
|
|
to_register28_en => to_register28_en,
|
573 |
|
|
to_register29_ce => to_register29_ce,
|
574 |
|
|
to_register29_clk => to_register29_clk,
|
575 |
|
|
to_register29_clr => to_register29_clr,
|
576 |
|
|
to_register29_data_in => to_register29_data_in,
|
577 |
|
|
to_register29_en => to_register29_en,
|
578 |
|
|
to_register2_ce => to_register2_ce,
|
579 |
|
|
to_register2_clk => to_register2_clk,
|
580 |
|
|
to_register2_clr => to_register2_clr,
|
581 |
|
|
to_register2_data_in => to_register2_data_in,
|
582 |
|
|
to_register2_en => to_register2_en,
|
583 |
|
|
to_register30_ce => to_register30_ce,
|
584 |
|
|
to_register30_clk => to_register30_clk,
|
585 |
|
|
to_register30_clr => to_register30_clr,
|
586 |
|
|
to_register30_data_in => to_register30_data_in,
|
587 |
|
|
to_register30_en => to_register30_en,
|
588 |
|
|
to_register31_ce => to_register31_ce,
|
589 |
|
|
to_register31_clk => to_register31_clk,
|
590 |
|
|
to_register31_clr => to_register31_clr,
|
591 |
|
|
to_register31_data_in => to_register31_data_in,
|
592 |
|
|
to_register31_en => to_register31_en,
|
593 |
|
|
to_register32_ce => to_register32_ce,
|
594 |
|
|
to_register32_clk => to_register32_clk,
|
595 |
|
|
to_register32_clr => to_register32_clr,
|
596 |
|
|
to_register32_data_in => to_register32_data_in,
|
597 |
|
|
to_register32_en => to_register32_en,
|
598 |
|
|
to_register33_ce => to_register33_ce,
|
599 |
|
|
to_register33_clk => to_register33_clk,
|
600 |
|
|
to_register33_clr => to_register33_clr,
|
601 |
|
|
to_register33_data_in => to_register33_data_in,
|
602 |
|
|
to_register33_en => to_register33_en,
|
603 |
|
|
to_register34_ce => to_register34_ce,
|
604 |
|
|
to_register34_clk => to_register34_clk,
|
605 |
|
|
to_register34_clr => to_register34_clr,
|
606 |
|
|
to_register34_data_in => to_register34_data_in,
|
607 |
|
|
to_register34_en => to_register34_en,
|
608 |
|
|
to_register3_ce => to_register3_ce,
|
609 |
|
|
to_register3_clk => to_register3_clk,
|
610 |
|
|
to_register3_clr => to_register3_clr,
|
611 |
|
|
to_register3_data_in => to_register3_data_in,
|
612 |
|
|
to_register3_en => to_register3_en,
|
613 |
|
|
to_register4_ce => to_register4_ce,
|
614 |
|
|
to_register4_clk => to_register4_clk,
|
615 |
|
|
to_register4_clr => to_register4_clr,
|
616 |
|
|
to_register4_data_in => to_register4_data_in,
|
617 |
|
|
to_register4_en => to_register4_en,
|
618 |
|
|
to_register5_ce => to_register5_ce,
|
619 |
|
|
to_register5_clk => to_register5_clk,
|
620 |
|
|
to_register5_clr => to_register5_clr,
|
621 |
|
|
to_register5_data_in => to_register5_data_in,
|
622 |
|
|
to_register5_en => to_register5_en,
|
623 |
|
|
to_register6_ce => to_register6_ce,
|
624 |
|
|
to_register6_clk => to_register6_clk,
|
625 |
|
|
to_register6_clr => to_register6_clr,
|
626 |
|
|
to_register6_data_in => to_register6_data_in,
|
627 |
|
|
to_register6_en => to_register6_en,
|
628 |
|
|
to_register7_ce => to_register7_ce,
|
629 |
|
|
to_register7_clk => to_register7_clk,
|
630 |
|
|
to_register7_clr => to_register7_clr,
|
631 |
|
|
to_register7_data_in => to_register7_data_in,
|
632 |
|
|
to_register7_en => to_register7_en,
|
633 |
|
|
to_register8_ce => to_register8_ce,
|
634 |
|
|
to_register8_clk => to_register8_clk,
|
635 |
|
|
to_register8_clr => to_register8_clr,
|
636 |
|
|
to_register8_data_in => to_register8_data_in,
|
637 |
|
|
to_register8_en => to_register8_en,
|
638 |
|
|
to_register9_ce => to_register9_ce,
|
639 |
|
|
to_register9_clk => to_register9_clk,
|
640 |
|
|
to_register9_clr => to_register9_clr,
|
641 |
|
|
to_register9_data_in => to_register9_data_in,
|
642 |
|
|
to_register9_en => to_register9_en);
|
643 |
|
|
-- INST_TAG_END ------ End INSTANTIATION Template ------------
|