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-- This file is owned and controlled by Xilinx and must be used solely --
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-- for design, simulation, implementation and creation of design files --
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-- limited to Xilinx devices or technologies. Use with non-Xilinx --
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-- devices or technologies is expressly prohibited and immediately --
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-- terminates your license. --
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-- --
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-- XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" SOLELY --
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-- FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR XILINX DEVICES. BY --
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-- PROVIDING THIS DESIGN, CODE, OR INFORMATION AS ONE POSSIBLE --
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-- IMPLEMENTATION OF THIS FEATURE, APPLICATION OR STANDARD, XILINX IS --
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-- MAKING NO REPRESENTATION THAT THIS IMPLEMENTATION IS FREE FROM ANY --
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-- CLAIMS OF INFRINGEMENT, AND YOU ARE RESPONSIBLE FOR OBTAINING ANY --
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-- RIGHTS YOU MAY REQUIRE FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY --
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-- DISCLAIMS ANY WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE --
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-- IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR --
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-- REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF --
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-- INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A --
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-- PARTICULAR PURPOSE. --
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-- --
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-- Xilinx products are not intended for use in life support appliances, --
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-- devices, or systems. Use in such applications are expressly --
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-- prohibited. --
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-- --
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-- (c) Copyright 1995-2012 Xilinx, Inc. --
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-- All rights reserved. --
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--------------------------------------------------------------------------------
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--------------------------------------------------------------------------------
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-- You must compile the wrapper file cntr_11_0_341fbb8cfa0e669e.vhd when simulating
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-- the core, cntr_11_0_341fbb8cfa0e669e. When compiling the wrapper file, be sure to
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-- reference the XilinxCoreLib VHDL simulation library. For detailed
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-- instructions, please refer to the "CORE Generator Help".
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-- The synthesis directives "translate_off/translate_on" specified
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-- below are supported by Xilinx, Mentor Graphics and Synplicity
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-- synthesis tools. Ensure they are correct for your synthesis tool(s).
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LIBRARY ieee;
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USE ieee.std_logic_1164.ALL;
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-- synthesis translate_off
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LIBRARY XilinxCoreLib;
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-- synthesis translate_on
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ENTITY cntr_11_0_341fbb8cfa0e669e IS
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PORT (
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clk : IN STD_LOGIC;
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ce : IN STD_LOGIC;
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sinit : IN STD_LOGIC;
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q : OUT STD_LOGIC_VECTOR(11 DOWNTO 0)
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);
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END cntr_11_0_341fbb8cfa0e669e;
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ARCHITECTURE cntr_11_0_341fbb8cfa0e669e_a OF cntr_11_0_341fbb8cfa0e669e IS
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-- synthesis translate_off
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COMPONENT wrapped_cntr_11_0_341fbb8cfa0e669e
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PORT (
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clk : IN STD_LOGIC;
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ce : IN STD_LOGIC;
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sinit : IN STD_LOGIC;
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q : OUT STD_LOGIC_VECTOR(11 DOWNTO 0)
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);
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END COMPONENT;
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-- Configuration specification
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FOR ALL : wrapped_cntr_11_0_341fbb8cfa0e669e USE ENTITY XilinxCoreLib.c_counter_binary_v11_0(behavioral)
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GENERIC MAP (
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c_ainit_val => "0",
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c_ce_overrides_sync => 0,
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c_count_by => "1",
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c_count_mode => 0,
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c_count_to => "1",
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c_fb_latency => 0,
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c_has_ce => 1,
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c_has_load => 0,
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c_has_sclr => 0,
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c_has_sinit => 1,
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c_has_sset => 0,
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c_has_thresh0 => 0,
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c_implementation => 0,
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c_latency => 1,
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c_load_low => 0,
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c_restrict_count => 0,
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c_sclr_overrides_sset => 1,
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c_sinit_val => "0",
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c_thresh0_value => "1",
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c_verbosity => 0,
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c_width => 12,
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c_xdevicefamily => "virtex6"
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);
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-- synthesis translate_on
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BEGIN
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-- synthesis translate_off
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U0 : wrapped_cntr_11_0_341fbb8cfa0e669e
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PORT MAP (
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clk => clk,
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ce => ce,
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sinit => sinit,
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q => q
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);
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-- synthesis translate_on
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END cntr_11_0_341fbb8cfa0e669e_a;
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