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//-----------------------------------------------------------------------------
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//
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// (c) Copyright 2009-2011 Xilinx, Inc. All rights reserved.
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//
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// This file contains confidential and proprietary information
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// of Xilinx, Inc. and is protected under U.S. and
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// international copyright and other intellectual property
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// laws.
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//
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// DISCLAIMER
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// This disclaimer is not a license and does not grant any
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// rights to the materials distributed herewith. Except as
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// otherwise provided in a valid license issued to you by
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// Xilinx, and to the maximum extent permitted by applicable
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// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
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// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
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// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
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// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
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// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
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// (2) Xilinx shall not be liable (whether in contract or tort,
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// including negligence, or under any other theory of
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// liability) for any loss or damage of any kind or nature
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// related to, arising under or in connection with these
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// materials, including for any direct, or any indirect,
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// special, incidental, or consequential loss or damage
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// (including loss of data, profits, goodwill, or any type of
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// loss or damage suffered as a result of any action brought
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// by a third party) even if such damage or loss was
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// reasonably foreseeable or Xilinx had been advised of the
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// possibility of the same.
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//
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// CRITICAL APPLICATIONS
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// Xilinx products are not designed or intended to be fail-
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// safe, or for use in any application requiring fail-safe
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// performance, such as life-support or safety devices or
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// systems, Class III medical devices, nuclear facilities,
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// applications related to the deployment of airbags, or any
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// other applications that could lead to death, personal
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// injury, or severe property or environmental damage
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// (individually and collectively, "Critical
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// Applications"). Customer assumes the sole risk and
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// liability of any use of Xilinx products in Critical
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// Applications, subject only to applicable laws and
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// regulations governing limitations on product liability.
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//
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// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
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// PART OF THIS FILE AT ALL TIMES.
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//
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//-----------------------------------------------------------------------------
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// Project : Virtex-6 Integrated Block for PCI Express
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// File : pcie_app_v6.v
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// Version : 1.7
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//--
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//-- Description: PCI Express Endpoint sample application
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//-- design.
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//--
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//------------------------------------------------------------------------------
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`timescale 1ns / 1ps
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`define PCI_EXP_EP_OUI 24'h000A35
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`define PCI_EXP_EP_DSN_1 {{8'h1},`PCI_EXP_EP_OUI}
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`define PCI_EXP_EP_DSN_2 32'h00000001
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module pcie_app_v6
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(
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input trn_clk,
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input trn_reset_n,
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input trn_lnk_up_n,
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// Tx
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input [5:0] trn_tbuf_av,
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input trn_tcfg_req_n,
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input trn_terr_drop_n,
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input trn_tdst_rdy_n,
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output [63:0] trn_td,
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output trn_trem_n,
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output trn_tsof_n,
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output trn_teof_n,
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output trn_tsrc_rdy_n,
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output trn_tsrc_dsc_n,
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output trn_terrfwd_n,
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output trn_tcfg_gnt_n,
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output trn_tstr_n,
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// Rx
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input [63:0] trn_rd,
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input trn_rrem_n,
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input trn_rsof_n,
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input trn_reof_n,
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input trn_rsrc_rdy_n,
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input trn_rsrc_dsc_n,
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input trn_rerrfwd_n,
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input [6:0] trn_rbar_hit_n,
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output trn_rdst_rdy_n,
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output trn_rnp_ok_n,
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// Flow Control
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input [11:0] trn_fc_cpld,
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input [7:0] trn_fc_cplh,
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input [11:0] trn_fc_npd,
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input [7:0] trn_fc_nph,
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input [11:0] trn_fc_pd,
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input [7:0] trn_fc_ph,
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output [2:0] trn_fc_sel,
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input [31:0] cfg_do,
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input cfg_rd_wr_done_n,
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output [31:0] cfg_di,
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output [3:0] cfg_byte_en_n,
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output [9:0] cfg_dwaddr,
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output cfg_wr_en_n,
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output cfg_rd_en_n,
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output cfg_err_cor_n,
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output cfg_err_ur_n,
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output cfg_err_ecrc_n,
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output cfg_err_cpl_timeout_n,
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output cfg_err_cpl_abort_n,
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output cfg_err_cpl_unexpect_n,
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output cfg_err_posted_n,
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output cfg_err_locked_n,
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output [47:0] cfg_err_tlp_cpl_header,
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input cfg_err_cpl_rdy_n,
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output cfg_interrupt_n,
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input cfg_interrupt_rdy_n,
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output cfg_interrupt_assert_n,
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output [7:0] cfg_interrupt_di,
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input [7:0] cfg_interrupt_do,
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input [2:0] cfg_interrupt_mmenable,
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input cfg_interrupt_msienable,
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input cfg_interrupt_msixenable,
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input cfg_interrupt_msixfm,
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output cfg_turnoff_ok_n,
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input cfg_to_turnoff_n,
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output cfg_trn_pending_n,
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output cfg_pm_wake_n,
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input [7:0] cfg_bus_number,
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input [4:0] cfg_device_number,
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input [2:0] cfg_function_number,
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input [15:0] cfg_status,
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input [15:0] cfg_command,
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input [15:0] cfg_dstatus,
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input [15:0] cfg_dcommand,
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input [15:0] cfg_lstatus,
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input [15:0] cfg_lcommand,
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input [15:0] cfg_dcommand2,
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input [2:0] cfg_pcie_link_state_n,
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output [1:0] pl_directed_link_change,
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input [5:0] pl_ltssm_state,
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output [1:0] pl_directed_link_width,
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output pl_directed_link_speed,
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output pl_directed_link_auton,
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output pl_upstream_prefer_deemph,
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input [1:0] pl_sel_link_width,
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input pl_sel_link_rate,
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input pl_link_gen2_capable,
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input pl_link_partner_gen2_supported,
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input [2:0] pl_initial_link_width,
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input pl_link_upcfg_capable,
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input [1:0] pl_lane_reversal_mode,
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input pl_received_hot_rst,
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output [63:0] cfg_dsn
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);
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wire [7:0] trn_trem;
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//
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// Core input tie-offs
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//
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assign trn_fc_sel = 3'b0;
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assign trn_rnp_ok_n = 1'b0;
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assign trn_terrfwd_n = 1'b1;
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assign trn_tcfg_gnt_n = 1'b0;
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assign trn_tecrc_gen_n = 1'b1;
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assign cfg_err_cor_n = 1'b1;
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assign cfg_err_ur_n = 1'b1;
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assign cfg_err_ecrc_n = 1'b1;
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assign cfg_err_cpl_timeout_n = 1'b1;
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assign cfg_err_cpl_abort_n = 1'b1;
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assign cfg_err_cpl_unexpect_n = 1'b1;
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assign cfg_err_posted_n = 1'b0;
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assign cfg_err_locked_n = 1'b1;
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assign cfg_pm_wake_n = 1'b1;
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assign cfg_trn_pending_n = 1'b1;
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assign trn_tstr_n = 1'b0;
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assign cfg_interrupt_assert_n = 1'b1;
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assign cfg_interrupt_n = 1'b1;
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assign cfg_dwaddr = 0;
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assign cfg_rd_en_n = 1;
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assign pl_directed_link_change = 0;
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assign pl_directed_link_width = 0;
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assign pl_directed_link_speed = 0;
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assign pl_directed_link_auton = 0;
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assign pl_upstream_prefer_deemph = 1'b1;
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assign cfg_interrupt_di = 8'b0;
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assign cfg_err_tlp_cpl_header = 47'h0;
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assign cfg_di = 0;
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assign cfg_byte_en_n = 4'hf;
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assign cfg_wr_en_n = 1;
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assign cfg_dsn = {`PCI_EXP_EP_DSN_2, `PCI_EXP_EP_DSN_1};
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assign trn_trem_n = (trn_trem == 8'h0F) ? 1'b1 : 1'b0;
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//
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// Programmable I/O Module
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//
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wire [15:0] cfg_completer_id = { cfg_bus_number, cfg_device_number, cfg_function_number };
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wire cfg_bus_mstr_enable = cfg_command[2];
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PIO PIO (
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.trn_clk ( trn_clk ), // I
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.trn_reset_n ( trn_reset_n ), // I
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.trn_lnk_up_n ( trn_lnk_up_n ), // I
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.trn_td ( trn_td ), // O [63:0]
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.trn_trem_n ( trn_trem ), // O [7:0]
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.trn_tsof_n ( trn_tsof_n ), // O
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.trn_teof_n ( trn_teof_n ), // O
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.trn_tsrc_rdy_n ( trn_tsrc_rdy_n ), // O
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.trn_tsrc_dsc_n ( trn_tsrc_dsc_n ), // O
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.trn_tdst_rdy_n ( trn_tdst_rdy_n ), // I
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.trn_tdst_dsc_n ( 1'b1 ), // I
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.trn_rd ( trn_rd ), // I [63:0]
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.trn_rrem_n ( (trn_rrem_n == 1'b1) ? 8'h0F : 8'h00), // I [7:0]
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.trn_rsof_n ( trn_rsof_n ), // I
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.trn_reof_n ( trn_reof_n ), // I
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.trn_rsrc_rdy_n ( trn_rsrc_rdy_n ), // I
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.trn_rsrc_dsc_n ( trn_rsrc_dsc_n ), // I
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.trn_rdst_rdy_n ( trn_rdst_rdy_n ), // O
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.trn_rbar_hit_n ( trn_rbar_hit_n ), // I [6:0]
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.cfg_to_turnoff_n ( cfg_to_turnoff_n ), // I
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.cfg_turnoff_ok_n ( cfg_turnoff_ok_n ), // O
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.cfg_completer_id ( cfg_completer_id ), // I [15:0]
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.cfg_bus_mstr_enable (cfg_bus_mstr_enable ) // I
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);
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endmodule // pcie_app
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