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//-----------------------------------------------------------------------------
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//
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// (c) Copyright 2009-2011 Xilinx, Inc. All rights reserved.
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//
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// This file contains confidential and proprietary information
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// of Xilinx, Inc. and is protected under U.S. and
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// international copyright and other intellectual property
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// laws.
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//
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// DISCLAIMER
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// This disclaimer is not a license and does not grant any
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// rights to the materials distributed herewith. Except as
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// otherwise provided in a valid license issued to you by
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// Xilinx, and to the maximum extent permitted by applicable
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// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
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// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
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// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
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// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
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// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
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// (2) Xilinx shall not be liable (whether in contract or tort,
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// including negligence, or under any other theory of
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// liability) for any loss or damage of any kind or nature
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// related to, arising under or in connection with these
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// materials, including for any direct, or any indirect,
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// special, incidental, or consequential loss or damage
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// (including loss of data, profits, goodwill, or any type of
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// loss or damage suffered as a result of any action brought
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// by a third party) even if such damage or loss was
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// reasonably foreseeable or Xilinx had been advised of the
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// possibility of the same.
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//
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// CRITICAL APPLICATIONS
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// Xilinx products are not designed or intended to be fail-
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// safe, or for use in any application requiring fail-safe
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// performance, such as life-support or safety devices or
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// systems, Class III medical devices, nuclear facilities,
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// applications related to the deployment of airbags, or any
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// other applications that could lead to death, personal
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// injury, or severe property or environmental damage
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// (individually and collectively, "Critical
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// Applications"). Customer assumes the sole risk and
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// liability of any use of Xilinx products in Critical
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// Applications, subject only to applicable laws and
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// regulations governing limitations on product liability.
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//
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// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
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// PART OF THIS FILE AT ALL TIMES.
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//
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//-----------------------------------------------------------------------------
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// Project : Virtex-6 Integrated Block for PCI Express
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// File : gtx_wrapper_v6.v
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// Version : 1.7
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//-- Description: GTX module for Virtex6 PCIe Block
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//--
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//--
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//--
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//--------------------------------------------------------------------------------
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`timescale 1ns/1ns
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module gtx_wrapper_v6 (
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// TX
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TX,
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TX_,
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TxData,
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TxDataK,
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TxElecIdle,
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TxCompliance,
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// RX
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RX,
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RX_,
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RxData,
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RxDataK,
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RxPolarity,
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RxValid,
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RxElecIdle,
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RxStatus,
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// other
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GTRefClkout,
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plm_in_l0,
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plm_in_rl,
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plm_in_dt,
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plm_in_rs,
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RxPLLLkDet,
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TxDetectRx,
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PhyStatus,
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TXPdownAsynch,
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PowerDown,
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Rate,
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Reset_n,
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GTReset_n,
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PCLK,
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REFCLK,
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TxDeemph,
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TxMargin,
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TxSwing,
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ChanIsAligned,
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local_pcs_reset,
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RxResetDone,
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SyncDone,
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DRPCLK,
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TxOutClk
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);
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parameter NO_OF_LANES = 1;
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parameter REF_CLK_FREQ = 0;
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parameter PL_FAST_TRAIN = "FALSE";
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localparam GTX_PLL_DIVSEL_FB = (REF_CLK_FREQ == 0) ? 5 :
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(REF_CLK_FREQ == 1) ? 4 :
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(REF_CLK_FREQ == 2) ? 2 : 0;
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localparam SIMULATION = (PL_FAST_TRAIN == "TRUE") ? 1 : 0;
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localparam RXPLL_CP_CFG = (REF_CLK_FREQ == 0) ? 8'h05 :
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(REF_CLK_FREQ == 1) ? 8'h05 :
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(REF_CLK_FREQ == 2) ? 8'h05 : 8'h05;
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localparam TXPLL_CP_CFG = (REF_CLK_FREQ == 0) ? 8'h05 :
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(REF_CLK_FREQ == 1) ? 8'h05 :
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(REF_CLK_FREQ == 2) ? 8'h05 : 8'h05;
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localparam RX_CLK25_DIVIDER = (REF_CLK_FREQ == 0) ? 4 :
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(REF_CLK_FREQ == 1) ? 5 :
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(REF_CLK_FREQ == 2) ? 10 : 10 ;
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localparam TX_CLK25_DIVIDER = (REF_CLK_FREQ == 0) ? 4 :
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(REF_CLK_FREQ == 1) ? 5 :
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(REF_CLK_FREQ == 2) ? 10 : 10 ;
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// TX
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output [NO_OF_LANES-1:0] TX;
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output [NO_OF_LANES-1:0] TX_;
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input [(NO_OF_LANES*16)-1:0] TxData;
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input [(NO_OF_LANES*2)-1:0] TxDataK;
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input [NO_OF_LANES-1:0] TxElecIdle;
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input [NO_OF_LANES-1:0] TxCompliance;
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// RX
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input [NO_OF_LANES-1:0] RX;
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input [NO_OF_LANES-1:0] RX_;
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output [(NO_OF_LANES*16)-1:0] RxData;
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output [(NO_OF_LANES*2)-1:0] RxDataK;
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input [NO_OF_LANES-1:0] RxPolarity;
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output [NO_OF_LANES-1:0] RxValid;
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output [NO_OF_LANES-1:0] RxElecIdle;
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output [(NO_OF_LANES*3)-1:0] RxStatus;
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// other
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output [NO_OF_LANES-1:0] GTRefClkout;
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input plm_in_l0;
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input plm_in_rl;
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input plm_in_dt;
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input plm_in_rs;
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output [NO_OF_LANES-1:0] RxPLLLkDet;
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input TxDetectRx;
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output [NO_OF_LANES-1:0] PhyStatus;
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input PCLK;
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output [NO_OF_LANES-1:0] ChanIsAligned;
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input TXPdownAsynch;
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input [(NO_OF_LANES*2)-1:0] PowerDown;
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input Rate;
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input Reset_n;
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input GTReset_n;
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input REFCLK;
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input TxDeemph;
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input TxMargin;
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input TxSwing;
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input local_pcs_reset;
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output RxResetDone;
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output SyncDone;
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input DRPCLK;
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output TxOutClk;
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genvar i;
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// dummy signals to avoid port mismatch with DUAL_GTX
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wire [15:0] RxData_dummy;
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wire [1:0] RxDataK_dummy;
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wire [15:0] TxData_dummy;
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wire [1:0] TxDataK_dummy;
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// inputs
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wire [(NO_OF_LANES*16)-1:0] GTX_TxData = TxData;
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wire [(NO_OF_LANES*2)-1:0] GTX_TxDataK = TxDataK;
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wire [(NO_OF_LANES)-1:0] GTX_TxElecIdle = TxElecIdle;
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wire [(NO_OF_LANES-1):0] GTX_TxCompliance = TxCompliance;
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wire [(NO_OF_LANES)-1:0] GTX_RXP = RX[(NO_OF_LANES)-1:0];
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wire [(NO_OF_LANES)-1:0] GTX_RXN = RX_[(NO_OF_LANES)-1:0];
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// outputs
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wire [(NO_OF_LANES)-1:0] GTX_TXP;
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wire [(NO_OF_LANES)-1:0] GTX_TXN;
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wire [(NO_OF_LANES*16)-1:0] GTX_RxData;
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wire [(NO_OF_LANES*2)-1:0] GTX_RxDataK;
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wire [(NO_OF_LANES)-1:0] GTX_RxPolarity = RxPolarity ;
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wire [(NO_OF_LANES)-1:0] GTX_RxValid;
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wire [(NO_OF_LANES)-1:0] GTX_RxElecIdle;
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wire [(NO_OF_LANES-1):0] GTX_RxResetDone;
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wire [(NO_OF_LANES*3)-1:0] GTX_RxChbondLevel;
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wire [(NO_OF_LANES*3)-1:0] GTX_RxStatus;
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wire [3:0] RXCHBOND [NO_OF_LANES+1:0];
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wire [3:0] TXBYPASS8B10B = 4'b0000;
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wire RXDEC8B10BUSE = 1'b1;
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wire [NO_OF_LANES-1:0] GTX_PhyStatus;
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wire RESETDONE [NO_OF_LANES-1:0];
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wire REFCLK;
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wire GTXRESET = 1'b0;
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wire [NO_OF_LANES-1:0] SYNC_DONE;
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wire [NO_OF_LANES-1:0] OUT_DIV_RESET;
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wire [NO_OF_LANES-1:0] PCS_RESET;
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wire [NO_OF_LANES-1:0] TXENPMAPHASEALIGN;
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wire [NO_OF_LANES-1:0] TXPMASETPHASE;
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wire [NO_OF_LANES-1:0] TXRESETDONE;
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wire [NO_OF_LANES-1:0] TXRATEDONE;
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wire [NO_OF_LANES-1:0] PHYSTATUS;
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wire [NO_OF_LANES-1:0] RXVALID;
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wire [NO_OF_LANES-1:0] RATE_CLK_SEL;
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wire [NO_OF_LANES-1:0] TXOCLK;
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wire [NO_OF_LANES-1:0] TXDLYALIGNDISABLE;
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wire [NO_OF_LANES-1:0] TXDLYALIGNRESET;
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reg [(NO_OF_LANES-1):0] GTX_RxResetDone_q;
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reg [(NO_OF_LANES-1):0] TXRESETDONE_q;
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wire [NO_OF_LANES-1:0] RxValid;
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wire [(NO_OF_LANES*8-1):0] daddr;
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wire [NO_OF_LANES-1:0] den;
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wire [(NO_OF_LANES*16-1):0] din;
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wire [NO_OF_LANES-1:0] dwe;
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wire [(NO_OF_LANES*4-1):0] drpstate;
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wire [NO_OF_LANES-1:0] drdy;
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wire [(NO_OF_LANES*16-1):0] dout;
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wire write_drp_cb_fts;
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wire write_drp_cb_ts1;
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assign RxResetDone = &(GTX_RxResetDone_q[(NO_OF_LANES)-1:0]);
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assign TX[(NO_OF_LANES)-1:0] = GTX_TXP[(NO_OF_LANES)-1:0];
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assign TX_[(NO_OF_LANES)-1:0] = GTX_TXN[(NO_OF_LANES)-1:0];
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assign RXCHBOND[0] = 4'b0000;
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assign TxData_dummy = 16'b0;
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assign TxDataK_dummy = 2'b0;
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assign SyncDone = &(SYNC_DONE[(NO_OF_LANES)-1:0]);
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assign TxOutClk = TXOCLK[0];
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assign write_drp_cb_fts = plm_in_l0;
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assign write_drp_cb_ts1 = plm_in_rl | plm_in_dt;
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// pipeline to improve timing
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always @ (posedge PCLK) begin
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GTX_RxResetDone_q[(NO_OF_LANES)-1:0] <= GTX_RxResetDone[(NO_OF_LANES)-1:0];
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TXRESETDONE_q[(NO_OF_LANES)-1:0] <= TXRESETDONE[(NO_OF_LANES)-1:0];
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end
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generate
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for (i=0; i < NO_OF_LANES; i=i+1) begin: GTXD
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assign GTX_RxChbondLevel[(3*i)+2:(3*i)] = (NO_OF_LANES-(i+1));
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GTX_DRP_CHANALIGN_FIX_3752_V6 # (
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.C_SIMULATION(SIMULATION)
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) GTX_DRP_CHANALIGN_FIX_3752 (
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.dwe(dwe[i]),
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.din(din[(16*i)+15:(16*i)]),
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.den(den[i]),
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.daddr(daddr[(8*i)+7:(8*i)]),
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.drpstate(drpstate[(4*i)+3:(4*i)]),
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.write_ts1(write_drp_cb_ts1),
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.write_fts(write_drp_cb_fts),
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.dout(dout[(16*i)+15:(16*i)]),
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.drdy(drdy[i]),
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.Reset_n(Reset_n),
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.drp_clk(DRPCLK)
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);
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GTX_RX_VALID_FILTER_V6 # (
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.CLK_COR_MIN_LAT(28)
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)
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GTX_RX_VALID_FILTER (
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.USER_RXCHARISK ( RxDataK[(2*i)+1:2*i] ), //O
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.USER_RXDATA ( RxData[(16*i)+15:(16*i)+0] ), //O
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.USER_RXVALID ( RxValid[i] ), //O
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.USER_RXELECIDLE ( RxElecIdle[i] ), //O
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.USER_RX_STATUS ( RxStatus[(3*i)+2:(3*i)] ), //O
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.USER_RX_PHY_STATUS ( PhyStatus[i] ), //O
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.GT_RXCHARISK ( GTX_RxDataK[(2*i)+1:2*i] ), //I
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.GT_RXDATA ( GTX_RxData[(16*i)+15:(16*i)+0] ), //I
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.GT_RXVALID ( GTX_RxValid[i] ), //I
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.GT_RXELECIDLE ( GTX_RxElecIdle[i] ), //I
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.GT_RX_STATUS ( GTX_RxStatus[(3*i)+2:(3*i)] ), //I
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.GT_RX_PHY_STATUS ( PHYSTATUS[i] ),
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.PLM_IN_L0 ( plm_in_l0 ), //I
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.PLM_IN_RS ( plm_in_rs ), //I
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.USER_CLK ( PCLK ), //I
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.RESET ( !Reset_n ) //I
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);
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|
|
GTX_TX_SYNC_RATE_V6 # (
|
319 |
|
|
.C_SIMULATION(SIMULATION)
|
320 |
|
|
)
|
321 |
|
|
GTX_TX_SYNC (
|
322 |
|
|
|
323 |
|
|
.ENPMAPHASEALIGN ( TXENPMAPHASEALIGN[i] ), //O
|
324 |
|
|
.PMASETPHASE ( TXPMASETPHASE[i] ), //O
|
325 |
|
|
.SYNC_DONE ( SYNC_DONE[i] ), //O
|
326 |
|
|
.OUT_DIV_RESET ( OUT_DIV_RESET[i] ), //O
|
327 |
|
|
.PCS_RESET ( PCS_RESET[i] ), //O
|
328 |
|
|
.USER_PHYSTATUS ( PHYSTATUS[i] ), //O
|
329 |
|
|
.TXALIGNDISABLE ( TXDLYALIGNDISABLE[i] ), //O
|
330 |
|
|
.DELAYALIGNRESET ( TXDLYALIGNRESET[i] ), //O
|
331 |
|
|
|
332 |
|
|
.USER_CLK ( PCLK), //I
|
333 |
|
|
.RESET ( !Reset_n ), //I
|
334 |
|
|
.RATE ( Rate ), //I
|
335 |
|
|
.RATEDONE ( TXRATEDONE[i] ), //I
|
336 |
|
|
.GT_PHYSTATUS ( GTX_PhyStatus[i] ), //I
|
337 |
|
|
.RESETDONE ( TXRESETDONE_q[i] & GTX_RxResetDone_q[i] ) //I
|
338 |
|
|
|
339 |
|
|
);
|
340 |
|
|
|
341 |
|
|
GTXE1 # (
|
342 |
|
|
|
343 |
|
|
.TX_DRIVE_MODE("PIPE"),
|
344 |
|
|
.TX_DEEMPH_1(5'b10010),
|
345 |
|
|
.TX_MARGIN_FULL_0(7'b100_1101),
|
346 |
|
|
|
347 |
|
|
.TX_CLK_SOURCE("RXPLL"),
|
348 |
|
|
.POWER_SAVE(10'b0000110100),
|
349 |
|
|
.CM_TRIM ( 2'b01 ),
|
350 |
|
|
.PMA_CDR_SCAN ( 27'h640404C ),
|
351 |
|
|
.PMA_CFG( 76'h0040000040000000003 ),
|
352 |
|
|
.RCV_TERM_GND ("TRUE"),
|
353 |
|
|
.RCV_TERM_VTTRX ("FALSE"),
|
354 |
|
|
.RX_DLYALIGN_EDGESET(5'b00010),
|
355 |
|
|
.RX_DLYALIGN_LPFINC(4'b0110),
|
356 |
|
|
.RX_DLYALIGN_OVRDSETTING(8'b10000000),
|
357 |
|
|
.TERMINATION_CTRL(5'b00000),
|
358 |
|
|
.TERMINATION_OVRD("FALSE"),
|
359 |
|
|
.TX_DLYALIGN_LPFINC(4'b0110),
|
360 |
|
|
.TX_DLYALIGN_OVRDSETTING(8'b10000000),
|
361 |
|
|
.TXPLL_CP_CFG( TXPLL_CP_CFG ),
|
362 |
|
|
.OOBDETECT_THRESHOLD( 3'b011 ),
|
363 |
|
|
.RXPLL_CP_CFG ( RXPLL_CP_CFG ),
|
364 |
|
|
//.TX_DETECT_RX_CFG( 14'h1832 ),
|
365 |
|
|
.TX_TDCC_CFG ( 2'b11 ),
|
366 |
|
|
.BIAS_CFG ( 17'h00000 ),
|
367 |
|
|
.AC_CAP_DIS ( "FALSE" ),
|
368 |
|
|
.DFE_CFG ( 8'b00011011 ),
|
369 |
|
|
.SIM_TX_ELEC_IDLE_LEVEL("1"),
|
370 |
|
|
.SIM_RECEIVER_DETECT_PASS("TRUE"),
|
371 |
|
|
.RX_EN_REALIGN_RESET_BUF("FALSE"),
|
372 |
|
|
.TX_IDLE_ASSERT_DELAY(3'b100), // TX-idle-set-to-idle (13 UI)
|
373 |
|
|
.TX_IDLE_DEASSERT_DELAY(3'b010), // TX-idle-to-diff (7 UI)
|
374 |
|
|
.CHAN_BOND_SEQ_2_CFG(5'b11111), // 5'b11111 for PCIE mode, 5'b00000 for other modes
|
375 |
|
|
.CHAN_BOND_KEEP_ALIGN("TRUE"),
|
376 |
|
|
.RX_IDLE_HI_CNT(4'b1000),
|
377 |
|
|
.RX_IDLE_LO_CNT(4'b0000),
|
378 |
|
|
.RX_EN_IDLE_RESET_BUF("TRUE"),
|
379 |
|
|
.TX_DATA_WIDTH(20),
|
380 |
|
|
.RX_DATA_WIDTH(20),
|
381 |
|
|
.ALIGN_COMMA_WORD(1),
|
382 |
|
|
.CHAN_BOND_1_MAX_SKEW(7),
|
383 |
|
|
.CHAN_BOND_2_MAX_SKEW(1),
|
384 |
|
|
.CHAN_BOND_SEQ_1_1(10'b0001000101), // D5.2 (end TS2)
|
385 |
|
|
.CHAN_BOND_SEQ_1_2(10'b0001000101), // D5.2 (end TS2)
|
386 |
|
|
.CHAN_BOND_SEQ_1_3(10'b0001000101), // D5.2 (end TS2)
|
387 |
|
|
.CHAN_BOND_SEQ_1_4(10'b0110111100), // K28.5 (COM)
|
388 |
|
|
.CHAN_BOND_SEQ_1_ENABLE(4'b1111), // order is 4321
|
389 |
|
|
.CHAN_BOND_SEQ_2_1(10'b0100111100), // K28.1 (FTS)
|
390 |
|
|
.CHAN_BOND_SEQ_2_2(10'b0100111100), // K28.1 (FTS)
|
391 |
|
|
.CHAN_BOND_SEQ_2_3(10'b0110111100), // K28.5 (COM)
|
392 |
|
|
.CHAN_BOND_SEQ_2_4(10'b0100111100), // K28.1 (FTS)
|
393 |
|
|
.CHAN_BOND_SEQ_2_ENABLE(4'b1111), // order is 4321
|
394 |
|
|
.CHAN_BOND_SEQ_2_USE("TRUE"),
|
395 |
|
|
.CHAN_BOND_SEQ_LEN(4), // 1..4
|
396 |
|
|
.RX_CLK25_DIVIDER(RX_CLK25_DIVIDER),
|
397 |
|
|
.TX_CLK25_DIVIDER(TX_CLK25_DIVIDER),
|
398 |
|
|
.CLK_COR_ADJ_LEN(1), // 1..4
|
399 |
|
|
.CLK_COR_DET_LEN(1), // 1..4
|
400 |
|
|
.CLK_COR_INSERT_IDLE_FLAG("FALSE"),
|
401 |
|
|
.CLK_COR_KEEP_IDLE("FALSE"),
|
402 |
|
|
.CLK_COR_MAX_LAT(30),
|
403 |
|
|
.CLK_COR_MIN_LAT(28),
|
404 |
|
|
.CLK_COR_PRECEDENCE("TRUE"),
|
405 |
|
|
.CLK_CORRECT_USE("TRUE"),
|
406 |
|
|
.CLK_COR_REPEAT_WAIT(0),
|
407 |
|
|
.CLK_COR_SEQ_1_1(10'b0100011100), // K28.0 (SKP)
|
408 |
|
|
.CLK_COR_SEQ_1_2(10'b0000000000),
|
409 |
|
|
.CLK_COR_SEQ_1_3(10'b0000000000),
|
410 |
|
|
.CLK_COR_SEQ_1_4(10'b0000000000),
|
411 |
|
|
.CLK_COR_SEQ_1_ENABLE(4'b1111),
|
412 |
|
|
.CLK_COR_SEQ_2_1(10'b0000000000),
|
413 |
|
|
.CLK_COR_SEQ_2_2(10'b0000000000),
|
414 |
|
|
.CLK_COR_SEQ_2_3(10'b0000000000),
|
415 |
|
|
.CLK_COR_SEQ_2_4(10'b0000000000),
|
416 |
|
|
.CLK_COR_SEQ_2_ENABLE(4'b1111),
|
417 |
|
|
.CLK_COR_SEQ_2_USE("FALSE"),
|
418 |
|
|
.COMMA_10B_ENABLE(10'b1111111111),
|
419 |
|
|
.COMMA_DOUBLE("FALSE"),
|
420 |
|
|
.DEC_MCOMMA_DETECT("TRUE"),
|
421 |
|
|
.DEC_PCOMMA_DETECT("TRUE"),
|
422 |
|
|
.DEC_VALID_COMMA_ONLY("TRUE"),
|
423 |
|
|
.MCOMMA_10B_VALUE(10'b1010000011),
|
424 |
|
|
.MCOMMA_DETECT("TRUE"),
|
425 |
|
|
.PCI_EXPRESS_MODE("TRUE"),
|
426 |
|
|
.PCOMMA_10B_VALUE(10'b0101111100),
|
427 |
|
|
.PCOMMA_DETECT("TRUE"),
|
428 |
|
|
.RXPLL_DIVSEL_FB(GTX_PLL_DIVSEL_FB), // 1..5, 8, 10
|
429 |
|
|
.TXPLL_DIVSEL_FB(GTX_PLL_DIVSEL_FB), // 1..5, 8, 10
|
430 |
|
|
.RXPLL_DIVSEL_REF(1), // 1..6, 8, 10, 12, 16, 20
|
431 |
|
|
.TXPLL_DIVSEL_REF(1), // 1..6, 8, 10, 12, 16, 20
|
432 |
|
|
.RXPLL_DIVSEL_OUT(2), // 1, 2, 4
|
433 |
|
|
.TXPLL_DIVSEL_OUT(2), // 1, 2, 4
|
434 |
|
|
.RXPLL_DIVSEL45_FB(5),
|
435 |
|
|
.TXPLL_DIVSEL45_FB(5),
|
436 |
|
|
.RX_BUFFER_USE("TRUE"),
|
437 |
|
|
.RX_DECODE_SEQ_MATCH("TRUE"),
|
438 |
|
|
.RX_LOS_INVALID_INCR(8), // power of 2: 1..128
|
439 |
|
|
.RX_LOSS_OF_SYNC_FSM("FALSE"),
|
440 |
|
|
.RX_LOS_THRESHOLD(128), // power of 2: 4..512
|
441 |
|
|
.RX_SLIDE_MODE("OFF"), // 00=OFF 01=AUTO 10=PCS 11=PMA
|
442 |
|
|
.RX_XCLK_SEL ("RXREC"),
|
443 |
|
|
.TX_BUFFER_USE("FALSE"), // Must be set to FALSE for use by PCIE
|
444 |
|
|
.TX_XCLK_SEL ("TXUSR"), // Must be set to TXUSR for use by PCIE
|
445 |
|
|
.TXPLL_LKDET_CFG (3'b101),
|
446 |
|
|
.RX_EYE_SCANMODE (2'b00),
|
447 |
|
|
.RX_EYE_OFFSET (8'h4C),
|
448 |
|
|
.PMA_RX_CFG ( 25'h05ce008 ),
|
449 |
|
|
.TRANS_TIME_NON_P2(8'h2), // Reduced simulation time
|
450 |
|
|
.TRANS_TIME_FROM_P2(12'h03c), // Reduced simulation time
|
451 |
|
|
.TRANS_TIME_TO_P2(10'h064), // Reduced simulation time
|
452 |
|
|
.TRANS_TIME_RATE(8'hD7), // Reduced simulation time
|
453 |
|
|
.SHOW_REALIGN_COMMA("FALSE"),
|
454 |
|
|
.TX_PMADATA_OPT(1'b1), // Lockup latch between PCS and PMA
|
455 |
|
|
.PMA_TX_CFG( 20'h80082 ), // Aligns posedge of USRCLK
|
456 |
|
|
.TXOUTCLK_CTRL("TXPLLREFCLK_DIV1")
|
457 |
|
|
|
458 |
|
|
)
|
459 |
|
|
GTX (
|
460 |
|
|
|
461 |
|
|
.COMFINISH (),
|
462 |
|
|
.COMINITDET (),
|
463 |
|
|
.COMSASDET (),
|
464 |
|
|
.COMWAKEDET (),
|
465 |
|
|
.DADDR (daddr[(8*i)+7:(8*i)]),
|
466 |
|
|
.DCLK (DRPCLK),
|
467 |
|
|
.DEN (den[i]),
|
468 |
|
|
.DFECLKDLYADJ ( 6'h0 ),
|
469 |
|
|
.DFECLKDLYADJMON (),
|
470 |
|
|
.DFEDLYOVRD ( 1'b1 ),
|
471 |
|
|
.DFEEYEDACMON (),
|
472 |
|
|
.DFESENSCAL (),
|
473 |
|
|
.DFETAP1 (0),
|
474 |
|
|
.DFETAP1MONITOR (),
|
475 |
|
|
.DFETAP2 (5'h0),
|
476 |
|
|
.DFETAP2MONITOR (),
|
477 |
|
|
.DFETAP3 (4'h0),
|
478 |
|
|
.DFETAP3MONITOR (),
|
479 |
|
|
.DFETAP4 (4'h0),
|
480 |
|
|
.DFETAP4MONITOR (),
|
481 |
|
|
.DFETAPOVRD ( 1'b1 ),
|
482 |
|
|
.DI (din[(16*i)+15:(16*i)]),
|
483 |
|
|
.DRDY (drdy[i]),
|
484 |
|
|
.DRPDO (dout[(16*i)+15:(16*i)]),
|
485 |
|
|
.DWE (dwe[i]),
|
486 |
|
|
.GATERXELECIDLE ( 1'b0 ),
|
487 |
|
|
.GREFCLKRX (0),
|
488 |
|
|
.GREFCLKTX (0),
|
489 |
|
|
.GTXRXRESET ( ~GTReset_n ),
|
490 |
|
|
.GTXTEST ( {11'b10000000000,OUT_DIV_RESET[i],1'b0} ),
|
491 |
|
|
.GTXTXRESET ( ~GTReset_n ),
|
492 |
|
|
.LOOPBACK ( 3'b000 ),
|
493 |
|
|
.MGTREFCLKFAB (),
|
494 |
|
|
.MGTREFCLKRX ( {1'b0,REFCLK} ),
|
495 |
|
|
.MGTREFCLKTX ( {1'b0,REFCLK} ),
|
496 |
|
|
.NORTHREFCLKRX (0),
|
497 |
|
|
.NORTHREFCLKTX (0),
|
498 |
|
|
.PHYSTATUS ( GTX_PhyStatus[i] ),
|
499 |
|
|
.PLLRXRESET ( 1'b0 ),
|
500 |
|
|
.PLLTXRESET ( 1'b0 ),
|
501 |
|
|
.PRBSCNTRESET ( 1'b0 ),
|
502 |
|
|
.RXBUFRESET ( 1'b0 ),
|
503 |
|
|
.RXBUFSTATUS (),
|
504 |
|
|
.RXBYTEISALIGNED (),
|
505 |
|
|
.RXBYTEREALIGN (),
|
506 |
|
|
.RXCDRRESET ( 1'b0 ),
|
507 |
|
|
.RXCHANBONDSEQ (),
|
508 |
|
|
.RXCHANISALIGNED ( ChanIsAligned[i] ),
|
509 |
|
|
.RXCHANREALIGN (),
|
510 |
|
|
.RXCHARISCOMMA (),
|
511 |
|
|
.RXCHARISK ( {RxDataK_dummy[1:0], GTX_RxDataK[(2*i)+1:2*i]} ),
|
512 |
|
|
.RXCHBONDI ( RXCHBOND[i] ),
|
513 |
|
|
.RXCHBONDLEVEL ( GTX_RxChbondLevel[(3*i)+2:(3*i)] ),
|
514 |
|
|
.RXCHBONDMASTER ( (i == 0) ),
|
515 |
|
|
.RXCHBONDO ( RXCHBOND[i+1] ),
|
516 |
|
|
.RXCHBONDSLAVE ( (i > 0) ),
|
517 |
|
|
.RXCLKCORCNT (),
|
518 |
|
|
.RXCOMMADET (),
|
519 |
|
|
.RXCOMMADETUSE ( 1'b1 ),
|
520 |
|
|
.RXDATA ( {RxData_dummy[15:0],GTX_RxData[(16*i)+15:(16*i)+0]} ),
|
521 |
|
|
.RXDATAVALID (),
|
522 |
|
|
.RXDEC8B10BUSE ( RXDEC8B10BUSE ),
|
523 |
|
|
.RXDISPERR (),
|
524 |
|
|
.RXDLYALIGNDISABLE ( 1'b1),
|
525 |
|
|
.RXELECIDLE ( GTX_RxElecIdle[i] ),
|
526 |
|
|
.RXENCHANSYNC ( 1'b1 ),
|
527 |
|
|
.RXENMCOMMAALIGN ( 1'b1 ),
|
528 |
|
|
.RXENPCOMMAALIGN ( 1'b1 ),
|
529 |
|
|
.RXENPMAPHASEALIGN ( 1'b0 ),
|
530 |
|
|
.RXENPRBSTST ( 3'b0 ),
|
531 |
|
|
.RXENSAMPLEALIGN ( 1'b0 ),
|
532 |
|
|
.RXDLYALIGNMONENB ( 1'b1 ),
|
533 |
|
|
.RXEQMIX ( 10'b0110000011 ),
|
534 |
|
|
.RXGEARBOXSLIP ( 1'b0 ),
|
535 |
|
|
.RXHEADER (),
|
536 |
|
|
.RXHEADERVALID (),
|
537 |
|
|
.RXLOSSOFSYNC (),
|
538 |
|
|
.RXN ( GTX_RXN[i] ),
|
539 |
|
|
.RXNOTINTABLE (),
|
540 |
|
|
.RXOVERSAMPLEERR (),
|
541 |
|
|
.RXP ( GTX_RXP[i] ),
|
542 |
|
|
.RXPLLLKDET ( RxPLLLkDet[i] ),
|
543 |
|
|
.RXPLLLKDETEN ( 1'b1 ),
|
544 |
|
|
.RXPLLPOWERDOWN ( 1'b0 ),
|
545 |
|
|
.RXPLLREFSELDY ( 3'b000 ),
|
546 |
|
|
.RXPMASETPHASE ( 1'b0 ),
|
547 |
|
|
.RXPOLARITY ( GTX_RxPolarity[i] ),
|
548 |
|
|
.RXPOWERDOWN ( PowerDown[(2*i)+1:(2*i)] ),
|
549 |
|
|
.RXPRBSERR (),
|
550 |
|
|
.RXRATE ( {1'b1, Rate} ),
|
551 |
|
|
.RXRATEDONE ( ),
|
552 |
|
|
.RXRECCLK ( RXRECCLK ),
|
553 |
|
|
.RXRECCLKPCS ( ),
|
554 |
|
|
.RXRESET ( ~GTReset_n | local_pcs_reset | PCS_RESET[i] ),
|
555 |
|
|
.RXRESETDONE ( GTX_RxResetDone[i] ),
|
556 |
|
|
.RXRUNDISP (),
|
557 |
|
|
.RXSLIDE ( 1'b0 ),
|
558 |
|
|
.RXSTARTOFSEQ (),
|
559 |
|
|
.RXSTATUS ( GTX_RxStatus[(3*i)+2:(3*i)] ),
|
560 |
|
|
.RXUSRCLK ( PCLK ),
|
561 |
|
|
.RXUSRCLK2 ( PCLK ),
|
562 |
|
|
.RXVALID (GTX_RxValid[i]),
|
563 |
|
|
.SOUTHREFCLKRX (0),
|
564 |
|
|
.SOUTHREFCLKTX (0),
|
565 |
|
|
.TSTCLK0 ( 1'b0 ),
|
566 |
|
|
.TSTCLK1 ( 1'b0 ),
|
567 |
|
|
.TSTIN ( {20{1'b1}} ),
|
568 |
|
|
.TSTOUT (),
|
569 |
|
|
.TXBUFDIFFCTRL ( 3'b111 ),
|
570 |
|
|
.TXBUFSTATUS (),
|
571 |
|
|
.TXBYPASS8B10B ( TXBYPASS8B10B[3:0] ),
|
572 |
|
|
.TXCHARDISPMODE ( {3'b000, GTX_TxCompliance[i]} ),
|
573 |
|
|
.TXCHARDISPVAL ( 4'b0000 ),
|
574 |
|
|
.TXCHARISK ( {TxDataK_dummy[1:0], GTX_TxDataK[(2*i)+1:2*i]} ),
|
575 |
|
|
.TXCOMINIT ( 1'b0 ),
|
576 |
|
|
.TXCOMSAS ( 1'b0 ),
|
577 |
|
|
.TXCOMWAKE ( 1'b0 ),
|
578 |
|
|
.TXDATA ( {TxData_dummy[15:0], GTX_TxData[(16*i)+15:(16*i)+0]} ),
|
579 |
|
|
.TXDEEMPH ( TxDeemph ),
|
580 |
|
|
.TXDETECTRX ( TxDetectRx ),
|
581 |
|
|
.TXDIFFCTRL ( 4'b1111 ),
|
582 |
|
|
.TXDLYALIGNDISABLE ( TXDLYALIGNDISABLE[i] ),
|
583 |
|
|
.TXDLYALIGNRESET ( TXDLYALIGNRESET[i] ),
|
584 |
|
|
.TXELECIDLE ( GTX_TxElecIdle[i] ),
|
585 |
|
|
.TXENC8B10BUSE ( 1'b1 ),
|
586 |
|
|
.TXENPMAPHASEALIGN ( TXENPMAPHASEALIGN[i] ),
|
587 |
|
|
.TXENPRBSTST (0),
|
588 |
|
|
.TXGEARBOXREADY (),
|
589 |
|
|
.TXHEADER (0),
|
590 |
|
|
.TXINHIBIT ( 1'b0 ),
|
591 |
|
|
.TXKERR (),
|
592 |
|
|
.TXMARGIN ( {TxMargin, 2'b00} ),
|
593 |
|
|
.TXN ( GTX_TXN[i] ),
|
594 |
|
|
.TXOUTCLK ( TXOCLK[i] ),
|
595 |
|
|
.TXOUTCLKPCS (),
|
596 |
|
|
.TXP ( GTX_TXP[i] ),
|
597 |
|
|
.TXPDOWNASYNCH ( TXPdownAsynch ),
|
598 |
|
|
.TXPLLLKDET ( ),
|
599 |
|
|
.TXPLLLKDETEN ( 1'b0 ),
|
600 |
|
|
.TXPLLPOWERDOWN ( 1'b0 ),
|
601 |
|
|
.TXPLLREFSELDY ( 3'b000 ),
|
602 |
|
|
.TXPMASETPHASE ( TXPMASETPHASE[i] ),
|
603 |
|
|
.TXPOLARITY ( 1'b0 ),
|
604 |
|
|
.TXPOSTEMPHASIS (0),
|
605 |
|
|
.TXPOWERDOWN ( PowerDown[(2*i)+1:(2*i)] ),
|
606 |
|
|
.TXPRBSFORCEERR (0),
|
607 |
|
|
.TXPREEMPHASIS (0),
|
608 |
|
|
.TXRATE ( {1'b1, Rate} ),
|
609 |
|
|
.TXRESET ( ~GTReset_n | local_pcs_reset | PCS_RESET[i] ),
|
610 |
|
|
.TXRESETDONE ( TXRESETDONE[i] ),
|
611 |
|
|
.TXRUNDISP (),
|
612 |
|
|
.TXSEQUENCE (0),
|
613 |
|
|
.TXSTARTSEQ (0),
|
614 |
|
|
.TXSWING ( TxSwing ),
|
615 |
|
|
.TXUSRCLK ( PCLK ),
|
616 |
|
|
.TXUSRCLK2 ( PCLK ),
|
617 |
|
|
.USRCODEERR (0),
|
618 |
|
|
.IGNORESIGDET (0),
|
619 |
|
|
.PERFCLKRX (0),
|
620 |
|
|
.PERFCLKTX (0),
|
621 |
|
|
.RXDLYALIGNMONITOR (),
|
622 |
|
|
.RXDLYALIGNOVERRIDE ( 1'b0 ),
|
623 |
|
|
.RXDLYALIGNRESET (0),
|
624 |
|
|
.RXDLYALIGNSWPPRECURB ( 1'b1 ),
|
625 |
|
|
.RXDLYALIGNUPDSW ( 1'b0 ),
|
626 |
|
|
.TXDLYALIGNMONITOR (),
|
627 |
|
|
.TXDLYALIGNOVERRIDE ( 1'b0 ),
|
628 |
|
|
.TXDLYALIGNUPDSW ( 1'b0 ),
|
629 |
|
|
.TXDLYALIGNMONENB ( 1'b1 ),
|
630 |
|
|
.TXRATEDONE ( TXRATEDONE[i] )
|
631 |
|
|
|
632 |
|
|
|
633 |
|
|
);
|
634 |
|
|
end
|
635 |
|
|
|
636 |
|
|
endgenerate
|
637 |
|
|
|
638 |
|
|
endmodule
|