| 1 |
3 |
weng_ziti |
##############################################################
|
| 2 |
|
|
#
|
| 3 |
|
|
# Xilinx Core Generator version 11.5
|
| 4 |
|
|
# Date: Wed May 19 15:19:37 2010
|
| 5 |
|
|
#
|
| 6 |
|
|
##############################################################
|
| 7 |
|
|
#
|
| 8 |
|
|
# This file contains the customisation parameters for a
|
| 9 |
|
|
# Xilinx CORE Generator IP GUI. It is strongly recommended
|
| 10 |
|
|
# that you do not manually alter this file as it may cause
|
| 11 |
|
|
# unexpected and unsupported behavior.
|
| 12 |
|
|
#
|
| 13 |
|
|
##############################################################
|
| 14 |
|
|
#
|
| 15 |
|
|
# BEGIN Project Options
|
| 16 |
|
|
SET addpads = False
|
| 17 |
|
|
SET asysymbol = True
|
| 18 |
|
|
SET busformat = BusFormatAngleBracketNotRipped
|
| 19 |
|
|
SET createndf = False
|
| 20 |
|
|
SET designentry = VHDL
|
| 21 |
|
|
SET device = xc5vlx110t
|
| 22 |
|
|
SET devicefamily = virtex5
|
| 23 |
|
|
SET flowvendor = Foundation_iSE
|
| 24 |
|
|
SET formalverification = False
|
| 25 |
|
|
SET foundationsym = False
|
| 26 |
|
|
SET implementationfiletype = Ngc
|
| 27 |
|
|
SET package = ff1136
|
| 28 |
|
|
SET removerpms = False
|
| 29 |
|
|
SET simulationfiles = Behavioral
|
| 30 |
|
|
SET speedgrade = -1
|
| 31 |
|
|
SET verilogsim = True
|
| 32 |
|
|
SET vhdlsim = True
|
| 33 |
|
|
# END Project Options
|
| 34 |
|
|
# BEGIN Select
|
| 35 |
|
|
SELECT Fifo_Generator family Xilinx,_Inc. 4.4
|
| 36 |
|
|
# END Select
|
| 37 |
|
|
# BEGIN Parameters
|
| 38 |
|
|
CSET almost_empty_flag=false
|
| 39 |
|
|
CSET almost_full_flag=false
|
| 40 |
|
|
CSET component_name=eb_fifo_counted
|
| 41 |
|
|
CSET data_count=false
|
| 42 |
|
|
CSET data_count_width=14
|
| 43 |
|
|
CSET disable_timing_violations=false
|
| 44 |
|
|
CSET dout_reset_value=0
|
| 45 |
|
|
CSET empty_threshold_assert_value=4096
|
| 46 |
|
|
CSET empty_threshold_negate_value=4097
|
| 47 |
|
|
CSET enable_ecc=false
|
| 48 |
|
|
CSET enable_int_clk=false
|
| 49 |
|
|
CSET fifo_implementation=Independent_Clocks_Block_RAM
|
| 50 |
|
|
CSET full_flags_reset_value=1
|
| 51 |
|
|
CSET full_threshold_assert_value=12287
|
| 52 |
|
|
CSET full_threshold_negate_value=12286
|
| 53 |
|
|
CSET input_data_width=72
|
| 54 |
|
|
CSET input_depth=16384
|
| 55 |
|
|
CSET output_data_width=72
|
| 56 |
|
|
CSET output_depth=16384
|
| 57 |
|
|
CSET overflow_flag=false
|
| 58 |
|
|
CSET overflow_sense=Active_High
|
| 59 |
|
|
CSET performance_options=Standard_FIFO
|
| 60 |
|
|
CSET programmable_empty_type=Single_Programmable_Empty_Threshold_Constant
|
| 61 |
|
|
CSET programmable_full_type=Single_Programmable_Full_Threshold_Constant
|
| 62 |
|
|
CSET read_clock_frequency=1
|
| 63 |
|
|
CSET read_data_count=true
|
| 64 |
|
|
CSET read_data_count_width=14
|
| 65 |
|
|
CSET reset_pin=true
|
| 66 |
|
|
CSET reset_type=Asynchronous_Reset
|
| 67 |
|
|
CSET underflow_flag=false
|
| 68 |
|
|
CSET underflow_sense=Active_High
|
| 69 |
|
|
CSET use_dout_reset=true
|
| 70 |
|
|
CSET use_embedded_registers=false
|
| 71 |
|
|
CSET use_extra_logic=false
|
| 72 |
|
|
CSET valid_flag=false
|
| 73 |
|
|
CSET valid_sense=Active_High
|
| 74 |
|
|
CSET write_acknowledge_flag=false
|
| 75 |
|
|
CSET write_acknowledge_sense=Active_High
|
| 76 |
|
|
CSET write_clock_frequency=1
|
| 77 |
|
|
CSET write_data_count=false
|
| 78 |
|
|
CSET write_data_count_width=14
|
| 79 |
|
|
# END Parameters
|
| 80 |
|
|
GENERATE
|
| 81 |
|
|
# CRC: 9ba94312
|
