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weng_ziti |
##############################################################
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#
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# Xilinx Core Generator version 11.5
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# Date: Wed May 19 15:23:06 2010
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#
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##############################################################
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#
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# This file contains the customisation parameters for a
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# Xilinx CORE Generator IP GUI. It is strongly recommended
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# that you do not manually alter this file as it may cause
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# unexpected and unsupported behavior.
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#
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##############################################################
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#
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# BEGIN Project Options
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SET addpads = False
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SET asysymbol = True
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SET busformat = BusFormatAngleBracketNotRipped
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SET createndf = False
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SET designentry = VHDL
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SET device = xc5vlx110t
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SET devicefamily = virtex5
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SET flowvendor = Foundation_iSE
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SET formalverification = False
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SET foundationsym = False
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SET implementationfiletype = Ngc
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SET package = ff1136
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SET removerpms = False
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SET simulationfiles = Structural
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SET speedgrade = -1
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SET verilogsim = True
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SET vhdlsim = True
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# END Project Options
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# BEGIN Select
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SELECT Endpoint_Block_Plus_for_PCI_Express family Xilinx,_Inc. 1.9
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# END Select
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# BEGIN Parameters
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CSET acceptable_l0_latency=No_limit
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CSET acceptable_l1_latency=No_limit
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CSET advanced_flow_control_credit=Header_Credit
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CSET aux_max_current=0mA
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CSET bar0_64bit=false
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CSET bar0_enabled=true
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CSET bar0_prefetchable=false
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CSET bar0_scale=Kilobytes
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CSET bar0_size=64
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CSET bar0_type=Memory
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CSET bar0_value=FFFF0000
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CSET bar1_64bit=false
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CSET bar1_enabled=true
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CSET bar1_prefetchable=false
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CSET bar1_scale=Megabytes
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CSET bar1_size=1
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CSET bar1_type=Memory
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CSET bar1_value=FFF00000
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CSET bar2_64bit=false
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CSET bar2_enabled=true
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CSET bar2_prefetchable=false
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CSET bar2_scale=Kilobytes
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CSET bar2_size=4
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CSET bar2_type=Memory
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CSET bar2_value=FFFFF000
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CSET bar3_64bit=false
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CSET bar3_enabled=false
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CSET bar3_prefetchable=false
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CSET bar3_scale=Kilobytes
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CSET bar3_size=64
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CSET bar3_type=IO
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CSET bar3_value=00000000
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CSET bar4_64bit=false
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CSET bar4_enabled=false
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CSET bar4_prefetchable=false
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CSET bar4_scale=Kilobytes
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CSET bar4_size=64
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CSET bar4_type=IO
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CSET bar4_value=00000000
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CSET bar5_enabled=false
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CSET bar5_prefetchable=false
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CSET bar5_scale=Kilobytes
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CSET bar5_size=64
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CSET bar5_type=IO
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CSET bar5_value=00000000
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CSET capabilities_register=0001
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CSET capability_version=1
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CSET cardbus_cis_pointer=00000000
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CSET class_code_base=05
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CSET class_code_interface=00
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CSET class_code_sub=00
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CSET class_code_value=050000
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CSET component_name=v5pcie_ep_blk_plus_4x
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CSET d0_pme_support=true
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CSET d0_power_consumed=0
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CSET d0_power_consumed_factor=0
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CSET d0_power_dissipated=0
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CSET d0_power_dissipated_factor=0
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CSET d1_pme_support=false
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CSET d1_power_consumed=0
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CSET d1_power_consumed_factor=0
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CSET d1_power_dissipated=0
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CSET d1_power_dissipated_factor=0
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CSET d1_support=false
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CSET d2_pme_support=false
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CSET d2_power_consumed=0
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CSET d2_power_consumed_factor=0
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CSET d2_power_dissipated=0
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CSET d2_power_dissipated_factor=0
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CSET d2_support=false
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CSET d3_power_consumed=0
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CSET d3_power_consumed_factor=0
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CSET d3_power_dissipated=0
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CSET d3_power_dissipated_factor=0
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CSET d3cold_pme_support=false
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CSET d3hot_pme_support=false
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CSET device_capabilities_register=00000FC2
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CSET device_id=0153
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CSET device_port_type=PCI_Express_Endpoint_device
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CSET device_specific_initialization=false
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CSET enable_aspm_l1_support=false
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CSET enable_slot_clock_cfg=true
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CSET expansion_rom_bar=FFF00001
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CSET expansion_rom_enabled=true
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CSET expansion_rom_scale=Megabytes
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CSET expansion_rom_size=1
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CSET force_no_scrambling=false
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CSET gt_debug_ports=false
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CSET interface_freq=125_default
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CSET lane_width=X4
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CSET link_capabilities_register=0003F441
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CSET max_payload_size=512_bytes
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CSET maximum_link_speed=1
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CSET maximum_link_width=4
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CSET msi=1_vector
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CSET reference_freq=100
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CSET revision_id=06
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CSET subsystem_id=ABB2
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CSET subsystem_vendor_id=0084
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CSET trim_tlp_digest=true
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CSET tx_diff_boost=true
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CSET tx_diff_ctrl=800
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CSET tx_pre_emphasis=52
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CSET vendor_id=10DC
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# END Parameters
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GENERATE
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# CRC: ad3b4333
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