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[/] [pcie_sg_dma/] [trunk/] [rtl/] [tlpControl.vhd] - Blame information for rev 3

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Line No. Rev Author Line
1 2 weng_ziti 
----------------------------------------------------------------------------------
2 
-- Company:  ziti, Uni. HD
3 
-- Engineer:  wgao
4 
--
5 
-- Create Date:    11:09:49 18 Oct 2006
6 
-- Design Name:
7 
-- Module Name:    tlpControl - Behavioral
8 
-- Project Name:
9 
-- Target Devices:
10 
-- Tool versions:
11 
-- Description:
12 
--
13 
-- Dependencies:
14 
--
15 
-- Revision 1.00 - first release.  18.10.2006
16 
--
17 
-- Additional Comments:
18 
--
19 
----------------------------------------------------------------------------------
20 
 
21 
library IEEE;
22 
use IEEE.STD_LOGIC_1164.ALL;
23 
use IEEE.STD_LOGIC_ARITH.ALL;
24 
use IEEE.STD_LOGIC_UNSIGNED.ALL;
25 
 
26 
library work;
27 
use work.abb64Package.all;
28 
--use work.busmacro_xc4v_pkg.all;
29 
 
30 
-- Uncomment the following library declaration if instantiating
31 
-- any Xilinx primitives in this code.
32 
--library UNISIM;
33 
--use UNISIM.VComponents.all;
34 
 
35 
entity tlpControl is
36 
    port (
37 
 
38 
      --  Test pin, emulating DDR data flow discontinuity
39 
      mbuf_UserFull            : IN   std_logic;
40 
      trn_Blinker              : OUT  std_logic;
41 
 
42 3 weng_ziti 
--      -- DCB protocol interface
43 
--      protocol_link_act        : IN  std_logic_vector(2-1 downto 0);
44 
--      protocol_rst             : OUT std_logic;
45 
--
46 
--      -- Interrupter triggers
47 
--      DAQ_irq                  : IN  std_logic;
48 
--      CTL_irq                  : IN  std_logic;
49 
--      DLM_irq                  : IN  std_logic;
50 
--
51 
--      -- Fabric side: CTL Rx
52 
--      ctl_rv                   : OUT std_logic;
53 
--      ctl_rd                   : OUT std_logic_vector(C_DBUS_WIDTH/2-1 downto 0);
54 
--
55 
--      -- Fabric side: CTL Tx
56 
--      ctl_ttake                : OUT std_logic;
57 
--      ctl_tv                   : IN  std_logic;
58 
--      ctl_td                   : IN  std_logic_vector(C_DBUS_WIDTH/2-1 downto 0);
59 
--      ctl_tstop                : OUT std_logic;
60 
--
61 
--      ctl_reset                : OUT std_logic;
62 
--      ctl_status               : IN  std_logic_vector(C_DBUS_WIDTH/2-1 downto 0);
63 
--
64 
--      -- Fabric side: DLM Rx
65 
--      dlm_tv                   : OUT std_logic;
66 
--      dlm_td                   : OUT std_logic_vector(C_DBUS_WIDTH/2-1 downto 0);
67 
--
68 
--      -- Fabric side: DLM Tx
69 
--      dlm_rv                   : IN  std_logic;
70 
--      dlm_rd                   : IN  std_logic_vector(C_DBUS_WIDTH/2-1 downto 0);
71 2 weng_ziti 
 
72 
      -- Event Buffer FIFO interface
73 
      eb_FIFO_we               : OUT std_logic;
74 
      eb_FIFO_wsof             : OUT std_logic;
75 
      eb_FIFO_weof             : OUT std_logic;
76 
      eb_FIFO_din              : OUT std_logic_vector(C_DBUS_WIDTH-1 downto 0);
77 
      eb_FIFO_re               : OUT std_logic;
78 
      eb_FIFO_empty            : IN  std_logic;
79 
      eb_FIFO_qout             : IN  std_logic_vector(C_DBUS_WIDTH-1 downto 0);
80 
      eb_FIFO_ow               : IN  std_logic;
81 
 
82 
      eb_FIFO_data_count       : IN  std_logic_vector(C_FIFO_DC_WIDTH downto 0);
83 
 
84 
      pio_reading_status       : OUT std_logic;
85 
      eb_FIFO_Status           : IN  std_logic_vector(C_DBUS_WIDTH-1 downto 0);
86 
      eb_FIFO_Rst              : OUT std_logic;
87 
 
88 
      Link_Buf_full            : IN  std_logic;
89 
 
90 
      -- Debugging signals
91 
      DMA_us_Done              : OUT std_logic;
92 
      DMA_us_Busy              : OUT std_logic;
93 
      DMA_us_Busy_LED          : OUT std_logic;
94 
      DMA_ds_Done              : OUT std_logic;
95 
      DMA_ds_Busy              : OUT std_logic;
96 
      DMA_ds_Busy_LED          : OUT std_logic;
97 
      DMA_ds_Start             : OUT std_logic;
98 
 
99 
      self_feed_daq            : OUT std_logic;
100 
 
101 
      -- DDR control interface
102 
      DDR_Ready                : IN    std_logic;
103 
 
104 
      DDR_wr_sof               : OUT   std_logic;
105 
      DDR_wr_eof               : OUT   std_logic;
106 
      DDR_wr_v                 : OUT   std_logic;
107 
      DDR_wr_FA                : OUT   std_logic;
108 
      DDR_wr_Shift             : OUT   std_logic;
109 
      DDR_wr_Mask              : OUT   std_logic_vector(2-1 downto 0);
110 
      DDR_wr_din               : OUT   std_logic_vector(C_DBUS_WIDTH-1 downto 0);
111 
      DDR_wr_full              : IN    std_logic;
112 
 
113 
      DDR_rdc_sof              : OUT   std_logic;
114 
      DDR_rdc_eof              : OUT   std_logic;
115 
      DDR_rdc_v                : OUT   std_logic;
116 
      DDR_rdc_FA               : OUT   std_logic;
117 
      DDR_rdc_Shift            : OUT   std_logic;
118 
      DDR_rdc_din              : OUT   std_logic_vector(C_DBUS_WIDTH-1 downto 0);
119 
      DDR_rdc_full             : IN    std_logic;
120 
 
121 
--      DDR_rdD_sof              : IN    std_logic;
122 
--      DDR_rdD_eof              : IN    std_logic;
123 
--      DDR_rdDout_V             : IN    std_logic;
124 
--      DDR_rdDout               : IN    std_logic_vector(C_DBUS_WIDTH-1 downto 0);
125 
 
126 
      -- DDR payload FIFO Read Port
127 
      DDR_FIFO_RdEn            : OUT std_logic;
128 
      DDR_FIFO_Empty           : IN  std_logic;
129 
      DDR_FIFO_RdQout          : IN  std_logic_vector(C_DBUS_WIDTH-1 downto 0);
130 
 
131 3 weng_ziti 
--      -- Data generator table write
132 
--      tab_we                   : OUT std_logic_vector(2-1 downto 0);
133 
--      tab_wa                   : OUT std_logic_vector(12-1 downto 0);
134 
--      tab_wd                   : OUT std_logic_vector(C_DBUS_WIDTH-1 downto 0);
135 
--
136 
--      DG_is_Running            : IN  std_logic;
137 
--      DG_Reset                 : OUT std_logic;
138 
--      DG_Mask                  : OUT std_logic;
139 2 weng_ziti 
 
140 
      -- Common interface
141 
      trn_clk                  : IN  std_logic;
142 
      trn_reset_n              : IN  std_logic;
143 
      trn_lnk_up_n             : IN  std_logic;
144 
 
145 
      -- Transaction receive interface
146 
      trn_rsof_n               : IN  std_logic;
147 
      trn_reof_n               : IN  std_logic;
148 
      trn_rd                   : IN  std_logic_vector(C_DBUS_WIDTH-1 downto 0);
149 
      trn_rrem_n               : IN  std_logic_vector(C_DBUS_WIDTH/8-1 downto 0);
150 
      trn_rerrfwd_n            : IN  std_logic;
151 
      trn_rsrc_rdy_n           : IN  std_logic;
152 
      trn_rdst_rdy_n           : OUT std_logic;
153 
      trn_rnp_ok_n             : OUT std_logic;
154 
      trn_rsrc_dsc_n           : IN  std_logic;
155 
      trn_rbar_hit_n           : IN  std_logic_vector(C_BAR_NUMBER-1 downto 0);
156 
--    trn_rfc_ph_av              : IN  std_logic_vector(7 downto 0);
157 
--    trn_rfc_pd_av              : IN  std_logic_vector(11 downto 0);
158 
--    trn_rfc_nph_av             : IN  std_logic_vector(7 downto 0);
159 
--    trn_rfc_npd_av             : IN  std_logic_vector(11 downto 0);
160 
--    trn_rfc_cplh_av            : IN  std_logic_vector(7 downto 0);
161 
--    trn_rfc_cpld_av            : IN  std_logic_vector(11 downto 0);
162 
 
163 
      -- Transaction transmit interface
164 
      trn_tsof_n              : OUT std_logic;
165 
      trn_teof_n              : OUT std_logic;
166 
      trn_td                  : OUT std_logic_vector(C_DBUS_WIDTH-1 downto 0);
167 
      trn_trem_n              : OUT std_logic_vector(C_DBUS_WIDTH/8-1 downto 0);
168 
      trn_terrfwd_n           : OUT std_logic;
169 
      trn_tsrc_rdy_n          : OUT std_logic;
170 
      trn_tdst_rdy_n          : IN  std_logic;
171 
      trn_tsrc_dsc_n          : OUT std_logic;
172 
      trn_tdst_dsc_n          : IN  std_logic;
173 
      trn_tbuf_av             : IN  std_logic_vector(C_TBUF_AWIDTH-1 downto 0);
174 
 
175 
      Format_Shower           : OUT   std_logic;
176 
 
177 
      -- Interrupt Interface
178 
                cfg_interrupt_n         : OUT std_logic;
179 
                cfg_interrupt_rdy_n     : IN  std_logic;
180 
                cfg_interrupt_mmenable  : IN  std_logic_VECTOR(2 downto 0);
181 
                cfg_interrupt_msienable : IN  std_logic;
182 
                cfg_interrupt_di        : OUT std_logic_VECTOR(7 downto 0);
183 
                cfg_interrupt_do        : IN  std_logic_VECTOR(7 downto 0);
184 
                cfg_interrupt_assert_n  : OUT std_logic;
185 
 
186 
      -- Local signals
187 
      pcie_link_width         : IN  std_logic_vector(CINT_BIT_LWIDTH_IN_GSR_TOP-CINT_BIT_LWIDTH_IN_GSR_BOT downto 0);
188 
      cfg_dcommand            : IN  std_logic_vector(16-1 downto 0);
189 
      localID                 : IN  std_logic_vector(C_ID_WIDTH-1 downto 0)
190 
         );
191 
 
192 
end entity tlpControl;
193 
 
194 
 
195 
 
196 
architecture Behavioral of tlpControl is
197 
 
198 
  signal trn_lnk_up_i       : std_logic;
199 
 
200 
---- Rx transaction control
201 
  component rx_Transact
202 
    port (
203 
      -- Common ports
204 
      trn_clk            : IN  std_logic;
205 
      trn_reset_n        : IN  std_logic;
206 
      trn_lnk_up_n       : IN  std_logic;
207 
 
208 
      -- Transaction receive interface
209 
      trn_rsof_n         : IN  std_logic;
210 
      trn_reof_n         : IN  std_logic;
211 
      trn_rd             : IN  std_logic_vector(C_DBUS_WIDTH-1 downto 0);
212 
      trn_rrem_n         : IN  std_logic_vector(C_DBUS_WIDTH/8-1 downto 0);
213 
      trn_rerrfwd_n      : IN  std_logic;
214 
      trn_rsrc_rdy_n     : IN  std_logic;
215 
      trn_rdst_rdy_n     : OUT std_logic;
216 
      trn_rnp_ok_n       : OUT std_logic;
217 
      trn_rsrc_dsc_n     : IN  std_logic;
218 
      trn_rbar_hit_n     : IN  std_logic_vector(C_BAR_NUMBER-1 downto 0);
219 
 
220 
--      trn_rfc_ph_av      : IN  std_logic_vector(7 downto 0);
221 
--      trn_rfc_pd_av      : IN  std_logic_vector(11 downto 0);
222 
--      trn_rfc_nph_av     : IN  std_logic_vector(7 downto 0);
223 
--      trn_rfc_npd_av     : IN  std_logic_vector(11 downto 0);
224 
--      trn_rfc_cplh_av    : IN  std_logic_vector(7 downto 0);
225 
--      trn_rfc_cpld_av    : IN  std_logic_vector(11 downto 0);
226 
 
227 
 
228 
      -- MRd Channel
229 
      pioCplD_Req        : OUT std_logic;
230 
      pioCplD_RE         : IN  std_logic;
231 
      pioCplD_Qout       : OUT std_logic_vector(C_CHANNEL_BUF_WIDTH-1 downto 0);
232 
      pio_FC_stop        : IN  std_logic;
233 
 
234 
 
235 
      -- MRd-downstream packet Channel
236 
      dsMRd_Req          : OUT std_logic;
237 
      dsMRd_RE           : IN  std_logic;
238 
      dsMRd_Qout         : OUT std_logic_vector(C_CHANNEL_BUF_WIDTH-1 downto 0);
239 
 
240 
 
241 
      -- Upstream MWr/MRd Channel
242 
      usTlp_Req          : OUT std_logic;
243 
      usTlp_RE           : IN  std_logic;
244 
      usTlp_Qout         : OUT std_logic_vector(C_CHANNEL_BUF_WIDTH-1 downto 0);
245 
      us_FC_stop         : IN  std_logic;
246 
      us_Last_sof        : IN  std_logic;
247 
      us_Last_eof        : IN  std_logic;
248 
 
249 
      -- Irpt Channel
250 
      Irpt_Req           : OUT std_logic;
251 
      Irpt_RE            : IN  std_logic;
252 
      Irpt_Qout          : OUT std_logic_vector(C_CHANNEL_BUF_WIDTH-1 downto 0);
253 
 
254 
 
255 
      -- Interrupt Interface
256 
                cfg_interrupt_n         : OUT std_logic;
257 
                cfg_interrupt_rdy_n     : IN  std_logic;
258 
                cfg_interrupt_mmenable  : IN  std_logic_VECTOR(2 downto 0);
259 
                cfg_interrupt_msienable : IN  std_logic;
260 
                cfg_interrupt_di        : OUT std_logic_VECTOR(7 downto 0);
261 
                cfg_interrupt_do        : IN  std_logic_VECTOR(7 downto 0);
262 
                cfg_interrupt_assert_n  : OUT std_logic;
263 
 
264 
 
265 
      -- Event Buffer write port
266 
      eb_FIFO_we              : OUT std_logic;
267 
      eb_FIFO_wsof            : OUT std_logic;
268 
      eb_FIFO_weof            : OUT std_logic;
269 
      eb_FIFO_din             : OUT std_logic_vector(C_DBUS_WIDTH-1 downto 0);
270 
 
271 
      eb_FIFO_data_count      : IN  std_logic_vector(C_FIFO_DC_WIDTH downto 0);
272 
      eb_FIFO_Empty           : IN  std_logic;
273 
      eb_FIFO_Reading         : IN  std_logic;
274 
      pio_reading_status      : OUT std_logic;
275 
 
276 
      -- Registers Write Port
277 
      Regs_WrEn0         : OUT std_logic;
278 
      Regs_WrMask0       : OUT std_logic_vector(2-1 downto 0);
279 
      Regs_WrAddr0       : OUT std_logic_vector(C_EP_AWIDTH-1 downto 0);
280 
      Regs_WrDin0        : OUT std_logic_vector(C_DBUS_WIDTH-1 downto 0);
281 
 
282 
      Regs_WrEn1         : OUT std_logic;
283 
      Regs_WrMask1       : OUT std_logic_vector(2-1 downto 0);
284 
      Regs_WrAddr1       : OUT std_logic_vector(C_EP_AWIDTH-1 downto 0);
285 
      Regs_WrDin1        : OUT std_logic_vector(C_DBUS_WIDTH-1 downto 0);
286 
 
287 
      -- Downstream DMA transferred bytes count up
288 
      ds_DMA_Bytes_Add   : OUT std_logic;
289 
      ds_DMA_Bytes       : OUT std_logic_vector(C_TLP_FLD_WIDTH_OF_LENG+2 downto 0);
290 
 
291 
      -- --------------------------
292 
      -- Registers
293 
      DMA_ds_PA          : IN  std_logic_vector(C_DBUS_WIDTH-1 downto 0);
294 
      DMA_ds_HA          : IN  std_logic_vector(C_DBUS_WIDTH-1 downto 0);
295 
      DMA_ds_BDA         : IN  std_logic_vector(C_DBUS_WIDTH-1 downto 0);
296 
      DMA_ds_Length      : IN  std_logic_vector(C_DBUS_WIDTH-1 downto 0);
297 
      DMA_ds_Control     : IN  std_logic_vector(C_DBUS_WIDTH-1 downto 0);
298 
      dsDMA_BDA_eq_Null  : IN  std_logic;
299 
      DMA_ds_Status      : OUT std_logic_vector(C_DBUS_WIDTH-1 downto 0);
300 
      DMA_ds_Done        : OUT std_logic;
301 
      DMA_ds_Busy        : OUT std_logic;
302 
      DMA_ds_Tout        : OUT std_logic;
303 
 
304 
      -- Calculation in advance, for better timing
305 
      dsHA_is_64b        : IN  std_logic;
306 
      dsBDA_is_64b       : IN  std_logic;
307 
 
308 
      -- Calculation in advance, for better timing
309 
      dsLeng_Hi19b_True  : IN  std_logic;
310 
      dsLeng_Lo7b_True   : IN  std_logic;
311 
 
312 
 
313 
      dsDMA_Start        : IN  std_logic;
314 
      dsDMA_Stop         : IN  std_logic;
315 
      dsDMA_Start2       : IN  std_logic;
316 
      dsDMA_Stop2        : IN  std_logic;
317 
      dsDMA_Channel_Rst  : IN  std_logic;
318 
      dsDMA_Cmd_Ack      : OUT std_logic;
319 
 
320 
      DMA_us_PA          : IN  std_logic_vector(C_DBUS_WIDTH-1 downto 0);
321 
      DMA_us_HA          : IN  std_logic_vector(C_DBUS_WIDTH-1 downto 0);
322 
      DMA_us_BDA         : IN  std_logic_vector(C_DBUS_WIDTH-1 downto 0);
323 
      DMA_us_Length      : IN  std_logic_vector(C_DBUS_WIDTH-1 downto 0);
324 
      DMA_us_Control     : IN  std_logic_vector(C_DBUS_WIDTH-1 downto 0);
325 
      usDMA_BDA_eq_Null  : IN  std_logic;
326 
      us_MWr_Param_Vec   : IN  std_logic_vector(6-1   downto 0);
327 
      DMA_us_Status      : OUT std_logic_vector(C_DBUS_WIDTH-1 downto 0);
328 
      DMA_us_Done        : OUT std_logic;
329 
      DMA_us_Busy        : OUT std_logic;
330 
      DMA_us_Tout        : OUT std_logic;
331 
 
332 
      -- Calculation in advance, for better timing
333 
      usHA_is_64b        : IN  std_logic;
334 
      usBDA_is_64b       : IN  std_logic;
335 
 
336 
      -- Calculation in advance, for better timing
337 
      usLeng_Hi19b_True  : IN  std_logic;
338 
      usLeng_Lo7b_True   : IN  std_logic;
339 
 
340 
 
341 
      usDMA_Start        : IN  std_logic;
342 
      usDMA_Stop         : IN  std_logic;
343 
      usDMA_Start2       : IN  std_logic;
344 
      usDMA_Stop2        : IN  std_logic;
345 
      usDMA_Channel_Rst  : IN  std_logic;
346 
      usDMA_Cmd_Ack      : OUT std_logic;
347 
 
348 
      MRd_Channel_Rst    : IN  std_logic;
349 
 
350 
      Sys_IRQ            : IN  std_logic_vector(C_DBUS_WIDTH-1 downto 0);
351 
 
352 
 
353 
      -- DDR write port
354 
      DDR_wr_sof_A       : OUT   std_logic;
355 
      DDR_wr_eof_A       : OUT   std_logic;
356 
      DDR_wr_v_A         : OUT   std_logic;
357 
      DDR_wr_FA_A        : OUT   std_logic;
358 
      DDR_wr_Shift_A     : OUT   std_logic;
359 
      DDR_wr_Mask_A      : OUT   std_logic_vector(2-1 downto 0);
360 
      DDR_wr_din_A       : OUT   std_logic_vector(C_DBUS_WIDTH-1 downto 0);
361 
 
362 
      DDR_wr_sof_B       : OUT   std_logic;
363 
      DDR_wr_eof_B       : OUT   std_logic;
364 
      DDR_wr_v_B         : OUT   std_logic;
365 
      DDR_wr_FA_B        : OUT   std_logic;
366 
      DDR_wr_Shift_B     : OUT   std_logic;
367 
      DDR_wr_Mask_B      : OUT   std_logic_vector(2-1 downto 0);
368 
      DDR_wr_din_B       : OUT   std_logic_vector(C_DBUS_WIDTH-1 downto 0);
369 
 
370 
      DDR_wr_full        : IN    std_logic;
371 
 
372 
      Link_Buf_full      : IN  std_logic;
373 
 
374 3 weng_ziti 
--      -- Data generator table write
375 
--      tab_we             : OUT std_logic_vector(2-1 downto 0);
376 
--      tab_wa             : OUT std_logic_vector(12-1 downto 0);
377 
--      tab_wd             : OUT std_logic_vector(C_DBUS_WIDTH-1 downto 0);
378 2 weng_ziti 
 
379 
      -- Interrupt generator signals
380 
      IG_Reset           : IN  std_logic;
381 
      IG_Host_Clear      : IN  std_logic;
382 
      IG_Latency         : IN  std_logic_vector(C_DBUS_WIDTH-1   downto 0);
383 
      IG_Num_Assert      : OUT std_logic_vector(C_DBUS_WIDTH-1   downto 0);
384 
      IG_Num_Deassert    : OUT std_logic_vector(C_DBUS_WIDTH-1   downto 0);
385 
      IG_Asserting       : OUT std_logic;
386 
 
387 
 
388 
      -- Additional
389 
      cfg_dcommand       : IN  std_logic_vector(16-1 downto 0);
390 
      localID            : IN  std_logic_vector(C_ID_WIDTH-1 downto 0)
391 
    );
392 
  end component rx_Transact;
393 
 
394 
  -- Downstream DMA transferred bytes count up
395 
  signal ds_DMA_Bytes_Add   : std_logic;
396 
  signal ds_DMA_Bytes       : std_logic_vector(C_TLP_FLD_WIDTH_OF_LENG+2 downto 0);
397 
 
398 
 
399 
---- Tx transaction control
400 
  component tx_Transact
401 
    port (
402 
      -- Common ports
403 
      trn_clk            : IN  std_logic;
404 
      trn_reset_n        : IN  std_logic;
405 
      trn_lnk_up_n       : IN  std_logic;
406 
 
407 
      -- Transaction
408 
      trn_tsof_n         : OUT std_logic;
409 
      trn_teof_n         : OUT std_logic;
410 
      trn_td             : OUT std_logic_vector(C_DBUS_WIDTH-1 downto 0);
411 
      trn_trem_n         : OUT std_logic_vector(C_DBUS_WIDTH/8-1 downto 0);
412 
      trn_terrfwd_n      : OUT std_logic;
413 
      trn_tsrc_rdy_n     : OUT std_logic;
414 
      trn_tdst_rdy_n     : IN  std_logic;
415 
      trn_tsrc_dsc_n     : OUT std_logic;
416 
      trn_tdst_dsc_n     : IN  std_logic;
417 
      trn_tbuf_av        : IN  std_logic_vector(C_TBUF_AWIDTH-1 downto 0);
418 
 
419 
      -- Upstream DMA transferred bytes count up
420 
      us_DMA_Bytes_Add   : OUT std_logic;
421 
      us_DMA_Bytes       : OUT std_logic_vector(C_TLP_FLD_WIDTH_OF_LENG+2 downto 0);
422 
 
423 
      -- MRd Channel
424 
      pioCplD_Req        : IN  std_logic;
425 
      pioCplD_RE         : OUT std_logic;
426 
      pioCplD_Qout       : IN  std_logic_vector(C_CHANNEL_BUF_WIDTH-1 downto 0);
427 
      pio_FC_stop        : OUT std_logic;
428 
 
429 
 
430 
      -- MRd-downstream packet Channel
431 
      dsMRd_Req          : IN  std_logic;
432 
      dsMRd_RE           : OUT std_logic;
433 
      dsMRd_Qout         : IN  std_logic_vector(C_CHANNEL_BUF_WIDTH-1 downto 0);
434 
 
435 
 
436 
      -- Upstream MWr Channel
437 
      usTlp_Req          : IN  std_logic;
438 
      usTlp_RE           : OUT std_logic;
439 
      usTlp_Qout         : IN  std_logic_vector(C_CHANNEL_BUF_WIDTH-1 downto 0);
440 
      us_FC_stop         : OUT std_logic;
441 
      us_Last_sof        : OUT std_logic;
442 
      us_Last_eof        : OUT std_logic;
443 
 
444 
 
445 
      -- Irpt Channel
446 
      Irpt_Req           : IN  std_logic;
447 
      Irpt_RE            : OUT std_logic;
448 
      Irpt_Qout          : IN  std_logic_vector(C_CHANNEL_BUF_WIDTH-1 downto 0);
449 
 
450 
 
451 
      -- Event Buffer FIFO read port
452 
      eb_FIFO_re         : OUT std_logic;
453 
      eb_FIFO_empty      : IN  std_logic;
454 
      eb_FIFO_qout       : IN  std_logic_vector(C_DBUS_WIDTH-1 downto 0);
455 
 
456 
      -- With Rx port
457 
      Regs_RdAddr        : OUT std_logic_vector(C_EP_AWIDTH-1 downto 0);
458 
      Regs_RdQout        : IN  std_logic_vector(C_DBUS_WIDTH-1 downto 0);
459 
 
460 
      -- Message routing method
461 
      Msg_Routing        : IN  std_logic_vector(C_GCR_MSG_ROUT_BIT_TOP-C_GCR_MSG_ROUT_BIT_BOT downto 0);
462 
 
463 
 
464 
      --  DDR read port
465 
      DDR_rdc_sof        : OUT   std_logic;
466 
      DDR_rdc_eof        : OUT   std_logic;
467 
      DDR_rdc_v          : OUT   std_logic;
468 
      DDR_rdc_FA         : OUT   std_logic;
469 
      DDR_rdc_Shift      : OUT   std_logic;
470 
      DDR_rdc_din        : OUT   std_logic_vector(C_DBUS_WIDTH-1 downto 0);
471 
      DDR_rdc_full       : IN    std_logic;
472 
 
473 
--      DDR_rdD_sof        : IN    std_logic;
474 
--      DDR_rdD_eof        : IN    std_logic;
475 
--      DDR_rdDout_V       : IN    std_logic;
476 
--      DDR_rdDout         : IN    std_logic_vector(C_DBUS_WIDTH-1 downto 0);
477 
 
478 
      -- DDR payload FIFO Read Port
479 
      DDR_FIFO_RdEn      : OUT std_logic;
480 
      DDR_FIFO_Empty     : IN  std_logic;
481 
      DDR_FIFO_RdQout    : IN  std_logic_vector(C_DBUS_WIDTH-1 downto 0);
482 
 
483 
      -- Additional
484 
      Tx_TimeOut         : OUT std_logic;
485 
      Tx_eb_TimeOut      : OUT std_logic;
486 
      Format_Shower      : OUT   std_logic;
487 
      Tx_Reset           : IN  std_logic;
488 
      mbuf_UserFull      : IN  std_logic;
489 
      localID            : IN  std_logic_vector(C_ID_WIDTH-1 downto 0)
490 
    );
491 
  end component tx_Transact;
492 
 
493 
 
494 
  -- Upstream DMA transferred bytes count up
495 
  signal   us_DMA_Bytes_Add   : std_logic;
496 
  signal   us_DMA_Bytes       : std_logic_vector(C_TLP_FLD_WIDTH_OF_LENG+2 downto 0);
497 
 
498 
  -- ------------------------------------------------
499 
  -- United memory space consisting of registers.
500 
  --
501 
  component Regs_Group
502 
    port (
503 
 
504 3 weng_ziti 
--      -- DCB protocol interface
505 
--              protocol_link_act        : IN  std_logic_vector(2-1 downto 0);
506 
--              protocol_rst             : OUT std_logic;
507 
--
508 
--      -- Fabric side: CTL Rx
509 
--      ctl_rv                   : OUT std_logic;
510 
--      ctl_rd                   : OUT std_logic_vector(C_DBUS_WIDTH/2-1 downto 0);
511 
--
512 
--      -- Fabric side: CTL Tx
513 
--      ctl_ttake                : OUT std_logic;
514 
--      ctl_tv                   : IN  std_logic;
515 
--      ctl_td                   : IN  std_logic_vector(C_DBUS_WIDTH/2-1 downto 0);
516 
--      ctl_tstop                : OUT std_logic;
517 
--
518 
--      ctl_reset                : OUT std_logic;
519 
--      ctl_status               : IN  std_logic_vector(C_DBUS_WIDTH/2-1 downto 0);
520 
--
521 
--      -- Fabric side: DLM Rx
522 
--      dlm_tv                   : OUT std_logic;
523 
--      dlm_td                   : OUT std_logic_vector(C_DBUS_WIDTH/2-1 downto 0);
524 
--
525 
--      -- Fabric side: DLM Tx
526 
--      dlm_rv                   : IN  std_logic;
527 
--      dlm_rd                   : IN  std_logic_vector(C_DBUS_WIDTH/2-1 downto 0);
528 2 weng_ziti 
 
529 
      -- Event Buffer status
530 
      eb_FIFO_Status           : IN  std_logic_vector(C_DBUS_WIDTH-1 downto 0);
531 
      eb_FIFO_Rst              : OUT std_logic;
532 
 
533 
      self_feed_daq            : OUT std_logic;
534 
 
535 
      -- Register Write
536 
      Regs_WrEnA               : IN  std_logic;
537 
      Regs_WrMaskA             : IN  std_logic_vector(2-1 downto 0);
538 
      Regs_WrAddrA             : IN  std_logic_vector(C_EP_AWIDTH-1   downto 0);
539 
      Regs_WrDinA              : IN  std_logic_vector(C_DBUS_WIDTH-1   downto 0);
540 
 
541 
      Regs_WrEnB               : IN  std_logic;
542 
      Regs_WrMaskB             : IN  std_logic_vector(2-1 downto 0);
543 
      Regs_WrAddrB             : IN  std_logic_vector(C_EP_AWIDTH-1   downto 0);
544 
      Regs_WrDinB              : IN  std_logic_vector(C_DBUS_WIDTH-1   downto 0);
545 
 
546 
      Regs_RdAddr              : IN  std_logic_vector(C_EP_AWIDTH-1   downto 0);
547 
      Regs_RdQout              : OUT std_logic_vector(C_DBUS_WIDTH-1   downto 0);
548 
 
549 
      -- Downstream DMA transferred bytes count up
550 
      ds_DMA_Bytes_Add         : IN  std_logic;
551 
      ds_DMA_Bytes             : IN  std_logic_vector(C_TLP_FLD_WIDTH_OF_LENG+2 downto 0);
552 
 
553 
      -- Register Values
554 
      DMA_ds_PA                : OUT std_logic_vector(C_DBUS_WIDTH-1 downto 0);
555 
      DMA_ds_HA                : OUT std_logic_vector(C_DBUS_WIDTH-1 downto 0);
556 
      DMA_ds_BDA               : OUT std_logic_vector(C_DBUS_WIDTH-1 downto 0);
557 
      DMA_ds_Length            : OUT std_logic_vector(C_DBUS_WIDTH-1 downto 0);
558 
      DMA_ds_Control           : OUT std_logic_vector(C_DBUS_WIDTH-1 downto 0);
559 
      dsDMA_BDA_eq_Null        : OUT std_logic;
560 
      DMA_ds_Status            : IN  std_logic_vector(C_DBUS_WIDTH-1 downto 0);
561 
      DMA_ds_Done              : IN  std_logic;
562 
--      DMA_ds_Busy              : IN  std_logic;
563 
      DMA_ds_Tout              : IN  std_logic;
564 
 
565 
      -- Calculation in advance, for better timing
566 
      dsHA_is_64b              : OUT std_logic;
567 
      dsBDA_is_64b             : OUT std_logic;
568 
 
569 
      -- Calculation in advance, for better timing
570 
      dsLeng_Hi19b_True        : OUT std_logic;
571 
      dsLeng_Lo7b_True         : OUT std_logic;
572 
 
573 
 
574 
      dsDMA_Start              : OUT std_logic;
575 
      dsDMA_Stop               : OUT std_logic;
576 
      dsDMA_Start2             : OUT std_logic;
577 
      dsDMA_Stop2              : OUT std_logic;
578 
      dsDMA_Channel_Rst        : OUT std_logic;
579 
      dsDMA_Cmd_Ack            : IN  std_logic;
580 
 
581 
      -- Upstream DMA transferred bytes count up
582 
      us_DMA_Bytes_Add         : IN  std_logic;
583 
      us_DMA_Bytes             : IN  std_logic_vector(C_TLP_FLD_WIDTH_OF_LENG+2 downto 0);
584 
 
585 
      DMA_us_PA                : OUT std_logic_vector(C_DBUS_WIDTH-1 downto 0);
586 
      DMA_us_HA                : OUT std_logic_vector(C_DBUS_WIDTH-1 downto 0);
587 
      DMA_us_BDA               : OUT std_logic_vector(C_DBUS_WIDTH-1 downto 0);
588 
      DMA_us_Length            : OUT std_logic_vector(C_DBUS_WIDTH-1 downto 0);
589 
      DMA_us_Control           : OUT std_logic_vector(C_DBUS_WIDTH-1 downto 0);
590 
      usDMA_BDA_eq_Null        : OUT std_logic;
591 
      us_MWr_Param_Vec         : OUT std_logic_vector(6-1   downto 0);
592 
      DMA_us_Status            : IN  std_logic_vector(C_DBUS_WIDTH-1 downto 0);
593 
      DMA_us_Done              : IN  std_logic;
594 
--      DMA_us_Busy              : IN  std_logic;
595 
      DMA_us_Tout              : IN  std_logic;
596 
 
597 
      -- Calculation in advance, for better timing
598 
      usHA_is_64b              : OUT std_logic;
599 
      usBDA_is_64b             : OUT std_logic;
600 
 
601 
      -- Calculation in advance, for better timing
602 
      usLeng_Hi19b_True        : OUT std_logic;
603 
      usLeng_Lo7b_True         : OUT std_logic;
604 
 
605 
 
606 
      usDMA_Start              : OUT std_logic;
607 
      usDMA_Stop               : OUT std_logic;
608 
      usDMA_Start2             : OUT std_logic;
609 
      usDMA_Stop2              : OUT std_logic;
610 
      usDMA_Channel_Rst        : OUT std_logic;
611 
      usDMA_Cmd_Ack            : IN  std_logic;
612 
 
613 
      -- Reset signals
614 
      MRd_Channel_Rst          : OUT std_logic;
615 
      Tx_Reset                 : OUT std_logic;
616 
 
617 
      -- to Interrupt module
618 
      Sys_IRQ                  : OUT std_logic_vector(C_DBUS_WIDTH-1 downto 0);
619 3 weng_ziti 
--      DAQ_irq                  : IN  std_logic;
620 
--      CTL_irq                  : IN  std_logic;
621 
--      DLM_irq                  : IN  std_logic;
622 2 weng_ziti 
 
623 
      -- System error and info
624 
      eb_FIFO_ow               : IN  std_logic;
625 
      Tx_TimeOut               : IN  std_logic;
626 
      Tx_eb_TimeOut            : IN  std_logic;
627 
      Msg_Routing              : OUT std_logic_vector(C_GCR_MSG_ROUT_BIT_TOP-C_GCR_MSG_ROUT_BIT_BOT downto 0);
628 
      pcie_link_width          : IN  std_logic_vector(CINT_BIT_LWIDTH_IN_GSR_TOP-CINT_BIT_LWIDTH_IN_GSR_BOT downto 0);
629 
      cfg_dcommand             : IN  std_logic_vector(16-1 downto 0);
630 
 
631 
      -- Interrupt Generation Signals
632 
      IG_Reset                 : OUT std_logic;
633 
      IG_Host_Clear            : OUT std_logic;
634 
      IG_Latency               : OUT std_logic_vector(C_DBUS_WIDTH-1   downto 0);
635 
      IG_Num_Assert            : IN  std_logic_vector(C_DBUS_WIDTH-1   downto 0);
636 
      IG_Num_Deassert          : IN  std_logic_vector(C_DBUS_WIDTH-1   downto 0);
637 
      IG_Asserting             : IN  std_logic;
638 
 
639 3 weng_ziti 
--      -- Data generator control
640 
--      DG_is_Running            : IN  std_logic;
641 
--      DG_Reset                 : OUT std_logic;
642 
--      DG_Mask                  : OUT std_logic;
643 2 weng_ziti 
 
644 
      -- Common interface
645 
      trn_clk                  : IN  std_logic;
646 
      trn_lnk_up_n             : IN  std_logic;
647 
      trn_reset_n              : IN  std_logic
648 
    );
649 
  end component Regs_Group;
650 
 
651 
 
652 
  -- DDR write port
653 
  signal  DDR_wr_sof_A         : std_logic;
654 
  signal  DDR_wr_eof_A         : std_logic;
655 
  signal  DDR_wr_v_A           : std_logic;
656 
  signal  DDR_wr_FA_A          : std_logic;
657 
  signal  DDR_wr_Shift_A       : std_logic;
658 
  signal  DDR_wr_Mask_A        : std_logic_vector(2-1 downto 0);
659 
  signal  DDR_wr_din_A         : std_logic_vector(C_DBUS_WIDTH-1 downto 0);
660 
 
661 
  signal  DDR_wr_sof_B         : std_logic;
662 
  signal  DDR_wr_eof_B         : std_logic;
663 
  signal  DDR_wr_v_B           : std_logic;
664 
  signal  DDR_wr_FA_B          : std_logic;
665 
  signal  DDR_wr_Shift_B       : std_logic;
666 
  signal  DDR_wr_Mask_B        : std_logic_vector(2-1 downto 0);
667 
  signal  DDR_wr_din_B         : std_logic_vector(C_DBUS_WIDTH-1 downto 0);
668 
 
669 
  signal  DDR_wr_sof_i         : std_logic;
670 
  signal  DDR_wr_eof_i         : std_logic;
671 
  signal  DDR_wr_v_i           : std_logic;
672 
  signal  DDR_wr_FA_i          : std_logic;
673 
  signal  DDR_wr_Shift_i       : std_logic;
674 
  signal  DDR_wr_Mask_i        : std_logic_vector(2-1 downto 0);
675 
  signal  DDR_wr_din_i         : std_logic_vector(C_DBUS_WIDTH-1 downto 0)
676 
                               := (OTHERS=>'0');
677 
 
678 
  signal  DDR_wr_sof_A_r1      : std_logic;
679 
  signal  DDR_wr_eof_A_r1      : std_logic;
680 
  signal  DDR_wr_v_A_r1        : std_logic;
681 
  signal  DDR_wr_FA_A_r1       : std_logic;
682 
  signal  DDR_wr_Shift_A_r1    : std_logic;
683 
  signal  DDR_wr_Mask_A_r1     : std_logic_vector(2-1 downto 0);
684 
  signal  DDR_wr_din_A_r1      : std_logic_vector(C_DBUS_WIDTH-1 downto 0);
685 
 
686 
  signal  DDR_wr_sof_A_r2      : std_logic;
687 
  signal  DDR_wr_eof_A_r2      : std_logic;
688 
  signal  DDR_wr_v_A_r2        : std_logic;
689 
  signal  DDR_wr_FA_A_r2       : std_logic;
690 
  signal  DDR_wr_Shift_A_r2    : std_logic;
691 
  signal  DDR_wr_Mask_A_r2     : std_logic_vector(2-1 downto 0);
692 
  signal  DDR_wr_din_A_r2      : std_logic_vector(C_DBUS_WIDTH-1 downto 0);
693 
 
694 
  signal  DDR_wr_sof_A_r3      : std_logic;
695 
  signal  DDR_wr_eof_A_r3      : std_logic;
696 
  signal  DDR_wr_v_A_r3        : std_logic;
697 
  signal  DDR_wr_FA_A_r3       : std_logic;
698 
  signal  DDR_wr_Shift_A_r3    : std_logic;
699 
  signal  DDR_wr_Mask_A_r3     : std_logic_vector(2-1 downto 0);
700 
  signal  DDR_wr_din_A_r3      : std_logic_vector(C_DBUS_WIDTH-1 downto 0);
701 
 
702 
  -- eb FIFO read enable
703 
  signal  eb_FIFO_RdEn_i       : std_logic;
704 
 
705 
  -- Flow control signals
706 
  signal  pio_FC_stop          : std_logic;
707 
  signal  us_FC_stop           : std_logic;
708 
  signal  us_Last_sof          : std_logic;
709 
  signal  us_Last_eof          : std_logic;
710 
 
711 
 
712 
  -- Signals between Tx_Transact and Rx_Transact
713 
  signal  pioCplD_Req          : std_logic;
714 
  signal  pioCplD_RE           : std_logic;
715 
  signal  pioCplD_Qout         : std_logic_vector(C_CHANNEL_BUF_WIDTH-1 downto 0);
716 
 
717 
  -- MRd-downstream packet Channel
718 
  signal  dsMRd_Req            : std_logic;
719 
  signal  dsMRd_RE             : std_logic;
720 
  signal  dsMRd_Qout           : std_logic_vector(C_CHANNEL_BUF_WIDTH-1 downto 0);
721 
 
722 
  -- Upstream MWr Channel
723 
  signal  usTlp_Req            : std_logic;
724 
  signal  usTlp_RE             : std_logic;
725 
  signal  usTlp_Qout           : std_logic_vector(C_CHANNEL_BUF_WIDTH-1 downto 0);
726 
 
727 
  -- Irpt Channel
728 
  signal  Irpt_Req             : std_logic;
729 
  signal  Irpt_RE              : std_logic;
730 
  signal  Irpt_Qout            : std_logic_vector(C_CHANNEL_BUF_WIDTH-1 downto 0);
731 
 
732 
 
733 
  -- Registers Write Port
734 
  signal  Regs_WrEnA           : std_logic;
735 
  signal  Regs_WrMaskA         : std_logic_vector(2-1 downto 0);
736 
  signal  Regs_WrAddrA         : std_logic_vector(C_EP_AWIDTH-1 downto 0);
737 
  signal  Regs_WrDinA          : std_logic_vector(C_DBUS_WIDTH-1 downto 0);
738 
 
739 
  signal  Regs_WrEnB           : std_logic;
740 
  signal  Regs_WrMaskB         : std_logic_vector(2-1 downto 0);
741 
  signal  Regs_WrAddrB         : std_logic_vector(C_EP_AWIDTH-1 downto 0);
742 
  signal  Regs_WrDinB          : std_logic_vector(C_DBUS_WIDTH-1 downto 0);
743 
 
744 
 
745 
  -- Dex parameters to downstream DMA
746 
  signal  DMA_ds_PA            : std_logic_vector(C_DBUS_WIDTH-1 downto 0);
747 
  signal  DMA_ds_HA            : std_logic_vector(C_DBUS_WIDTH-1 downto 0);
748 
  signal  DMA_ds_BDA           : std_logic_vector(C_DBUS_WIDTH-1 downto 0);
749 
  signal  DMA_ds_Length        : std_logic_vector(C_DBUS_WIDTH-1 downto 0);
750 
  signal  DMA_ds_Control       : std_logic_vector(C_DBUS_WIDTH-1 downto 0);
751 
  signal  dsDMA_BDA_eq_Null    : std_logic;
752 
  signal  DMA_ds_Status        : std_logic_vector(C_DBUS_WIDTH-1 downto 0);
753 
  signal  DMA_ds_Done_i        : std_logic;
754 
  signal  DMA_ds_Busy_i        : std_logic;
755 
  signal  DMA_ds_Busy_led_i    : std_logic;
756 
  signal  cnt_ds_Busy          : std_logic_vector(20-1   downto 0);
757 
  signal  DMA_ds_Tout          : std_logic;
758 
 
759 
  -- Calculation in advance, for better timing
760 
  signal  dsHA_is_64b          : std_logic;
761 
  signal  dsBDA_is_64b         : std_logic;
762 
  -- Calculation in advance, for better timing
763 
  signal  dsLeng_Hi19b_True    : std_logic;
764 
  signal  dsLeng_Lo7b_True     : std_logic;
765 
 
766 
  -- Downstream Control Signals
767 
  signal  dsDMA_Start          : std_logic;
768 
  signal  dsDMA_Stop           : std_logic;
769 
  signal  dsDMA_Start2         : std_logic;
770 
  signal  dsDMA_Stop2          : std_logic;
771 
  signal  dsDMA_Cmd_Ack        : std_logic;
772 
  signal  dsDMA_Channel_Rst    : std_logic;
773 
 
774 
  -- Dex parameters to upstream DMA
775 
  signal  DMA_us_PA            : std_logic_vector(C_DBUS_WIDTH-1 downto 0);
776 
  signal  DMA_us_HA            : std_logic_vector(C_DBUS_WIDTH-1 downto 0);
777 
  signal  DMA_us_BDA           : std_logic_vector(C_DBUS_WIDTH-1 downto 0);
778 
  signal  DMA_us_Length        : std_logic_vector(C_DBUS_WIDTH-1 downto 0);
779 
  signal  DMA_us_Control       : std_logic_vector(C_DBUS_WIDTH-1 downto 0);
780 
  signal  usDMA_BDA_eq_Null    : std_logic;
781 
  signal  us_MWr_Param_Vec     : std_logic_vector(6-1   downto 0);
782 
  signal  DMA_us_Status        : std_logic_vector(C_DBUS_WIDTH-1 downto 0);
783 
  signal  DMA_us_Done_i        : std_logic;
784 
  signal  DMA_us_Busy_i        : std_logic;
785 
  signal  DMA_us_Busy_led_i    : std_logic;
786 
  signal  cnt_us_Busy          : std_logic_vector(20-1   downto 0);
787 
  signal  DMA_us_Tout          : std_logic;
788 
 
789 
  -- Calculation in advance, for better timing
790 
  signal  usHA_is_64b          : std_logic;
791 
  signal  usBDA_is_64b         : std_logic;
792 
  -- Calculation in advance, for better timing
793 
  signal  usLeng_Hi19b_True    : std_logic;
794 
  signal  usLeng_Lo7b_True     : std_logic;
795 
 
796 
  -- Upstream Control Signals
797 
  signal  usDMA_Start          : std_logic;
798 
  signal  usDMA_Stop           : std_logic;
799 
  signal  usDMA_Start2         : std_logic;
800 
  signal  usDMA_Stop2          : std_logic;
801 
  signal  usDMA_Cmd_Ack        : std_logic;
802 
  signal  usDMA_Channel_Rst    : std_logic;
803 
 
804 
 
805 
  --      MRd Channel Reset
806 
  signal  MRd_Channel_Rst      : std_logic;
807 
 
808 
  --      Tx module Reset
809 
  signal  Tx_Reset             : std_logic;
810 
 
811 
  --      Tx time out
812 
  signal  Tx_TimeOut           : std_logic;
813 
  signal  Tx_eb_TimeOut        : std_logic;
814 
 
815 
  -- Registers read port
816 
  signal  Regs_RdAddr          : std_logic_vector(C_EP_AWIDTH-1 downto 0);
817 
  signal  Regs_RdQout          : std_logic_vector(C_DBUS_WIDTH-1 downto 0);
818 
 
819 
  -- Register to Interrupt module
820 
  signal  Sys_IRQ              : std_logic_vector(C_DBUS_WIDTH-1 downto 0);
821 
 
822 
  -- Message routing method
823 
  signal  Msg_Routing          : std_logic_vector(C_GCR_MSG_ROUT_BIT_TOP-C_GCR_MSG_ROUT_BIT_BOT downto 0);
824 
 
825 
  -- Interrupt Generation Signals
826 
  signal  IG_Reset             : std_logic;
827 
  signal  IG_Host_Clear        : std_logic;
828 
  signal  IG_Latency           : std_logic_vector(C_DBUS_WIDTH-1   downto 0);
829 
  signal  IG_Num_Assert        : std_logic_vector(C_DBUS_WIDTH-1   downto 0);
830 
  signal  IG_Num_Deassert      : std_logic_vector(C_DBUS_WIDTH-1   downto 0);
831 
  signal  IG_Asserting         : std_logic;
832 
 
833 
  -- Test blinker
834 
  signal  trn_Blinker_cnt      : std_logic_vector(31 downto 0) := (OTHERS=>'0');
835 
 
836 
begin
837 
 
838 
 
839 
   DDR_wr_v            <=  DDR_wr_v_i      ;
840 
   DDR_wr_sof          <=  DDR_wr_sof_i    ;
841 
   DDR_wr_eof          <=  DDR_wr_eof_i    ;
842 
   DDR_wr_FA           <=  DDR_wr_FA_i     ;
843 
   DDR_wr_Shift        <=  DDR_wr_Shift_i  ;
844 
   DDR_wr_Mask         <=  DDR_wr_Mask_i   ;
845 
   DDR_wr_din          <=  DDR_wr_din_i    ;
846 
 
847 
   trn_Blinker         <=  trn_Blinker_cnt(26)   ;
848 
   DMA_ds_Start        <=  dsDMA_Start     ;
849 
 
850 
   DMA_us_Busy         <=  DMA_us_Busy_i   ;
851 
   DMA_us_Busy_LED     <=  DMA_us_Busy_led_i   ;
852 
   DMA_ds_Busy         <=  DMA_ds_Busy_i   ;
853 
   DMA_ds_Busy_LED     <=  DMA_ds_Busy_led_i   ;
854 
 
855 
   eb_FIFO_re          <=  eb_FIFO_RdEn_i  ;
856 
 
857 
   DMA_ds_Done         <=  DMA_ds_Done_i   ;
858 
   DMA_us_Done         <=  DMA_us_Done_i   ;
859 
 
860 
   trn_lnk_up_i        <=  not trn_lnk_up_n;
861 
 
862 
   -- -------------------------------------------------------
863 
   -- Delay DDR write port A for 2 cycles
864 
   --
865 
   SynDelay_DDR_write_PIO:
866 
   process ( trn_clk )
867 
   begin
868 
      if trn_clk'event and trn_clk = '1' then
869 
        DDR_wr_v_A_r1     <=  DDR_wr_v_A;
870 
        DDR_wr_sof_A_r1   <=  DDR_wr_sof_A;
871 
        DDR_wr_eof_A_r1   <=  DDR_wr_eof_A;
872 
        DDR_wr_FA_A_r1    <=  DDR_wr_FA_A;
873 
        DDR_wr_Shift_A_r1 <=  DDR_wr_Shift_A;
874 
        DDR_wr_Mask_A_r1  <=  DDR_wr_Mask_A;
875 
        DDR_wr_din_A_r1   <=  DDR_wr_din_A;
876 
 
877 
        DDR_wr_v_A_r2     <=  DDR_wr_v_A_r1;
878 
        DDR_wr_sof_A_r2   <=  DDR_wr_sof_A_r1;
879 
        DDR_wr_eof_A_r2   <=  DDR_wr_eof_A_r1;
880 
        DDR_wr_FA_A_r2    <=  DDR_wr_FA_A_r1;
881 
        DDR_wr_Shift_A_r2 <=  DDR_wr_Shift_A_r1;
882 
        DDR_wr_Mask_A_r2  <=  DDR_wr_Mask_A_r1;
883 
        DDR_wr_din_A_r2   <=  DDR_wr_din_A_r1;
884 
 
885 
        DDR_wr_v_A_r3     <=  DDR_wr_v_A_r2;
886 
        DDR_wr_sof_A_r3   <=  DDR_wr_sof_A_r2;
887 
        DDR_wr_eof_A_r3   <=  DDR_wr_eof_A_r2;
888 
        DDR_wr_FA_A_r3    <=  DDR_wr_FA_A_r2;
889 
        DDR_wr_Shift_A_r3 <=  DDR_wr_Shift_A_r2;
890 
        DDR_wr_Mask_A_r3  <=  DDR_wr_Mask_A_r2;
891 
        DDR_wr_din_A_r3   <=  DDR_wr_din_A_r2;
892 
      end if;
893 
   end process;
894 
 
895 
 
896 
   -- -------------------------------------------------------
897 
   -- DDR writes: DDR Writes
898 
   --
899 
   SynProc_DDR_write:
900 
   process ( trn_clk )
901 
   begin
902 
      if trn_clk'event and trn_clk = '1' then
903 
        DDR_wr_v_i     <=  DDR_wr_v_A_r3 or DDR_wr_v_B;
904 
        if DDR_wr_v_A_r3 = '1' then
905 
          DDR_wr_sof_i   <=  DDR_wr_sof_A_r3;
906 
          DDR_wr_eof_i   <=  DDR_wr_eof_A_r3;
907 
          DDR_wr_FA_i    <=  DDR_wr_FA_A_r3;
908 
          DDR_wr_Shift_i <=  DDR_wr_Shift_A_r3;
909 
          DDR_wr_Mask_i  <=  DDR_wr_Mask_A_r3;
910 
          DDR_wr_din_i   <=  DDR_wr_din_A_r3;
911 
        elsif DDR_wr_v_B = '1' then
912 
          DDR_wr_sof_i   <=  DDR_wr_sof_B;
913 
          DDR_wr_eof_i   <=  DDR_wr_eof_B;
914 
          DDR_wr_FA_i    <=  DDR_wr_FA_B ;
915 
          DDR_wr_Shift_i <=  DDR_wr_Shift_B ;
916 
          DDR_wr_Mask_i  <=  DDR_wr_Mask_B;
917 
          DDR_wr_din_i   <=  DDR_wr_din_B;
918 
        else
919 
          DDR_wr_sof_i   <=  DDR_wr_sof_i;
920 
          DDR_wr_eof_i   <=  DDR_wr_eof_i;
921 
          DDR_wr_FA_i    <=  DDR_wr_FA_i ;
922 
          DDR_wr_Shift_i <=  DDR_wr_Shift_i ;
923 
          DDR_wr_Mask_i  <=  DDR_wr_Mask_i;
924 
          DDR_wr_din_i   <=  DDR_wr_din_i;
925 
        end if;
926 
      end if;
927 
   end process;
928 
 
929 
   -- -------------------------------------------------------
930 
   -- trn blink
931 
   --
932 
   SynProc_trn_blinker:
933 
   process ( trn_clk )
934 
   begin
935 
      if trn_clk'event and trn_clk = '1' then
936 
        trn_Blinker_cnt     <=  trn_Blinker_cnt + '1';
937 
      end if;
938 
   end process;
939 
 
940 
   -- -------------------------------------------------------
941 
   -- DMA upstream Busy display
942 
   --
943 
   SynProc_DMA_us_Busy_LED:
944 
   process ( trn_clk, DMA_us_Busy_i)
945 
   begin
946 
      if DMA_us_Busy_i='1' then
947 
        DMA_us_Busy_led_i <=  '1';
948 
        cnt_us_Busy       <=  (OTHERS=>'0');
949 
      elsif trn_clk'event and trn_clk = '1' then
950 
        if cnt_us_Busy=X"80000" then
951 
          DMA_us_Busy_led_i <=  '0';
952 
          cnt_us_Busy       <=  cnt_us_Busy;
953 
        else
954 
          DMA_us_Busy_led_i <=  DMA_us_Busy_led_i;
955 
          cnt_us_Busy       <=  cnt_us_Busy + '1';
956 
        end if;
957 
      end if;
958 
   end process;
959 
 
960 
   -- -------------------------------------------------------
961 
   -- DMA downstream Busy display
962 
   --
963 
   SynProc_DMA_ds_Busy_LED:
964 
   process ( trn_clk, DMA_ds_Busy_i)
965 
   begin
966 
      if DMA_ds_Busy_i='1' then
967 
        DMA_ds_Busy_led_i <=  '1';
968 
        cnt_ds_Busy       <=  (OTHERS=>'0');
969 
      elsif trn_clk'event and trn_clk = '1' then
970 
        if cnt_ds_Busy=X"FFFFF" then
971 
          DMA_ds_Busy_led_i <=  '0';
972 
          cnt_ds_Busy       <=  cnt_ds_Busy;
973 
        else
974 
          DMA_ds_Busy_led_i <=  DMA_ds_Busy_led_i;
975 
          cnt_ds_Busy       <=  cnt_ds_Busy + '1';
976 
        end if;
977 
      end if;
978 
   end process;
979 
 
980 
--    DDR_wr_v     <=  DDR_wr_v_A or DDR_wr_v_B;
981 
--    DDR_wr_sof   <=  DDR_wr_sof_A  when DDR_wr_v_A='1'  else  DDR_wr_sof_B;
982 
--    DDR_wr_eof   <=  DDR_wr_eof_A  when DDR_wr_v_A='1'  else  DDR_wr_eof_B;
983 
--    DDR_wr_FA    <=  DDR_wr_FA_A   when DDR_wr_v_A='1'  else  DDR_wr_FA_B;
984 
--    DDR_wr_din   <=  DDR_wr_din_A  when DDR_wr_v_A='1'  else  DDR_wr_din_B;
985 
 
986 
 
987 
    -- Rx TLP interface
988 
    rx_Itf:
989 
    rx_Transact
990 
    port map(
991 
      -- Common ports
992 
      trn_clk            => trn_clk,             -- IN  std_logic,
993 
      trn_reset_n        => trn_lnk_up_i     , -- trn_reset_n,         -- IN  std_logic,
994 
      trn_lnk_up_n       => trn_lnk_up_n,        -- IN  std_logic,
995 
 
996 
      -- Transaction receive interface
997 
      trn_rsof_n         => trn_rsof_n,          -- IN  std_logic,
998 
      trn_reof_n         => trn_reof_n,          -- IN  std_logic,
999 
      trn_rd             => trn_rd,              -- IN  std_logic_vector(31 downto 0),
1000 
      trn_rrem_n         => trn_rrem_n,          -- IN  STD_LOGIC_VECTOR (  7 downto 0 );
1001 
      trn_rerrfwd_n      => trn_rerrfwd_n,       -- IN  std_logic,
1002 
      trn_rsrc_rdy_n     => trn_rsrc_rdy_n,      -- IN  std_logic,
1003 
      trn_rdst_rdy_n     => trn_rdst_rdy_n,      -- OUT std_logic,
1004 
      trn_rnp_ok_n       => trn_rnp_ok_n,        -- OUT std_logic,
1005 
      trn_rsrc_dsc_n     => trn_rsrc_dsc_n,      -- IN std_logic,
1006 
      trn_rbar_hit_n     => trn_rbar_hit_n,      -- IN  std_logic_vector(6 downto 0),
1007 
--    trn_rfc_ph_av        => trn_rfc_ph_av,       -- IN  std_logic_vector(7 downto 0),
1008 
--    trn_rfc_pd_av        => trn_rfc_pd_av,       -- IN  std_logic_vector(11 downto 0),
1009 
--    trn_rfc_nph_av       => trn_rfc_nph_av,      -- IN  std_logic_vector(7 downto 0),
1010 
--    trn_rfc_npd_av       => trn_rfc_npd_av,      -- IN  std_logic_vector(11 downto 0),
1011 
--    trn_rfc_cplh_av      => trn_rfc_cplh_av,     -- IN  std_logic_vector(7 downto 0),
1012 
--    trn_rfc_cpld_av      => trn_rfc_cpld_av,     -- IN  std_logic_vector(11 downto 0),
1013 
 
1014 
 
1015 
      -- MRd Channel
1016 
      pioCplD_Req        => pioCplD_Req,         -- OUT std_logic;
1017 
      pioCplD_RE         => pioCplD_RE,          -- IN  std_logic;
1018 
      pioCplD_Qout       => pioCplD_Qout,        -- OUT std_logic_vector(96 downto 0);
1019 
      pio_FC_stop        => pio_FC_stop,         -- IN  std_logic;
1020 
 
1021 
      -- downstream MRd Channel
1022 
      dsMRd_Req          => dsMRd_Req,           -- OUT std_logic;
1023 
      dsMRd_RE           => dsMRd_RE,            -- IN  std_logic;
1024 
      dsMRd_Qout         => dsMRd_Qout,          -- OUT std_logic_vector(96 downto 0);
1025 
 
1026 
      -- Upstream MWr/MRd Channel
1027 
      usTlp_Req          => usTlp_Req,           -- OUT std_logic;
1028 
      usTlp_RE           => usTlp_RE,            -- IN  std_logic;
1029 
      usTlp_Qout         => usTlp_Qout,          -- OUT std_logic_vector(96 downto 0);
1030 
      us_FC_stop         => us_FC_stop,          -- IN  std_logic;
1031 
      us_Last_sof        => us_Last_sof,         -- IN  std_logic;
1032 
      us_Last_eof        => us_Last_eof,         -- IN  std_logic;
1033 
 
1034 
      -- Irpt Channel
1035 
      Irpt_Req           => Irpt_Req,            -- OUT std_logic;
1036 
      Irpt_RE            => Irpt_RE,             -- IN  std_logic;
1037 
      Irpt_Qout          => Irpt_Qout,           -- OUT std_logic_vector(96 downto 0);
1038 
 
1039 
 
1040 
      -- Interrupt Interface
1041 
                cfg_interrupt_n         => cfg_interrupt_n         ,  -- OUT std_logic;
1042 
                cfg_interrupt_rdy_n     => cfg_interrupt_rdy_n     ,  -- IN std_logic;
1043 
                cfg_interrupt_mmenable  => cfg_interrupt_mmenable  ,  -- IN std_logic_VECTOR(2 downto 0);
1044 
                cfg_interrupt_msienable => cfg_interrupt_msienable ,  -- IN std_logic;
1045 
                cfg_interrupt_di        => cfg_interrupt_di        ,  -- OUT std_logic_VECTOR(7 downto 0);
1046 
                cfg_interrupt_do        => cfg_interrupt_do        ,  -- IN std_logic_VECTOR(7 downto 0);
1047 
                cfg_interrupt_assert_n  => cfg_interrupt_assert_n  ,  -- OUT std_logic;
1048 
 
1049 
 
1050 
      -- Event Buffer write port
1051 
      eb_FIFO_we          =>  eb_FIFO_we    ,       -- OUT std_logic;
1052 
      eb_FIFO_wsof        =>  eb_FIFO_wsof  ,       -- OUT std_logic;
1053 
      eb_FIFO_weof        =>  eb_FIFO_weof  ,       -- OUT std_logic;
1054 
      eb_FIFO_din         =>  eb_FIFO_din   ,       -- OUT std_logic_vector(C_DBUS_WIDTH-1 downto 0);
1055 
 
1056 
      eb_FIFO_data_count  =>  eb_FIFO_data_count,   -- IN  std_logic_vector(C_FIFO_DC_WIDTH downto 0);
1057 
      eb_FIFO_Empty       =>  eb_FIFO_Empty     ,   -- IN  std_logic;
1058 
      eb_FIFO_Reading     =>  eb_FIFO_RdEn_i    ,   -- IN  std_logic;
1059 
      pio_reading_status  =>  pio_reading_status    ,   -- OUT std_logic;
1060 
 
1061 
      -- Register Write
1062 
      Regs_WrEn0          =>  Regs_WrEnA    ,       -- OUT std_logic;
1063 
      Regs_WrMask0        =>  Regs_WrMaskA  ,       -- OUT std_logic_vector(2-1   downto 0);
1064 
      Regs_WrAddr0        =>  Regs_WrAddrA  ,       -- OUT std_logic_vector(16-1   downto 0);
1065 
      Regs_WrDin0         =>  Regs_WrDinA   ,       -- OUT std_logic_vector(32-1   downto 0);
1066 
 
1067 
      Regs_WrEn1          =>  Regs_WrEnB    ,       -- OUT std_logic;
1068 
      Regs_WrMask1        =>  Regs_WrMaskB  ,       -- OUT std_logic_vector(2-1   downto 0);
1069 
      Regs_WrAddr1        =>  Regs_WrAddrB  ,       -- OUT std_logic_vector(16-1   downto 0);
1070 
      Regs_WrDin1         =>  Regs_WrDinB   ,       -- OUT std_logic_vector(32-1   downto 0);
1071 
 
1072 
      -- Downstream DMA transferred bytes count up
1073 
      ds_DMA_Bytes_Add    =>  ds_DMA_Bytes_Add     ,  -- OUT std_logic;
1074 
      ds_DMA_Bytes        =>  ds_DMA_Bytes         ,  -- OUT std_logic_vector(C_TLP_FLD_WIDTH_OF_LENG+2 downto 0);
1075 
 
1076 
      -- Registers
1077 
                DMA_ds_PA           =>  DMA_ds_PA            ,  -- IN  std_logic_vector(63 downto 0);
1078 
                DMA_ds_HA           =>  DMA_ds_HA            ,  -- IN  std_logic_vector(63 downto 0);
1079 
                DMA_ds_BDA          =>  DMA_ds_BDA           ,  -- IN  std_logic_vector(63 downto 0);
1080 
                DMA_ds_Length       =>  DMA_ds_Length        ,  -- IN  std_logic_vector(31 downto 0);
1081 
                DMA_ds_Control      =>  DMA_ds_Control       ,  -- IN  std_logic_vector(31 downto 0);
1082 
      dsDMA_BDA_eq_Null   =>  dsDMA_BDA_eq_Null    ,  -- IN  std_logic;
1083 
                DMA_ds_Status       =>  DMA_ds_Status        ,  -- OUT std_logic_vector(31 downto 0);
1084 
      DMA_ds_Done         =>  DMA_ds_Done_i        ,  -- OUT std_logic;
1085 
      DMA_ds_Busy         =>  DMA_ds_Busy_i        ,  -- OUT std_logic;
1086 
      DMA_ds_Tout         =>  DMA_ds_Tout          ,  -- OUT std_logic;
1087 
 
1088 
      dsHA_is_64b         =>  dsHA_is_64b          ,  -- IN  std_logic;
1089 
      dsBDA_is_64b        =>  dsBDA_is_64b         ,  -- IN  std_logic;
1090 
 
1091 
      dsLeng_Hi19b_True   =>  dsLeng_Hi19b_True    ,  -- IN  std_logic;
1092 
      dsLeng_Lo7b_True    =>  dsLeng_Lo7b_True     ,  -- IN  std_logic;
1093 
 
1094 
                dsDMA_Start         =>  dsDMA_Start          ,  -- IN  std_logic;
1095 
                dsDMA_Stop          =>  dsDMA_Stop           ,  -- IN  std_logic;
1096 
                dsDMA_Start2        =>  dsDMA_Start2         ,  -- IN  std_logic;
1097 
                dsDMA_Stop2         =>  dsDMA_Stop2          ,  -- IN  std_logic;
1098 
                dsDMA_Channel_Rst   =>  dsDMA_Channel_Rst    ,  -- IN  std_logic;
1099 
      dsDMA_Cmd_Ack       =>  dsDMA_Cmd_Ack        ,  -- OUT std_logic;
1100 
 
1101 
                DMA_us_PA           =>  DMA_us_PA            ,  -- IN  std_logic_vector(63 downto 0);
1102 
                DMA_us_HA           =>  DMA_us_HA            ,  -- IN  std_logic_vector(63 downto 0);
1103 
                DMA_us_BDA          =>  DMA_us_BDA           ,  -- IN  std_logic_vector(63 downto 0);
1104 
                DMA_us_Length       =>  DMA_us_Length        ,  -- IN  std_logic_vector(31 downto 0);
1105 
                DMA_us_Control      =>  DMA_us_Control       ,  -- IN  std_logic_vector(31 downto 0);
1106 
      usDMA_BDA_eq_Null   =>  usDMA_BDA_eq_Null    ,  -- IN  std_logic;
1107 
      us_MWr_Param_Vec    =>  us_MWr_Param_Vec     ,  -- IN  std_logic_vector(6-1   downto 0);
1108 
                DMA_us_Status       =>  DMA_us_Status        ,  -- OUT std_logic_vector(31 downto 0);
1109 
      DMA_us_Done         =>  DMA_us_Done_i        ,  -- OUT std_logic;
1110 
      DMA_us_Busy         =>  DMA_us_Busy_i        ,  -- OUT std_logic;
1111 
      DMA_us_Tout         =>  DMA_us_Tout          ,  -- OUT std_logic;
1112 
 
1113 
      usHA_is_64b         =>  usHA_is_64b          ,  -- IN  std_logic;
1114 
      usBDA_is_64b        =>  usBDA_is_64b         ,  -- IN  std_logic;
1115 
 
1116 
      usLeng_Hi19b_True   =>  usLeng_Hi19b_True    ,  -- IN  std_logic;
1117 
      usLeng_Lo7b_True    =>  usLeng_Lo7b_True     ,  -- IN  std_logic;
1118 
 
1119 
 
1120 
                usDMA_Start         =>  usDMA_Start          ,  -- IN  std_logic;
1121 
                usDMA_Stop          =>  usDMA_Stop           ,  -- IN  std_logic;
1122 
                usDMA_Start2        =>  usDMA_Start2         ,  -- IN  std_logic;
1123 
                usDMA_Stop2         =>  usDMA_Stop2          ,  -- IN  std_logic;
1124 
                usDMA_Channel_Rst   =>  usDMA_Channel_Rst    ,  -- IN  std_logic;
1125 
      usDMA_Cmd_Ack       =>  usDMA_Cmd_Ack        ,  -- OUT std_logic;
1126 
 
1127 
 
1128 
      -- Reset signals
1129 
                MRd_Channel_Rst     =>  MRd_Channel_Rst      ,  -- IN  std_logic;
1130 
 
1131 
      -- to Interrupt module
1132 
      Sys_IRQ             =>  Sys_IRQ              ,  -- IN  std_logic_vector(31 downto 0);
1133 
 
1134 
      IG_Reset            =>  IG_Reset             ,
1135 
      IG_Host_Clear       =>  IG_Host_Clear        ,
1136 
      IG_Latency          =>  IG_Latency           ,
1137 
      IG_Num_Assert       =>  IG_Num_Assert        ,
1138 
      IG_Num_Deassert     =>  IG_Num_Deassert      ,
1139 
      IG_Asserting        =>  IG_Asserting         ,
1140 
 
1141 
 
1142 
      -- DDR write port
1143 
      DDR_wr_sof_A        =>  DDR_wr_sof_A    , -- OUT   std_logic;
1144 
      DDR_wr_eof_A        =>  DDR_wr_eof_A    , -- OUT   std_logic;
1145 
      DDR_wr_v_A          =>  DDR_wr_v_A      , -- OUT   std_logic;
1146 
      DDR_wr_FA_A         =>  DDR_wr_FA_A     , -- OUT   std_logic;
1147 
      DDR_wr_Shift_A      =>  DDR_wr_Shift_A  , -- OUT   std_logic;
1148 
      DDR_wr_Mask_A       =>  DDR_wr_Mask_A   , -- OUT   std_logic_vector(2-1 downto 0);
1149 
      DDR_wr_din_A        =>  DDR_wr_din_A    , -- OUT   std_logic_vector(C_DBUS_WIDTH-1 downto 0);
1150 
 
1151 
      DDR_wr_sof_B        =>  DDR_wr_sof_B    , -- OUT   std_logic;
1152 
      DDR_wr_eof_B        =>  DDR_wr_eof_B    , -- OUT   std_logic;
1153 
      DDR_wr_v_B          =>  DDR_wr_v_B      , -- OUT   std_logic;
1154 
      DDR_wr_FA_B         =>  DDR_wr_FA_B     , -- OUT   std_logic;
1155 
      DDR_wr_Shift_B      =>  DDR_wr_Shift_B  , -- OUT   std_logic;
1156 
      DDR_wr_Mask_B       =>  DDR_wr_Mask_B   , -- OUT   std_logic_vector(2-1 downto 0);
1157 
      DDR_wr_din_B        =>  DDR_wr_din_B    , -- OUT   std_logic_vector(C_DBUS_WIDTH-1 downto 0);
1158 
 
1159 
      DDR_wr_full         =>  DDR_wr_full     , -- IN    std_logic;
1160 
 
1161 
 
1162 
      Link_Buf_full       =>  Link_Buf_full   , -- IN    std_logic;
1163 
 
1164 
 
1165 3 weng_ziti 
--      -- Data generator table write
1166 
--      tab_we              =>  tab_we          , -- OUT std_logic_vector(2-1 downto 0);
1167 
--      tab_wa              =>  tab_wa          , -- OUT std_logic_vector(12-1 downto 0);
1168 
--      tab_wd              =>  tab_wd          , -- OUT std_logic_vector(C_DBUS_WIDTH-1 downto 0);
1169 2 weng_ziti 
 
1170 
      -- Additional
1171 
      cfg_dcommand        =>  cfg_dcommand         ,  -- IN  std_logic_vector(15 downto 0)
1172 
      localID             =>  localID                 -- IN  std_logic_vector(15 downto 0)
1173 
    );
1174 
 
1175 
 
1176 
 
1177 
    -- Tx TLP interface
1178 
    tx_Itf:
1179 
    tx_Transact
1180 
    port map(
1181 
      -- Common ports
1182 
      trn_clk             => trn_clk,             -- IN  std_logic,
1183 
      trn_reset_n         => trn_lnk_up_i     , -- trn_reset_n,         -- IN  std_logic,
1184 
      trn_lnk_up_n        => trn_lnk_up_n,        -- IN  std_logic,
1185 
 
1186 
      -- Transaction
1187 
      trn_tsof_n          => trn_tsof_n,          -- OUT std_logic,
1188 
      trn_teof_n          => trn_teof_n,          -- OUT std_logic,
1189 
      trn_td              => trn_td,              -- OUT std_logic_vector(31 downto 0),
1190 
      trn_trem_n          => trn_trem_n,          -- OUT STD_LOGIC_VECTOR (  7 downto 0 );
1191 
      trn_terrfwd_n       => trn_terrfwd_n,       -- OUT std_logic,
1192 
      trn_tsrc_rdy_n      => trn_tsrc_rdy_n,      -- OUT std_logic,
1193 
      trn_tdst_rdy_n      => trn_tdst_rdy_n,      -- IN  std_logic,
1194 
      trn_tsrc_dsc_n      => trn_tsrc_dsc_n,      -- OUT std_logic,
1195 
      trn_tdst_dsc_n      => trn_tdst_dsc_n,      -- IN  std_logic,
1196 
      trn_tbuf_av         => trn_tbuf_av,         -- IN  std_logic_vector(6 downto 0),
1197 
 
1198 
      -- Upstream DMA transferred bytes count up
1199 
      us_DMA_Bytes_Add    => us_DMA_Bytes_Add,    -- OUT std_logic;
1200 
      us_DMA_Bytes        => us_DMA_Bytes,        -- OUT std_logic_vector(C_TLP_FLD_WIDTH_OF_LENG+2 downto 0);
1201 
 
1202 
      -- MRd Channel
1203 
      pioCplD_Req         => pioCplD_Req,         -- IN  std_logic;
1204 
      pioCplD_RE          => pioCplD_RE,          -- OUT std_logic;
1205 
      pioCplD_Qout        => pioCplD_Qout,        -- IN  std_logic_vector(96 downto 0);
1206 
      pio_FC_stop         => pio_FC_stop,         -- OUT std_logic;
1207 
 
1208 
      -- downstream MRd Channel
1209 
      dsMRd_Req           => dsMRd_Req,           -- IN  std_logic;
1210 
      dsMRd_RE            => dsMRd_RE,            -- OUT std_logic;
1211 
      dsMRd_Qout          => dsMRd_Qout,          -- IN  std_logic_vector(96 downto 0);
1212 
 
1213 
      -- Upstream MWr/MRd Channel
1214 
      usTlp_Req           => usTlp_Req,           -- IN  std_logic;
1215 
      usTlp_RE            => usTlp_RE,            -- OUT std_logic;
1216 
      usTlp_Qout          => usTlp_Qout,          -- IN  std_logic_vector(96 downto 0);
1217 
      us_FC_stop          => us_FC_stop,          -- OUT std_logic;
1218 
      us_Last_sof         => us_Last_sof,         -- OUT std_logic;
1219 
      us_Last_eof         => us_Last_eof,         -- OUT std_logic;
1220 
 
1221 
      -- Irpt Channel
1222 
      Irpt_Req            => Irpt_Req,            -- IN  std_logic;
1223 
      Irpt_RE             => Irpt_RE,             -- OUT std_logic;
1224 
      Irpt_Qout           => Irpt_Qout,           -- IN  std_logic_vector(96 downto 0);
1225 
 
1226 
 
1227 
      -- Event Buffer FIFO read port
1228 
      eb_FIFO_re          => eb_FIFO_RdEn_i,      -- OUT std_logic;
1229 
      eb_FIFO_empty       => eb_FIFO_empty ,      -- IN  std_logic;
1230 
      eb_FIFO_qout        => eb_FIFO_qout  ,      -- IN  std_logic_vector(C_DBUS_WIDTH-1 downto 0);
1231 
 
1232 
      -- Registers read
1233 
      Regs_RdAddr         => Regs_RdAddr,         -- OUT std_logic_vector(15 downto 0);
1234 
      Regs_RdQout         => Regs_RdQout,         -- IN  std_logic_vector(31 downto 0);
1235 
 
1236 
      -- Message routing method
1237 
      Msg_Routing         => Msg_Routing,
1238 
 
1239 
      --  DDR read port
1240 
      DDR_rdc_sof         =>  DDR_rdc_sof       ,  -- OUT   std_logic;
1241 
      DDR_rdc_eof         =>  DDR_rdc_eof       ,  -- OUT   std_logic;
1242 
      DDR_rdc_v           =>  DDR_rdc_v         ,  -- OUT   std_logic;
1243 
      DDR_rdc_FA          =>  DDR_rdc_FA        ,  -- OUT   std_logic;
1244 
      DDR_rdc_Shift       =>  DDR_rdc_Shift     ,  -- OUT   std_logic;
1245 
      DDR_rdc_din         =>  DDR_rdc_din       ,  -- OUT   std_logic_vector(C_DBUS_WIDTH-1 downto 0);
1246 
      DDR_rdc_full        =>  DDR_rdc_full      ,  -- IN    std_logic;
1247 
 
1248 
      -- DDR payload FIFO Read Port
1249 
      DDR_FIFO_RdEn       =>  DDR_FIFO_RdEn     ,  -- OUT std_logic;
1250 
      DDR_FIFO_Empty      =>  DDR_FIFO_Empty    ,  -- IN  std_logic;
1251 
      DDR_FIFO_RdQout     =>  DDR_FIFO_RdQout   ,  -- IN  std_logic_vector(C_DBUS_WIDTH-1 downto 0);
1252 
--      DDR_rdD_sof         =>  DDR_rdD_sof       ,  -- IN    std_logic;
1253 
--      DDR_rdD_eof         =>  DDR_rdD_eof       ,  -- IN    std_logic;
1254 
--      DDR_rdDout_V        =>  DDR_rdDout_V      ,  -- IN    std_logic;
1255 
--      DDR_rdDout          =>  DDR_rdDout        ,  -- IN    std_logic_vector(C_DBUS_WIDTH-1 downto 0);
1256 
 
1257 
 
1258 
      -- Additional
1259 
      Tx_TimeOut          => Tx_TimeOut,          -- OUT std_logic;
1260 
      Tx_eb_TimeOut       => Tx_eb_TimeOut,       -- OUT std_logic;
1261 
      Format_Shower       => Format_Shower,       -- OUT std_logic;
1262 
      Tx_Reset            => Tx_Reset,            -- IN  std_logic;
1263 
      mbuf_UserFull       => mbuf_UserFull,       -- IN  std_logic;
1264 
      localID             => localID              -- IN  std_logic_vector(15 downto 0)
1265 
    );
1266 
 
1267 
 
1268 
 
1269 
  -- ------------------------------------------------
1270 
  --   Unified memory space
1271 
  -- ------------------------------------------------
1272 
   Memory_Space:
1273 
   Regs_Group
1274 
   PORT MAP(
1275 
 
1276 3 weng_ziti 
--      -- DCB protocol interface
1277 
--      protocol_link_act   =>  protocol_link_act    ,  -- IN  std_logic_vector(2-1 downto 0);
1278 
--      protocol_rst        =>  protocol_rst         ,  -- OUT std_logic;
1279 
--
1280 
--      -- Fabric side: CTL Rx
1281 
--      ctl_rv              =>  ctl_rv               ,  -- OUT std_logic;
1282 
--      ctl_rd              =>  ctl_rd               ,  -- OUT std_logic_vector(C_DBUS_WIDTH/2-1 downto 0);
1283 
--
1284 
--      -- Fabric side: CTL Tx
1285 
--      ctl_ttake           =>  ctl_ttake            ,  -- OUT std_logic;
1286 
--      ctl_tv              =>  ctl_tv               ,  -- IN  std_logic;
1287 
--      ctl_td              =>  ctl_td               ,  -- IN  std_logic_vector(C_DBUS_WIDTH/2-1 downto 0);
1288 
--      ctl_tstop           =>  ctl_tstop            ,  -- OUT std_logic;
1289 
--
1290 
--      ctl_reset           =>  ctl_reset            ,  -- OUT std_logic;
1291 
--      ctl_status          =>  ctl_status           ,  -- IN  std_logic_vector(C_DBUS_WIDTH/2-1 downto 0);
1292 
--
1293 
--      -- Fabric side: DLM Rx
1294 
--      dlm_tv              =>  dlm_tv               ,  -- OUT std_logic;
1295 
--      dlm_td              =>  dlm_td               ,  -- OUT std_logic_vector(C_DBUS_WIDTH/2-1 downto 0);
1296 
--
1297 
--      -- Fabric side: DLM Tx
1298 
--      dlm_rv              =>  dlm_rv               ,  -- IN  std_logic;
1299 
--      dlm_rd              =>  dlm_rd               ,  -- IN  std_logic_vector(C_DBUS_WIDTH/2-1 downto 0);
1300 2 weng_ziti 
 
1301 
      -- Event Buffer status + reset
1302 
      eb_FIFO_Status      =>  eb_FIFO_Status  ,      -- IN  std_logic_vector(C_DBUS_WIDTH-1 downto 0);
1303 
      eb_FIFO_Rst         =>  eb_FIFO_Rst     ,      -- OUT std_logic;
1304 
 
1305 
      self_feed_daq       =>  self_feed_daq   ,      -- OUT std_logic;
1306 
 
1307 
      -- Registers
1308 
      Regs_WrEnA          =>  Regs_WrEnA      ,      -- IN  std_logic;
1309 
      Regs_WrMaskA        =>  Regs_WrMaskA    ,      -- IN  std_logic_vector(2-1   downto 0);
1310 
      Regs_WrAddrA        =>  Regs_WrAddrA    ,      -- IN  std_logic_vector(16-1   downto 0);
1311 
      Regs_WrDinA         =>  Regs_WrDinA     ,      -- IN  std_logic_vector(32-1   downto 0);
1312 
 
1313 
      Regs_WrEnB          =>  Regs_WrEnB      ,      -- IN  std_logic;
1314 
      Regs_WrMaskB        =>  Regs_WrMaskB    ,      -- IN  std_logic_vector(2-1   downto 0);
1315 
      Regs_WrAddrB        =>  Regs_WrAddrB    ,      -- IN  std_logic_vector(16-1   downto 0);
1316 
      Regs_WrDinB         =>  Regs_WrDinB     ,      -- IN  std_logic_vector(32-1   downto 0);
1317 
 
1318 
 
1319 
      Regs_RdAddr         =>  Regs_RdAddr     ,      -- IN  std_logic_vector(15 downto 0);
1320 
      Regs_RdQout         =>  Regs_RdQout     ,      -- OUT std_logic_vector(31 downto 0);
1321 
 
1322 
      -- Downstream DMA transferred bytes count up
1323 
      ds_DMA_Bytes_Add    =>  ds_DMA_Bytes_Add     , -- IN  std_logic;
1324 
      ds_DMA_Bytes        =>  ds_DMA_Bytes         , -- IN  std_logic_vector(C_TLP_FLD_WIDTH_OF_LENG+2 downto 0);
1325 
 
1326 
      -- Register values
1327 
      DMA_ds_PA           =>  DMA_ds_PA            ,  -- OUT std_logic_vector(63 downto 0);
1328 
      DMA_ds_HA           =>  DMA_ds_HA            ,  -- OUT std_logic_vector(63 downto 0);
1329 
      DMA_ds_BDA          =>  DMA_ds_BDA           ,  -- OUT std_logic_vector(63 downto 0);
1330 
      DMA_ds_Length       =>  DMA_ds_Length        ,  -- OUT std_logic_vector(31 downto 0);
1331 
      DMA_ds_Control      =>  DMA_ds_Control       ,  -- OUT std_logic_vector(31 downto 0);
1332 
      dsDMA_BDA_eq_Null   =>  dsDMA_BDA_eq_Null    ,  -- OUT std_logic;
1333 
      DMA_ds_Status       =>  DMA_ds_Status        ,  -- IN  std_logic_vector(31 downto 0);
1334 
      DMA_ds_Done         =>  DMA_ds_Done_i        ,  -- IN  std_logic;
1335 
      DMA_ds_Tout         =>  DMA_ds_Tout          ,  -- IN  std_logic;
1336 
 
1337 
      dsHA_is_64b         =>  dsHA_is_64b          ,  -- OUT std_logic;
1338 
      dsBDA_is_64b        =>  dsBDA_is_64b         ,  -- OUT std_logic;
1339 
 
1340 
      dsLeng_Hi19b_True   =>  dsLeng_Hi19b_True    ,  -- OUT std_logic;
1341 
      dsLeng_Lo7b_True    =>  dsLeng_Lo7b_True     ,  -- OUT std_logic;
1342 
 
1343 
      dsDMA_Start         =>  dsDMA_Start          ,  -- OUT std_logic;
1344 
      dsDMA_Stop          =>  dsDMA_Stop           ,  -- OUT std_logic;
1345 
      dsDMA_Start2        =>  dsDMA_Start2         ,  -- OUT std_logic;
1346 
      dsDMA_Stop2         =>  dsDMA_Stop2          ,  -- OUT std_logic;
1347 
      dsDMA_Channel_Rst   =>  dsDMA_Channel_Rst    ,  -- OUT std_logic;
1348 
      dsDMA_Cmd_Ack       =>  dsDMA_Cmd_Ack        ,  -- IN  std_logic;
1349 
 
1350 
      -- Upstream DMA transferred bytes count up
1351 
      us_DMA_Bytes_Add    =>  us_DMA_Bytes_Add     ,  -- IN  std_logic;
1352 
      us_DMA_Bytes        =>  us_DMA_Bytes         ,  -- IN  std_logic_vector(C_TLP_FLD_WIDTH_OF_LENG+2 downto 0);
1353 
 
1354 
      DMA_us_PA           =>  DMA_us_PA            ,  -- OUT std_logic_vector(63 downto 0);
1355 
      DMA_us_HA           =>  DMA_us_HA            ,  -- OUT std_logic_vector(63 downto 0);
1356 
      DMA_us_BDA          =>  DMA_us_BDA           ,  -- OUT std_logic_vector(63 downto 0);
1357 
      DMA_us_Length       =>  DMA_us_Length        ,  -- OUT std_logic_vector(31 downto 0);
1358 
      DMA_us_Control      =>  DMA_us_Control       ,  -- OUT std_logic_vector(31 downto 0);
1359 
      usDMA_BDA_eq_Null   =>  usDMA_BDA_eq_Null    ,  -- OUT std_logic;
1360 
      us_MWr_Param_Vec    =>  us_MWr_Param_Vec     ,  -- OUT std_logic_vector(6-1   downto 0);
1361 
      DMA_us_Status       =>  DMA_us_Status        ,  -- IN  std_logic_vector(31 downto 0);
1362 
      DMA_us_Done         =>  DMA_us_Done_i        ,  -- IN  std_logic;
1363 
      DMA_us_Tout         =>  DMA_us_Tout          ,  -- IN  std_logic;
1364 
 
1365 
      usHA_is_64b         =>  usHA_is_64b          ,  -- OUT std_logic;
1366 
      usBDA_is_64b        =>  usBDA_is_64b         ,  -- OUT std_logic;
1367 
 
1368 
      usLeng_Hi19b_True   =>  usLeng_Hi19b_True    ,  -- OUT std_logic;
1369 
      usLeng_Lo7b_True    =>  usLeng_Lo7b_True     ,  -- OUT std_logic;
1370 
 
1371 
 
1372 
      usDMA_Start         =>  usDMA_Start          ,  -- OUT std_logic;
1373 
      usDMA_Stop          =>  usDMA_Stop           ,  -- OUT std_logic;
1374 
      usDMA_Start2        =>  usDMA_Start2         ,  -- OUT std_logic;
1375 
      usDMA_Stop2         =>  usDMA_Stop2          ,  -- OUT std_logic;
1376 
      usDMA_Channel_Rst   =>  usDMA_Channel_Rst    ,  -- OUT std_logic;
1377 
      usDMA_Cmd_Ack       =>  usDMA_Cmd_Ack        ,  -- IN  std_logic;
1378 
 
1379 
      -- Reset signals
1380 
      MRd_Channel_Rst     =>  MRd_Channel_Rst      ,  -- OUT std_logic;
1381 
      Tx_Reset            =>  Tx_Reset             ,  -- OUT std_logic;
1382 
 
1383 
      -- to Interrupt module
1384 
      Sys_IRQ             =>  Sys_IRQ              ,  -- OUT std_logic_vector(31 downto 0);
1385 3 weng_ziti 
--      DAQ_irq             =>  DAQ_irq              ,  -- IN  std_logic;
1386 
--      CTL_irq             =>  CTL_irq              ,  -- IN  std_logic;
1387 
--      DLM_irq             =>  DLM_irq              ,  -- IN  std_logic;
1388 2 weng_ziti 
 
1389 
      -- System error and info
1390 
      eb_FIFO_ow          =>  eb_FIFO_ow           ,
1391 
      Tx_TimeOut          =>  Tx_TimeOut           ,
1392 
      Tx_eb_TimeOut       =>  Tx_eb_TimeOut        ,
1393 
      Msg_Routing         =>  Msg_Routing          ,
1394 
      pcie_link_width     =>  pcie_link_width      ,
1395 
      cfg_dcommand        =>  cfg_dcommand         ,
1396 
 
1397 
      -- Interrupt Generation Signals
1398 
      IG_Reset            =>  IG_Reset             ,
1399 
      IG_Host_Clear       =>  IG_Host_Clear        ,
1400 
      IG_Latency          =>  IG_Latency           ,
1401 
      IG_Num_Assert       =>  IG_Num_Assert        ,
1402 
      IG_Num_Deassert     =>  IG_Num_Deassert      ,
1403 
      IG_Asserting        =>  IG_Asserting         ,
1404 
 
1405 3 weng_ziti 
--      -- Data generator control
1406 
--      DG_is_Running       =>  DG_is_Running        ,
1407 
--      DG_Reset            =>  DG_Reset             ,
1408 
--      DG_Mask             =>  DG_Mask              ,
1409 2 weng_ziti 
 
1410 
      -- Common
1411 
      trn_clk             =>  trn_clk              ,  -- IN  std_logic;
1412 
      trn_lnk_up_n        =>  trn_lnk_up_n         ,  -- IN  std_logic,
1413 
      trn_reset_n         =>  trn_reset_n             -- IN  std_logic;
1414 
        );
1415 
 
1416 
 
1417 
end architecture Behavioral;

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