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[/] [pcie_sg_dma/] [trunk/] [rtl/] [tx_Transact.vhd] - Blame information for rev 2

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Line No. Rev Author Line
1 2 weng_ziti 
----------------------------------------------------------------------------------
2 
-- Company:  ziti, Uni. HD
3 
-- Engineer:  wgao
4 
--
5 
-- Design Name:
6 
-- Module Name:    tx_Transact - Behavioral
7 
-- Project Name:
8 
-- Target Devices:
9 
-- Tool versions:
10 
-- Description:
11 
--
12 
-- Dependencies:
13 
--
14 
-- Revision 1.00 - first release.  14.12.2006
15 
--
16 
-- Additional Comments:
17 
--
18 
----------------------------------------------------------------------------------
19 
 
20 
library IEEE;
21 
use IEEE.STD_LOGIC_1164.ALL;
22 
use IEEE.STD_LOGIC_ARITH.ALL;
23 
use IEEE.STD_LOGIC_UNSIGNED.ALL;
24 
 
25 
library work;
26 
use work.abb64Package.all;
27 
 
28 
-- Uncomment the following library declaration if instantiating
29 
-- any Xilinx primitives in this code.
30 
--library UNISIM;
31 
--use UNISIM.VComponents.all;
32 
 
33 
entity tx_Transact is
34 
    port (
35 
      -- Common ports
36 
      trn_clk            : IN  std_logic;
37 
      trn_reset_n        : IN  std_logic;
38 
      trn_lnk_up_n       : IN  std_logic;
39 
 
40 
      -- Transaction
41 
      trn_tsof_n         : OUT std_logic;
42 
      trn_teof_n         : OUT std_logic;
43 
      trn_td             : OUT std_logic_vector(C_DBUS_WIDTH-1 downto 0);
44 
      trn_trem_n         : OUT std_logic_vector(C_DBUS_WIDTH/8-1 downto 0);
45 
      trn_terrfwd_n      : OUT std_logic;
46 
      trn_tsrc_rdy_n     : OUT std_logic;
47 
      trn_tdst_rdy_n     : IN  std_logic;
48 
      trn_tsrc_dsc_n     : OUT std_logic;
49 
      trn_tdst_dsc_n     : IN  std_logic;
50 
      trn_tbuf_av        : IN  std_logic_vector(C_TBUF_AWIDTH-1 downto 0);
51 
 
52 
      -- Upstream DMA transferred bytes count up
53 
      us_DMA_Bytes_Add   : OUT std_logic;
54 
      us_DMA_Bytes       : OUT std_logic_vector(C_TLP_FLD_WIDTH_OF_LENG+2 downto 0);
55 
 
56 
      -- Event Buffer FIFO read port
57 
      eb_FIFO_re         : OUT std_logic;
58 
      eb_FIFO_empty      : IN  std_logic;
59 
      eb_FIFO_qout       : IN  std_logic_vector(C_DBUS_WIDTH-1 downto 0);
60 
 
61 
      -- Read interface for Tx port
62 
      Regs_RdAddr        : OUT std_logic_vector(C_EP_AWIDTH-1   downto 0);
63 
      Regs_RdQout        : IN  std_logic_vector(C_DBUS_WIDTH-1   downto 0);
64 
 
65 
      -- Irpt Channel
66 
      Irpt_Req           : IN  std_logic;
67 
      Irpt_RE            : OUT std_logic;
68 
      Irpt_Qout          : IN  std_logic_vector(C_CHANNEL_BUF_WIDTH-1 downto 0);
69 
 
70 
      -- PIO MRd Channel
71 
      pioCplD_Req        : IN  std_logic;
72 
      pioCplD_RE         : OUT std_logic;
73 
      pioCplD_Qout       : IN  std_logic_vector(C_CHANNEL_BUF_WIDTH-1 downto 0);
74 
      pio_FC_stop        : OUT std_logic;
75 
 
76 
      -- downstream MRd Channel
77 
      dsMRd_Req          : IN  std_logic;
78 
      dsMRd_RE           : OUT std_logic;
79 
      dsMRd_Qout         : IN  std_logic_vector(C_CHANNEL_BUF_WIDTH-1 downto 0);
80 
 
81 
      -- upstream MWr/MRd Channel
82 
      usTlp_Req          : IN  std_logic;
83 
      usTlp_RE           : OUT std_logic;
84 
      usTlp_Qout         : IN  std_logic_vector(C_CHANNEL_BUF_WIDTH-1 downto 0);
85 
      us_FC_stop         : OUT std_logic;
86 
      us_Last_sof        : OUT std_logic;
87 
      us_Last_eof        : OUT std_logic;
88 
 
89 
      -- Message routing method
90 
      Msg_Routing        : IN  std_logic_vector(C_GCR_MSG_ROUT_BIT_TOP-C_GCR_MSG_ROUT_BIT_BOT downto 0);
91 
 
92 
      --  DDR read port
93 
      DDR_rdc_sof        : OUT   std_logic;
94 
      DDR_rdc_eof        : OUT   std_logic;
95 
      DDR_rdc_v          : OUT   std_logic;
96 
      DDR_rdc_FA         : OUT   std_logic;
97 
      DDR_rdc_Shift      : OUT   std_logic;
98 
      DDR_rdc_din        : OUT   std_logic_vector(C_DBUS_WIDTH-1 downto 0);
99 
      DDR_rdc_full       : IN    std_logic;
100 
 
101 
      -- DDR payload FIFO Read Port
102 
      DDR_FIFO_RdEn      : OUT std_logic;
103 
      DDR_FIFO_Empty     : IN  std_logic;
104 
      DDR_FIFO_RdQout    : IN  std_logic_vector(C_DBUS_WIDTH-1 downto 0);
105 
--      DDR_rdD_sof        : IN    std_logic;
106 
--      DDR_rdD_eof        : IN    std_logic;
107 
--      DDR_rdDout_V       : IN    std_logic;
108 
--      DDR_rdDout         : IN    std_logic_vector(C_DBUS_WIDTH-1 downto 0);
109 
 
110 
 
111 
      -- Additional
112 
      Tx_TimeOut         : OUT   std_logic;
113 
      Tx_eb_TimeOut      : OUT   std_logic;
114 
      Format_Shower      : OUT   std_logic;
115 
      mbuf_UserFull      : IN  std_logic;
116 
      Tx_Reset           : IN  std_logic;
117 
      localID            : IN  std_logic_vector(C_ID_WIDTH-1 downto 0)
118 
    );
119 
 
120 
end tx_Transact;
121 
 
122 
 
123 
architecture Behavioral of tx_Transact is
124 
 
125 
  type TxTrnStates is      ( St_TxIdle           -- Idle
126 
 
127 
--                           , St_d_CmdReq         -- Issue the read command to MemReader
128 
                           , St_d_CmdAck         -- Wait for the read command ACK from MemReader
129 
                           , St_d_Header0        -- 1st Header for TLP with payload
130 
                           , St_d_Header2        -- 2nd Header for TLP with payload
131 
--                           , St_d_HeaderPlus     -- Extra Header for TLP4 with payload
132 
                           , St_d_1st_Data       -- Last Header for TLP3/4 with payload
133 
                           , St_d_Payload        -- Data for TLP with payload
134 
                           , St_d_Payload_used   -- Data flow from memory buffer discontinued
135 
                           , St_d_Tail           -- Last data for TLP with payload
136 
                           , St_d_Tail_chk       -- Last data extended for TLP with payload
137 
                           , St_d_AfterChk       -- Last data extended for TLP with payload if arbitrating
138 
 
139 
                           , St_nd_Prepare       -- Prepare for 1st Header of TLP without payload
140 
--                           , St_nd_Header1       -- 1st Header for TLP without payload
141 
                           , St_nd_Header2       -- 2nd Header for TLP without payload
142 
--                           , St_nd_HeaderPlus    -- Extra Header for TLP4 without payload
143 
                           , St_nd_HeaderLast    -- Tail processing for the last dword of TLP w/o payload
144 
                           , St_nd_Arbitration   -- One extra cycle for arbitration
145 
                           );
146 
 
147 
  -- State variables
148 
  signal   TxTrn_State            : TxTrnStates;
149 
 
150 
  -- Signals with the arbitrator
151 
  signal   take_an_Arbitration    : std_logic;
152 
  signal   Req_Bundle             : std_logic_vector (C_CHANNEL_NUMBER-1 downto 0);
153 
  signal   Read_a_Buffer          : std_logic_vector (C_CHANNEL_NUMBER-1 downto 0);
154 
  signal   Read_aBuffer_r1        : std_logic;
155 
  signal   Read_aBuffer_r2        : std_logic;
156 
  signal   Read_aBuffer_r3        : std_logic;
157 
  signal   Ack_Indice             : std_logic_vector (C_CHANNEL_NUMBER-1 downto 0);
158 
 
159 
  signal   Tx_Indicator           : std_logic_vector (C_CHANNEL_NUMBER-1 downto 0);
160 
  signal   b1_Tx_Indicator        : std_logic_vector (C_CHANNEL_NUMBER-1 downto 0);
161 
  signal   vec_ChQout_Valid       : std_logic_vector (C_CHANNEL_NUMBER-1 downto 0);
162 
  signal   Tx_Busy                : std_logic;
163 
 
164 
  -- Channel buffer output token bits
165 
  signal   usTLP_is_MWr           : std_logic;
166 
  signal   TLP_is_CplD            : std_logic;
167 
 
168 
  -- Bit information, telling whether the outgoing TLP has payload
169 
  signal   ChBuf_has_Payload      : std_logic;
170 
  signal   ChBuf_No_Payload       : std_logic;
171 
 
172 
  -- Channel buffers output OR'ed and registered
173 
  signal   Trn_Qout_wire          :  std_logic_vector(C_CHANNEL_BUF_WIDTH-1 downto 0);
174 
  signal   Trn_Qout_reg           :  std_logic_vector(C_CHANNEL_BUF_WIDTH-1 downto 0);
175 
 
176 
  --  Addresses from different channel buffer
177 
  signal   mAddr_pioCplD          : std_logic_vector(C_PRAM_AWIDTH-1+2 downto 0);
178 
  signal   mAddr_usTlp            : std_logic_vector(C_PRAM_AWIDTH-1+2 downto 0);
179 
  signal   DDRAddr_usTlp          : std_logic_vector(C_DDR_IAWIDTH-1 downto 0);
180 
  signal   Regs_Addr_pioCplD      : std_logic_vector(C_EP_AWIDTH-1 downto 0);
181 
  signal   DDRAddr_pioCplD        : std_logic_vector(C_DDR_IAWIDTH-1 downto 0);
182 
  --  BAR number
183 
  signal   BAR_pioCplD            : std_logic_vector(C_ENCODE_BAR_NUMBER-1 downto 0);
184 
  signal   BAR_usTlp              : std_logic_vector(C_ENCODE_BAR_NUMBER-1 downto 0);
185 
  --  Misc. info.
186 
  signal   AInc_usTlp             : std_logic;
187 
  signal   pioCplD_is_0Leng       : std_logic;
188 
 
189 
  -- Delay for requests from Channel Buffers
190 
  signal   Irpt_Req_r1            : std_logic;
191 
  signal   pioCplD_Req_r1         : std_logic;
192 
  signal   dsMRd_Req_r1           : std_logic;
193 
  signal   usTlp_Req_r1           : std_logic;
194 
 
195 
  -- Registered channel buffer outputs
196 
  signal   Irpt_Qout_to_TLP       : std_logic_vector(C_CHANNEL_BUF_WIDTH-1 downto 0);
197 
  signal   pioCplD_Qout_to_TLP    : std_logic_vector(C_CHANNEL_BUF_WIDTH-1 downto 0);
198 
  signal   dsMRd_Qout_to_TLP      : std_logic_vector(C_CHANNEL_BUF_WIDTH-1 downto 0);
199 
  signal   usTlp_Qout_to_TLP      : std_logic_vector(C_CHANNEL_BUF_WIDTH-1 downto 0);
200 
 
201 
  signal   pioCplD_Req_Min_Leng   : std_logic;
202 
  signal   pioCplD_Req_2DW_Leng   : std_logic;
203 
  signal   usTlp_Req_Min_Leng     : std_logic;
204 
  signal   usTlp_Req_2DW_Leng     : std_logic;
205 
 
206 
  --  Channel buffer read enables
207 
  signal   Irpt_RE_i              : std_logic;
208 
  signal   pioCplD_RE_i           : std_logic;
209 
  signal   dsMRd_RE_i             : std_logic;
210 
  signal   usTlp_RE_i             : std_logic;
211 
 
212 
  -- Flow controls
213 
  signal   pio_FC_stop_i          : std_logic;
214 
  signal   us_FC_stop_i           : std_logic;
215 
 
216 
  -- Local reset for tx
217 
  signal   trn_tx_Reset_n         : std_logic;
218 
 
219 
  -- Alias for transaction interface signals
220 
  signal   trn_td_i               : std_logic_vector(C_DBUS_WIDTH-1 downto 0);
221 
  signal   trn_tsof_n_i           : std_logic;
222 
  signal   trn_trem_n_i           : std_logic_vector(C_DBUS_WIDTH/8-1 downto 0);
223 
  signal   trn_teof_n_i           : std_logic;
224 
  signal   Format_Shower_i        : std_logic;
225 
 
226 
  signal   trn_tsrc_rdy_n_i       : std_logic;
227 
  signal   trn_tsrc_dsc_n_i       : std_logic;
228 
  signal   trn_terrfwd_n_i        : std_logic;
229 
 
230 
  signal   trn_tdst_rdy_n_i       : std_logic;
231 
  signal   trn_tdst_rdy_n_r1      : std_logic;
232 
 
233 
  signal   trn_tdst_dsc_n_i       : std_logic;
234 
  signal   trn_tbuf_av_i          : std_logic_vector(C_TBUF_AWIDTH-1 downto 0);
235 
 
236 
  -- Upstream DMA transferred bytes count up
237 
  signal   us_DMA_Bytes_Add_i     : std_logic;
238 
  signal   us_DMA_Bytes_i         : std_logic_vector(C_TLP_FLD_WIDTH_OF_LENG+2 downto 0);
239 
 
240 
  ---------------------  Memory Reader  -----------------------------
241 
  ---
242 
  --- Memory reader is the interface to access all sorts of memories
243 
  ---   BRAM, FIFO, Registers, as well as possible DDR SDRAM
244 
  ---
245 
  -------------------------------------------------------------------
246 
  COMPONENT
247 
  tx_Mem_Reader
248 
  PORT(
249 
       DDR_rdc_sof           : OUT   std_logic;
250 
       DDR_rdc_eof           : OUT   std_logic;
251 
       DDR_rdc_v             : OUT   std_logic;
252 
       DDR_rdc_FA            : OUT   std_logic;
253 
       DDR_rdc_Shift         : OUT   std_logic;
254 
       DDR_rdc_din           : OUT   std_logic_vector(C_DBUS_WIDTH-1 downto 0);
255 
       DDR_rdc_full          : IN    std_logic;
256 
 
257 
--       DDR_rdD_sof           : IN    std_logic;
258 
--       DDR_rdD_eof           : IN    std_logic;
259 
--       DDR_rdDout_V          : IN    std_logic;
260 
--       DDR_rdDout            : IN    std_logic_vector(C_DBUS_WIDTH-1 downto 0);
261 
 
262 
       DDR_FIFO_RdEn         : OUT   std_logic;
263 
       DDR_FIFO_Empty        : IN    std_logic;
264 
       DDR_FIFO_RdQout       : IN    std_logic_vector(C_DBUS_WIDTH-1 downto 0);
265 
 
266 
       eb_FIFO_re            : OUT   std_logic;
267 
       eb_FIFO_empty         : IN    std_logic;
268 
       eb_FIFO_qout          : IN    std_logic_vector(C_DBUS_WIDTH-1 downto 0);
269 
 
270 
       Regs_RdAddr           : OUT   std_logic_vector(C_EP_AWIDTH-1 downto 0);
271 
       Regs_RdQout           : IN    std_logic_vector(C_DBUS_WIDTH-1 downto 0);
272 
 
273 
       RdNumber              : IN    std_logic_vector(C_TLP_FLD_WIDTH_OF_LENG-1 downto 0);
274 
       RdNumber_eq_One       : IN    std_logic;
275 
       RdNumber_eq_Two       : IN    std_logic;
276 
       StartAddr             : IN    std_logic_vector(C_DBUS_WIDTH-1 downto 0);
277 
       Shift_1st_QWord       : IN    std_logic;
278 
       FixedAddr             : IN    std_logic;
279 
       is_CplD               : IN    std_logic;
280 
       BAR_value             : IN    std_logic_vector(C_ENCODE_BAR_NUMBER-1 downto 0);
281 
       RdCmd_Req             : IN    std_logic;
282 
       RdCmd_Ack             : OUT   std_logic;
283 
 
284 
       mbuf_WE               : OUT   std_logic;
285 
       mbuf_Din              : OUT   std_logic_vector(C_DBUS_WIDTH*9/8-1 downto 0);
286 
       mbuf_Full             : IN    std_logic;
287 
       mbuf_aFull            : IN    std_logic;
288 
       mbuf_UserFull         : IN    std_logic;
289 
 
290 
       Tx_TimeOut            : OUT   std_logic;
291 
       Tx_eb_TimeOut         : OUT   std_logic;
292 
       mReader_Rst_n         : IN    std_logic;
293 
       trn_clk               : IN    std_logic
294 
      );
295 
  END COMPONENT;
296 
 
297 
  signal   RdNumber               : std_logic_vector(C_TLP_FLD_WIDTH_OF_LENG-1 downto 0);
298 
  signal   RdNumber_eq_One        : std_logic;
299 
  signal   RdNumber_eq_Two        : std_logic;
300 
  signal   StartAddr              : std_logic_vector(C_DBUS_WIDTH-1 downto 0);
301 
  signal   Shift_1st_QWord        : std_logic;
302 
  signal   FixedAddr              : std_logic;
303 
  signal   is_CplD                : std_logic;
304 
  signal   BAR_value              : std_logic_vector(C_ENCODE_BAR_NUMBER-1 downto 0);
305 
  signal   RdCmd_Req              : std_logic;
306 
  signal   RdCmd_Ack              : std_logic;
307 
 
308 
 
309 
  ---------------------  Memory Buffer  -----------------------------
310 
  ---
311 
  --- A unified memory buffer holding the payload for the next tx TLP
312 
  ---   34 bits wide, wherein 2 additional framing bits
313 
  ---   temporarily 64 data depth, possibly deepened.
314 
  ---
315 
  -------------------------------------------------------------------
316 
  component
317 
  mBuf_128x72
318 
  port (
319 
        clk                  : IN     std_logic;
320 
        rst                  : IN     std_logic;
321 
        wr_en                : IN     std_logic;
322 
        din                  : IN     std_logic_VECTOR(C_DBUS_WIDTH*9/8-1 downto 0);
323 
        prog_full            : OUT    std_logic;
324 
        full                 : OUT    std_logic;
325 
        rd_en                : IN     std_logic;
326 
        dout                 : OUT    std_logic_VECTOR(C_DBUS_WIDTH*9/8-1 downto 0);
327 
        empty                : OUT    std_logic
328 
       );
329 
  end component;
330 
 
331 
  signal   mbuf_reset_b3          : std_logic;
332 
  signal   mbuf_reset_b2          : std_logic;
333 
  signal   mbuf_reset_b1          : std_logic;
334 
  signal   mbuf_reset             : std_logic;
335 
  signal   mbuf_WE                : std_logic;
336 
  signal   mbuf_Din               : std_logic_VECTOR(C_DBUS_WIDTH*9/8-1 downto 0);
337 
  signal   mbuf_Full              : std_logic;
338 
  signal   mbuf_aFull             : std_logic;
339 
  signal   mbuf_RE                : std_logic;
340 
  signal   mbuf_Qout              : std_logic_VECTOR(C_DBUS_WIDTH*9/8-1 downto 0);
341 
  signal   mbuf_Empty             : std_logic;
342 
  -- Calculated infomation
343 
  signal   mbuf_RE_ok             : std_logic;
344 
  signal   mbuf_Qvalid            : std_logic;
345 
 
346 
--  signal   Payload_Rd_Debt        : std_logic;
347 
  signal   Payload_rd_count       : std_logic_VECTOR(C_TLP_FLD_WIDTH_OF_LENG-1 downto 0);
348 
 
349 
  ---------------------  Output arbitration  ------------------------
350 
  ---
351 
  --- For sake of fairness, the priorities are cycled every time
352 
  ---   a service is done, after which the priority of the request
353 
  ---   just serviced is set to the lowest and other lower priorities
354 
  ---   increased and higher stay.
355 
  ---
356 
  -------------------------------------------------------------------
357 
  COMPONENT
358 
  Tx_Output_Arbitor
359 
  PORT(
360 
        rst_n                : IN    std_logic;
361 
        clk                  : IN    std_logic;
362 
        arbtake              : IN    std_logic;
363 
        Req                  : IN    std_logic_vector(C_ARBITRATE_WIDTH-1 downto 0);
364 
        bufread              : OUT   std_logic_vector(C_ARBITRATE_WIDTH-1 downto 0);
365 
        Ack                  : OUT   std_logic_vector(C_ARBITRATE_WIDTH-1 downto 0)
366 
      );
367 
  END COMPONENT;
368 
 
369 
  type ArbReqStates is     ( StA_idle            -- Intial idle
370 
                           , StA_req             -- Wait for ack from mReader module
371 
                           , StA_take            -- Waiting for arbitration take signal
372 
                           );
373 
 
374 
  -- Arbitration State variables
375 
  signal   arq_State              : ArbReqStates;
376 
 
377 
begin
378 
 
379 
   -- Connect outputs
380 
   trn_td                <= trn_td_i;
381 
   trn_tsof_n            <= trn_tsof_n_i;
382 
   trn_trem_n            <= trn_trem_n_i;
383 
   trn_teof_n            <= trn_teof_n_i;
384 
 
385 
   trn_tsrc_rdy_n        <= trn_tsrc_rdy_n_i;
386 
   trn_tsrc_dsc_n        <= trn_tsrc_dsc_n_i;
387 
   trn_terrfwd_n         <= trn_terrfwd_n_i;
388 
 
389 
   Format_Shower         <= Format_Shower_i;
390 
   us_Last_sof           <= usTLP_is_MWr and not trn_tsof_n_i;
391 
   us_Last_eof           <= usTLP_is_MWr and not trn_teof_n_i;
392 
 
393 
   -- Connect inputs
394 
   trn_tdst_rdy_n_i      <= trn_tdst_rdy_n;
395 
   trn_tdst_dsc_n_i      <= trn_tdst_dsc_n;
396 
   trn_tbuf_av_i         <= trn_tbuf_av;
397 
 
398 
 
399 
   -- Always deasserted
400 
   trn_tsrc_dsc_n_i      <= '1';
401 
   trn_terrfwd_n_i       <= '1';
402 
--   trn_trem_n_i          <= (OTHERS=>'0');
403 
 
404 
 
405 
   -- Upstream DMA transferred bytes counting up
406 
   us_DMA_Bytes_Add      <= us_DMA_Bytes_Add_i;
407 
   us_DMA_Bytes          <= us_DMA_Bytes_i    ;
408 
 
409 
 
410 
   -- Flow controls
411 
   pio_FC_stop           <= pio_FC_stop_i;
412 
   us_FC_stop            <= us_FC_stop_i;
413 
 
414 
 
415 
-----------------------------------------------------
416 
-- Synchronous Delay: trn_tdst_rdy_n_i
417 
--
418 
   Synchron_Delay_trn_tdst_rdy_n_i:
419 
   process ( trn_clk )
420 
   begin
421 
     if trn_clk'event and trn_clk = '1' then
422 
        trn_tdst_rdy_n_r1    <= trn_tdst_rdy_n_i;
423 
      end if;
424 
   end process;
425 
 
426 
---------------------------------------------------------------------------------
427 
-- Synchronous Calculation: us_FC_stop, pio_FC_stop
428 
--
429 
   Synch_Calc_FC_stop:
430 
   process ( trn_clk, Tx_Reset)
431 
   begin
432 
      if Tx_Reset = '1' then
433 
         us_FC_stop_i        <= '1';
434 
         pio_FC_stop_i       <= '1';
435 
      elsif trn_clk'event and trn_clk = '1' then
436 
        if trn_tbuf_av_i(C_TBUF_AWIDTH-1 downto 1) /=C_ALL_ZEROS(C_TBUF_AWIDTH-1 downto 1) then
437 
           us_FC_stop_i        <= '0';
438 
           pio_FC_stop_i       <= '0';
439 
        else
440 
           us_FC_stop_i        <= '1';
441 
           pio_FC_stop_i       <= '1';
442 
        end if;
443 
      end if;
444 
   end process;
445 
 
446 
 
447 
   -- Channel buffer read enable
448 
   Irpt_RE               <= Irpt_RE_i;
449 
   pioCplD_RE            <= pioCplD_RE_i;
450 
   dsMRd_RE              <= dsMRd_RE_i;
451 
   usTlp_RE              <= usTlp_RE_i;
452 
 
453 
 
454 
-- -----------------------------------
455 
--   Synchronized Local reset
456 
--
457 
   Syn_Local_Reset:
458 
   process ( trn_clk, trn_reset_n)
459 
   begin
460 
      if trn_reset_n = '0' then
461 
         trn_tx_Reset_n   <= '0';
462 
      elsif trn_clk'event and trn_clk = '1' then
463 
         trn_tx_Reset_n   <= trn_tdst_dsc_n_i and not Tx_Reset;
464 
      end if;
465 
   end process;
466 
 
467 
-- -----------------------------------
468 
--   Format detector
469 
--
470 
   Syn_Format_Shower:
471 
   process ( trn_clk, trn_reset_n)
472 
   begin
473 
      if trn_reset_n = '0' then
474 
         Format_Shower_i   <= '0';
475 
      elsif trn_clk'event and trn_clk = '1' then
476 
         if Format_Shower_i = '0' then
477 
           if trn_tsof_n_i='0' and trn_tsrc_rdy_n_i='0' and trn_tdst_rdy_n_i='0' then
478 
              Format_Shower_i   <= '1';
479 
           else
480 
              Format_Shower_i   <= '0';
481 
           end if;
482 
         else
483 
           if trn_teof_n_i='0' and trn_tsrc_rdy_n_i='0' and trn_tdst_rdy_n_i='0' then
484 
              Format_Shower_i   <= '0';
485 
           else
486 
              Format_Shower_i   <= '1';
487 
           end if;
488 
         end if;
489 
      end if;
490 
   end process;
491 
 
492 
------------------------------------------------------------
493 
---             Memory reader
494 
------------------------------------------------------------
495 
   ABB_Tx_MReader:
496 
   tx_Mem_Reader
497 
   PORT MAP(
498 
            DDR_rdc_sof     => DDR_rdc_sof     ,  --  OUT   std_logic;
499 
            DDR_rdc_eof     => DDR_rdc_eof     ,  --  OUT   std_logic;
500 
            DDR_rdc_v       => DDR_rdc_v       ,  --  OUT   std_logic;
501 
            DDR_rdc_FA      => DDR_rdc_FA      ,  --  OUT   std_logic;
502 
            DDR_rdc_Shift   => DDR_rdc_Shift   ,  --  OUT   std_logic;
503 
            DDR_rdc_din     => DDR_rdc_din     ,  --  OUT   std_logic_vector(C_DBUS_WIDTH-1 downto 0);
504 
            DDR_rdc_full    => DDR_rdc_full    ,  --  IN    std_logic;
505 
 
506 
--            DDR_rdD_sof     => DDR_rdD_sof     ,  --  IN    std_logic;
507 
--            DDR_rdD_eof     => DDR_rdD_eof     ,  --  IN    std_logic;
508 
--            DDR_rdDout_V    => DDR_rdDout_V    ,  --  IN    std_logic;
509 
--            DDR_rdDout      => DDR_rdDout      ,  --  IN    std_logic_vector(C_DBUS_WIDTH-1 downto 0);
510 
 
511 
            DDR_FIFO_RdEn   => DDR_FIFO_RdEn   ,  -- OUT std_logic;
512 
            DDR_FIFO_Empty  => DDR_FIFO_Empty  ,  -- IN  std_logic;
513 
            DDR_FIFO_RdQout => DDR_FIFO_RdQout ,  -- IN  std_logic_vector(C_DBUS_WIDTH-1 downto 0);
514 
 
515 
            eb_FIFO_re      => eb_FIFO_re      ,  -- OUT std_logic;
516 
            eb_FIFO_empty   => eb_FIFO_empty   ,  -- IN  std_logic;
517 
            eb_FIFO_qout    => eb_FIFO_qout    ,  -- IN  std_logic_vector(C_DBUS_WIDTH-1 downto 0);
518 
 
519 
            Regs_RdAddr     => Regs_RdAddr     ,  -- OUT std_logic_vector(C_EP_AWIDTH-1 downto 0);
520 
            Regs_RdQout     => Regs_RdQout     ,  -- IN  std_logic_vector(C_DBUS_WIDTH-1 downto 0);
521 
 
522 
            RdNumber        => RdNumber        ,  -- IN  std_logic_vector(C_DBUS_WIDTH-1 downto 0);
523 
            RdNumber_eq_One => RdNumber_eq_One ,  -- IN  std_logic;
524 
            RdNumber_eq_Two => RdNumber_eq_Two ,  -- IN  std_logic;
525 
            StartAddr       => StartAddr       ,  -- IN  std_logic_vector(C_DBUS_WIDTH-1 downto 0);
526 
            Shift_1st_QWord => Shift_1st_QWord ,  -- IN  std_logic;
527 
            FixedAddr       => '0',         -- FixedAddr       ,  -- IN  std_logic;
528 
            is_CplD         => is_CplD         ,  -- IN  std_logic;
529 
            BAR_value       => BAR_value       ,  -- IN  std_logic_vector(C_ENCODE_BAR_NUMBER-1 downto 0);
530 
            RdCmd_Req       => RdCmd_Req       ,  -- IN  std_logic;
531 
            RdCmd_Ack       => RdCmd_Ack       ,  -- OUT std_logic;
532 
 
533 
            mbuf_WE         => mbuf_WE         ,  -- OUT std_logic;
534 
            mbuf_Din        => mbuf_Din        ,  -- OUT std_logic_vector(C_DBUS_WIDTH-1 downto 0);
535 
            mbuf_Full       => mbuf_Full       ,  -- IN  std_logic;
536 
            mbuf_aFull      => mbuf_aFull      ,  -- IN  std_logic;
537 
            mbuf_UserFull   => mbuf_UserFull   ,  -- IN  std_logic;
538 
 
539 
            Tx_TimeOut      => Tx_TimeOut      ,  -- OUT std_logic;
540 
            Tx_eb_TimeOut   => Tx_eb_TimeOut   ,  -- OUT std_logic;
541 
            mReader_Rst_n   => trn_tx_Reset_n  ,  -- IN  std_logic;
542 
            trn_clk         => trn_clk            -- IN  std_logic
543 
           );
544 
 
545 
 
546 
------------------------------------------------------------
547 
---             Memory buffer
548 
------------------------------------------------------------
549 
   ABB_Tx_MBuffer:
550 
   mBuf_128x72
551 
   PORT MAP(
552 
            wr_en         => mbuf_WE               , -- IN  std_logic;
553 
            din           => mbuf_Din              , -- IN  std_logic_VECTOR(C_DBUS_WIDTH+1 downto 0);
554 
            prog_full     => mbuf_aFull            , -- OUT std_logic;
555 
            full          => mbuf_Full             , -- OUT std_logic;
556 
            rd_en         => mbuf_RE               , -- IN  std_logic;
557 
            dout          => mbuf_Qout             , -- OUT std_logic_VECTOR(C_DBUS_WIDTH+1 downto 0);
558 
            empty         => mbuf_Empty            , -- OUT std_logic
559 
            rst           => mbuf_reset, --Tx_Reset              , -- IN  std_logic;
560 
            clk           => trn_clk                 -- IN  std_logic;
561 
           );
562 
 
563 
   mbuf_RE        <=  mbuf_RE_ok and (not trn_tdst_rdy_n_i or trn_tsrc_rdy_n_i);
564 
 
565 
 
566 
-- ---------------------------------------------------
567 
-- State Machine Tx: mbuf_reset
568 
--
569 
   TxFSM_Output_mbuf_reset:
570 
   process ( trn_clk, trn_tx_Reset_n)
571 
   begin
572 
      if trn_tx_Reset_n = '0' then
573 
         mbuf_reset_b3           <= '1';
574 
         mbuf_reset_b2           <= '1';
575 
         mbuf_reset_b1           <= '1';
576 
         mbuf_reset              <= '1';
577 
 
578 
      elsif trn_clk'event and trn_clk = '1' then
579 
 
580 
         mbuf_reset_b3 <= '0';
581 
         mbuf_reset_b2 <= mbuf_reset_b3;
582 
         mbuf_reset_b1 <= mbuf_reset_b2;
583 
         mbuf_reset    <= mbuf_reset_b3 or mbuf_reset_b2 or mbuf_reset_b1;
584 
 
585 
      end if;
586 
   end process;
587 
 
588 
 
589 
---------------------------------------------------------------------------------
590 
-- Synchronous Delay: mbuf_Qout Valid
591 
--
592 
   Synchron_Delay_mbuf_Qvalid:
593 
   process ( trn_clk, Tx_Reset)
594 
   begin
595 
      if Tx_Reset = '1' then
596 
         mbuf_Qvalid        <= '0';
597 
      elsif trn_clk'event and trn_clk = '1' then
598 
        if     mbuf_Qvalid='0' and mbuf_RE='1' and mbuf_Empty='0' then  -- a valid data is going out
599 
           mbuf_Qvalid          <= '1';
600 
        elsif  mbuf_Qvalid='1' and mbuf_RE='1' and mbuf_Empty='1' then  -- an invalid data is going out
601 
           mbuf_Qvalid          <= '0';
602 
        else                                                        -- state stays
603 
           mbuf_Qvalid          <= mbuf_Qvalid;
604 
        end if;
605 
      end if;
606 
   end process;
607 
 
608 
 
609 
------------------------------------------------------------
610 
---             Output arbitration
611 
------------------------------------------------------------
612 
   O_Arbitration:
613 
   Tx_Output_Arbitor
614 
   PORT MAP(
615 
            rst_n         => trn_tx_Reset_n,
616 
            clk           => trn_clk,
617 
            arbtake       => take_an_Arbitration,
618 
            Req           => Req_Bundle,
619 
            bufread       => Read_a_Buffer,
620 
            Ack           => Ack_Indice
621 
           );
622 
 
623 
 
624 
-----------------------------------------------------
625 
-- Synchronous Delay: Channel Requests
626 
--
627 
   Synchron_Delay_ChRequests:
628 
   process ( trn_clk )
629 
   begin
630 
     if trn_clk'event and trn_clk = '1' then
631 
         Irpt_Req_r1      <= Irpt_Req;
632 
         pioCplD_Req_r1   <= pioCplD_Req;
633 
         dsMRd_Req_r1     <= dsMRd_Req;
634 
         usTlp_Req_r1     <= usTlp_Req;
635 
      end if;
636 
   end process;
637 
 
638 
 
639 
-----------------------------------------------------
640 
-- Synchronous Delay: Read_a_Buffer
641 
--
642 
   Synchron_Delay_Read_a_Buffer:
643 
   process ( trn_clk )
644 
   begin
645 
     if trn_clk'event and trn_clk = '1' then
646 
        Read_aBuffer_r3      <= Read_aBuffer_r2;
647 
        Read_aBuffer_r2      <= Read_aBuffer_r1;
648 
        if Read_a_Buffer=C_ALL_ZEROS(C_CHANNEL_NUMBER-1 downto 0) then
649 
           Read_aBuffer_r1      <= '0';
650 
        else
651 
           Read_aBuffer_r1      <= '1';
652 
        end if;
653 
      end if;
654 
   end process;
655 
 
656 
 
657 
-----------------------------------------------------
658 
-- Synchronous Delay: Tx_Busy
659 
--
660 
   Synchron_Delay_Tx_Busy:
661 
   process ( trn_clk )
662 
   begin
663 
     if trn_clk'event and trn_clk = '1' then
664 
         Tx_Indicator     <= b1_Tx_Indicator;
665 
         Tx_Busy          <= (b1_Tx_Indicator(C_CHAN_INDEX_IRPT)   and vec_ChQout_Valid(C_CHAN_INDEX_IRPT)  )
666 
                          or (b1_Tx_Indicator(C_CHAN_INDEX_MRD)    and vec_ChQout_Valid(C_CHAN_INDEX_MRD)   )
667 
                          or (b1_Tx_Indicator(C_CHAN_INDEX_DMA_DS) and vec_ChQout_Valid(C_CHAN_INDEX_DMA_DS))
668 
                          or (b1_Tx_Indicator(C_CHAN_INDEX_DMA_US) and vec_ChQout_Valid(C_CHAN_INDEX_DMA_US))
669 
                          ;
670 
      end if;
671 
   end process;
672 
 
673 
 
674 
-- ---------------------------------------------
675 
-- Reg : Channel Buffer Qout has Payload
676 
--
677 
   Reg_ChBuf_with_Payload:
678 
   process ( trn_clk )
679 
   begin
680 
      if trn_clk'event and trn_clk = '1' then
681 
         ChBuf_has_Payload     <= (b1_Tx_Indicator(C_CHAN_INDEX_MRD)    and TLP_is_CplD  and vec_ChQout_Valid(C_CHAN_INDEX_MRD)   )
682 
                               or (b1_Tx_Indicator(C_CHAN_INDEX_DMA_US) and usTLP_is_MWr and vec_ChQout_Valid(C_CHAN_INDEX_DMA_US))
683 
                               ;
684 
      end if;
685 
   end process;
686 
 
687 
-- ---------------------------------------------
688 
-- Channel Buffer Qout has no Payload
689 
--   (! subordinate to ChBuf_has_Payload ! )
690 
--
691 
   ChBuf_No_Payload      <=   Tx_Busy;
692 
 
693 
 
694 
-- Arbitrator inputs
695 
   Req_Bundle(C_CHAN_INDEX_IRPT)         <= Irpt_Req_r1;
696 
   Req_Bundle(C_CHAN_INDEX_MRD)          <= pioCplD_Req_r1;
697 
   Req_Bundle(C_CHAN_INDEX_DMA_DS)       <= dsMRd_Req_r1;
698 
   Req_Bundle(C_CHAN_INDEX_DMA_US)       <= usTlp_Req_r1;
699 
 
700 
-- Arbitrator outputs
701 
   b1_Tx_Indicator(C_CHAN_INDEX_IRPT)    <= Ack_Indice(C_CHAN_INDEX_IRPT);
702 
   b1_Tx_Indicator(C_CHAN_INDEX_MRD)     <= Ack_Indice(C_CHAN_INDEX_MRD);
703 
   b1_Tx_Indicator(C_CHAN_INDEX_DMA_DS)  <= Ack_Indice(C_CHAN_INDEX_DMA_DS);
704 
   b1_Tx_Indicator(C_CHAN_INDEX_DMA_US)  <= Ack_Indice(C_CHAN_INDEX_DMA_US);
705 
 
706 
 
707 
-- Arbitrator reads channel buffers
708 
   Irpt_RE_i                             <= Read_a_Buffer(C_CHAN_INDEX_IRPT);
709 
   pioCplD_RE_i                          <= Read_a_Buffer(C_CHAN_INDEX_MRD);
710 
   dsMRd_RE_i                            <= Read_a_Buffer(C_CHAN_INDEX_DMA_DS);
711 
   usTlp_RE_i                            <= Read_a_Buffer(C_CHAN_INDEX_DMA_US);
712 
 
713 
 
714 
-- determine whether the upstream TLP is an MWr or an MRd.
715 
   usTLP_is_MWr          <= usTlp_Qout  (C_CHBUF_FMT_BIT_TOP);
716 
   TLP_is_CplD           <= pioCplD_Qout(C_CHBUF_FMT_BIT_TOP);
717 
 
718 
 
719 
-- check if the Channel buffer output is valid
720 
   vec_ChQout_Valid(C_CHAN_INDEX_IRPT)    <= Irpt_Qout   (C_CHBUF_QVALID_BIT);
721 
   vec_ChQout_Valid(C_CHAN_INDEX_MRD)     <= pioCplD_Qout(C_CHBUF_QVALID_BIT);
722 
   vec_ChQout_Valid(C_CHAN_INDEX_DMA_DS)  <= dsMRd_Qout  (C_CHBUF_QVALID_BIT);
723 
   vec_ChQout_Valid(C_CHAN_INDEX_DMA_US)  <= usTlp_Qout  (C_CHBUF_QVALID_BIT);
724 
 
725 
 
726 
-- -----------------------------------
727 
-- Delay : Channel_Buffer_Qout
728 
--         Bit-mapping is done
729 
--
730 
   Delay_Channel_Buffer_Qout:
731 
   process ( trn_clk, trn_tx_Reset_n)
732 
   begin
733 
      if trn_tx_Reset_n = '0' then
734 
         Irpt_Qout_to_TLP      <= (Others=>'0');
735 
         pioCplD_Qout_to_TLP   <= (Others=>'0');
736 
         dsMRd_Qout_to_TLP     <= (Others=>'0');
737 
         usTlp_Qout_to_TLP     <= (Others=>'0');
738 
 
739 
         pioCplD_Req_Min_Leng  <= '0';
740 
         pioCplD_Req_2DW_Leng  <= '0';
741 
         usTlp_Req_Min_Leng    <= '0';
742 
         usTlp_Req_2DW_Leng    <= '0';
743 
 
744 
         Regs_Addr_pioCplD     <= (Others=>'1');
745 
         mAddr_pioCplD         <= (Others=>'1');
746 
         mAddr_usTlp           <= (Others=>'1');
747 
         AInc_usTlp            <= '1';
748 
         BAR_pioCplD           <= (Others=>'1');
749 
         BAR_usTlp             <= (Others=>'1');
750 
         pioCplD_is_0Leng      <= '0';
751 
 
752 
      elsif trn_clk'event and trn_clk = '1' then
753 
 
754 
         if b1_Tx_Indicator(C_CHAN_INDEX_IRPT)='1' then
755 
            Irpt_Qout_to_TLP  <= (Others=>'0');   -- must be 1st argument
756 
            -- 1st header Hi
757 
            Irpt_Qout_to_TLP(C_TLP_FMT_BIT_TOP downto C_TLP_FMT_BIT_BOT)    <= Irpt_Qout(C_CHBUF_FMT_BIT_TOP downto C_CHBUF_FMT_BIT_BOT);
758 
--            Irpt_Qout_to_TLP(C_TLP_TYPE_BIT_TOP downto C_TLP_TYPE_BIT_BOT)  <= C_TYPE_OF_MSG; --Irpt_Qout(C_CHBUF_MSGTYPE_BIT_TOP downto C_CHBUF_MSGTYPE_BIT_BOT);
759 
            Irpt_Qout_to_TLP(C_TLP_TYPE_BIT_TOP downto C_TLP_TYPE_BIT_BOT)  <= C_TYPE_OF_MSG(C_TLP_TYPE_BIT_TOP
760 
                                                                               downto C_TLP_TYPE_BIT_BOT+1+C_GCR_MSG_ROUT_BIT_TOP-C_GCR_MSG_ROUT_BIT_BOT)
761 
                                                                             & Msg_Routing;
762 
            Irpt_Qout_to_TLP(C_TLP_TC_BIT_TOP   downto C_TLP_TC_BIT_BOT)    <= Irpt_Qout(C_CHBUF_TC_BIT_TOP downto C_CHBUF_TC_BIT_BOT);
763 
            Irpt_Qout_to_TLP(C_TLP_LENG_BIT_TOP downto C_TLP_LENG_BIT_BOT)  <= Irpt_Qout(C_CHBUF_LENG_BIT_TOP downto C_CHBUF_LENG_BIT_BOT);
764 
 
765 
            -- 1st header Lo
766 
            Irpt_Qout_to_TLP(C_TLP_REQID_BIT_TOP downto C_TLP_REQID_BIT_BOT)  <= localID;
767 
            Irpt_Qout_to_TLP(C_TLP_TAG_BIT_TOP   downto C_TLP_TAG_BIT_BOT)    <= Irpt_Qout(C_CHBUF_TAG_BIT_TOP downto C_CHBUF_TAG_BIT_BOT);
768 
            Irpt_Qout_to_TLP(C_MSG_CODE_BIT_TOP  downto C_MSG_CODE_BIT_BOT)   <= Irpt_Qout(C_CHBUF_MSG_CODE_BIT_TOP downto C_CHBUF_MSG_CODE_BIT_BOT);
769 
            -- 2nd headers all zero
770 
            -- ...
771 
 
772 
         else
773 
            Irpt_Qout_to_TLP     <= (Others=>'0');
774 
         end if;
775 
 
776 
 
777 
         if b1_Tx_Indicator(C_CHAN_INDEX_MRD)='1' then
778 
            pioCplD_Qout_to_TLP  <= (Others=>'0');   -- must be 1st argument
779 
            -- 1st header Hi
780 
            pioCplD_Qout_to_TLP(C_TLP_FMT_BIT_TOP  downto C_TLP_FMT_BIT_BOT)   <= pioCplD_Qout(C_CHBUF_FMT_BIT_TOP  downto C_CHBUF_FMT_BIT_BOT);
781 
            pioCplD_Qout_to_TLP(C_TLP_TYPE_BIT_TOP downto C_TLP_TYPE_BIT_BOT)  <= C_TYPE_COMPLETION; --pioCplD_Qout(C_CHBUF_TYPE_BIT_TOP downto C_CHBUF_TYPE_BIT_BOT);
782 
            pioCplD_Qout_to_TLP(C_TLP_TC_BIT_TOP   downto C_TLP_TC_BIT_BOT)    <= pioCplD_Qout(C_CHBUF_TC_BIT_TOP   downto C_CHBUF_TC_BIT_BOT);
783 
            pioCplD_Qout_to_TLP(C_TLP_ATTR_BIT_TOP downto C_TLP_ATTR_BIT_BOT)  <= pioCplD_Qout(C_CHBUF_ATTR_BIT_TOP downto C_CHBUF_ATTR_BIT_BOT);
784 
            pioCplD_Qout_to_TLP(C_TLP_LENG_BIT_TOP downto C_TLP_LENG_BIT_BOT)  <= pioCplD_Qout(C_CHBUF_LENG_BIT_TOP downto C_CHBUF_LENG_BIT_BOT);
785 
            -- 1st header Lo
786 
            pioCplD_Qout_to_TLP(C_CPLD_CPLT_ID_BIT_TOP downto C_CPLD_CPLT_ID_BIT_BOT)  <= localID;
787 
            pioCplD_Qout_to_TLP(C_CPLD_CS_BIT_TOP     downto C_CPLD_CS_BIT_BOT)        <= pioCplD_Qout(C_CHBUF_CPLD_CS_BIT_TOP downto C_CHBUF_CPLD_CS_BIT_BOT);
788 
            pioCplD_Qout_to_TLP(C_CPLD_BC_BIT_TOP     downto C_CPLD_BC_BIT_BOT)        <= pioCplD_Qout(C_CHBUF_CPLD_BC_BIT_TOP downto C_CHBUF_CPLD_BC_BIT_BOT);
789 
            -- 2nd header Hi
790 
            pioCplD_Qout_to_TLP(C_DBUS_WIDTH+C_CPLD_REQID_BIT_TOP downto C_DBUS_WIDTH+C_CPLD_REQID_BIT_BOT)  <= pioCplD_Qout(C_CHBUF_CPLD_REQID_BIT_TOP downto C_CHBUF_CPLD_REQID_BIT_BOT);
791 
            pioCplD_Qout_to_TLP(C_DBUS_WIDTH+C_CPLD_TAG_BIT_TOP   downto C_DBUS_WIDTH+C_CPLD_TAG_BIT_BOT)    <= pioCplD_Qout(C_CHBUF_CPLD_TAG_BIT_TOP   downto C_CHBUF_CPLD_TAG_BIT_BOT);
792 
            pioCplD_Qout_to_TLP(C_DBUS_WIDTH+C_CPLD_LA_BIT_TOP    downto C_DBUS_WIDTH+C_CPLD_LA_BIT_BOT)     <= pioCplD_Qout(C_CHBUF_CPLD_LA_BIT_TOP    downto C_CHBUF_CPLD_LA_BIT_BOT);
793 
            -- no 2nd header Lo
794 
 
795 
            if pioCplD_Qout(C_CHBUF_LENG_BIT_TOP downto C_CHBUF_LENG_BIT_BOT)
796 
               = CONV_STD_LOGIC_VECTOR(1, C_TLP_FLD_WIDTH_OF_LENG)
797 
               then
798 
               pioCplD_Req_Min_Leng  <= '1';
799 
            else
800 
               pioCplD_Req_Min_Leng  <= '0';
801 
            end if;
802 
            if pioCplD_Qout(C_CHBUF_LENG_BIT_TOP downto C_CHBUF_LENG_BIT_BOT)
803 
               = CONV_STD_LOGIC_VECTOR(2, C_TLP_FLD_WIDTH_OF_LENG)
804 
               then
805 
               pioCplD_Req_2DW_Leng  <= '1';
806 
            else
807 
               pioCplD_Req_2DW_Leng  <= '0';
808 
            end if;
809 
 
810 
            -- Misc
811 
            Regs_Addr_pioCplD    <= pioCplD_Qout(C_CHBUF_PA_BIT_TOP downto C_CHBUF_PA_BIT_BOT);
812 
            mAddr_pioCplD        <= pioCplD_Qout(C_CHBUF_MA_BIT_TOP downto C_CHBUF_MA_BIT_BOT);  -- !! C_CHBUF_MA_BIT_BOT);
813 
            DDRAddr_pioCplD      <= pioCplD_Qout(C_CHBUF_DDA_BIT_TOP downto C_CHBUF_DDA_BIT_BOT);
814 
            BAR_pioCplD          <= pioCplD_Qout(C_CHBUF_CPLD_BAR_BIT_TOP downto C_CHBUF_CPLD_BAR_BIT_BOT);
815 
            pioCplD_is_0Leng     <= pioCplD_Qout(C_CHBUF_0LENG_BIT);
816 
         else
817 
            pioCplD_Req_Min_Leng <= '0';
818 
            pioCplD_Req_2DW_Leng <= '0';
819 
            pioCplD_Qout_to_TLP  <= (Others=>'0');
820 
            Regs_Addr_pioCplD    <= (Others=>'1');
821 
            mAddr_pioCplD        <= (Others=>'1');
822 
            DDRAddr_pioCplD      <= (Others=>'1');
823 
            BAR_pioCplD          <= (Others=>'1');
824 
            pioCplD_is_0Leng     <= '0';
825 
         end if;
826 
 
827 
 
828 
         if b1_Tx_Indicator(C_CHAN_INDEX_DMA_US)='1' then
829 
            usTlp_Qout_to_TLP  <= (Others=>'0');   -- must be 1st argument
830 
            -- 1st header HI
831 
            usTlp_Qout_to_TLP(C_TLP_FMT_BIT_TOP  downto C_TLP_FMT_BIT_BOT)   <= usTlp_Qout(C_CHBUF_FMT_BIT_TOP  downto C_CHBUF_FMT_BIT_BOT);
832 
            usTlp_Qout_to_TLP(C_TLP_TYPE_BIT_TOP downto C_TLP_TYPE_BIT_BOT)  <= C_ALL_ZEROS(C_TLP_TYPE_BIT_TOP  downto C_TLP_TYPE_BIT_BOT);
833 
            usTlp_Qout_to_TLP(C_TLP_TC_BIT_TOP   downto C_TLP_TC_BIT_BOT)    <= usTlp_Qout(C_CHBUF_TC_BIT_TOP   downto C_CHBUF_TC_BIT_BOT);
834 
            usTlp_Qout_to_TLP(C_TLP_ATTR_BIT_TOP downto C_TLP_ATTR_BIT_BOT)  <= usTlp_Qout(C_CHBUF_ATTR_BIT_TOP downto C_CHBUF_ATTR_BIT_BOT);
835 
            usTlp_Qout_to_TLP(C_TLP_LENG_BIT_TOP downto C_TLP_LENG_BIT_BOT)  <= usTlp_Qout(C_CHBUF_LENG_BIT_TOP downto C_CHBUF_LENG_BIT_BOT);
836 
            -- 1st header LO
837 
            usTlp_Qout_to_TLP(C_TLP_REQID_BIT_TOP   downto C_TLP_REQID_BIT_BOT)    <= localID;
838 
            usTlp_Qout_to_TLP(C_TLP_TAG_BIT_TOP     downto C_TLP_TAG_BIT_BOT)      <= usTlp_Qout(C_CHBUF_TAG_BIT_TOP   downto C_CHBUF_TAG_BIT_BOT);
839 
            usTlp_Qout_to_TLP(C_TLP_LAST_BE_BIT_TOP downto C_TLP_LAST_BE_BIT_BOT)  <= C_ALL_ONES(C_TLP_LAST_BE_BIT_TOP downto C_TLP_LAST_BE_BIT_BOT);
840 
            usTlp_Qout_to_TLP(C_TLP_1ST_BE_BIT_TOP  downto C_TLP_1ST_BE_BIT_BOT)   <= C_ALL_ONES(C_TLP_1ST_BE_BIT_TOP  downto C_TLP_1ST_BE_BIT_BOT);
841 
            -- 2nd header HI (Address)
842 
--            usTlp_Qout_to_TLP(2*C_DBUS_WIDTH-1 downto C_DBUS_WIDTH)    <= usTlp_Qout(C_CHBUF_HA_BIT_TOP downto C_CHBUF_HA_BIT_BOT);
843 
            if usTlp_Qout(C_CHBUF_FMT_BIT_BOT)='1' then  -- 4DW MWr
844 
               usTlp_Qout_to_TLP(2*C_DBUS_WIDTH-1 downto C_DBUS_WIDTH+32)    <= usTlp_Qout(C_CHBUF_HA_BIT_TOP downto C_CHBUF_HA_BIT_BOT+32);
845 
            else
846 
               usTlp_Qout_to_TLP(2*C_DBUS_WIDTH-1 downto C_DBUS_WIDTH+32)    <= usTlp_Qout(C_CHBUF_HA_BIT_TOP-32 downto C_CHBUF_HA_BIT_BOT);
847 
            end if;
848 
            -- 2nd header LO (Address)
849 
            usTlp_Qout_to_TLP(2*C_DBUS_WIDTH-1-32 downto C_DBUS_WIDTH)    <= usTlp_Qout(C_CHBUF_HA_BIT_TOP-32 downto C_CHBUF_HA_BIT_BOT);
850 
 
851 
            --
852 
            if usTlp_Qout(C_CHBUF_LENG_BIT_TOP downto C_CHBUF_LENG_BIT_BOT)
853 
               = CONV_STD_LOGIC_VECTOR(1, C_TLP_FLD_WIDTH_OF_LENG)
854 
               then
855 
               usTlp_Req_Min_Leng  <= '1';
856 
            else
857 
               usTlp_Req_Min_Leng  <= '0';
858 
            end if;
859 
            if usTlp_Qout(C_CHBUF_LENG_BIT_TOP downto C_CHBUF_LENG_BIT_BOT)
860 
               = CONV_STD_LOGIC_VECTOR(2, C_TLP_FLD_WIDTH_OF_LENG)
861 
               then
862 
               usTlp_Req_2DW_Leng  <= '1';
863 
            else
864 
               usTlp_Req_2DW_Leng  <= '0';
865 
            end if;
866 
 
867 
            -- Misc
868 
            DDRAddr_usTlp        <= usTlp_Qout(C_CHBUF_DDA_BIT_TOP downto C_CHBUF_DDA_BIT_BOT);
869 
            mAddr_usTlp          <= usTlp_Qout(C_CHBUF_MA_BIT_TOP downto C_CHBUF_MA_BIT_BOT);  -- !! C_CHBUF_MA_BIT_BOT);
870 
            AInc_usTlp           <= usTlp_Qout(C_CHBUF_AINC_BIT);
871 
            BAR_usTlp            <= usTlp_Qout(C_CHBUF_DMA_BAR_BIT_TOP downto C_CHBUF_DMA_BAR_BIT_BOT);
872 
 
873 
         else
874 
            usTlp_Req_Min_Leng   <= '0';
875 
            usTlp_Req_2DW_Leng   <= '0';
876 
            usTlp_Qout_to_TLP    <= (Others=>'0');
877 
            DDRAddr_usTlp        <= (Others=>'1');
878 
            mAddr_usTlp          <= (Others=>'1');
879 
            AInc_usTlp           <= '1';
880 
            BAR_usTlp            <= (Others=>'1');
881 
         end if;
882 
 
883 
 
884 
         if b1_Tx_Indicator(C_CHAN_INDEX_DMA_DS)='1' then
885 
            dsMRd_Qout_to_TLP  <= (Others=>'0');   -- must be 1st argument
886 
            -- 1st header HI
887 
            dsMRd_Qout_to_TLP(C_TLP_FMT_BIT_TOP  downto C_TLP_FMT_BIT_BOT)   <= dsMRd_Qout(C_CHBUF_FMT_BIT_TOP  downto C_CHBUF_FMT_BIT_BOT);
888 
            dsMRd_Qout_to_TLP(C_TLP_TYPE_BIT_TOP downto C_TLP_TYPE_BIT_BOT)  <= C_ALL_ZEROS(C_TLP_TYPE_BIT_TOP  downto C_TLP_TYPE_BIT_BOT);
889 
            dsMRd_Qout_to_TLP(C_TLP_TC_BIT_TOP   downto C_TLP_TC_BIT_BOT)    <= dsMRd_Qout(C_CHBUF_TC_BIT_TOP   downto C_CHBUF_TC_BIT_BOT);
890 
            dsMRd_Qout_to_TLP(C_TLP_ATTR_BIT_TOP downto C_TLP_ATTR_BIT_BOT)  <= dsMRd_Qout(C_CHBUF_ATTR_BIT_TOP downto C_CHBUF_ATTR_BIT_BOT);
891 
            dsMRd_Qout_to_TLP(C_TLP_LENG_BIT_TOP downto C_TLP_LENG_BIT_BOT)  <= dsMRd_Qout(C_CHBUF_LENG_BIT_TOP downto C_CHBUF_LENG_BIT_BOT);
892 
            -- 1st header LO
893 
            dsMRd_Qout_to_TLP(C_TLP_REQID_BIT_TOP   downto C_TLP_REQID_BIT_BOT)    <= localID;
894 
            dsMRd_Qout_to_TLP(C_TLP_TAG_BIT_TOP     downto C_TLP_TAG_BIT_BOT)      <= dsMRd_Qout(C_CHBUF_TAG_BIT_TOP   downto C_CHBUF_TAG_BIT_BOT);
895 
            dsMRd_Qout_to_TLP(C_TLP_LAST_BE_BIT_TOP downto C_TLP_LAST_BE_BIT_BOT)  <= C_ALL_ONES(C_TLP_LAST_BE_BIT_TOP downto C_TLP_LAST_BE_BIT_BOT);
896 
            dsMRd_Qout_to_TLP(C_TLP_1ST_BE_BIT_TOP  downto C_TLP_1ST_BE_BIT_BOT)   <= C_ALL_ONES(C_TLP_1ST_BE_BIT_TOP  downto C_TLP_1ST_BE_BIT_BOT);
897 
            -- 2nd header (Address)
898 
            dsMRd_Qout_to_TLP(2*C_DBUS_WIDTH-1 downto C_DBUS_WIDTH)    <= dsMRd_Qout(C_CHBUF_HA_BIT_TOP downto C_CHBUF_HA_BIT_BOT);
899 
 
900 
         else
901 
            dsMRd_Qout_to_TLP    <= (Others=>'0');
902 
         end if;
903 
 
904 
      end if;
905 
   end process;
906 
 
907 
 
908 
-- OR-wired channel buffer outputs
909 
   Trn_Qout_wire        <= Irpt_Qout_to_TLP
910 
                        or pioCplD_Qout_to_TLP
911 
                        or dsMRd_Qout_to_TLP
912 
                        or usTlp_Qout_to_TLP
913 
                        ;
914 
 
915 
-- ---------------------------------------------------
916 
-- State Machine: Tx output control
917 
--
918 
   TxFSM_OutputControl:
919 
   process ( trn_clk, trn_tx_Reset_n)
920 
   begin
921 
      if trn_tx_Reset_n = '0' then
922 
         trn_tsrc_rdy_n_i     <= '1';
923 
         trn_tsof_n_i         <= '1';
924 
         trn_teof_n_i         <= '1';
925 
         trn_td_i             <= (Others=>'0');
926 
         trn_trem_n_i         <= (Others=>'0');
927 
         TxTrn_State          <= St_TxIdle;
928 
 
929 
      elsif trn_clk'event and trn_clk = '1' then
930 
 
931 
         case TxTrn_State is
932 
 
933 
            when St_TxIdle    =>
934 
              trn_tsrc_rdy_n_i     <= '1';
935 
              trn_tsof_n_i         <= '1';
936 
              trn_teof_n_i         <= '1';
937 
              trn_td_i             <= (Others=>'0');
938 
              trn_trem_n_i         <= (Others=>'0');
939 
 
940 
              if ChBuf_has_Payload = '1' then
941 
                TxTrn_State          <= St_d_CmdAck;   -- St_d_CmdReq;
942 
              elsif ChBuf_No_Payload = '1' then
943 
                TxTrn_State          <= St_nd_Prepare;
944 
              else
945 
                TxTrn_State          <= St_TxIdle;
946 
              end if;
947 
 
948 
 
949 
            --- --- --- --- --- --- --- --- --- --- --- --- ---
950 
            --- --- --- --- --- --- --- --- --- --- --- --- ---
951 
 
952 
            when St_nd_Prepare    =>
953 
              trn_teof_n_i         <= '1';
954 
              if trn_tdst_rdy_n_i = '0' then
955 
                TxTrn_State          <= St_nd_Header2;
956 
                trn_tsrc_rdy_n_i     <= '0';
957 
                trn_tsof_n_i         <= '0';
958 
                trn_td_i             <= Trn_Qout_reg (C_DBUS_WIDTH-1 downto 0);
959 
              else
960 
                TxTrn_State          <= St_nd_Prepare;
961 
                trn_tsrc_rdy_n_i     <= '1';
962 
                trn_tsof_n_i         <= '1';
963 
                trn_td_i             <= (Others=>'0');
964 
              end if;
965 
 
966 
 
967 
            when St_nd_Header2    =>
968 
              trn_tsrc_rdy_n_i     <= '0';
969 
              if trn_tdst_rdy_n_i = '1' then
970 
                TxTrn_State          <= St_nd_Header2;
971 
                trn_tsof_n_i         <= trn_tsof_n_i;
972 
                trn_teof_n_i         <= '1';
973 
                trn_td_i             <= trn_td_i; -- Trn_Qout_reg (C_DBUS_WIDTH-1 downto 0);
974 
              else                                                    -- 3DW header
975 
                TxTrn_State          <= St_nd_HeaderLast;
976 
                trn_tsof_n_i         <= '1';
977 
                trn_teof_n_i         <= '0';
978 
                if Trn_Qout_reg (C_TLP_FMT_BIT_BOT) = '1' then       -- 4DW header
979 
                  trn_trem_n_i         <= X"00";
980 
                  trn_td_i             <= Trn_Qout_reg (C_DBUS_WIDTH*2-1 downto C_DBUS_WIDTH);
981 
                else
982 
                  trn_trem_n_i         <= X"0F";
983 
                  trn_td_i             <= Trn_Qout_reg (C_DBUS_WIDTH-1+32 downto C_DBUS_WIDTH) & X"00000000";
984 
                end if;
985 
              end if;
986 
 
987 
 
988 
            when St_nd_HeaderLast    =>
989 
              trn_tsof_n_i         <= '1';
990 
              if trn_tdst_rdy_n_i = '1' then
991 
                TxTrn_State          <= St_nd_HeaderLast;
992 
                trn_tsrc_rdy_n_i     <= '0';
993 
                trn_teof_n_i         <= '0';
994 
                trn_td_i             <= trn_td_i;
995 
                trn_trem_n_i         <= trn_trem_n_i;
996 
              else
997 
                TxTrn_State          <= St_nd_Arbitration;  -- St_TxIdle;
998 
                trn_tsrc_rdy_n_i     <= '1';
999 
                trn_teof_n_i         <= '1';
1000 
                trn_td_i             <= trn_td_i;
1001 
                trn_trem_n_i         <= trn_trem_n_i;
1002 
              end if;
1003 
 
1004 
            when St_nd_Arbitration    =>
1005 
              trn_tsof_n_i         <= '1';
1006 
              TxTrn_State          <= St_TxIdle;
1007 
              trn_tsrc_rdy_n_i     <= '1';
1008 
              trn_teof_n_i         <= '1';
1009 
              trn_td_i             <= trn_td_i;
1010 
              trn_trem_n_i         <= (OTHERS=>'0');
1011 
 
1012 
 
1013 
            --- --- --- --- --- --- --- --- --- --- --- --- ---
1014 
            --- --- --- --- --- --- --- --- --- --- --- --- ---
1015 
 
1016 
--            when St_d_CmdReq    =>
1017 
--              if RdCmd_Ack = '1' then
1018 
--                RdCmd_Req            <= '0';
1019 
--                TxTrn_State          <= St_d_CmdAck;
1020 
--              else
1021 
--                RdCmd_Req            <= '1';
1022 
--                TxTrn_State          <= St_d_CmdReq;
1023 
--              end if;
1024 
 
1025 
 
1026 
            when St_d_CmdAck    =>
1027 
              trn_teof_n_i         <= '1';
1028 
              if mbuf_Empty = '0' and trn_tdst_rdy_n_i = '0' then
1029 
                trn_tsrc_rdy_n_i     <= '1';
1030 
                trn_tsof_n_i         <= '1';
1031 
                trn_td_i             <= (Others=>'0');
1032 
                TxTrn_State          <= St_d_Header0;
1033 
              else
1034 
                trn_tsrc_rdy_n_i     <= '1';
1035 
                trn_tsof_n_i         <= '1';
1036 
                trn_td_i             <= (Others=>'0');
1037 
                TxTrn_State          <= St_d_CmdAck;
1038 
              end if;
1039 
 
1040 
 
1041 
            when St_d_Header0    =>
1042 
              if trn_tdst_rdy_n_i = '0' then
1043 
                trn_tsrc_rdy_n_i     <= '0';
1044 
                trn_tsof_n_i         <= '0';
1045 
                trn_teof_n_i         <= '1';
1046 
                trn_td_i             <= Trn_Qout_reg (C_DBUS_WIDTH-1 downto 0);
1047 
                TxTrn_State          <= St_d_Header2;
1048 
              else
1049 
                trn_tsrc_rdy_n_i     <= '1';
1050 
                trn_tsof_n_i         <= '1';
1051 
                trn_teof_n_i         <= '1';
1052 
                trn_td_i             <= trn_td_i;
1053 
                TxTrn_State          <= St_d_Header0;
1054 
              end if;
1055 
 
1056 
 
1057 
            when St_d_Header2    =>
1058 
              trn_tsrc_rdy_n_i     <= '0';
1059 
              trn_trem_n_i         <= (OTHERS=>'0');
1060 
              if trn_tdst_rdy_n_i = '1' then
1061 
                TxTrn_State          <= St_d_Header2;
1062 
                trn_td_i             <= Trn_Qout_reg (C_DBUS_WIDTH-1 downto 0);
1063 
                trn_tsof_n_i         <= '0';
1064 
                trn_teof_n_i         <= '1';
1065 
              elsif Trn_Qout_reg (C_TLP_FMT_BIT_BOT) = '1' then   -- 4DW header
1066 
                TxTrn_State          <= St_d_1st_Data;  -- St_d_HeaderPlus;
1067 
                trn_td_i             <= Trn_Qout_reg (C_DBUS_WIDTH*2-1 downto C_DBUS_WIDTH);
1068 
                trn_tsof_n_i         <= '1';
1069 
                trn_teof_n_i         <= '1';
1070 
              else                                                -- 3DW header
1071 
                trn_td_i             <= Trn_Qout_reg (C_DBUS_WIDTH*2-1 downto C_DBUS_WIDTH+32)
1072 
                                      & mbuf_Qout(C_DBUS_WIDTH-1-32 downto 0);
1073 
                trn_tsof_n_i         <= '1';
1074 
                trn_teof_n_i         <= mbuf_Qout(C_DBUS_WIDTH);
1075 
                if mbuf_Qout(C_DBUS_WIDTH) = '0' then
1076 
                  TxTrn_State          <= St_d_Tail_chk;
1077 
                else
1078 
                  TxTrn_State          <= St_d_1st_Data;
1079 
                end if;
1080 
              end if;
1081 
 
1082 
 
1083 
            when St_d_1st_Data    =>
1084 
              if trn_tdst_rdy_n_i = '1' then
1085 
                TxTrn_State          <= St_d_1st_Data;
1086 
                trn_teof_n_i         <= '1';
1087 
                trn_td_i             <= trn_td_i;
1088 
                trn_tsrc_rdy_n_i     <= '0';
1089 
              elsif mbuf_Qout(C_DBUS_WIDTH) = '0' then
1090 
                TxTrn_State          <= St_d_Tail_chk;
1091 
                trn_teof_n_i         <= '0';
1092 
                trn_trem_n_i         <= X"0" & mbuf_Qout(70) & mbuf_Qout(70)
1093 
                                             & mbuf_Qout(70) & mbuf_Qout(70);
1094 
                trn_td_i             <= mbuf_Qout(C_DBUS_WIDTH-1 downto 0);
1095 
                trn_tsrc_rdy_n_i     <= not mbuf_Qvalid; -- '0';
1096 
              elsif mbuf_Qvalid = '0' then
1097 
                TxTrn_State          <= St_d_Payload_used;
1098 
                trn_teof_n_i         <= '1';
1099 
                trn_td_i             <= mbuf_Qout(C_DBUS_WIDTH-1 downto 0);
1100 
                trn_tsrc_rdy_n_i     <= '1';
1101 
              else
1102 
                TxTrn_State          <= St_d_Payload;
1103 
                trn_teof_n_i         <= '1';
1104 
                trn_td_i             <= mbuf_Qout(C_DBUS_WIDTH-1 downto 0);
1105 
                trn_tsrc_rdy_n_i     <= '0';
1106 
              end if;
1107 
 
1108 
 
1109 
            when St_d_Payload    =>
1110 
              if trn_tdst_rdy_n_i='1' then
1111 
                trn_td_i             <= trn_td_i;
1112 
                trn_teof_n_i         <= trn_teof_n_i;
1113 
                trn_trem_n_i         <= trn_trem_n_i;
1114 
                trn_tsrc_rdy_n_i     <= '0';
1115 
                if mbuf_Qout(C_DBUS_WIDTH) = '0' then
1116 
                  TxTrn_State          <= St_d_Tail;
1117 
                elsif mbuf_Qvalid='1' then
1118 
                  TxTrn_State          <= St_d_Payload;
1119 
                else
1120 
                  TxTrn_State          <= St_d_Payload_used;
1121 
                end if;
1122 
              else
1123 
                trn_td_i             <= mbuf_Qout(C_DBUS_WIDTH-1 downto 0);
1124 
                trn_teof_n_i         <= mbuf_Qout(C_DBUS_WIDTH);
1125 
                trn_tsrc_rdy_n_i     <= mbuf_Qout(C_DBUS_WIDTH) and not mbuf_Qvalid;
1126 
                if mbuf_Qout(C_DBUS_WIDTH) = '0' then
1127 
                  TxTrn_State          <= St_d_Tail_chk;
1128 
                  trn_trem_n_i         <= X"0" & mbuf_Qout(70) & mbuf_Qout(70)
1129 
                                               & mbuf_Qout(70) & mbuf_Qout(70);
1130 
                elsif mbuf_Qvalid='1' then
1131 
                  trn_trem_n_i         <= (OTHERS=>'0');
1132 
                  TxTrn_State          <= St_d_Payload;
1133 
                else
1134 
                  trn_trem_n_i         <= (OTHERS=>'0');
1135 
                  TxTrn_State          <= St_d_Payload_used;
1136 
                end if;
1137 
              end if;
1138 
 
1139 
 
1140 
            when St_d_Payload_used    =>
1141 
              if trn_tsrc_rdy_n_i='0' then
1142 
                trn_td_i             <= mbuf_Qout(C_DBUS_WIDTH-1 downto 0);
1143 
                trn_tsrc_rdy_n_i     <= not mbuf_Qvalid and not trn_tdst_rdy_n_i;
1144 
                if mbuf_Qout(C_DBUS_WIDTH) = '0' then
1145 
                  trn_teof_n_i         <= '0';
1146 
                  trn_trem_n_i         <= X"0" & mbuf_Qout(70) & mbuf_Qout(70)
1147 
                                               & mbuf_Qout(70) & mbuf_Qout(70);
1148 
                else
1149 
                  trn_teof_n_i         <= '1';
1150 
                  trn_trem_n_i         <= (OTHERS=>'0');
1151 
                end if;
1152 
                if mbuf_Qvalid='1' then
1153 
                  TxTrn_State          <= St_d_Payload;
1154 
                else
1155 
                  TxTrn_State          <= St_d_Payload_used;
1156 
                end if;
1157 
              elsif mbuf_Qvalid='1' then
1158 
                  trn_td_i             <= mbuf_Qout(C_DBUS_WIDTH-1 downto 0);
1159 
                  trn_tsrc_rdy_n_i     <= '0';
1160 
                  if mbuf_Qout(C_DBUS_WIDTH) = '0' then
1161 
                    trn_teof_n_i         <= '0';
1162 
                    trn_trem_n_i         <= X"0" & mbuf_Qout(70) & mbuf_Qout(70)
1163 
                                                 & mbuf_Qout(70) & mbuf_Qout(70);
1164 
                  else
1165 
                    trn_teof_n_i         <= '1';
1166 
                    trn_trem_n_i         <= (OTHERS=>'0');
1167 
                  end if;
1168 
                  if mbuf_Qout(C_DBUS_WIDTH) = '0' then
1169 
                    TxTrn_State          <= St_d_Tail_chk;
1170 
                  else
1171 
                    TxTrn_State          <= St_d_Payload;
1172 
                  end if;
1173 
              else
1174 
                  TxTrn_State          <= St_d_Payload_used;
1175 
                  trn_td_i             <= trn_td_i;
1176 
                  trn_teof_n_i         <= trn_teof_n_i;
1177 
                  trn_trem_n_i         <= trn_trem_n_i;
1178 
                  trn_tsrc_rdy_n_i     <= '1';
1179 
              end if;
1180 
 
1181 
 
1182 
            when St_d_Tail    =>
1183 
              trn_tsrc_rdy_n_i     <= '0';
1184 
              if trn_tdst_rdy_n_i = '1' then
1185 
                TxTrn_State          <= St_d_Tail;
1186 
                trn_teof_n_i         <= trn_teof_n_i;
1187 
                trn_trem_n_i         <= trn_trem_n_i;
1188 
                trn_td_i             <= trn_td_i;
1189 
              else
1190 
                TxTrn_State          <= St_d_Tail_chk;
1191 
                trn_teof_n_i         <= '0';
1192 
                trn_trem_n_i         <= X"0" & mbuf_Qout(70) & mbuf_Qout(70)
1193 
                                             & mbuf_Qout(70) & mbuf_Qout(70);
1194 
                trn_td_i             <= mbuf_Qout(C_DBUS_WIDTH-1 downto 0);
1195 
              end if;
1196 
 
1197 
 
1198 
            when St_d_Tail_chk    =>
1199 
              if trn_tdst_rdy_n_i = '1' then
1200 
                trn_tsrc_rdy_n_i     <= '0';
1201 
                trn_teof_n_i         <= '0';
1202 
                trn_trem_n_i         <= trn_trem_n_i;
1203 
                trn_td_i             <= trn_td_i;
1204 
                TxTrn_State          <= St_d_Tail_chk;
1205 
              elsif take_an_Arbitration = '1' then
1206 
                trn_tsrc_rdy_n_i     <= '1';
1207 
                trn_teof_n_i         <= '1';
1208 
                trn_td_i             <= (Others=>'0');
1209 
                trn_trem_n_i         <= (Others=>'0');
1210 
                TxTrn_State          <= St_d_AfterChk;
1211 
              else
1212 
                trn_tsrc_rdy_n_i     <= '1';
1213 
                trn_teof_n_i         <= '1';
1214 
                trn_td_i             <= (Others=>'0');
1215 
                trn_trem_n_i         <= (Others=>'0');
1216 
                TxTrn_State          <= St_TxIdle;
1217 
              end if;
1218 
 
1219 
 
1220 
            when St_d_AfterChk    =>
1221 
              trn_tsrc_rdy_n_i     <= '1';
1222 
              trn_teof_n_i         <= '1';
1223 
              trn_td_i             <= (Others=>'0');
1224 
              trn_trem_n_i         <= (Others=>'0');
1225 
              TxTrn_State          <= St_TxIdle;
1226 
 
1227 
 
1228 
            when Others    =>
1229 
               trn_tsrc_rdy_n_i     <= '1';
1230 
               trn_tsof_n_i         <= '1';
1231 
               trn_teof_n_i         <= '1';
1232 
               trn_td_i             <= (Others=>'0');
1233 
               trn_trem_n_i         <= (Others=>'0');
1234 
               TxTrn_State          <= St_TxIdle;
1235 
 
1236 
         end case;
1237 
 
1238 
 
1239 
      end if;
1240 
   end process;
1241 
 
1242 
 
1243 
-- ---------------------------------------------------
1244 
-- State Machine output: mbuf_RE_ok
1245 
--
1246 
   TxFSM_Output_mbuf_RE_ok:
1247 
   process ( trn_clk, trn_tx_Reset_n)
1248 
   begin
1249 
      if trn_tx_Reset_n = '0' then
1250 
         mbuf_RE_ok     <= '0';
1251 
 
1252 
      elsif trn_clk'event and trn_clk = '1' then
1253 
 
1254 
         case TxTrn_State is
1255 
 
1256 
            when St_TxIdle    =>
1257 
              mbuf_RE_ok           <= '0';
1258 
 
1259 
            when St_d_CmdAck    =>
1260 
              mbuf_RE_ok           <= not mbuf_Empty and not trn_tdst_rdy_n_i;
1261 
 
1262 
            when St_d_Header0    =>
1263 
              mbuf_RE_ok           <= not Trn_Qout_reg(C_TLP_FMT_BIT_BOT) and not trn_tdst_rdy_n_i;      -- '1'; -- 4DW
1264 
 
1265 
            when St_d_Header2    =>
1266 
              if Trn_Qout_reg(C_TLP_FMT_BIT_BOT)='1' then          -- 4DW header
1267 
                mbuf_RE_ok           <= not trn_tdst_rdy_n_i;
1268 
              elsif Payload_rd_count=CONV_STD_LOGIC_VECTOR(0, C_TLP_FLD_WIDTH_OF_LENG) then
1269 
                mbuf_RE_ok           <= '0';
1270 
              elsif Payload_rd_count=CONV_STD_LOGIC_VECTOR(1, C_TLP_FLD_WIDTH_OF_LENG) then
1271 
                mbuf_RE_ok           <= not mbuf_RE or mbuf_Empty;
1272 
              else                                                 -- 3DW header
1273 
                mbuf_RE_ok           <= not trn_tsrc_rdy_n_i;  -- or trn_tdst_rdy_n_i;
1274 
              end if;
1275 
 
1276 
            when St_d_1st_Data    =>
1277 
              if Payload_rd_count=CONV_STD_LOGIC_VECTOR(0, C_TLP_FLD_WIDTH_OF_LENG) then
1278 
                mbuf_RE_ok           <= '0';
1279 
              elsif Payload_rd_count=CONV_STD_LOGIC_VECTOR(1, C_TLP_FLD_WIDTH_OF_LENG) then
1280 
                mbuf_RE_ok           <= not mbuf_RE or mbuf_Empty;
1281 
              else
1282 
                mbuf_RE_ok           <= '1';
1283 
              end if;
1284 
 
1285 
            when St_d_Payload    =>
1286 
              if Payload_rd_count=CONV_STD_LOGIC_VECTOR(0, C_TLP_FLD_WIDTH_OF_LENG) then
1287 
                mbuf_RE_ok           <= '0';
1288 
              elsif Payload_rd_count=CONV_STD_LOGIC_VECTOR(1, C_TLP_FLD_WIDTH_OF_LENG) then
1289 
                mbuf_RE_ok           <= not mbuf_RE or mbuf_Empty;
1290 
              else
1291 
                mbuf_RE_ok           <= '1';
1292 
              end if;
1293 
 
1294 
            when St_d_Payload_used    =>
1295 
              if Payload_rd_count=CONV_STD_LOGIC_VECTOR(0, C_TLP_FLD_WIDTH_OF_LENG) then
1296 
                mbuf_RE_ok           <= '0';
1297 
              elsif Payload_rd_count=CONV_STD_LOGIC_VECTOR(1, C_TLP_FLD_WIDTH_OF_LENG) then
1298 
                mbuf_RE_ok           <= not mbuf_RE or mbuf_Empty;
1299 
              else
1300 
                mbuf_RE_ok           <= '1';
1301 
              end if;
1302 
 
1303 
            when Others    =>
1304 
               mbuf_RE_ok           <= '0';
1305 
 
1306 
         end case;
1307 
 
1308 
      end if;
1309 
   end process;
1310 
 
1311 
 
1312 
-- ---------------------------------------------------
1313 
-- State Machine output: Payload_rd_count
1314 
--
1315 
   TxFSM_Output_Payload_rd_count:
1316 
   process ( trn_clk, trn_tx_Reset_n)
1317 
   begin
1318 
      if trn_tx_Reset_n = '0' then
1319 
         Payload_rd_count     <= (Others=>'0');
1320 
 
1321 
      elsif trn_clk'event and trn_clk = '1' then
1322 
 
1323 
         case TxTrn_State is
1324 
 
1325 
            when St_d_CmdAck    =>
1326 
              if Trn_Qout_reg(C_TLP_LENG_BIT_BOT)='0'              -- Length[0]
1327 
                 and Trn_Qout_reg(C_TLP_FMT_BIT_BOT)='1'           -- 4-DW
1328 
                 then
1329 
                Payload_rd_count     <=  '0'&Trn_Qout_wire(C_TLP_FLD_WIDTH_OF_LENG-1+32 downto 32+1);
1330 
              else
1331 
                Payload_rd_count     <=  ('0'&Trn_Qout_wire(C_TLP_FLD_WIDTH_OF_LENG-1+32 downto 32+1)) + '1';
1332 
              end if;
1333 
 
1334 
            when Others    =>
1335 
              if mbuf_RE='1' and mbuf_Empty='0' then
1336 
                Payload_rd_count     <=  Payload_rd_count - '1';
1337 
              else
1338 
                Payload_rd_count     <=  Payload_rd_count;
1339 
              end if;
1340 
 
1341 
         end case;
1342 
 
1343 
      end if;
1344 
   end process;
1345 
 
1346 
 
1347 
-- ---------------------------------------------------
1348 
-- State Machine output: take_an_Arbitration
1349 
--
1350 
   TxFSM_take_an_Arbitration:
1351 
   process ( trn_clk, trn_tx_Reset_n)
1352 
   begin
1353 
      if trn_tx_Reset_n = '0' then
1354 
         take_an_Arbitration     <= '0';
1355 
         Trn_Qout_reg            <= (Others=>'0');
1356 
 
1357 
      elsif trn_clk'event and trn_clk = '1' then
1358 
 
1359 
         case TxTrn_State is
1360 
 
1361 
            when St_nd_Header2    =>
1362 
              if trn_tdst_rdy_n_i = '0' then
1363 
                take_an_Arbitration  <= '1';
1364 
              else
1365 
                take_an_Arbitration  <= '0';
1366 
              end if;
1367 
 
1368 
            when St_d_Header2    =>             -- //  St_d_Header0
1369 
              if trn_tdst_rdy_n_i = '0' then
1370 
                take_an_Arbitration  <= '1';
1371 
              else
1372 
                take_an_Arbitration  <= '0';
1373 
              end if;
1374 
 
1375 
            when Others    =>
1376 
               take_an_Arbitration  <= '0';
1377 
 
1378 
         end case;
1379 
 
1380 
         if Read_aBuffer_r2='1' then
1381 
           Trn_Qout_reg         <= Trn_Qout_wire;
1382 
         else
1383 
           Trn_Qout_reg         <= Trn_Qout_reg;
1384 
         end if;
1385 
 
1386 
      end if;
1387 
   end process;
1388 
 
1389 
 
1390 
-- ---------------------------------------------------
1391 
-- State Machine: Arbitration requests data
1392 
--
1393 
   TxFSM_arq_State:
1394 
   process ( trn_clk, trn_tx_Reset_n)
1395 
   begin
1396 
      if trn_tx_Reset_n = '0' then
1397 
         RdNumber             <= (Others=>'0');
1398 
         RdNumber_eq_One      <= '0';
1399 
         RdNumber_eq_Two      <= '0';
1400 
         StartAddr            <= (Others=>'0');
1401 
         Shift_1st_QWord      <= '0';
1402 
         is_CplD              <= '0';
1403 
         BAR_value            <= (Others=>'0');
1404 
         RdCmd_Req            <= '0';
1405 
         arq_State            <= StA_idle;
1406 
 
1407 
      elsif trn_clk'event and trn_clk = '1' then
1408 
 
1409 
         case arq_State is
1410 
 
1411 
            when StA_idle    =>
1412 
              if ChBuf_has_Payload = '1' and Read_aBuffer_r2='1' then
1413 
                RdNumber             <=  Trn_Qout_wire (C_TLP_FLD_WIDTH_OF_LENG-1+32 downto 32);
1414 
                RdNumber_eq_One      <=  pioCplD_Req_Min_Leng or usTlp_Req_Min_Leng;
1415 
                RdNumber_eq_Two      <=  pioCplD_Req_2DW_Leng or usTlp_Req_2DW_Leng;
1416 
                RdCmd_Req            <=  '1';
1417 
                if pioCplD_is_0Leng='1' then
1418 
                  BAR_value            <=  '0' & CONV_STD_LOGIC_VECTOR(CINT_REGS_SPACE_BAR, C_ENCODE_BAR_NUMBER-1);
1419 
                  StartAddr            <=  C_ALL_ONES(C_DBUS_WIDTH-1 downto 0) ;
1420 
                  Shift_1st_QWord      <=  '1';
1421 
                  is_CplD              <=  '0';
1422 
                elsif BAR_pioCplD=CONV_STD_LOGIC_VECTOR(CINT_DDR_SPACE_BAR, C_ENCODE_BAR_NUMBER) then
1423 
                  BAR_value            <=  '0' & BAR_pioCplD(C_ENCODE_BAR_NUMBER-2 downto 0);
1424 
                  StartAddr            <=  (C_ALL_ONES(C_DBUS_WIDTH-1 downto C_DDR_IAWIDTH) & DDRAddr_pioCplD);
1425 
                  Shift_1st_QWord      <=  '1';
1426 
                  is_CplD              <=  '1';
1427 
                elsif BAR_pioCplD=CONV_STD_LOGIC_VECTOR(CINT_FIFO_SPACE_BAR, C_ENCODE_BAR_NUMBER) then
1428 
                  BAR_value            <=  '0' & BAR_pioCplD(C_ENCODE_BAR_NUMBER-2 downto 0);
1429 
                  StartAddr            <=  (C_ALL_ONES(C_DBUS_WIDTH-1 downto C_PRAM_AWIDTH+2) & mAddr_pioCplD);
1430 
                  Shift_1st_QWord      <=  '1';
1431 
                  is_CplD              <=  '1';
1432 
                elsif BAR_usTlp=CONV_STD_LOGIC_VECTOR(CINT_DDR_SPACE_BAR, C_ENCODE_BAR_NUMBER) then
1433 
                  BAR_value            <=  '0' & BAR_usTlp(C_ENCODE_BAR_NUMBER-2 downto 0);
1434 
                  StartAddr            <=  C_ALL_ONES(C_DBUS_WIDTH-1 downto C_DDR_IAWIDTH) & DDRAddr_usTlp;
1435 
                  Shift_1st_QWord      <=  not usTlp_Qout_to_TLP(C_TLP_FMT_BIT_BOT);
1436 
                  is_CplD              <=  '0';
1437 
                elsif BAR_usTlp=CONV_STD_LOGIC_VECTOR(CINT_FIFO_SPACE_BAR, C_ENCODE_BAR_NUMBER) then
1438 
                  BAR_value            <=  '0' & BAR_usTlp(C_ENCODE_BAR_NUMBER-2 downto 0);
1439 
                  StartAddr            <=  C_ALL_ONES(C_DBUS_WIDTH-1 downto C_DDR_IAWIDTH) & DDRAddr_usTlp;
1440 
                  Shift_1st_QWord      <=  not usTlp_Qout_to_TLP(C_TLP_FMT_BIT_BOT);
1441 
                  is_CplD              <=  '0';
1442 
                else
1443 
                  BAR_value            <=  '0' & BAR_pioCplD(C_ENCODE_BAR_NUMBER-2 downto 0);
1444 
                  StartAddr            <=  (C_ALL_ONES(C_DBUS_WIDTH-1 downto C_EP_AWIDTH) & Regs_Addr_pioCplD);
1445 
                  Shift_1st_QWord      <=  '1';
1446 
                  is_CplD              <=  '0';
1447 
                end if;
1448 
                arq_State            <=  StA_req;
1449 
              else
1450 
                RdNumber             <=  RdNumber;
1451 
                RdNumber_eq_One      <=  RdNumber_eq_One;
1452 
                RdNumber_eq_Two      <=  RdNumber_eq_Two;
1453 
                RdCmd_Req            <=  '0';
1454 
                BAR_value            <=  BAR_value;
1455 
                StartAddr            <=  StartAddr;
1456 
                Shift_1st_QWord      <=  Shift_1st_QWord;
1457 
                is_CplD              <=  is_CplD;
1458 
                arq_State            <=  StA_idle;
1459 
              end if;
1460 
 
1461 
            when StA_req    =>
1462 
              if RdCmd_Ack = '1' then
1463 
                RdCmd_Req          <= '0';
1464 
                arq_State          <= StA_idle;
1465 
              else
1466 
                RdCmd_Req          <= '1';
1467 
                arq_State          <= StA_req;
1468 
              end if;
1469 
 
1470 
            when Others    =>
1471 
              RdNumber           <=  RdNumber;
1472 
              RdNumber_eq_One    <=  RdNumber_eq_One;
1473 
              RdNumber_eq_Two    <=  RdNumber_eq_Two;
1474 
              RdCmd_Req          <=  '0';
1475 
              BAR_value          <=  BAR_value;
1476 
              StartAddr          <=  StartAddr;
1477 
              Shift_1st_QWord    <=  Shift_1st_QWord;
1478 
              is_CplD            <=  is_CplD;
1479 
              arq_State          <=  StA_idle;
1480 
 
1481 
         end case;
1482 
 
1483 
      end if;
1484 
   end process;
1485 
 
1486 
 
1487 
---------------------------------------------------------------------------------
1488 
-- Synchronous Accumulation: us_DMA_Bytes
1489 
--
1490 
   Synch_Acc_us_DMA_Bytes:
1491 
   process ( trn_clk )
1492 
   begin
1493 
      if trn_clk'event and trn_clk = '1' then
1494 
        us_DMA_Bytes_i   <= '0' & trn_td_i(32+C_TLP_FLD_WIDTH_OF_LENG-1 downto 32) & "00";
1495 
        if trn_td_i(C_TLP_FMT_BIT_TOP) = '1'
1496 
           and trn_td_i(C_TLP_TYPE_BIT_TOP downto C_TLP_TYPE_BIT_BOT)
1497 
               = C_ALL_ZEROS(C_TLP_TYPE_BIT_TOP downto C_TLP_TYPE_BIT_BOT) then
1498 
           us_DMA_Bytes_Add_i  <=  not trn_tsof_n_i
1499 
                               and not trn_tsrc_rdy_n_i
1500 
                               and not trn_tdst_rdy_n_i
1501 
                               ;
1502 
        else
1503 
           us_DMA_Bytes_Add_i  <= '0';
1504 
        end if;
1505 
      end if;
1506 
   end process;
1507 
 
1508 
 
1509 
end architecture Behavioral;

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