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-------------------------------------------------------------------
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--!
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--! PDP-8 Processor
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--!
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--! \brief
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--! CPU Type Definitions
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--!
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--! \details
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--!
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--!
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--! \file
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--! cpu_types.vhd
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--!
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--! \author
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--! Rob Doyle - doyle (at) cox (dot) net
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--!
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--------------------------------------------------------------------
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--
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-- Copyright (C) 2009, 2011, 2012 Rob Doyle
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--
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-- This source file may be used and distributed without
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-- restriction provided that this copyright statement is not
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-- removed from the file and that any derivative work contains
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-- the original copyright notice and the associated disclaimer.
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--
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-- This source file is free software; you can redistribute it
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-- and/or modify it under the terms of the GNU Lesser General
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-- Public License as published by the Free Software Foundation;
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-- version 2.1 of the License.
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--
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-- This source is distributed in the hope that it will be
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-- useful, but WITHOUT ANY WARRANTY; without even the implied
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-- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
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-- PURPOSE. See the GNU Lesser General Public License for more
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-- details.
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--
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-- You should have received a copy of the GNU Lesser General
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-- Public License along with this source; if not, download it
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-- from http://www.gnu.org/licenses/lgpl.txt
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--
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--------------------------------------------------------------------
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--
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-- Comments are formatted for doxygen
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--
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library ieee; --! IEEE Library
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use ieee.std_logic_1164.all; --! IEEE 1164
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use ieee.numeric_std.all; --! IEEE Numeric Standard
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--
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--! CPU Type Definition Package
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--
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package cpu_types is
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--!
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--! Type definitions common to everything.
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--!
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subtype addr_t is std_logic_vector( 0 to 11); --! MA[0:11]
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subtype xaddr_t is std_logic_vector( 0 to 14); --! EMA[0:2] & MA[0:11]
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subtype data_t is std_logic_vector( 0 to 11); --! XD[0:11]
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subtype ldata_t is std_logic_vector( 0 to 12); --! Data with Link bit
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subtype field_t is std_logic_vector( 0 to 2); --! Address Field
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subtype sf_t is std_logic_vector( 0 to 6); --! Save Field Type
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subtype page_t is std_logic_vector( 0 to 4); --! Address Page
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subtype word_t is std_logic_vector( 0 to 6); --! Address Word
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subtype sc_t is std_logic_vector( 0 to 4); --! SC Reg Type
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subtype swDATA_t is data_t; --! Switch Data type
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subtype eaeir_t is std_logic_vector( 0 to 3); --! EAE IR
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subtype eae_t is std_logic_vector( 0 to 24); --! EAE Register
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subtype devNUM_t is std_logic_vector( 0 to 5); --! IOT Device Number
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subtype devOP_t is std_logic_vector( 0 to 2); --! IOT OP Code
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--!
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--! OPCODES
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--!
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subtype opcode_t is std_logic_vector(0 to 2);
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constant opAND : opcode_t := "000"; --! AND Opcode
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constant opTAD : opcode_t := "001"; --! TAD Opcode
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constant opISZ : opcode_t := "010"; --! ISZ Opcode
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constant opDCA : opcode_t := "011"; --! DCA Opcode
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constant opJMS : opcode_t := "100"; --! JMS Opcode
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constant opJMP : opcode_t := "101"; --! JMP Opcode
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constant opIOT : opcode_t := "110"; --! IOT Opcode
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constant opOPR : opcode_t := "111"; --! OPR Opcode
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--!
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--! MRI Addressing Modes
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--!
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subtype amode_t is std_logic_vector(0 to 1);
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constant amDZ : amode_t := "00"; --! Direct, Zero Page
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constant amDC : amode_t := "01"; --! Direct, Current Page
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constant amIZ : amode_t := "10"; --! Indirect, Zero Page
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constant amIC : amode_t := "11"; --! Indirect, Currnt Page
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--!
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--! EAE Opcodes
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--!
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constant opEAENOP : EAEIR_t := "0000"; --! EAE NOP Opcode
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constant opEAEACS : EAEIR_t := "0001"; --! EAE ACS Opcode
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constant opEAEMUY : EAEIR_t := "0010"; --! EAE MUY Opcode
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constant opEAEDVI : EAEIR_t := "0011"; --! EAE DVI Opcode
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constant opEAENMI : EAEIR_t := "0100"; --! EAE NMI Opcode
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constant opEAESHL : EAEIR_t := "0101"; --! EAE SHL Opcode
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constant opEAEASR : EAEIR_t := "0110"; --! EAE ASR Opcode
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constant opEAELSR : EAEIR_t := "0111"; --! EAE LSR Opcode
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constant opEAESCA : EAEIR_t := "1000"; --! EAE SCA Opcode
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constant opEAEDAD : EAEIR_t := "1001"; --! EAE DAD Opcode
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constant opEAEDST : EAEIR_t := "1010"; --! EAE DST Opcode
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constant opEAEDPSZ : EAEIR_t := "1100"; --! EAE DPSZ Opcode
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constant opEAEDPIC : EAEIR_t := "1101"; --! EAE DPIC Opcode
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constant opEAEDCM : EAEIR_t := "1110"; --! EAE DCM Opcode
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constant opEAESAM : EAEIR_t := "1111"; --! EAE SAM Opcode
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--!
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--! CPU Configuration
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--!
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subtype swCPU_t is std_logic_vector(0 to 3);
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constant swPDP8 : swCPU_t := "0000"; --! Straight Eight
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constant swPDP8S : swCPU_t := "0001"; --! PDP-8/S
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constant swPDP8I : swCPU_t := "0010"; --! PDP-8/I
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constant swPDP8L : swCPU_t := "0011"; --! PDP-8/L
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constant swPDP8E : swCPU_t := "0100"; --! PDP-8/E/F/M
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constant swPDP8F : swCPU_t := "0100"; --! PDP-8/E/F/M
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constant swPDP8M : swCPU_t := "0100"; --! PDP-8/E/F/M
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constant swPDP8A : swCPU_t := "0101"; --! PDP-8/A
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constant swHD6100 : swCPU_t := "0110"; --! HD6100
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constant swHD6120 : swCPU_t := "0111"; --! HD6120
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--!
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--! Device Control (c0, c1) Pins
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--! C1 high causes read after write
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--! C0 high causes AC to be cleared
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--!
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subtype devc_t is std_logic_vector(0 to 1);
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constant devWR : devc_t := "00"; --! Device WR
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constant devRD : devc_t := "01"; --! Device Read with OR
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constant devWRCLR : devc_t := "10"; --! Device Write with clear
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constant devRDCLR : devc_t := "11"; --! Device Read with clear
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--!
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--! Bus Operation
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--!
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type busOP_t is (
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busopNOP, --! IDLE/NOP
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busopRESET, --! Reset
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busopIOCLR, --! IOCLR
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busopFETCHaddr, --! Instruction Fetch Addr
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busopFETCHdata, --! Instruction Fetch Data
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busopWRIB, --! Write with XMA = IB
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busopRDIBaddr, --! Read addr with XMA = IB
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busopRDIBdata, --! Read data with XMA = IB
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busopWRIF, --! Write with XMA = IF
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busopRDIFaddr, --! Read addr with XMA = IF
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busopRDIFdata, --! Read data with XMA = IF
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busopWRDF, --! Write with XMA = DF
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busopRDDFaddr, --! Read addr with XMA = DF
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busopRDDFdata, --! Read data with XMA = DF
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busopWRZF, --! Write with XMA = 0
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busopRDZFaddr, --! Read addr with XMA = 0
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busopRDZFdata, --! Read data with XMA = 0
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busopWRIOT, --! IOT Write
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busopRDIOT --! IOT Read
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);
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--!
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--! Options Configuration
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--!
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type swOPT_t is record
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KE8 : std_logic; --! KE8 - Extended Arithmetic Element Provided
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KM8E : std_logic; --! KM8E - Extended Memory Provided
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TSD : std_logic; --! Time Share Disable
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SP0 : std_logic; --! Spare 0
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SP1 : std_logic; --! Spare 1
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SP2 : std_logic; --! Spare 2
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SP3 : std_logic; --! Spare 3
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STARTUP : std_logic; --! Boot to Panel Mode (HD6120)
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end record;
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--!
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--! Registers
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--!
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type regs_t is record
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PC : data_t; --! PC Register
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AC : data_t; --! AC Register
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IR : data_t; --! IR Register
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MA : data_t; --! MA Register
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MD : data_t; --! MD Register
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MQ : data_t; --! MQ Register
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ST : data_t; --! ST Register
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SC : data_t; --! SC Register
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XMA : field_t; --! XMA Register
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end record;
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--!
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--! Bus Signals
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--!
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type bus_t is record
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addr : addr_t; --! Address Bus Output
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eaddr : field_t; --! Extended Address
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data : data_t; --! Data Bus Output
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ioclr : std_logic; --! IO Clear
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dataf : std_logic; --! Data Field
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ifetch : std_logic; --! Instruction Fetch
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memsel : std_logic; --! Asserted during memory operations
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rd : std_logic; --! Read
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wr : std_logic; --! Write
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lxpar : std_logic; --! Load Panel Address Register
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lxmar : std_logic; --! Load Memory Address Register
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lxdar : std_logic; --! Load Device Address Register
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dmagnt : std_logic; --! DMA Grant
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intgnt : std_logic; --! INT Grant
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end record;
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--!
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--! CPU Output Bus
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--!
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type cpu_t is record
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regs : regs_t; --! Registers
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buss : bus_t; --! Bus Signals
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run : std_logic; --! Run
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end record;
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--!
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--! Device DMA Output(s)
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--!
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type dma_t is record
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req : std_logic; --! DMA Request
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rd : std_logic; --! DMA Read
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wr : std_logic; --! DMA Write
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memsel : std_logic; --! DMA Memsel
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lxmar : std_logic; --! DMA LXMAR
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lxpar : std_logic; --! DMA LXPAR
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addr : addr_t; --! DMA Address
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eaddr : field_t; --! Extended Address
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end record;
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constant nullDMA : dma_t := ('0', '0', '0', '0', '0', '0',
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(others => '0'), (others => '0'));
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--!
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--! Device Output Bus
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--!
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type dev_t is record
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ack : std_logic; --! Bus Ack
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data : data_t; --! Data Out
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devc : devc_t; --! Device Control
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skip : std_logic; --! Skip
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cpreq : std_logic; --! Control Panel Request
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intr : std_logic; --! Interrupt Request
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dma : dma_t; --! DMA
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end record;
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constant nullDEV : dev_t := ('0', (others => '0'), devWR, '0', '0', '0', nullDMA);
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--!
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--! Control Switches
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--!
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type swCNTL_t is record
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boot : std_logic; --! Boot Switch
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lock : std_logic; --! Panel Lock Switch
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loadADDR : std_logic; --! Load Address Switch
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loadEXTD : std_logic; --! Load Extended Address Switch
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clear : std_logic; --! Clear Switch
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cont : std_logic; --! Continue Switch
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exam : std_logic; --! Examine Switch
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halt : std_logic; --! Halt Switch
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step : std_logic; --! Single Step Switch
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dep : std_logic; --! Deposit Switch
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end record;
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--!
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--! System stuff
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--!
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type sys_t is record
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clk : std_logic; --! Clock
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rst : std_logic; --! Async: Reset
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end record;
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--!
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--! AC Operations
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--!
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type acOP_t is (
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acopNOP, --! LAC <- LAC
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acopIAC, --! IAC
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acopBSW, --! BSW
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acopRAL, --! RAL
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acopRTL, --! RTL
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acopR3L, --! R3L (HD6120 only)
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acopRAR, --! RAR
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acopRTR, --! RTR
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acopSHL0, --! LAC <- (LAC << 1) & '0'
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acopSHL1, --! LAC <- (LAC << 1) & '1'
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acopLSR, --! LAC <- '0' & (LAC >> 1)
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acopASR, --! LAC <- L & (LAC >> 1)
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acopUNDEF1, --! RAL RAR
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acopUNDEF2, --! RTL RTR
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acopPC, --! PC
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acopCML, --! 0 0 0 CML
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acopCMA, --! 0 0 CMA 0
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acopCMACML, --! 0 0 CMA CML
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acopCLL, --! 0 CLL 0 0
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acopCLLCML, --! 0 CLL 0 CML
|
| 320 |
|
|
acopCLLCMA, --! 0 CLL CMA 0
|
| 321 |
|
|
acopCLLCMACML, --! 0 CLL CMA CML
|
| 322 |
|
|
acopCLA, --! CLA 0 0 0
|
| 323 |
|
|
acopCLACML, --! CLA 0 0 CML
|
| 324 |
|
|
acopCLACMA, --! CLA 0 CMA 0
|
| 325 |
|
|
acopCLACMACML, --! CLA 0 CMA CML
|
| 326 |
|
|
acopCLACLL, --! CLA CLL 0 0
|
| 327 |
|
|
acopCLACLLCML, --! CLA CLL 0 CML
|
| 328 |
|
|
acopCLACLLCMA, --! CLA CLL CMA 0
|
| 329 |
|
|
acopCLACLLCMACML, --! CLA CLL CMA CML
|
| 330 |
|
|
acopRDF0, --! RDF0 (HD6120)
|
| 331 |
|
|
acopRIF0, --! RIF0 (HD6120)
|
| 332 |
|
|
acopRIB0, --! RIB0 (HD6120)
|
| 333 |
|
|
acopRDF1, --! RDF1 (PDP8)
|
| 334 |
|
|
acopRIF1, --! RIF1 (PDP8)
|
| 335 |
|
|
acopRIB1, --! RIB1 (PDP8)
|
| 336 |
|
|
acopPRS, --!
|
| 337 |
|
|
acopGTF1, --! HD6120 GTF
|
| 338 |
|
|
acopGTF2, --! PDP8 GTF
|
| 339 |
|
|
acopGCF, --!
|
| 340 |
|
|
acopEAELAC, --! LAC <- EAE(0 to 12)
|
| 341 |
|
|
acopEAEZAC, --! LAC <- '0' & EAE(1 to 12)
|
| 342 |
|
|
acopSUBMD, --! LAC <- LAC - MD
|
| 343 |
|
|
acopADDMD, --! LAC <- LAC + MD
|
| 344 |
|
|
acopADDMDP1, --! LAC <- LAC + MD + 1
|
| 345 |
|
|
acopANDMD, --! LAC <- L & (AC and MD)
|
| 346 |
|
|
acopORMD, --! LAC <- L & (AC or MD)
|
| 347 |
|
|
acopMQSUB, --! LAC <- MQ - AC
|
| 348 |
|
|
acopMQ, --! LAC <- L & MQ
|
| 349 |
|
|
acopZMQ, --! LAC <- '0' & MQ
|
| 350 |
|
|
acopMQP1, --! LAC <- MQ + 1
|
| 351 |
|
|
acopNEGMQ, --! LAC <- -MQ
|
| 352 |
|
|
acopNOTMQ, --! LAC <- not(MQ)
|
| 353 |
|
|
acopORMQ, --! LAC <- L & (AC or MQ)
|
| 354 |
|
|
acopSCA, --! LAC <- L & (AC or SC)
|
| 355 |
|
|
acopSP1, --! LAC <- '0' & SP1
|
| 356 |
|
|
acopSP2, --! LAC <- '0' & SP2
|
| 357 |
|
|
acopLAS, --! LAC <- L & SR
|
| 358 |
|
|
acopOSR --! LAC <- L & (AC or SR)
|
| 359 |
|
|
);
|
| 360 |
|
|
|
| 361 |
|
|
--!
|
| 362 |
|
|
--! BTSTRP Operation
|
| 363 |
|
|
--!
|
| 364 |
|
|
|
| 365 |
|
|
type btstrpOP_t is (
|
| 366 |
|
|
btstrpopNOP, --! BTSTRP <- BTSTRP
|
| 367 |
|
|
btstrpopCLR, --! BTSTRP <- '0'
|
| 368 |
|
|
btstrpopSET --! BTSTRP <- '1'
|
| 369 |
|
|
);
|
| 370 |
|
|
|
| 371 |
|
|
--!
|
| 372 |
|
|
--! CTRLFF Operation
|
| 373 |
|
|
--!
|
| 374 |
|
|
|
| 375 |
|
|
type ctrlffOP_t is (
|
| 376 |
|
|
ctrlffopNOP, --! CTRLFF <- CTRLFF
|
| 377 |
|
|
ctrlffopCLR, --! CTRLFF <- '0'
|
| 378 |
|
|
ctrlffopSET --! CTRLFF <- '1'
|
| 379 |
|
|
);
|
| 380 |
|
|
|
| 381 |
|
|
--!
|
| 382 |
|
|
--! Data Field Operation
|
| 383 |
|
|
--!
|
| 384 |
|
|
|
| 385 |
|
|
type dfOP_t is (
|
| 386 |
|
|
dfopNOP, --! DF <- DF
|
| 387 |
|
|
dfopCLR, --! DF <- "000"
|
| 388 |
|
|
dfopAC9to11, --! DF <- AC(9 to 11)
|
| 389 |
|
|
dfopIR6to8, --! DF <- IR(6 to 8)
|
| 390 |
|
|
dfopSF4to6, --! DF <- SF(4 to 6)
|
| 391 |
|
|
dfopSR9to11 --! DF <- SR(9 to 11)
|
| 392 |
|
|
);
|
| 393 |
|
|
|
| 394 |
|
|
--!
|
| 395 |
|
|
--! EAE Mode
|
| 396 |
|
|
--!
|
| 397 |
|
|
|
| 398 |
|
|
type eaeOP_t is (
|
| 399 |
|
|
eaeopNOP, --! EAE <- EAE
|
| 400 |
|
|
eaeopMUY --! EAE <- (MQ * MD) + AC;
|
| 401 |
|
|
--eaeopASRMD, --! EAE ASR MD
|
| 402 |
|
|
--eaeopLSRMD, --! EAE LSR MD
|
| 403 |
|
|
--eaeopSHLMD --! EAE SHL MD
|
| 404 |
|
|
);
|
| 405 |
|
|
|
| 406 |
|
|
--!
|
| 407 |
|
|
--! EAE Mode operation
|
| 408 |
|
|
--!
|
| 409 |
|
|
|
| 410 |
|
|
type emodeOP_t is (
|
| 411 |
|
|
emodeopNOP, --! eaeModeA <- eaeModeA
|
| 412 |
|
|
emodeopCLR, --! eaeModeA <- '0'
|
| 413 |
|
|
emodeopSET --! eaeModeA <- '1'
|
| 414 |
|
|
);
|
| 415 |
|
|
|
| 416 |
|
|
--!
|
| 417 |
|
|
--! Force Zero Operation
|
| 418 |
|
|
--!
|
| 419 |
|
|
|
| 420 |
|
|
type fzOP_t is (
|
| 421 |
|
|
fzopNOP, --! FZ <- FZ
|
| 422 |
|
|
fzopCLR, --! FZ <- '0'
|
| 423 |
|
|
fzopSET --! FZ <- '1'
|
| 424 |
|
|
);
|
| 425 |
|
|
|
| 426 |
|
|
--!
|
| 427 |
|
|
--! Greater Than Flag Operation
|
| 428 |
|
|
--!
|
| 429 |
|
|
|
| 430 |
|
|
type gtfOP_t is (
|
| 431 |
|
|
gtfopNOP, --! GT <- GT
|
| 432 |
|
|
gtfopCLR, --! GT <- '0'
|
| 433 |
|
|
gtfopSET, --! GT <- '1'
|
| 434 |
|
|
gtfopAC1 --! GT <- AC(1)
|
| 435 |
|
|
);
|
| 436 |
|
|
|
| 437 |
|
|
--!
|
| 438 |
|
|
--! Halt Trap Operation
|
| 439 |
|
|
--!
|
| 440 |
|
|
|
| 441 |
|
|
type hlttrpOP_t is (
|
| 442 |
|
|
hlttrpopNOP, --! HLTTRP <- HLTTRP
|
| 443 |
|
|
hlttrpopCLR, --! HLTTRP <- '0'
|
| 444 |
|
|
hlttrpopSET --! HLTTRP <- '1'
|
| 445 |
|
|
);
|
| 446 |
|
|
|
| 447 |
|
|
--!
|
| 448 |
|
|
--! Interrupt Enable Delay Operation
|
| 449 |
|
|
--!
|
| 450 |
|
|
|
| 451 |
|
|
type idOP_t is (
|
| 452 |
|
|
idopNOP, --! ID <- II
|
| 453 |
|
|
idopCLR, --! ID <- '0'
|
| 454 |
|
|
idopSET --! ID <- '1'
|
| 455 |
|
|
);
|
| 456 |
|
|
|
| 457 |
|
|
--!
|
| 458 |
|
|
--! Interrupt Enable Operation
|
| 459 |
|
|
--!
|
| 460 |
|
|
|
| 461 |
|
|
type ieOP_t is (
|
| 462 |
|
|
ieopNOP, --! IE <- IE
|
| 463 |
|
|
ieopCLR, --! IE <- '0'
|
| 464 |
|
|
ieopSET --! IE <- '1'
|
| 465 |
|
|
);
|
| 466 |
|
|
|
| 467 |
|
|
--!
|
| 468 |
|
|
--! Interrupt Inhibit Operation
|
| 469 |
|
|
--!
|
| 470 |
|
|
|
| 471 |
|
|
type iiOP_t is (
|
| 472 |
|
|
iiopNOP, --! II <- II
|
| 473 |
|
|
iiopCLR, --! II <- '0'
|
| 474 |
|
|
iiopSET --! II <- '1'
|
| 475 |
|
|
);
|
| 476 |
|
|
|
| 477 |
|
|
--!
|
| 478 |
|
|
--! IB Operation
|
| 479 |
|
|
--!
|
| 480 |
|
|
|
| 481 |
|
|
type ibOP_t is (
|
| 482 |
|
|
ibopNOP, --! IB <- INB
|
| 483 |
|
|
ibopCLR, --! IB <- "000"
|
| 484 |
|
|
ibopAC6to8, --! IB <- AC(6 to 8)
|
| 485 |
|
|
ibopIR6to8, --! IB <- IR(6 to 8)
|
| 486 |
|
|
ibopSF1to3 --! IB <- SF(1 to 3)
|
| 487 |
|
|
);
|
| 488 |
|
|
|
| 489 |
|
|
--!
|
| 490 |
|
|
--! IF Operation
|
| 491 |
|
|
--!
|
| 492 |
|
|
|
| 493 |
|
|
type ifOP_t is (
|
| 494 |
|
|
ifopNOP, --! IF <- IF
|
| 495 |
|
|
ifopCLR, --! IF <- "000"
|
| 496 |
|
|
ifopIB, --! IF <- IB
|
| 497 |
|
|
ifopSR6to8 --! IF <- SR(6 to 8)
|
| 498 |
|
|
);
|
| 499 |
|
|
|
| 500 |
|
|
--!
|
| 501 |
|
|
--! Instruction Register Operation
|
| 502 |
|
|
--!
|
| 503 |
|
|
|
| 504 |
|
|
type irOP_t is (
|
| 505 |
|
|
iropNOP, --! IR <- IR
|
| 506 |
|
|
iropMD --! IR <- MD (Fetch)
|
| 507 |
|
|
);
|
| 508 |
|
|
|
| 509 |
|
|
--!
|
| 510 |
|
|
--! Memory Address operations
|
| 511 |
|
|
--!
|
| 512 |
|
|
|
| 513 |
|
|
type maOP_t is (
|
| 514 |
|
|
maopNOP, --! MA <- MA
|
| 515 |
|
|
maop0000, --! MA <- o"0000"
|
| 516 |
|
|
maopINC, --! MA <- MA + 1
|
| 517 |
|
|
maopZP, --! MA <- zeroPage & IR(5 to 11)
|
| 518 |
|
|
maopCP, --! MA <- currPage & IR(5 to 11)
|
| 519 |
|
|
maopIR, --! MA <- IR
|
| 520 |
|
|
maopPC, --! MA <- PC
|
| 521 |
|
|
maopPCP1, --! MA <- PC + 1
|
| 522 |
|
|
maopMB, --! MA <- MB
|
| 523 |
|
|
maopMD, --! MA <- MD
|
| 524 |
|
|
maopMDP1, --! MA <- MD + 1
|
| 525 |
|
|
maopSP1, --! MA <- SP1
|
| 526 |
|
|
maopSP1P1, --! MA <- SP1 + 1
|
| 527 |
|
|
maopSP2, --! MA <- SP2
|
| 528 |
|
|
maopSP2P1, --! MA <- SP2 + 1
|
| 529 |
|
|
maopSR --! MA <- SR
|
| 530 |
|
|
);
|
| 531 |
|
|
|
| 532 |
|
|
--!
|
| 533 |
|
|
--! Memory Buffer operation
|
| 534 |
|
|
--!
|
| 535 |
|
|
|
| 536 |
|
|
type mbOP_t is (
|
| 537 |
|
|
mbopNOP, --! MB <- MB
|
| 538 |
|
|
mbopAC, --! MB <- AC
|
| 539 |
|
|
mbopMA, --! MB <- MA
|
| 540 |
|
|
mbopMD, --! MB <- MD
|
| 541 |
|
|
mbopMQ, --! MB <- MQ
|
| 542 |
|
|
mbopMDP1, --! MB <- MD + 1
|
| 543 |
|
|
mbopPC, --! MB <- PC
|
| 544 |
|
|
mbopPCP1, --! MB <- PC + 1
|
| 545 |
|
|
mbopSR --! MB <- SR
|
| 546 |
|
|
);
|
| 547 |
|
|
|
| 548 |
|
|
--!
|
| 549 |
|
|
--! Multiplier/Quotient Operations
|
| 550 |
|
|
--!
|
| 551 |
|
|
|
| 552 |
|
|
type mqOP_t is (
|
| 553 |
|
|
mqopNOP, --! MQ <- MQ
|
| 554 |
|
|
mqopCLR, --! MQ <- "0000"
|
| 555 |
|
|
mqopSET, --! MQ <- "7777"
|
| 556 |
|
|
mqopSHL0, --! MQ <- (MQ << 1) + 0
|
| 557 |
|
|
mqopSHL1, --! MQ <- (MQ << 1) + 1
|
| 558 |
|
|
mqopAC, --! MQ <- AC
|
| 559 |
|
|
mqopMD, --! MQ <- MD
|
| 560 |
|
|
mqopADDMD, --! MQ <- MQ + MD
|
| 561 |
|
|
mqopACP1, --! MQ <- AC + 1
|
| 562 |
|
|
mqopNEGAC, --! MQ <- -AC
|
| 563 |
|
|
mqopEAE, --! MQ <- low(EAE)
|
| 564 |
|
|
mqopSHR0, --! MQ <- '0' & MQ(0 to 10)
|
| 565 |
|
|
mqopSHR1 --! MQ <- '1' & MQ(0 to 10)
|
| 566 |
|
|
);
|
| 567 |
|
|
|
| 568 |
|
|
--!
|
| 569 |
|
|
--! MQA Operations
|
| 570 |
|
|
--!
|
| 571 |
|
|
|
| 572 |
|
|
type mqaOP_t is (
|
| 573 |
|
|
mqaopNOP, --! MQA <- MQA
|
| 574 |
|
|
mqaopCLR, --! MQA <- "0000"
|
| 575 |
|
|
mqaopMQ, --! MQA <- MQ
|
| 576 |
|
|
mqaopSHL --! MQA <- (MQA << 1)
|
| 577 |
|
|
);
|
| 578 |
|
|
|
| 579 |
|
|
--!
|
| 580 |
|
|
--! Program Counter Operations
|
| 581 |
|
|
--!
|
| 582 |
|
|
|
| 583 |
|
|
type pcOP_t is (
|
| 584 |
|
|
pcopNOP, --! PC <- PC
|
| 585 |
|
|
pcop0000, --! PC <- "0000"
|
| 586 |
|
|
pcop0001, --! PC <- "0001"
|
| 587 |
|
|
pcop7777, --! PC <- "7777"
|
| 588 |
|
|
pcopINC, --! PC <- PC + 1
|
| 589 |
|
|
pcopMA, --! PC <- MA
|
| 590 |
|
|
pcopMAP1, --! PC <- MA + 1
|
| 591 |
|
|
pcopMB, --! PC <- MB
|
| 592 |
|
|
pcopMBP1, --! PC <- MB + 1
|
| 593 |
|
|
pcopMD, --! PC <- MD
|
| 594 |
|
|
pcopMDP1, --! PC <- MD + 1
|
| 595 |
|
|
pcopSR, --! PC <- SR
|
| 596 |
|
|
pcopZP, --! PC <- "00000" & IR(5 to 11)
|
| 597 |
|
|
pcopCP, --! PC <- MA(0 to 4) & IR(5 to 11)
|
| 598 |
|
|
pcopZPP1, --! PC <- ("00000" & IR(5 to 11)) + "1"
|
| 599 |
|
|
pcopCPP1 --! PC <- (MA(0 to 4) & IR(5 to 11)) + "1"
|
| 600 |
|
|
);
|
| 601 |
|
|
|
| 602 |
|
|
--!
|
| 603 |
|
|
--! Panel Data Flag Operation
|
| 604 |
|
|
--!
|
| 605 |
|
|
|
| 606 |
|
|
type pdfOP_t is (
|
| 607 |
|
|
pdfopNOP, --! PDF <- PDF
|
| 608 |
|
|
pdfopCLR, --! PDF <- '0'
|
| 609 |
|
|
pdfopSET --! PDF <- '1'
|
| 610 |
|
|
);
|
| 611 |
|
|
|
| 612 |
|
|
--!
|
| 613 |
|
|
--! Panel Execute Operation
|
| 614 |
|
|
--!
|
| 615 |
|
|
|
| 616 |
|
|
type pexOP_t is (
|
| 617 |
|
|
pexopNOP, --! PEXFF <- PEXFF
|
| 618 |
|
|
pexopCLR, --! PEXFF <- '0'
|
| 619 |
|
|
pexopSET --! PEXFF <- '1'
|
| 620 |
|
|
);
|
| 621 |
|
|
|
| 622 |
|
|
--!
|
| 623 |
|
|
--! Panel Trap Operation
|
| 624 |
|
|
--!
|
| 625 |
|
|
|
| 626 |
|
|
type pnltrpOP_t is (
|
| 627 |
|
|
pnltrpopNOP, --! PNLTRP <- PNLTRP
|
| 628 |
|
|
pnltrpopCLR, --! PNLTRP <- '0'
|
| 629 |
|
|
pnltrpopSET --! PNLTRP <- '1'
|
| 630 |
|
|
);
|
| 631 |
|
|
|
| 632 |
|
|
--!
|
| 633 |
|
|
--! Power-up Trap Operation
|
| 634 |
|
|
--!
|
| 635 |
|
|
|
| 636 |
|
|
type pwrtrpOP_t is (
|
| 637 |
|
|
pwrtrpopNOP, --! PWRTRP <- PWRTRP
|
| 638 |
|
|
pwrtrpopCLR, --! PWRTRP <- '0'
|
| 639 |
|
|
pwrtrpopSET --! PWRTRP <- '1'
|
| 640 |
|
|
);
|
| 641 |
|
|
|
| 642 |
|
|
--!
|
| 643 |
|
|
--! Shift Count Operation
|
| 644 |
|
|
--!
|
| 645 |
|
|
|
| 646 |
|
|
type scOP_t is (
|
| 647 |
|
|
scopNOP, --! SC <- SP
|
| 648 |
|
|
scopCLR, --! SC <- "00000"
|
| 649 |
|
|
scopSET, --! SC <- "11111"
|
| 650 |
|
|
scop12, --! SC <- "01100"
|
| 651 |
|
|
scopAC7to11, --! SC <- AC(7 to 11)
|
| 652 |
|
|
scopMD7to11, --! SC <- MD(7 to 11)
|
| 653 |
|
|
scopNOTMD7to11, --! SC <- not(MD(7 to 11))
|
| 654 |
|
|
scopINC, --! SC <- SC + 1
|
| 655 |
|
|
scopDEC, --! SC <- SC - 1
|
| 656 |
|
|
scopMDP1 --! SC <- MD(7 to 11) + 1
|
| 657 |
|
|
);
|
| 658 |
|
|
|
| 659 |
|
|
--!
|
| 660 |
|
|
--! Stack Pointer Operation
|
| 661 |
|
|
--!
|
| 662 |
|
|
|
| 663 |
|
|
type spOP_t is (
|
| 664 |
|
|
spopNOP, --! SP <- SP
|
| 665 |
|
|
spopCLR, --! SP <- o"0000"
|
| 666 |
|
|
spopAC, --! SP <- AC
|
| 667 |
|
|
spopINC, --! SP <- SP + 1
|
| 668 |
|
|
spopDEC --! SP <- SP - 1
|
| 669 |
|
|
);
|
| 670 |
|
|
|
| 671 |
|
|
--!
|
| 672 |
|
|
--! User Buffer Operations
|
| 673 |
|
|
--!
|
| 674 |
|
|
|
| 675 |
|
|
type ubOP_t is (
|
| 676 |
|
|
ubopNOP,
|
| 677 |
|
|
ubopCLR,
|
| 678 |
|
|
ubopSET,
|
| 679 |
|
|
ubopAC5, --! UB <- AC(5)
|
| 680 |
|
|
ubopSF --! UB <- SF
|
| 681 |
|
|
);
|
| 682 |
|
|
|
| 683 |
|
|
--!
|
| 684 |
|
|
--! User Flag Operations
|
| 685 |
|
|
--!
|
| 686 |
|
|
|
| 687 |
|
|
type ufOP_t is (
|
| 688 |
|
|
ufopNOP, --! UF <- UF
|
| 689 |
|
|
ufopCLR, --! UF <- '0'
|
| 690 |
|
|
ufopSET, --! UF <- '1'
|
| 691 |
|
|
ufopUB --! UF <- UB
|
| 692 |
|
|
);
|
| 693 |
|
|
|
| 694 |
|
|
--!
|
| 695 |
|
|
--! Save Flags Operations
|
| 696 |
|
|
--!
|
| 697 |
|
|
|
| 698 |
|
|
type sfOP_t is (
|
| 699 |
|
|
sfopNOP, --! SF <- SF
|
| 700 |
|
|
sfopUBIBDF --! SF <- UB & IB & DF
|
| 701 |
|
|
);
|
| 702 |
|
|
|
| 703 |
|
|
--!
|
| 704 |
|
|
--! Switch Register Operations
|
| 705 |
|
|
--!
|
| 706 |
|
|
|
| 707 |
|
|
type srOP_t is (
|
| 708 |
|
|
sropNOP, --! SR <- SR
|
| 709 |
|
|
sropAC --! SR <- AC
|
| 710 |
|
|
);
|
| 711 |
|
|
|
| 712 |
|
|
--!
|
| 713 |
|
|
--! User Mode Trap Operation
|
| 714 |
|
|
--!
|
| 715 |
|
|
|
| 716 |
|
|
type usrtrpOP_t is (
|
| 717 |
|
|
usrtrpopNOP, --! USRTRP <- USRTRP
|
| 718 |
|
|
usrtrpopCLR, --! USRTRP <- '0'
|
| 719 |
|
|
usrtrpopSET --! USRTRP <- '1'
|
| 720 |
|
|
);
|
| 721 |
|
|
|
| 722 |
|
|
--!
|
| 723 |
|
|
--! Extended Memory Address Operations
|
| 724 |
|
|
--!
|
| 725 |
|
|
|
| 726 |
|
|
type xmaOP_t is (
|
| 727 |
|
|
xmaopNOP, --! XMA <- XMA
|
| 728 |
|
|
xmaopCLR, --! XMA <- "000"
|
| 729 |
|
|
xmaopDF, --! XMA <- DF
|
| 730 |
|
|
xmaopIF, --! XMA <- IF/INF
|
| 731 |
|
|
xmaopIB --! XMA <- IB
|
| 732 |
|
|
);
|
| 733 |
|
|
|
| 734 |
|
|
end cpu_types;
|
