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------------------------------------------------------------------
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--!
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--! PDP-8 Processor
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--!
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--! \brief
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--! CPU Multiplier Quotient (MQ) Register
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--!
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--! \details
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--! The Multiplier Quotient (MQ) Register is used during
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--! certain EAE instructions. Many times is is just used
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--! as a temporary register.
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--!
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--! The MQ register is modified as follows:
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--! -# The MQ reqister is set to 0000 when the Front Panel
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--! CLEAR switch is asserted, and
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--! -# The MQ reqister is set to 0000 when a Clear AC and MQ
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--! (CAM) instruction is executed, and
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--! -# The MQ reqister is set to 0000 when a CLA SWP
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--! instruction is executed, and
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--! -# The MQ is loaded with the contents of the AC register
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--! when a MQ Register Load (MQL) instruction is
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--! executed, and
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--! -# The MQ is loaded with the contents of the AC register
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--! when a Swap AC and MQ (SWP) instruction is
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--! executed, and
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--! -# The MQ register is updated during each of the
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--! following EAE instructions:
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--! -# the Double Precision Increment (DPIC)
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--! instruction, or
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--! -# the Double Precision Complement (DCM)
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--! instruction, or
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--! -# the Double Precision Add (DAD) instruction, or
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--! -# the Double Precision Divide (DVI) instruction, or
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--! -# the Double Precision Multiply (MUY) instruction, or
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--! -# the Arithmetic Shift Right (ASR) instruction, or
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--! -# the Logical Shift Right (LSR) instruction, or
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--! -# the Shift Left (SHL) instruction, or
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--!
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--! \file
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--! mq.vhd
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--!
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--! \author
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--! Rob Doyle - doyle (at) cox (dot) net
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--!
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--------------------------------------------------------------------
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--
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-- Copyright (C) 2009, 2010, 2011, 2012 Rob Doyle
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--
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-- This source file may be used and distributed without
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-- restriction provided that this copyright statement is not
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-- removed from the file and that any derivative work contains
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-- the original copyright notice and the associated disclaimer.
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--
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-- This source file is free software; you can redistribute it
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-- and/or modify it under the terms of the GNU Lesser General
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-- Public License as published by the Free Software Foundation;
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-- version 2.1 of the License.
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--
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-- This source is distributed in the hope that it will be
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-- useful, but WITHOUT ANY WARRANTY; without even the implied
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-- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
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-- PURPOSE. See the GNU Lesser General Public License for more
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-- details.
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--
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-- You should have received a copy of the GNU Lesser General
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-- Public License along with this source; if not, download it
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-- from http://www.gnu.org/licenses/lgpl.txt
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--
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--------------------------------------------------------------------
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--
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-- Comments are formatted for doxygen
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--
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library ieee; --! IEEE Library
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use ieee.std_logic_1164.all; --! IEEE 1164
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use ieee.numeric_std.all; --! IEEE Numeric Standard
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use work.cpu_types.all; --! Types
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--
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--! CPU Multiplier Quotient (MQ) Register Entity
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--
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entity eMQ is port (
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sys : in sys_t; --! Clock/Reset
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mqOP : in mqop_t; --! MQ Operation
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AC : in data_t; --! AC Register
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MD : in data_t; --! MD Register
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EAE : in eae_t; --! EAE Register
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MQ : out data_t --! MQ Output
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);
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end eMQ;
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--
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--! CPU Multiplier Quotient (MQ) Register RTL
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--
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architecture rtl of eMQ is
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signal mqREG : data_t; --! Multiplier Quotient Register
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signal addMUX1 : data_t; --! Adder Multiplexer #1 input
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signal addMUX2 : data_t; --! Adder Multiplexer #2 input
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signal shl0 : data_t; --! MQ <- (MQ << 1) + 0
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signal shl1 : data_t; --! MQ <- (MQ << 1) + 1
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signal shr0 : data_t; --! MQ <- 0 & (MQ >> 1)
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signal shr1 : data_t; --! MQ <- 1 & (MQ >> 1)
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signal eael : data_t; --! EAE (low word)
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begin
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--
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-- Shifts and Rotates
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--
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shl0 <= mqREG(1 to 11) & '0'; -- SHL0 <= (MQ << 1) & '0'
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shl1 <= mqREG(1 to 11) & '1'; -- SHL1 <= (MQ << 1) & '1'
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shr0 <= '0' & mqREG(0 to 10); -- SHR0 <= '0' & MQ(0 to 10)
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shr1 <= '1' & mqREG(0 to 10); -- SHR1 <= '1' & MQ(0 to 10)
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eael <= EAE(13 to 24); -- EAEL <= EAE(13 to 24)
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--
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-- Adder input #1 mux.
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--
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with mqOP select
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addMUX1 <= o"0000" when mqopNOP, -- MQ <- MQ
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o"0000" when mqopCLR, -- MQ <- "0000"
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o"0000" when mqopSET, -- MQ <- "7777"
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o"0000" when mqopSHL0, -- MQ <- (MQ << 1) & '0'
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o"0000" when mqopSHL1, -- MQ <- (MQ << 1) & '1'
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o"0000" when mqopAC, -- MQ <- AC
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o"0000" when mqopMD, -- MQ <- MD
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MD when mqopADDMD, -- MQ <- MQ + MD
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o"0001" when mqopACP1, -- MQ <- AC + 1
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o"0001" when mqopNEGAC, -- MQ <- -AC
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o"0000" when mqopEAE, -- MQ <- EAE(13 to 24)
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o"0000" when mqopSHR0, -- MQ <- '0' & MQ(0 to 10)
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o"0000" when mqopSHR1; -- MQ <- '1' & MQ(0 to 10)
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--
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-- Adder input #2 mux.
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--
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with mqOP select
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addMUX2 <= mqREG when mqopNOP, -- MQ <- MQ
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o"0000" when mqopCLR, -- MQ <- "0000"
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o"7777" when mqopSET, -- MQ <- "7777"
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shl0 when mqopSHL0, -- MQ <- (MQ << 1) + 0
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shl1 when mqopSHL1, -- MQ <- (MQ << 1) + 1
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AC when mqopAC, -- MQ <- AC
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MD when mqopMD, -- MQ <- MD
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mqREG when mqopADDMD, -- MQ <- MQ + MD
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AC when mqopACP1, -- MQ <- AC + 1
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not(AC) when mqopNEGAC, -- MQ <- -AC
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eael when mqopEAE, -- MQ <- EAE(13 to 24)
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shr0 when mqopSHR0, -- MQ <- '0' & MQ(0 to 10)
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shr1 when mqopSHR1; -- MQ <- '1' & MQ(0 to 10)
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--
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--! MQ Register
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--
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REG_MQ : process(sys)
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begin
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if sys.rst = '1' then
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mqREG <= o"0000";
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elsif rising_edge(sys.clk) then
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mqREG <= std_logic_vector(unsigned(addMUX2) + unsigned(addMUX1));
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end if;
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end process REG_MQ;
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MQ <= mqREG;
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end rtl;
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