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[/] [pdp8/] [trunk/] [testbench/] [sdsim.vhd] - Blame information for rev 2

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------------------------------------------------------------------
--!
--! PDP-8 Processor
--!
--! \brief
--!      SD Sim Testbench
--!
--! \details
--!      Test Bench.
--!
--! \file
--!      sdsim.vhd
--!
--! \author
--!      Rob Doyle - doyle (at) cox (dot) net
--!
--------------------------------------------------------------------
--
--  Copyright (C) 2012 Rob Doyle
--
-- This source file may be used and distributed without
-- restriction provided that this copyright statement is not
-- removed from the file and that any derivative work contains
-- the original copyright notice and the associated disclaimer.
--
-- This source file is free software; you can redistribute it
-- and/or modify it under the terms of the GNU Lesser General
-- Public License as published by the Free Software Foundation;
-- version 2.1 of the License.
--
-- This source is distributed in the hope that it will be
-- useful, but WITHOUT ANY WARRANTY; without even the implied
-- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
-- PURPOSE. See the GNU Lesser General Public License for more
-- details.
--
-- You should have received a copy of the GNU Lesser General
-- Public License along with this source; if not, download it
-- from http://www.gnu.org/licenses/lgpl.txt
--
--------------------------------------------------------------------
--
-- Comments are formatted for doxygen
--
 
 
library ieee;                                   --! IEEE Library
use ieee.std_logic_1164.all;                    --! IEEE 1164
use ieee.numeric_std.all;                       --! IEEE Numeric Standard
use ieee.std_logic_textio.all;                  --! IEEE Std Logic TextIO
use std.textio.all;                             --! TEXTIO
 
--
--! SDSIM Test Entity
--
 
entity eSDSIM is port (
    -- System
    clk        : in  std_logic;                 --! Clock
    rst        : in  std_logic;                 --! Reset
    -- SD Interface
    sdCD       : out std_logic;                 --! SD Card Detect
    sdWP       : out std_logic;                 --! SD Write Protect
    sdMISO     : out std_logic;                 --! SD Data In
    sdMOSI     : in  std_logic;                 --! SD Data Out
    sdSCLK     : in  std_logic;                 --! SD Clock
    sdCS       : in  std_logic                  --! SD Chip Select
);
end eSDSIM;
 
--
--! SDSIM Test Bench Behav
--
 
architecture behav of eSDSIM is
 
    --
    -- SPI Simulation
    --
 
    subtype sdCMD_t       is std_logic_vector(0 to 55);
    signal  spiRX         : sdCMD_t;
    signal  spiTX         : sdCMD_t;
    type    state_t       is (stateRESET, stateRSP,
                              stateREAD0, stateREAD1, stateREAD2,
                              stateWRITE0, stateWRITE1, stateWRITE2, stateWRITE3, stateWRITE4);
    signal  state         : state_t;
    signal  bitcnt        : integer range 0 to 55;
    signal  bytecnt       : integer range 0 to 511;
    signal  index         : integer range 0 to 4194303;
 
    --
    -- Disk Registers
    --
 
    subtype byte_t        is std_logic_vector(0 to 7);
    type    image_t       is array(0 to 3325951) of byte_t;
    file    OUTFILE       : text is out "STD_OUTPUT";
    type    imageFILE_t   is file of character;
    file    imageFILE     : imageFILE_t;
    shared variable image : image_t;
    shared variable size  : integer := 0;
 
 
begin
 
    sdCD <= '0';
    sdWP <= '0';
 
    --
    --! SD Interface
    --
 
    SDSIM : process(clk, rst)
        variable clkstat : std_logic_vector(0 to 1);
    begin
        if rst = '1' then
            spiRX  <= (others => '1');
            spiTX  <= (others => '1');
            state  <= stateRESET;
            index  <= 0;
        elsif rising_edge(clk) then
            clkstat(0 to 1) := clkstat(1) & sdSCLK;
 
            if sdCS = '1' then
                spiRX <= (others => '1');
            elsif clkstat = "01" then
                spiRX <= spiRX(1 to 55) & sdMOSI;
            end if;
 
            case state is
                when stateRESET =>
 
                    --
                    -- CMD0:
                    --
 
                    if spiRX(0 to 7) = x"40" then
                        if clkstat = "10" then
                            bitcnt <= 15;
                            spiTX  <= x"ff_01_ff_ff_ff_ff_ff";
                            state  <= stateRSP;
                        end if;
 
                    --
                    -- CMD8:
                    --
 
                    elsif spiRX(0 to 7) = x"48" then
                        if clkstat = "10" then
                            bitcnt <= 55;
                            spiTX  <= x"ff_01_00_00_01_aa_ff";
                            state  <= stateRSP;
                        end if;
 
                    --
                    -- CMD13:
                    --  Send Status
                    --
 
                    elsif spiRX(0 to 7) = x"4d" then
                        if clkstat = "10" then
                            bitcnt <= 39;
                            spiTX  <= x"ff_ff_00_00_ff_ff_ff";
                            state  <= stateRSP;
                        end if;
 
 
                    --
                    -- CMD17:
                    --  Read Single
                    --
 
                    elsif spiRX(0 to 7) = x"51" then
                        if clkstat = "10" then
                            bitcnt <= 47;
                            spiTX  <= x"ff_ff_00_ff_ff_fe_ff";
                            index  <= to_integer(unsigned(spiRX(27 to 39))) * 512;
                            state  <= stateREAD0;
                        end if;
 
                    --
                    -- CMD24:
                    --  Write Single
                    --
 
                    elsif spiRX(0 to 7) = x"58" then
                        if clkstat = "10" then
                            bitcnt <= 47;
                            spiTX  <= x"ff_ff_00_ff_ff_fe_ff";
                            index  <= to_integer(unsigned(spiRX(27 to 39))) * 512;
                            state  <= stateWRITE0;
                        end if;
 
                    --
                    -- ACMD41:
                    --
 
                    elsif spiRX(0 to 7) = x"69" then
                        if clkstat = "10" then
                            bitcnt <= 23;
                            spiTX  <= x"ff_00_ff_ff_ff_ff_ff";
                            state  <= stateRSP;
                        end if;
 
                    --
                    -- CMD55:
                    --
 
                    elsif spiRX(8 to 15) = x"77" then
                        if clkstat = "10" then
                            bitcnt <= 15;
                            spiTX  <= x"ff_01_ff_ff_ff_ff_ff";
                            state  <= stateRSP;
                        end if;
 
                    --
                    -- CMD58:
                    --
 
                    elsif spiRX(0 to 7) = x"7a" then
                        if clkstat = "10" then
                            bitcnt <= 55;
                            spiTX  <= x"ff_00_e0_ff_80_00_ff";
                            state  <= stateRSP;
                        end if;
                    end if;
 
                --
                -- Send Response:
                --
 
                when stateRSP =>
                    if bitcnt = 0 then
                        state <= stateRESET;
                    else
                        if clkstat = "10" then
                            bitcnt <= bitcnt - 1;
                            spiTX  <= spiTX(1 to 55) & '1';
                        end if;
                    end if;
 
                --
                -- stateREAD0:
                --
 
                when stateREAD0 =>
                    if clkstat = "10" then
                        if bitcnt = 0 then
                            bitcnt  <= 7;
                            bytecnt <= 0;
                            spiTX   <= image(index) & x"00_00_00_00_00_00";
                            index   <= index + 1;
                            state   <= stateREAD1;
                        else
                            bitcnt  <= bitcnt - 1;
                            spiTX   <= spiTX(1 to 55) & '1';
                        end if;
                    end if;
 
                --
                -- stateREAD1
                --
 
                when stateREAD1 =>
                    if clkstat = "10" then
                        if sdCS = '1' then
                            spiTX <= x"ff_ff_ff_ff_ff_ff_ff";
                            state <= stateRESET;
                        elsif bitcnt = 0 then
                            if bytecnt = 511 then
                                bitcnt  <= 15;
                                spiTX   <= x"ff_ff_ff_ff_ff_ff_ff";
                                state   <= stateREAD2;
                            else
                                bitcnt  <= 7;
                                spiTX   <= image(index) & x"00_00_00_00_00_00";
                                index   <= index + 1;
                                bytecnt <= bytecnt + 1;
                            end if;
                        else
                            bitcnt <= bitcnt - 1;
                            spiTX  <= spiTX(1 to 55) & '1';
                        end if;
                    end if;
 
                --
                -- stateREAD2:
                --  Send 2 CRC bytes
                --
 
                when stateREAD2 =>
                    if clkstat = "10" then
                        if bitcnt = 0 then
                            state <= stateRESET;
                        else
                            bitcnt <= bitcnt - 1;
                            spiTX  <= spiTX(1 to 55) & '1';
                        end if;
                    end if;
 
                --
                -- stateWRITE0:
                --
 
                when stateWRITE0 =>
                    if clkstat = "10" then
                        if bitcnt = 0 then
                            bitcnt  <= 7;
                            bytecnt <= 0;
                            image(index) := spiRX(48 to 55);
                            spiTX   <= x"ff_ff_ff_ff_ff_ff_ff";
                            index   <= index + 1;
                            state   <= stateWRITE1;
                        else
                            bitcnt  <= bitcnt - 1;
                            spiTX   <= spiTX(1 to 55) & '1';
                        end if;
                    end if;
 
                --
                -- stateWRITE1
                --
 
                when stateWRITE1 =>
                    if clkstat = "10" then
                        if sdCS = '1' then
                            spiTX <= x"ff_ff_ff_ff_ff_ff_ff";
                            state <= stateRESET;
                        elsif bitcnt = 0 then
                            if bytecnt = 511 then
                                bitcnt <= 55;
                                spiTX  <= x"ff_05_00_00_00_00_ff";
                                state  <= stateWRITE2;
                            else
                                bitcnt  <= 7;
                                image(index) := spiRX(48 to 55);
                                spiTX   <= x"ff_ff_ff_ff_ff_ff_ff";
                                index   <= index + 1;
                                bytecnt <= bytecnt + 1;
                            end if;
                        else
                            bitcnt <= bitcnt - 1;
                            spiTX  <= spiTX(1 to 55) & '1';
                        end if;
                    end if;
 
                --
                -- stateWRITE2:
                --  Write 2 CRC bytes plus some busy (zero) tokens
                --
 
                when stateWRITE2 =>
                    if clkstat = "10" then
                        if bitcnt = 0 or sdCS = '1' then
                            --bitcnt  <= 15;
                            --bytecnt <= 0;
                            --spiTX   <= x"00_ff_ff_ff_ff_ff_ff";
                            state   <= stateRESET;
                        else
                            bitcnt <= bitcnt - 1;
                            spiTX  <= spiTX(1 to 55) & '1';
                        end if;
                    end if;
 
                when others =>
                    null;
            end case;
 
        end if;
    end process SDSIM;
    sdMISO <= spiTX(0);
 
    --
    --! This process reads the disk file
    --
 
    DISKSIM : process
        variable c    : character;
        variable lin  : line;
    begin
        write(lin, string'("Reading Disk Image..."));
        writeline(OUTFILE, lin);
        --file_open(imageFILE, "multos8.rk05", read_mode);
        --file_open(imageFILE, "diag-games-kermit.rk05", read_mode);
        file_open(imageFILE, "advent.rk05", read_mode);
        while not endfile(imageFILE) loop
            read(imageFILE, c);
            image(size) := std_logic_vector(to_unsigned(character'pos(c), 8));
            size := size + 1;
        end loop;
        write(lin, string'("Done Reading Disk Image."));
        writeline(OUTFILE, lin);
        write(lin, string'("Read "));
        write(lin, size);
        write(lin, string'(" bytes"));
        writeline(OUTFILE, lin);
        wait;
    end process DISKSIM;
 
end behav;

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Subversion Repositories pdp8

[/] [pdp8/] [trunk/] [testbench/] [sdsim.vhd] - Blame information for rev 2

Line No.	Rev	Author	Line
1	2	trurl	`------------------------------------------------------------------`
2			`--!`
3			`--! PDP-8 Processor`
4			`--!`
5			`--! \brief`
6			`--! SD Sim Testbench`
7			`--!`
8			`--! \details`
9			`--! Test Bench.`
10			`--!`
11			`--! \file`
12			`--! sdsim.vhd`
13			`--!`
14			`--! \author`
15			`--! Rob Doyle - doyle (at) cox (dot) net`
16			`--!`
17			`--------------------------------------------------------------------`
18			`--`
19			`-- Copyright (C) 2012 Rob Doyle`
20			`--`
21			`-- This source file may be used and distributed without`
22			`-- restriction provided that this copyright statement is not`
23			`-- removed from the file and that any derivative work contains`
24			`-- the original copyright notice and the associated disclaimer.`
25			`--`
26			`-- This source file is free software; you can redistribute it`
27			`-- and/or modify it under the terms of the GNU Lesser General`
28			`-- Public License as published by the Free Software Foundation;`
29			`-- version 2.1 of the License.`
30			`--`
31			`-- This source is distributed in the hope that it will be`
32			`-- useful, but WITHOUT ANY WARRANTY; without even the implied`
33			`-- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR`
34			`-- PURPOSE. See the GNU Lesser General Public License for more`
35			`-- details.`
36			`--`
37			`-- You should have received a copy of the GNU Lesser General`
38			`-- Public License along with this source; if not, download it`
39			`-- from http://www.gnu.org/licenses/lgpl.txt`
40			`--`
41			`--------------------------------------------------------------------`
42			`--`
43			`-- Comments are formatted for doxygen`
44			`--`
45
46
47			`library ieee; --! IEEE Library`
48			`use ieee.std_logic_1164.all; --! IEEE 1164`
49			`use ieee.numeric_std.all; --! IEEE Numeric Standard`
50			`use ieee.std_logic_textio.all; --! IEEE Std Logic TextIO`
51			`use std.textio.all; --! TEXTIO`
52
53			`--`
54			`--! SDSIM Test Entity`
55			`--`
56
57			`entity eSDSIM is port (`
58			`-- System`
59			`clk : in std_logic; --! Clock`
60			`rst : in std_logic; --! Reset`
61			`-- SD Interface`
62			`sdCD : out std_logic; --! SD Card Detect`
63			`sdWP : out std_logic; --! SD Write Protect`
64			`sdMISO : out std_logic; --! SD Data In`
65			`sdMOSI : in std_logic; --! SD Data Out`
66			`sdSCLK : in std_logic; --! SD Clock`
67			`sdCS : in std_logic --! SD Chip Select`
68			`);`
69			`end eSDSIM;`
70
71			`--`
72			`--! SDSIM Test Bench Behav`
73			`--`
74
75			`architecture behav of eSDSIM is`
76
77			`--`
78			`-- SPI Simulation`
79			`--`
80
81			`subtype sdCMD_t is std_logic_vector(0 to 55);`
82			`signal spiRX : sdCMD_t;`
83			`signal spiTX : sdCMD_t;`
84			`type state_t is (stateRESET, stateRSP,`
85			`stateREAD0, stateREAD1, stateREAD2,`
86			`stateWRITE0, stateWRITE1, stateWRITE2, stateWRITE3, stateWRITE4);`
87			`signal state : state_t;`
88			`signal bitcnt : integer range 0 to 55;`
89			`signal bytecnt : integer range 0 to 511;`
90			`signal index : integer range 0 to 4194303;`
91
92			`--`
93			`-- Disk Registers`
94			`--`
95
96			`subtype byte_t is std_logic_vector(0 to 7);`
97			`type image_t is array(0 to 3325951) of byte_t;`
98			`file OUTFILE : text is out "STD_OUTPUT";`
99			`type imageFILE_t is file of character;`
100			`file imageFILE : imageFILE_t;`
101			`shared variable image : image_t;`
102			`shared variable size : integer := 0;`
103
104
105			`begin`
106
107			`sdCD <= '0';`
108			`sdWP <= '0';`
109
110			`--`
111			`--! SD Interface`
112			`--`
113
114			`SDSIM : process(clk, rst)`
115			`variable clkstat : std_logic_vector(0 to 1);`
116			`begin`
117			`if rst = '1' then`
118			`spiRX <= (others => '1');`
119			`spiTX <= (others => '1');`
120			`state <= stateRESET;`
121			`index <= 0;`
122			`elsif rising_edge(clk) then`
123			`clkstat(0 to 1) := clkstat(1) & sdSCLK;`
124
125			`if sdCS = '1' then`
126			`spiRX <= (others => '1');`
127			`elsif clkstat = "01" then`
128			`spiRX <= spiRX(1 to 55) & sdMOSI;`
129			`end if;`
130
131			`case state is`
132			`when stateRESET =>`
133
134			`--`
135			`-- CMD0:`
136			`--`
137
138			`if spiRX(0 to 7) = x"40" then`
139			`if clkstat = "10" then`
140			`bitcnt <= 15;`
141			`spiTX <= x"ff_01_ff_ff_ff_ff_ff";`
142			`state <= stateRSP;`
143			`end if;`
144
145			`--`
146			`-- CMD8:`
147			`--`
148
149			`elsif spiRX(0 to 7) = x"48" then`
150			`if clkstat = "10" then`
151			`bitcnt <= 55;`
152			`spiTX <= x"ff_01_00_00_01_aa_ff";`
153			`state <= stateRSP;`
154			`end if;`
155
156			`--`
157			`-- CMD13:`
158			`-- Send Status`
159			`--`
160
161			`elsif spiRX(0 to 7) = x"4d" then`
162			`if clkstat = "10" then`
163			`bitcnt <= 39;`
164			`spiTX <= x"ff_ff_00_00_ff_ff_ff";`
165			`state <= stateRSP;`
166			`end if;`
167
168
169			`--`
170			`-- CMD17:`
171			`-- Read Single`
172			`--`
173
174			`elsif spiRX(0 to 7) = x"51" then`
175			`if clkstat = "10" then`
176			`bitcnt <= 47;`
177			`spiTX <= x"ff_ff_00_ff_ff_fe_ff";`
178			`index <= to_integer(unsigned(spiRX(27 to 39))) * 512;`
179			`state <= stateREAD0;`
180			`end if;`
181
182			`--`
183			`-- CMD24:`
184			`-- Write Single`
185			`--`
186
187			`elsif spiRX(0 to 7) = x"58" then`
188			`if clkstat = "10" then`
189			`bitcnt <= 47;`
190			`spiTX <= x"ff_ff_00_ff_ff_fe_ff";`
191			`index <= to_integer(unsigned(spiRX(27 to 39))) * 512;`
192			`state <= stateWRITE0;`
193			`end if;`
194
195			`--`
196			`-- ACMD41:`
197			`--`
198
199			`elsif spiRX(0 to 7) = x"69" then`
200			`if clkstat = "10" then`
201			`bitcnt <= 23;`
202			`spiTX <= x"ff_00_ff_ff_ff_ff_ff";`
203			`state <= stateRSP;`
204			`end if;`
205
206			`--`
207			`-- CMD55:`
208			`--`
209
210			`elsif spiRX(8 to 15) = x"77" then`
211			`if clkstat = "10" then`
212			`bitcnt <= 15;`
213			`spiTX <= x"ff_01_ff_ff_ff_ff_ff";`
214			`state <= stateRSP;`
215			`end if;`
216
217			`--`
218			`-- CMD58:`
219			`--`
220
221			`elsif spiRX(0 to 7) = x"7a" then`
222			`if clkstat = "10" then`
223			`bitcnt <= 55;`
224			`spiTX <= x"ff_00_e0_ff_80_00_ff";`
225			`state <= stateRSP;`
226			`end if;`
227			`end if;`
228
229			`--`
230			`-- Send Response:`
231			`--`
232
233			`when stateRSP =>`
234			`if bitcnt = 0 then`
235			`state <= stateRESET;`
236			`else`
237			`if clkstat = "10" then`
238			`bitcnt <= bitcnt - 1;`
239			`spiTX <= spiTX(1 to 55) & '1';`
240			`end if;`
241			`end if;`
242
243			`--`
244			`-- stateREAD0:`
245			`--`
246
247			`when stateREAD0 =>`
248			`if clkstat = "10" then`
249			`if bitcnt = 0 then`
250			`bitcnt <= 7;`
251			`bytecnt <= 0;`
252			`spiTX <= image(index) & x"00_00_00_00_00_00";`
253			`index <= index + 1;`
254			`state <= stateREAD1;`
255			`else`
256			`bitcnt <= bitcnt - 1;`
257			`spiTX <= spiTX(1 to 55) & '1';`
258			`end if;`
259			`end if;`
260
261			`--`
262			`-- stateREAD1`
263			`--`
264
265			`when stateREAD1 =>`
266			`if clkstat = "10" then`
267			`if sdCS = '1' then`
268			`spiTX <= x"ff_ff_ff_ff_ff_ff_ff";`
269			`state <= stateRESET;`
270			`elsif bitcnt = 0 then`
271			`if bytecnt = 511 then`
272			`bitcnt <= 15;`
273			`spiTX <= x"ff_ff_ff_ff_ff_ff_ff";`
274			`state <= stateREAD2;`
275			`else`
276			`bitcnt <= 7;`
277			`spiTX <= image(index) & x"00_00_00_00_00_00";`
278			`index <= index + 1;`
279			`bytecnt <= bytecnt + 1;`
280			`end if;`
281			`else`
282			`bitcnt <= bitcnt - 1;`
283			`spiTX <= spiTX(1 to 55) & '1';`
284			`end if;`
285			`end if;`
286
287			`--`
288			`-- stateREAD2:`
289			`-- Send 2 CRC bytes`
290			`--`
291
292			`when stateREAD2 =>`
293			`if clkstat = "10" then`
294			`if bitcnt = 0 then`
295			`state <= stateRESET;`
296			`else`
297			`bitcnt <= bitcnt - 1;`
298			`spiTX <= spiTX(1 to 55) & '1';`
299			`end if;`
300			`end if;`
301
302			`--`
303			`-- stateWRITE0:`
304			`--`
305
306			`when stateWRITE0 =>`
307			`if clkstat = "10" then`
308			`if bitcnt = 0 then`
309			`bitcnt <= 7;`
310			`bytecnt <= 0;`
311			`image(index) := spiRX(48 to 55);`
312			`spiTX <= x"ff_ff_ff_ff_ff_ff_ff";`
313			`index <= index + 1;`
314			`state <= stateWRITE1;`
315			`else`
316			`bitcnt <= bitcnt - 1;`
317			`spiTX <= spiTX(1 to 55) & '1';`
318			`end if;`
319			`end if;`
320
321			`--`
322			`-- stateWRITE1`
323			`--`
324
325			`when stateWRITE1 =>`
326			`if clkstat = "10" then`
327			`if sdCS = '1' then`
328			`spiTX <= x"ff_ff_ff_ff_ff_ff_ff";`
329			`state <= stateRESET;`
330			`elsif bitcnt = 0 then`
331			`if bytecnt = 511 then`
332			`bitcnt <= 55;`
333			`spiTX <= x"ff_05_00_00_00_00_ff";`
334			`state <= stateWRITE2;`
335			`else`
336			`bitcnt <= 7;`
337			`image(index) := spiRX(48 to 55);`
338			`spiTX <= x"ff_ff_ff_ff_ff_ff_ff";`
339			`index <= index + 1;`
340			`bytecnt <= bytecnt + 1;`
341			`end if;`
342			`else`
343			`bitcnt <= bitcnt - 1;`
344			`spiTX <= spiTX(1 to 55) & '1';`
345			`end if;`
346			`end if;`
347
348			`--`
349			`-- stateWRITE2:`
350			`-- Write 2 CRC bytes plus some busy (zero) tokens`
351			`--`
352
353			`when stateWRITE2 =>`
354			`if clkstat = "10" then`
355			`if bitcnt = 0 or sdCS = '1' then`
356			`--bitcnt <= 15;`
357			`--bytecnt <= 0;`
358			`--spiTX <= x"00_ff_ff_ff_ff_ff_ff";`
359			`state <= stateRESET;`
360			`else`
361			`bitcnt <= bitcnt - 1;`
362			`spiTX <= spiTX(1 to 55) & '1';`
363			`end if;`
364			`end if;`
365
366			`when others =>`
367			`null;`
368			`end case;`
369
370			`end if;`
371			`end process SDSIM;`
372			`sdMISO <= spiTX(0);`
373
374			`--`
375			`--! This process reads the disk file`
376			`--`
377
378			`DISKSIM : process`
379			`variable c : character;`
380			`variable lin : line;`
381			`begin`
382			`write(lin, string'("Reading Disk Image..."));`
383			`writeline(OUTFILE, lin);`
384			`--file_open(imageFILE, "multos8.rk05", read_mode);`
385			`--file_open(imageFILE, "diag-games-kermit.rk05", read_mode);`
386			`file_open(imageFILE, "advent.rk05", read_mode);`
387			`while not endfile(imageFILE) loop`
388			`read(imageFILE, c);`
389			`image(size) := std_logic_vector(to_unsigned(character'pos(c), 8));`
390			`size := size + 1;`
391			`end loop;`
392			`write(lin, string'("Done Reading Disk Image."));`
393			`writeline(OUTFILE, lin);`
394			`write(lin, string'("Read "));`
395			`write(lin, size);`
396			`write(lin, string'(" bytes"));`
397			`writeline(OUTFILE, lin);`
398			`wait;`
399			`end process DISKSIM;`
400
401			`end behav;`