Subversion Repositories perlilog

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<P><B><FONT COLOR="#bf0000" SIZE="+2">Project Name: Perlilog</FONT></B></P>

<P><U>Description</U></P>

<P>Perlilog is a design tool, whose main target is easy integration of Verilog IP cores

for System-on-Chip (SoC) designs.

<P>At a smaller scale, Perlilog is a great starting point for writing scripts which handle

Verilog code in general. It comes with a rich set of functions, that can be used for several purposes,

such as instantiation of ASIC pads, automatic connection and generation of simple Verilog

modules, and so on.

<P>The philosophy behind Perilog is that an IP core should be like a black box. Fitting

it for a certain purpose should be as easy as defining the desired requirements. Connecting

the cores, to become a system, should be as easy as drawing a block diagram.

<P>With plain Verilog, the reality couldn't be further away. But by using Perlilog correctly,

integration can be that simple.

<P>Perlilog introduces a new meaning to "IP core". It also introduces a different way to

approaching the task of interfacing cores with each other.

<P>Perlilog was built to make core programming and integration intuitive tasks. As such, it

is based on new, rather natural concepts, which one must get used to in order to gain

the most of the tool.

<P>Perlilog is written in Perl, currently with no GUI.

While the scripts, that the system consists of, are rather sophisticated,

only plain Perl knowledge is needed to use its scripting capabilities.

<p>

<P><U>Bye bye Verilog?</U></P>

<P>Absolutely not. Verilog is still the language to define the functionality of the core.

The final output of a design, which incorporates Perlilog, is perfectly normal Verilog

files.

<P>Perlilog will do the following tasks instead of you:

<ul>

<li>Instantiation of modules

<li>Connection between modules

<li>Setting up modules' attributes (word width, address mapping on buses etc.)

</ul>

<p>

<P><U>Status of the project</U></P>

<P>The current version is highly usable for general scripts, which involve Verilog code.

As for sophisticated SoC generation, it still lacks script pieces, which makes it directly

useful to connect real-life cores.

<P>The project is known to be used by a few Verilog designers, and despite the official

"beta" stage, no significant bugs have been found. The project appears to be reliable.

<P>Features are added to Perlilog whenever the system is shown to be incapable of meeting

a reasonable need. Those who want to try Perlilog are encouraged to contact the

maintainer directly.

<P>The project comes with a guide, which includes all knowledge needed to enrich the tool, so it

can connect real-life IP cores as promised above.

<p>

<P><U>Download</U></P>

<P><TABLE WIDTH="616" BORDER="1" CELLSPACING="2" CELLPADDING="0">

  <TR>

    <TD COLSPAN="2">

    <P><CENTER><B>The Perlilog System and its documentation</B></CENTER></TD>

  </TR>

  <TR>

    <TD WIDTH="35%">

    <P><CENTER><B> Item</B></CENTER></TD>

    <TD WIDTH="65%">

    <P><CENTER><B> Link</B></CENTER></TD>

  </TR>

  <TR>

    <TD WIDTH="35%">

     The Perlilog system (tarball)</TD>

    <TD WIDTH="65%">

    <P><CENTER> <A HREF="Perlilog-0.3.tar.gz">Perlilog-0.3.tar.gz (47 kB)</A></CENTER></TD>

  </TR>

  <TR>

    <TD WIDTH="35%">

     A Guide to Perlilog (pdf)</TD>

    <TD WIDTH="65%">

    <P><CENTER> <A HREF="perlilog-guide-0.3.pdf">perlilog-guide-0.3.pdf (748 kB)</A></CENTER></TD>

  </TR>

</TABLE></P>

<p>

<P><U>Maintainer</U></P>

<P>The Perlilog project is maintained by its author, Eli Billauer. He can be reached at

<A HREF="mailto:elib@flextronics.co.il__NOSPAM">elib@flextronics.co.il__NOSPAM</A>.

<p><p>

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