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-------------------------------------------------------------------------------
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-- Title      : Digital PID Controller
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-- Project    : 
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-------------------------------------------------------------------------------
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-- File       : pid_controller.vhd
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-- Author     : Tomasz Turek  <tomasz.turek@gmail.com>
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-- Company    : SzuWar ZOO
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-- Created    : 12:56:06 20-07-2010
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-- Last update: 21:00:09 06-10-2010
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-- Platform   : Xilinx ISE 10.1.03
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-- Standard   : VHDL'93/02
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-------------------------------------------------------------------------------
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-- Description:
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--                            PID CONTROLLER
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--                                
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--                                 ___________                           ___
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--                                |           |                         |   |
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--                            |-->|  KP Gain  |------------------------>| + |
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--                            |   |___________|                         |   |
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--                            |                                         |   |
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--                            |                      ___________        |   |
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--                            |                     |  -iDelayD |       |   |   
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--                            |                  |--| Z         |<--|   |   |    
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--                            |                  |  |___________|   |   |   |
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--                            |                  |         ___      |   |   |
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--                            |                  |        |   |     |   |   |    _________
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--  _______     ___________   |    ___________   |------->| + |     |   |   |   |         |
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-- |       |   |           |  |   |           |           |   |-----|-->| + |-->| correct |
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-- | error |-->|  KM Gain  |--|-->|  KD Gain  |---------->| + |         |   |   |_________|
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-- |_______|   |___________|  |   |___________|           |___|         |   |
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--                            |                                         |   |
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--                            |                      ____               |   |
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--                            |                     |  -1|              |   |
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--                            |                  |--| Z  |<---|         |   |
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--                            |                  |  |____|    |         |   |
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--                            |                  |    ___     |         |   |
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--                            |                  |   |   |    |         |   |
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--                            |    ___________   |-->| + |    |         |   |
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--                            |   |           |      |   |----|-------->| + |
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--                            |-->|  KI Gain  |----->| + |              |   |
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--                                |___________|      |___|              |___|
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--
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-------------------------------------------------------------------------------
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-- Copyright (c) 2010 SzuWar ZOO
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-------------------------------------------------------------------------------
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-- Revisions  :
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-- Date                  Version  Author  Description
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-- 12:56:06 20-07-2010   1.0      aTomek  Created
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-- 19:29:34 04-10-2010   1.1      aTomek  Created
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-------------------------------------------------------------------------------
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library IEEE;
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use IEEE.STD_LOGIC_1164.ALL;
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use IEEE.STD_LOGIC_ARITH.ALL;
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use IEEE.STD_LOGIC_UNSIGNED.ALL;
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entity pid_controller is
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   generic
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      (
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            -- size of input and output data --
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            iDataWidith    : integer range 8 to 32 := 8;
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            -- proportionally gain --
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            iKP            : integer range 0 to 7  := 3;  -- 0 - /2, 1 - /4, 2 - /8, 3 - /16, 4 - /32, 5 - /64, 6 - /128, 7 - /256
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            -- integral gain --
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            iKI            : integer range 0 to 7  := 2;  -- 0 - /2, 1 - /4, 2 - /8, 3 - /16, 4 - /32, 5 - /64, 6 - /128, 7 - /256
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            -- differential gain --
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            iKD            : integer range 0 to 7  := 2;  -- 0 - /2, 1 - /4, 2 - /8, 3 - /16, 4 - /32, 5 - /64, 6 - /128, 7 - /256
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            -- master gain --
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            iKM            : integer range 0 to 7  := 1;  -- 0 - /1, 1 - /2, 2 - /4, 3 - /8 , 4 - /16, 5 - /32, 6 - /64 , 7 - /128
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            -- delay between samples of error --
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            iDelayD        : integer range 1 to 16 := 10;
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            -- 0 - controller use derivative of PATERN_I and PATERN_ESTIMATION_I, 1 - controller use error to work --
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            iWork          : integer range 0 to 1  := 1
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            );
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   port
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      (
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            CLK_I               : in  std_logic;
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            RESET_I             : in  std_logic;
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            -- error  --
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            ERROR_I             : in  std_logic_vector(iDataWidith - 1 downto 0);
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            -- threshold --
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            PATERN_I            : in  std_logic_vector(iDataWidith - 1 downto 0);
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            -- current sample --
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            PATERN_ESTIMATION_I : in  std_logic_vector(iDataWidith - 1 downto 0);
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            -- correction --
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            CORRECT_O           : out std_logic_vector(iDataWidith - 1 downto 0)
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            );
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end entity pid_controller;
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architecture rtl of pid_controller is
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-------------------------------------------------------------------------------
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-- functions --
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-------------------------------------------------------------------------------
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-- purpose: make a std_logic_vector of size c_size and build from c_value --
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   function f_something ( constant c_size : integer; signal c_value : std_logic) return std_logic_vector is
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      variable var_temp : std_logic_vector(c_size - 1 downto 0);
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   begin  -- function f_something --
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      var_temp := (others => c_value);
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      return var_temp;
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   end function f_something;
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-- examples:
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-- f_something(c_size => 3 , c_value => 'Z')  == "ZZZ"
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-- f_something(c_size => 3 , c_value => '1')  == "111"
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-- ...
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-------------------------------------------------------------------------------
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-- types --
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-------------------------------------------------------------------------------
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   -- delay register --
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   type type_sr is array (0 to iDelayD - 1) of std_logic_vector(iDataWidith - 1 downto 0);
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-------------------------------------------------------------------------------
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-- signals --
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-------------------------------------------------------------------------------
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   signal v_error    : std_logic_vector(iDataWidith - 1 downto 0);
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   signal v_error_KM : std_logic_vector(iDataWidith - 1 downto 0);
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   signal v_error_KP : std_logic_vector(iDataWidith - 1 downto 0);
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   signal v_error_KD : std_logic_vector(iDataWidith - 1 downto 0);
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   signal v_error_KI : std_logic_vector(iDataWidith - 1 downto 0);
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   signal t_div_late : type_sr;
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   signal v_div      : std_logic_vector(iDataWidith - 1 downto 0);
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   signal v_acu_earl : std_logic_vector(iDataWidith - 1 downto 0);
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   signal v_acu      : std_logic_vector(iDataWidith - 1 downto 0);
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   signal v_sum      : std_logic_vector(iDataWidith - 1 downto 0);
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begin  -- architecture rtl --
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-- choice source of input data --
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   v_error <= ERROR_I                                                                             when iWork = 1 else
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              conv_std_logic_vector(signed(PATERN_I) - signed(PATERN_ESTIMATION_I) , iDataWidith) when iWork = 0 else
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              (others => '0');
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-- master gain execute by shift of iKM bits to the right --
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   v_error_KM <= v_error                                                                                                when iKM = 0 else
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                 f_something(c_size => iKM , c_value => v_error(iDataWidith - 1)) & v_error(iDataWidith - 1 downto iKM) when iKM > 0 else
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                 (others => '0');
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-- proportionally gain execute by shift of (iKP - 1) bits to the right --
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   v_error_KP <= f_something(c_size => iKP + 1 , c_value => v_error_KM(iDataWidith - 1)) & v_error_KM(iDataWidith - 1 downto iKP + 1);
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-- derivative gain execute by shift of (iKD - 1) bits to the right --
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   v_error_KD <= f_something(c_size => iKD + 1 , c_value => v_error_KM(iDataWidith - 1)) & v_error_KM(iDataWidith - 1 downto iKD + 1);
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-- integral gain execute by shift of (iKI + 1) bits to the right --
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   v_error_KI <= f_something(c_size => iKI + 1 , c_value => v_error_KM(iDataWidith - 1)) & v_error_KM(iDataWidith - 1 downto iKI + 1);
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   DI00: process (CLK_I) is
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   begin  -- process DI00
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      if rising_edge(CLK_I) then
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         -- synchronous reset --
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         if RESET_I = '1' then
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            t_div_late <= (others => (others => '0'));
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            v_div      <= (others => '0');
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            v_acu      <= (others => '0');
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            v_acu_earl <= (others => '0');
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         else
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            -- delay register --
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            t_div_late <= v_error_KD & t_div_late(0 to iDelayD - 2);
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            -- difference between samples --
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            v_div <= conv_std_logic_vector(signed(v_error_KD) - signed(t_div_late(iDelayD - 1)) , iDataWidith);
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            -- integration of error --
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            v_acu <= conv_std_logic_vector(signed(v_error_KI) + signed(v_acu_earl) , iDataWidith);
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            -- sum of N - 1 samples of error --
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            v_acu_earl <= v_acu;
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         end if;
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      end if;
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   end process DI00;
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   -- first stage of adder -- 
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   v_sum <= conv_std_logic_vector(signed(v_acu) + signed(v_div) , iDataWidith);
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   -- correction and second stage of adder --
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   CORRECT_O <= conv_std_logic_vector(signed(v_error_KP) + signed(v_sum) , iDataWidith) when RESET_I  = '0' else
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                (others => '0');
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end architecture rtl;

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