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[/] [pid_controler/] [trunk/] [tb_pid_controller_0.vhd] - Blame information for rev 3

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1 3 aTomek1328 
-------------------------------------------------------------------------------
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-- Title      : Testbench for pid_controller
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-- Project    :
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-------------------------------------------------------------------------------
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-- File       : tb_pid_controller_0.vhd
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-- Author     : Tomasz Turek  <tomasz.turek@gmail.com>
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-- Company    : SzuWar ZOO
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-- Created    : 16:43:29 21-07-2010
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-- Last update: 20:54:54 04-10-2010
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-- Platform   : Xilinx ISE 10.1.03
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-- Standard   : VHDL'93/02
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-------------------------------------------------------------------------------
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-- Description:
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-------------------------------------------------------------------------------
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-- Copyright (c) 2010 SzuWar ZOO
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-------------------------------------------------------------------------------
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-- Revisions  :
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-- Date                  Version  Author  Description
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-- 16:43:29 21-07-2010   1.0      aTomek  Created
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-- 20:54:31 04-10-2010   1.1      aTomek  Created
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-------------------------------------------------------------------------------
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LIBRARY ieee;
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USE ieee.std_logic_1164.ALL;
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USE ieee.std_logic_unsigned.all;
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USE ieee.numeric_std.ALL;
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entity tb_pid_controller_0 is
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end entity tb_pid_controller_0;
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architecture testbench of tb_pid_controller_0 is
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-------------------------------------------------------------------------------
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-- components --
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-------------------------------------------------------------------------------
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   component pid_controller is
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      generic
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         (
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               iDataWidith    : integer range 8 to 32 := 12;
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               iKP            : integer range 0 to 7  := 2;  -- 0 - /2, 1 - /4, 2 - /8, 3 - /16, 4 - /32, 5 - /64, 6 - /128, 7 - /256
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               iKI            : integer range 0 to 7  := 3;  -- 0 - /2, 1 - /4, 2 - /8, 3 - /16, 4 - /32, 5 - /64, 6 - /128, 7 - /256
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               iKD            : integer range 0 to 7  := 4;  -- 0 - /2, 1 - /4, 2 - /8, 3 - /16, 4 - /32, 5 - /64, 6 - /128, 7 - /256
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               iKM            : integer range 0 to 7  := 0;  -- 0 - /1, 1 - /2, 2 - /4, 3 - /8 , 4 - /16, 5 - /32, 6 - /64 , 7 - /128
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               iDelayD        : integer range 1 to 16 := 1;
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               iWork          : integer range 0 to 1  := 1   -- 0 - różnica sygnałów sterujących, 1 - błąd
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               );
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      port
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         (
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               CLK_I               : in  std_logic;
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               RESET_I             : in  std_logic;
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               ERROR_I             : in  std_logic_vector(iDataWidith - 1 downto 0);
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               PATERN_I            : in  std_logic_vector(iDataWidith - 1 downto 0);
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               PATERN_ESTIMATION_I : in  std_logic_vector(iDataWidith - 1 downto 0);
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               CORRECT_O           : out std_logic_vector(iDataWidith - 1 downto 0)
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               );
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   end component pid_controller;
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-------------------------------------------------------------------------------
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-- constants --
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-------------------------------------------------------------------------------
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   constant TS : time := 5 ns;
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   constant iDataWidith    : integer range 8 to 32 := 12;
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   constant iKP            : integer range 0 to 7  := 2;  -- 0 - /2, 1 - /4, 2 - /8, 3 - /16, 4 - /32, 5 - /64, 6 - /128, 7 - /256
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   constant iKI            : integer range 0 to 7  := 1;  -- 0 - /2, 1 - /4, 2 - /8, 3 - /16, 4 - /32, 5 - /64, 6 - /128, 7 - /256
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   constant iKD            : integer range 0 to 7  := 1;  -- 0 - /2, 1 - /4, 2 - /8, 3 - /16, 4 - /32, 5 - /64, 6 - /128, 7 - /256
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   constant iKM            : integer range 0 to 7  := 0;  -- 0 - /1, 1 - /2, 2 - /4, 3 - /8 , 4 - /16, 5 - /32, 6 - /64 , 7 - /128
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   constant iDelayD        : integer range 1 to 16 := 16;
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   constant iWork          : integer range 0 to 1  := 0;
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-------------------------------------------------------------------------------
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-- signals --
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-------------------------------------------------------------------------------
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   -- Inputs --
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   signal CLK_I               : std_logic := '0';
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   signal RESET_I             : std_logic := '0';
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   signal ERROR_I             : std_logic_vector(iDataWidith - 1 downto 0) := x"00f";
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   signal PATERN_I            : std_logic_vector(iDataWidith - 1 downto 0) := x"6ff";
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   signal PATERN_ESTIMATION_I : std_logic_vector(iDataWidith - 1 downto 0) := x"007";
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   -- Outputs --
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   signal CORRECT_O           : std_logic_vector(iDataWidith - 1 downto 0);
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    -- Others --
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   signal v_count : std_logic_vector(15 downto 0) := x"0000";
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begin  -- architecture testbench
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   -- Unit Under Test --
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   uut :
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      pid_controler
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         generic map
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         (
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               iDataWidith    => iDataWidith,
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               iKP            => iKP,
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               iKI            => iKI,
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               iKD            => iKD,
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               iKM            => iKM,
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               iDelayD        => iDelayD,
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               iWork          => iWork
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               )
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         port map
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         (
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               CLK_I               => CLK_I,
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               RESET_I             => RESET_I,
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               ERROR_I             => ERROR_I,
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               PATERN_I            => PATERN_I,
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               PATERN_ESTIMATION_I => PATERN_ESTIMATION_I,
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               CORRECT_O           => CORRECT_O
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               );
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   -- stimulate proces --
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   stim_proc: process
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   begin
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      for i in 0 to 1000000 loop
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         CLK_I <= '0';
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         wait for TS;
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         CLK_I <= '1';
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         wait for TS;
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      end loop;  -- i
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   end process;
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   T0: process (CLK_I) is
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   begin  -- process T0
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      if rising_edge(CLK_I) then
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         case v_count is
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            when x"0010" =>
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               v_count <= v_count + 1;
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               RESET_I <= '1';
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            when x"0020" =>
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               v_count <= v_count + 1;
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               RESET_I <= '0';
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            when others =>
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               PATERN_ESTIMATION_I <= PATERN_I - 336 + CORRECT_O;
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               v_count <= v_count + 1;
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         end case;
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      end if;
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   end process T0;
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end architecture testbench;

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