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unicore |
/////////////////////////////////////////////////////////////////////
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//// ////
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//// FFT/IFFT 256 points transform ////
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//// ////
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//// Authors: Anatoliy Sergienko, Volodya Lepeha ////
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//// Company: Unicore Systems http://unicore.co.ua ////
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//// ////
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//// Downloaded from: http://www.opencores.org ////
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//// ////
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/////////////////////////////////////////////////////////////////////
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//// ////
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//// Copyright (C) 2006-2010 Unicore Systems LTD ////
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//// www.unicore.co.ua ////
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//// o.uzenkov@unicore.co.ua ////
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//// ////
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//// This source file may be used and distributed without ////
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//// restriction provided that this copyright statement is not ////
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//// removed from the file and that any derivative work contains ////
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//// the original copyright notice and the associated disclaimer.////
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//// ////
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//// THIS SOFTWARE IS PROVIDED "AS IS" ////
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//// AND ANY EXPRESSED OR IMPLIED WARRANTIES, ////
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//// INCLUDING, BUT NOT LIMITED TO, THE IMPLIED ////
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//// WARRANTIES OF MERCHANTABILITY, NONINFRINGEMENT ////
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//// AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. ////
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//// IN NO EVENT SHALL THE UNICORE SYSTEMS OR ITS ////
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//// CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, ////
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//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL ////
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//// DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT ////
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//// OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, ////
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//// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) ////
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//// HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, ////
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//// WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ////
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//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING ////
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//// IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, ////
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//// EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. ////
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//// ////
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/////////////////////////////////////////////////////////////////////
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//~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
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// DESCRIPTION : Stage of FFT 256 processor
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// FUNCTION: 16-point FFT
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// FILES: FFT16.v - stage, contains
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// MPUC707.v - multiplier to the factor 0.707.
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// PROPERTIES: 1) Fully pipelined
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// 2) Each clock cycle complex datum is entered
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// and complex result is outputted
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// 3) Has 16-clock cycle period starting with the START impulse
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// and continuing forever
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// 4) rounding is not used
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// 5)Algorithm is from the book "H.J.Nussbaumer FFT and convolution algorithms".
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// 6)IFFT is performed by substituting the output result order to the reversed one
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// (by exchanging - to + and + to -)
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//~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
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//Algorithm:
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///procedure FFT16(
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// X: in MEMOC; -- âõîäíîé ìàññèâ äàííûõ
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// y:out MEMOC) -- âûõîäíîé ìàññèâ ñïåêòðîâ
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// is
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// variable t1,t2,t3,t4,t5,t6,t7,t8,t9,t10: complex;
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// variable t11,t12,t13,t14,t15,t16,t17,t18,t19,t20: complex;
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// variable t21,t22,t23,t24,t25,t26: complex;
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// variable m0,m1,m2,m3,m4,m5,m6,m7,m8,m9,m10: complex;
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// variable m11,m12,m13,m14,m15,m16,m17: complex;
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// variable s1,s2,s3,s4,s5,s6,s7,s8,s9,s10: complex;
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// variable s11,s12,s13,s14,s15,s16,s17,s18,s19,s20: complex;
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// begin
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// t1:=x(0) + x(8); m4:=x(0) - x(8);
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// t2:=x(4) + x(12); m12:=-CBASE_j*(x(4)-x(12));
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// t3:=x(2) + x(10); t4:=x(2) - x(10);
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// t5:=x(6) + x(14); t6:=x(6) - x(14);
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// t7:=x(1) + x(9); t8:=x(1) - x(9);
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// t9:=x(3) + x(11); t10:=x(3) - x(11);
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// t11:=x(5) + x(13); t12:=x(5) - x(13);
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// t13:=x(7) + x(15); t14:=x(7) - x(15);
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// t15:=t1 + t2; m3:= t1 - t2;
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// t16:=t3 + t5; m11:= -CBASE_j*(t3 - t5);
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// t17:=t15 + t16; m2:= t15 - t16;
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// t18:=t7 + t11; t19:= t7 - t11;
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// t20:=t9 + t13; t21:= t9 - t13;
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// t22:=t18 + t20; m10:= -CBASE_j*(t18 - t20);
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// t23:=t8 + t14; t24:= t8 - t14;
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// t25:=t12 + t10; t26:= t12 - t10;
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//
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// m0:=t17 + t22; m1:=t17 - t22;
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// m13:=-CBASE_j*c707*(t19 + t21); m5:=c707*(t19 - t21);
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// m6:=c707*(t4 - t6); m14:=-CBASE_j*c707*(t4 + t6);
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//
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// m7:=c3*(t24+t26);
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// m8:=c13*(t24);
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// m9:=-s1_3*(t26);
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// s7:= m8 - m7;
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// s8:= m9 - m7;
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//
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// m15:=-CBASE_j*c1*(t23 + t25);
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// m16:= -CBASE_j*s1_3*(t23);
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// m17:=-CBASE_j*c13*(t25);
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// s15:= m15 - m16;
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// s16:= m15 - m17;
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//
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// s1:=m3 + m5; s2:=m3 - m5;
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// s3:=m13 + m11; s4:=m13 - m11;
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// s5:=m4 + m6; s6:=m4 - m6;
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// s9:=s5 + s7; s10:=s5 - s7;
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// s11:=s6 + s8; s12:=s6 - s8;
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// s13:=m12 + m14; s14:=m12 - m14;
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// s17:=s13 + s15; s18:=s13 - s15;
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// s19:=s14 + s16; s20:=s14 - s16;
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//
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// y(0):=m0; y(8):=m1;
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// y(1):=s9 + s17; y(15):=s9 - s17;
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// y(2):=s1 + s3; y(14):=s1 - s3;
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// y(3):=s12 - s20; y(13):=s12 + s20;
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// y(4):=m2 + m10; y(12):=m2 - m10;
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// y(5):=s11 + s19; y(11):=s11 - s19;
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// y(6):=s2 + s4; y(10):=s2 - s4;
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// y(7):=s10 - s18; y(9):=s10 + s18;
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// end procedure;
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//
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`timescale 1ns / 1ps
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`include "FFT256_CONFIG.inc"
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module FFT16 ( DOR ,DII ,RST ,ED ,CLK ,DOI ,START ,DIR ,RDY );
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`FFT256paramnb
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input ED ; //slowdown impulse
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wire ED ;
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input RST ;
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wire RST ;
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input CLK ;
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wire CLK ;
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input [nb-1:0] DII ;
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wire [nb-1:0] DII ;
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input START ;
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wire START ;
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input [nb-1:0] DIR ;
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wire [nb-1:0] DIR ;
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output [nb+3:0] DOI ;
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wire [nb+3:0] DOI ;
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output [nb+3:0] DOR ;
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wire [nb+3:0] DOR ;
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output RDY ;
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reg RDY ;
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reg [3:0] ct; //main phase counter
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reg [5:0] ctd; //delay counter
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always @( posedge CLK) begin //Control counter
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//
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if (RST) begin
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ct<=0;
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ctd<=63;
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RDY<=0; end
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else if (START) begin
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ct<=0;
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ctd<=0;
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RDY<=0; end
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else if (ED) begin
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RDY<=0;
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ct<=ct+1;
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if (ctd !=6'b111111)
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ctd<=ctd+1;
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if (ctd==44-16 )
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RDY<=1;
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end
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end
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reg signed [nb-1: 0] dr,d1r,d2r,d3r,d4r,d5r,d6r,d7r,d8r,di,d1i,d2i,d3i,d4i,d5i,d6i,d7i,d8i;
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always @(posedge CLK) // input register file
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begin
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if (ED) begin
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dr<=DIR;
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d1r<=dr; d2r<=d1r; d3r<=d2r;d4r<=d3r;
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d5r<=d4r;d6r<=d5r; d7r<=d6r; d8r<=d7r;
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di<=DII;
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d1i<=di; d2i<=d1i; d3i<=d2i; d4i<=d3i;
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d5i<=d4i; d6i<=d5i;d7i<=d6i; d8i<=d7i;
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end
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end
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reg signed [nb:0] s1r,s1d1r,s1d2r,s1d3r,s1d4r,s1d5r,s1d6r,s1d7r,s1d8r; //even result sums
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reg signed [nb:0] s1i,s1d1i,s1d2i,s1d3i,s1d4i,s1d5i,s1d6i,s1d7i,s1d8i; //even result sums
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reg signed [nb:0] s2r,s2d1r,s2d2r,s2d3r,s2d4r,s2d5r,s2d6r,s2d7r,s2d8r,m4_12r; //odd result sums
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reg signed [nb:0] s2i,s2d1i,s2d2i,s2d3i,s2d4i,s2d5i,s2d6i,s2d7i,s2d8i,m4_12i; //odd result sums
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always @(posedge CLK) begin // S1,S2 =t1-t14,m4,m12' and delayed
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if (ED && ((ct==9) || (ct==10) || (ct==11) ||(ct==12) ||
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(ct==13) || (ct==14) ||(ct==15) || (ct==0))) begin
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s1r<=d8r + dr ;
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s1i<=d8i + di ;
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s2r<=d8r - dr ;
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s2i<= d8i - di;
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end
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if (ED) begin //delayed results
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s1d1r<=s1r; s1d2r<=s1d1r; s1d1i<=s1i; s1d2i<=s1d1i;
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s1d3r<=s1d2r; s1d3i<=s1d2i; s1d4r<=s1d3r; s1d4i<=s1d3i;
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s1d5r<=s1d4r; s1d5i<=s1d4i; s1d6r<=s1d5r; s1d6i<=s1d5i;
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s1d7r<=s1d6r; s1d7i<=s1d6i; s1d8r<=s1d7r; s1d8i<=s1d7i;
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s2d1r<=s2r; s2d2r<=s2d1r; s2d1i<=s2i; s2d2i<=s2d1i;
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s2d3r<=s2d2r; s2d3i<=s2d2i; s2d4r<=s2d3r; s2d4i<=s2d3i;
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s2d5r<=s2d4r; s2d5i<=s2d4i; s2d6r<=s2d5r; s2d6i<=s2d5i;
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s2d7r<=s2d6r; s2d7i<=s2d6i; s2d8r<=s2d7r; s2d8i<=s2d7i;
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if (ct==2) begin
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m4_12r<=s2d8r; m4_12i<=s2d8i; end
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else if (ct==6) begin
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m4_12r<=s2d8i; m4_12i<= 0 - s2d8r;
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end
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end
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end
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///////////////////////////////////////////
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//arm of even result calculations
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////////////////////////////////////////////
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reg signed [nb+1:0] s3r,s3d1r,s3d2r,s3d3r,s3d4r,s3d5r,s3d6r;
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reg signed [nb+1:0] s3i,s3d1i,s3d2i,s3d3i,s3d4i,s3d5i,s3d6i;
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always @(posedge CLK) begin //ALU S3:
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if (ED) begin
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case (ct)
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14 ,15 : begin s3r<= s1d4r+s1r; //t15 //t18
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s3i<= s1d4i+ s1i ;end
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s3i<= s1d6i - s1d2i ;end
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2 ,3 : begin s3r<= s1d6r +s1d2r; //t16 ,t20
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s3i<= s1d6i+ s1d2i ; end
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4 ,5 : begin s3r<= s1d8r - s1d4r; // m11',t21
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s3i<= s1d8i - s1d4i ; end
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endcase
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s3d1r<=s3r; s3d1i<=s3i; s3d2r<=s3d1r; s3d2i<=s3d1i;
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s3d3r<=s3d2r; s3d3i<=s3d2i; s3d4r<=s3d3r; s3d4i<=s3d3i;
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s3d5r<=s3d4r; s3d5i<=s3d4i; s3d6r<=s3d5r; s3d6i<=s3d5i;
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end
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end
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reg signed [nb+2:0] s4r,s4d1r,s4d2r,s4d3r,s4d4r,s4d5r,s4d6r,s4d7r,m3r;
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reg signed [nb+2:0] s4i,s4d1i,s4d2i,s4d3i,s4d4i,s4d5i,s4d6i,s4d7i,m3i;
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always @ (posedge CLK) begin // S4
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if (ED) begin
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if ((ct==3) | (ct==4)) begin
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s4r<= s3d4r + s3r; //t17 ,t22
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s4i<= s3d4i + s3i; end
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else if ((ct==5) | (ct==6) | (ct==8) ) begin
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s4r<=s3d6r - s3d2r; //m2,m10', m5'
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s4i<= s3d6i - s3d2i; end
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else if (ct==7) begin
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s4r<=s3d1r + s3d5r; //m13
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s4i<= s3d1i + s3d5i;
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end
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s4d1r<=s4r; s4d1i<=s4i; s4d2r<=s4d1r; s4d2i<=s4d1i;
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s4d3r<=s4d2r; s4d3i<=s4d2i; s4d4r<=s4d3r; s4d4i<=s4d3i;
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s4d5r<=s4d4r; s4d5i<=s4d4i; s4d6r<=s4d5r; s4d6i<=s4d5i;
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s4d7r<=s4d6r; s4d7i<=s4d6i;
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if (ct==7) begin
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m3r<=s3d6r; //m3
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m3i<=s3d6i; end
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end
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end
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wire em707,mpyj7;
|
| 261 |
|
|
assign em707 = ((ct==8) || (ct==10 )||(ct==1) || (ct==5)); //control signals for the multiplier
|
| 262 |
|
|
assign mpyj7 = ((ct==8) || (ct==5));
|
| 263 |
|
|
|
| 264 |
|
|
reg signed [nb+2:0] s7r,s7d1r;
|
| 265 |
|
|
reg signed [nb+2:0] s7i,s7d1i;
|
| 266 |
|
|
wire signed [nb+2:0] m707r,m707i,m70r,m70i;
|
| 267 |
|
|
assign m70r = ((ct==1) || (ct==5))? s7r :s4r; //multiplexor at the multiplier input
|
| 268 |
|
|
assign m70i = ((ct==1) || (ct==5))? s7i :s4i;
|
| 269 |
|
|
|
| 270 |
|
|
MPUC707 #(nb+3) UM707( .CLK(CLK),.EI(ED),.ED(em707), .MPYJ(mpyj7), //multiplier by 0.707
|
| 271 |
|
|
.DR(m70r),.DI(m70i) ,.DOR(m707r) ,.DOI(m707i));
|
| 272 |
|
|
|
| 273 |
|
|
|
| 274 |
|
|
reg signed [nb+2:0] s3jr,s3ji, m10r,m10i;
|
| 275 |
|
|
always @ (posedge CLK) begin //multiply by J
|
| 276 |
|
|
if (ED) begin
|
| 277 |
|
|
case (ct)
|
| 278 |
|
|
11: begin s3jr<= s3d6i; //m11
|
| 279 |
|
|
s3ji<=0 - s3d6r; end
|
| 280 |
|
|
14: begin s3jr<= s4d7i; //m10
|
| 281 |
|
|
s3ji<=0 - s4d7r; end
|
| 282 |
|
|
endcase
|
| 283 |
|
|
if (ct==1) begin
|
| 284 |
|
|
m10r<=s3jr; //m10
|
| 285 |
|
|
m10i<=s3ji;
|
| 286 |
|
|
end
|
| 287 |
|
|
end
|
| 288 |
|
|
end
|
| 289 |
|
|
|
| 290 |
|
|
reg signed [nb+3:0] s5r,s5d1r,s5d2r,s5d3r,s5d4r,s5d5r,s5d6r,s5d7r,s5d8r,s5d9r, s5d10r,m2r,m2dr;
|
| 291 |
|
|
reg signed [nb+3:0] s5i,s5d1i,s5d2i,s5d3i,s5d4i,s5d5i,s5d6i,s5d7i,s5d8i,s5d9i,s5d10i,m2i,m2di;
|
| 292 |
|
|
always @ (posedge CLK) // S5:
|
| 293 |
|
|
if (ED) begin
|
| 294 |
|
|
case (ct)
|
| 295 |
|
|
10: begin s5r<=s4d5r + s4d6r; //m0
|
| 296 |
|
|
s5i<=s4d5i + s4d6i; end
|
| 297 |
|
|
11: begin s5r<=s4d7r - s4d6r; //m1
|
| 298 |
|
|
s5i<=s4d7i - s4d6i; end
|
| 299 |
|
|
12: begin s5r<=m707r + s3jr; //S3
|
| 300 |
|
|
s5i<= m707i+s3ji;end
|
| 301 |
|
|
13: begin s5r<=m707r - s3jr; //S4
|
| 302 |
|
|
s5i<= m707i - s3ji;end
|
| 303 |
|
|
14: begin s5r<= m3r+m707r; //S1
|
| 304 |
|
|
s5i<= m3i+m707i ;end
|
| 305 |
|
|
15: begin s5r<=m3r-m707r ; //S2
|
| 306 |
|
|
s5i<= m3i -m707i ;end
|
| 307 |
|
|
6: begin //S2
|
| 308 |
|
|
s5d10r<=s5d9r ; //S2
|
| 309 |
|
|
s5d10i<=s5d9i ;end
|
| 310 |
|
|
|
| 311 |
|
|
endcase
|
| 312 |
|
|
if ((ct==4)||(ct==5)||(ct==6)||(ct==7)) begin
|
| 313 |
|
|
s5d9r<=s5d8r ; s5d9i<=s5d8i ; end
|
| 314 |
|
|
|
| 315 |
|
|
s5d1r<=s5r; s5d1i<=s5i; s5d2r<=s5d1r; s5d2i<=s5d1i;
|
| 316 |
|
|
s5d3r<=s5d2r; s5d3i<=s5d2i; s5d4r<=s5d3r; s5d4i<=s5d3i;
|
| 317 |
|
|
s5d5r<=s5d4r; s5d5i<=s5d4i; s5d6r<=s5d5r; s5d6i<=s5d5i;
|
| 318 |
|
|
s5d7r<=s5d6r; s5d7i<=s5d6i; s5d8r<=s5d7r; s5d8i<=s5d7i;
|
| 319 |
|
|
|
| 320 |
|
|
if (ct==13) begin
|
| 321 |
|
|
m2r<=s4d7r; m2i<=s4d7i; end
|
| 322 |
|
|
if (ct==1) begin
|
| 323 |
|
|
m2dr<=m2r; m2di<=m2i; end
|
| 324 |
|
|
|
| 325 |
|
|
end
|
| 326 |
|
|
|
| 327 |
|
|
|
| 328 |
|
|
|
| 329 |
|
|
reg signed [nb+3:0] s6r,s6i ;
|
| 330 |
|
|
|
| 331 |
|
|
`ifdef FFT256paramifft // For IFFT
|
| 332 |
|
|
always @ (posedge CLK) begin // S6-- result adder
|
| 333 |
|
|
if (ED)
|
| 334 |
|
|
case (ct)
|
| 335 |
|
|
13: begin s6r<=s5d2r; // -- Y0
|
| 336 |
|
|
s6i<=(s5d2i);end //-- Y0
|
| 337 |
|
|
15: begin
|
| 338 |
|
|
s6r<=s5d2r - s5r ; //Y2
|
| 339 |
|
|
s6i<=s5d2i - s5i ; end
|
| 340 |
|
|
1: begin
|
| 341 |
|
|
s6r<=m2r - s3jr ; //Y4
|
| 342 |
|
|
s6i<=m2i - s3ji ; end
|
| 343 |
|
|
3: begin
|
| 344 |
|
|
s6r<=s5d3r - s5d5r ; //Y6
|
| 345 |
|
|
s6i<= s5d3i -s5d5i ; end
|
| 346 |
|
|
5:begin s6r<=(s5d9r) ; //-- Y8
|
| 347 |
|
|
s6i<=(s5d9i) ; end
|
| 348 |
|
|
7: begin
|
| 349 |
|
|
s6r<= s5d7r + s5d9r ; // Y10
|
| 350 |
|
|
s6i<= s5d7i + s5d9i ; end
|
| 351 |
|
|
9: begin // Y12
|
| 352 |
|
|
s6r<=m2dr +m10r ;
|
| 353 |
|
|
s6i<=m2di + m10i ;
|
| 354 |
|
|
end
|
| 355 |
|
|
11: begin // Y14
|
| 356 |
|
|
s6r<= s5d9r + s5d10r ;
|
| 357 |
|
|
s6i<= s5d9i + s5d10i ;
|
| 358 |
|
|
end
|
| 359 |
|
|
endcase
|
| 360 |
|
|
end
|
| 361 |
|
|
|
| 362 |
|
|
`else
|
| 363 |
|
|
always @ (posedge CLK) begin // S6-- result adder
|
| 364 |
|
|
if (ED)
|
| 365 |
|
|
case (ct)
|
| 366 |
|
|
13: begin s6r<=s5d2r; // -- Y0
|
| 367 |
|
|
s6i<=s5d2i;end //-- Y0
|
| 368 |
|
|
15: begin
|
| 369 |
|
|
s6r<=s5d2r + s5r ; //Y2
|
| 370 |
|
|
s6i<=s5d2i + s5i ; end
|
| 371 |
|
|
1: begin
|
| 372 |
|
|
s6r<=m2r + s3jr ; //Y4
|
| 373 |
|
|
s6i<=m2i + s3ji ; end
|
| 374 |
|
|
3: begin
|
| 375 |
|
|
s6r<=s5d3r + s5d5r ; //Y6
|
| 376 |
|
|
s6i<= s5d3i +s5d5i ; end
|
| 377 |
|
|
5:begin s6r<=s5d9r; //-- Y8
|
| 378 |
|
|
s6i<=s5d9i; end
|
| 379 |
|
|
7: begin
|
| 380 |
|
|
s6r<= s5d7r - s5d9r ; // Y10
|
| 381 |
|
|
s6i<= s5d7i - s5d9i ; end
|
| 382 |
|
|
9: begin // Y12
|
| 383 |
|
|
s6r<=m2dr -m10r ;
|
| 384 |
|
|
s6i<=m2di - m10i ;
|
| 385 |
|
|
end
|
| 386 |
|
|
11: begin // Y14
|
| 387 |
|
|
s6r<= s5d9r - s5d10r ;
|
| 388 |
|
|
s6i<= s5d9i - s5d10i ;
|
| 389 |
|
|
end
|
| 390 |
|
|
endcase
|
| 391 |
|
|
end
|
| 392 |
|
|
`endif
|
| 393 |
|
|
|
| 394 |
|
|
///////////////////////////////////////////////////////////
|
| 395 |
|
|
//arm of odd result calculations
|
| 396 |
|
|
//////////////////////////////////////////////////////////
|
| 397 |
|
|
|
| 398 |
|
|
always @(posedge CLK) begin //ALU S7:
|
| 399 |
|
|
if (ED)
|
| 400 |
|
|
case (ct)
|
| 401 |
|
|
15:begin s7r<= s2d2r-s2r; //t26
|
| 402 |
|
|
s7i<= s2d2i- s2i ;end
|
| 403 |
|
|
0: begin s7r<= s2d4r-s2r; //m6'
|
| 404 |
|
|
s7i<= s2d4i- s2i ;
|
| 405 |
|
|
s7d1r<=s7r;
|
| 406 |
|
|
s7d1i<=s7i;end
|
| 407 |
|
|
1: begin s7r<= s2d6r - s2r; //t24
|
| 408 |
|
|
s7i<= s2d6i - s2i; end
|
| 409 |
|
|
2: begin s7r<= s7r -s7d1r; //m7'
|
| 410 |
|
|
s7i<= s7i- s7d1i ; end
|
| 411 |
|
|
3: begin s7r<= s2d8r + s2d2r; // t23
|
| 412 |
|
|
s7i<= s2d8i + s2d2i ; end
|
| 413 |
|
|
4: begin s7r<= s2d8r + s2d4r; // m14'
|
| 414 |
|
|
s7i<= s2d8i + s2d4i ;
|
| 415 |
|
|
s7d1r<=s7r;
|
| 416 |
|
|
s7d1i<=s7i;end
|
| 417 |
|
|
5: begin s7r<= s2d8r + s2d6r; // t25
|
| 418 |
|
|
s7i<= s2d8i + s2d6i ; end
|
| 419 |
|
|
6: begin s7r<= s7r + s7d1r; //m15'
|
| 420 |
|
|
s7i<= s7i + s7d1i ; end
|
| 421 |
|
|
endcase
|
| 422 |
|
|
end
|
| 423 |
|
|
|
| 424 |
|
|
wire em541,mpyj541;
|
| 425 |
|
|
wire signed [nb+2:0] m541r,m541i;
|
| 426 |
|
|
assign em541 = ((ct==0) || (ct==4)); //control signals for the multiplier
|
| 427 |
|
|
assign mpyj541 = ((ct==4));
|
| 428 |
|
|
MPUC541 #(nb+3) UM541( .CLK(CLK),.EI(ED),.ED(em541), .MPYJ(mpyj541), //multiplier by 0.383
|
| 429 |
|
|
.DR(s7r),.DI(s7i) ,.DOR(m541r) ,.DOI(m541i));
|
| 430 |
|
|
|
| 431 |
|
|
|
| 432 |
|
|
wire em1307,mpyj1307;
|
| 433 |
|
|
wire signed [nb+2:0] m1307r,m1307i;
|
| 434 |
|
|
assign em1307 = ((ct==2) || (ct==6)); //control signals for the multiplier
|
| 435 |
|
|
assign mpyj1307 = ((ct==6));
|
| 436 |
|
|
MPUC1307 #(nb+3) UM1307( .CLK(CLK),.EI(ED),.ED(em1307), .MPYJ(mpyj1307), //multiplier by 1.306
|
| 437 |
|
|
.DR(s7r),.DI(s7i) ,.DOR(m1307r) ,.DOI(m1307i));
|
| 438 |
|
|
|
| 439 |
|
|
wire em383,mpyj383,c383;
|
| 440 |
|
|
wire signed [nb+2:0] m383r,m383i;
|
| 441 |
|
|
assign em383 = ((ct==3) || (ct==7)); //control signals for the multiplier
|
| 442 |
|
|
assign mpyj383 = ((ct==7));
|
| 443 |
|
|
assign c383 = (ct==3);
|
| 444 |
|
|
MPUC924_383 #(nb+3) UM383(.CLK(CLK),.EI(ED),.ED(em383),.MPYJ(mpyj383),.C383(c383), //multiplier by 0.383
|
| 445 |
|
|
.DR(s7r),.DI(s7i) ,.DOR(m383r) ,.DOI(m383i));
|
| 446 |
|
|
|
| 447 |
|
|
reg signed [nb+2:0] m8_17r,m8_17i,m9_16r,m9_16i;
|
| 448 |
|
|
always @(posedge CLK) begin //Reg-s
|
| 449 |
|
|
if (ED) begin
|
| 450 |
|
|
if (ct==4 || ct==8) begin
|
| 451 |
|
|
m9_16r<=m541r; //M9_ M16
|
| 452 |
|
|
m9_16i<=m541i;
|
| 453 |
|
|
end
|
| 454 |
|
|
if ( ct==6 || ct==10) begin
|
| 455 |
|
|
m8_17r<=m1307r; //M8_ M17
|
| 456 |
|
|
m8_17i<=m1307i;
|
| 457 |
|
|
end
|
| 458 |
|
|
end
|
| 459 |
|
|
end
|
| 460 |
|
|
|
| 461 |
|
|
|
| 462 |
|
|
|
| 463 |
|
|
|
| 464 |
|
|
reg signed [nb+2:0] s8r,s8i,s8d1r,s8d2r,s8d3r,s8d4r,s8d1i,s8d2i,s8d3i,s8d4i ;
|
| 465 |
|
|
always @ (posedge CLK) begin // S8-- adder
|
| 466 |
|
|
if (ED)
|
| 467 |
|
|
case (ct)
|
| 468 |
|
|
5,9: begin s8r<=m4_12r +m707r ; // -- S5 S13
|
| 469 |
|
|
s8i<=m4_12i +m707i ;end //--
|
| 470 |
|
|
6,10: begin
|
| 471 |
|
|
s8r<=m4_12r - m707r ; // -- S6 , S14
|
| 472 |
|
|
s8i<=m4_12i - m707i ; end
|
| 473 |
|
|
7: begin
|
| 474 |
|
|
s8r<=m8_17r - m383r ; // -- S7 ,S15
|
| 475 |
|
|
s8i<=m8_17i -m383i ; end
|
| 476 |
|
|
8: begin
|
| 477 |
|
|
s8r<=m9_16r - m383r ; // -- S8 , S16
|
| 478 |
|
|
s8i<=m9_16i -m383i ; end
|
| 479 |
|
|
11: begin
|
| 480 |
|
|
s8r<=m383r - m9_16r ; // -- S7 ,S15
|
| 481 |
|
|
s8i<=m383i - m9_16i; end
|
| 482 |
|
|
12: begin
|
| 483 |
|
|
s8r<=m383r - m8_17r; // -- S8 , S16
|
| 484 |
|
|
s8i<=m383i - m8_17i; end
|
| 485 |
|
|
endcase
|
| 486 |
|
|
s8d1r<=s8r; s8d1i<=s8i; s8d2r<=s8d1r; s8d2i<=s8d1i;
|
| 487 |
|
|
s8d3r<=s8d2r; s8d3i<=s8d2i; s8d4r<=s8d3r; s8d4i<=s8d3i;
|
| 488 |
|
|
end
|
| 489 |
|
|
|
| 490 |
|
|
reg signed [nb+3:0] s9r,s9d1r,s9d2r,s9d3r,s9d4r,s9d5r,s9d6r,s9d7r,s9d8r,s9d9r, s9d10r,s9d11r,s9d12r,s9d13r;
|
| 491 |
|
|
reg signed [nb+3:0] s9i,s9d1i,s9d2i,s9d3i,s9d4i,s9d5i,s9d6i,s9d7i,s9d8i,s9d9i,s9d10i,s9d11i,s9d12i,s9d13i;
|
| 492 |
|
|
always @ (posedge CLK) // ALU s9:
|
| 493 |
|
|
if (ED) begin
|
| 494 |
|
|
case (ct)
|
| 495 |
|
|
8,9,12: begin s9r<= s8r + s8d2r; // S9,S11 , S17
|
| 496 |
|
|
s9i<=s8i + s8d2i ; end
|
| 497 |
|
|
13: begin s9r<= s8d2r - s8r; // S20
|
| 498 |
|
|
s9i<=s8d2i - s8i ; end
|
| 499 |
|
|
10,11,14: begin s9r<=s8d4r - s8d2r; //S10, S12,S18
|
| 500 |
|
|
s9i<=s8d4i - s8d2i; end
|
| 501 |
|
|
15: begin s9r<=s8d4r + s8d2r; //S19
|
| 502 |
|
|
s9i<=s8d4i + s8d2i; end
|
| 503 |
|
|
endcase
|
| 504 |
|
|
|
| 505 |
|
|
s9d1r<=s9r; s9d1i<=s9i; s9d2r<=s9d1r; s9d2i<=s9d1i;
|
| 506 |
|
|
s9d3r<=s9d2r; s9d3i<=s9d2i; s9d4r<=s9d3r; s9d4i<=s9d3i;
|
| 507 |
|
|
s9d5r<=s9d4r; s9d5i<=s9d4i; s9d6r<=s9d5r; s9d6i<=s9d5i;
|
| 508 |
|
|
s9d7r<=s9d6r; s9d7i<=s9d6i; s9d8r<=s9d7r; s9d8i<=s9d7i;
|
| 509 |
|
|
|
| 510 |
|
|
s9d9r<=s9d8r ; s9d9i<=s9d8i ;
|
| 511 |
|
|
if ((ct!=8)) begin
|
| 512 |
|
|
s9d10r<=s9d9r ; s9d10i<=s9d9i ;
|
| 513 |
|
|
s9d11r<=s9d10r ; s9d11i<=s9d10i ; end
|
| 514 |
|
|
if ((ct==4) ||(ct==5) ||(ct==7) ||(ct==9) ) begin
|
| 515 |
|
|
s9d12r<=s9d11r ; s9d12i<=s9d11i ; end
|
| 516 |
|
|
if ((ct==5))begin
|
| 517 |
|
|
s9d13r<=s9d12r ; s9d13i<=s9d12i ; end
|
| 518 |
|
|
|
| 519 |
|
|
end
|
| 520 |
|
|
|
| 521 |
|
|
|
| 522 |
|
|
reg signed [nb+3:0] s10r,s10i;
|
| 523 |
|
|
reg signed [nb+3:0] s10dr,s10di;
|
| 524 |
|
|
|
| 525 |
|
|
`ifdef FFT256paramifft //For IFFT
|
| 526 |
|
|
always @ (posedge CLK) begin // S10-- result adder
|
| 527 |
|
|
if (ED)
|
| 528 |
|
|
case (ct)
|
| 529 |
|
|
13: begin s10r<=s9d4r -s9r ; // -- Y1
|
| 530 |
|
|
s10i<=s9d4i -s9i ;end //
|
| 531 |
|
|
15: begin
|
| 532 |
|
|
s10r<=s9d3r + s9d1r ; //-- Y3
|
| 533 |
|
|
s10i<=s9d3i + s9d1i ; end
|
| 534 |
|
|
1: begin
|
| 535 |
|
|
s10r<=s9d7r - s9d1r ; //-- Y5
|
| 536 |
|
|
s10i<=s9d7i - s9d1i ; end
|
| 537 |
|
|
3: begin
|
| 538 |
|
|
s10r<=s9d8r + s9d4r ; // -- Y7
|
| 539 |
|
|
s10i<= s9d8i + s9d4i ;end
|
| 540 |
|
|
|
| 541 |
|
|
5:begin s10r<=s9d10r - s9d6r ; //-- Y9
|
| 542 |
|
|
s10i<=s9d10i - s9d6i ; end
|
| 543 |
|
|
7: begin
|
| 544 |
|
|
s10r<=s9d12r + s9d7r ; //-- Y11
|
| 545 |
|
|
s10i<=s9d12i + s9d7i ; end
|
| 546 |
|
|
|
| 547 |
|
|
9: begin
|
| 548 |
|
|
s10r<= s9d12r - s9d10r ; // Y13
|
| 549 |
|
|
s10i<=s9d12i - s9d10i ; end
|
| 550 |
|
|
|
| 551 |
|
|
11: begin
|
| 552 |
|
|
s10r<= s9d13r + s9d12r ; // Y15
|
| 553 |
|
|
s10i<= s9d13i + s9d12i ; end
|
| 554 |
|
|
|
| 555 |
|
|
endcase
|
| 556 |
|
|
s10dr<=s10r; s10di<=s10i;
|
| 557 |
|
|
end
|
| 558 |
|
|
`else
|
| 559 |
|
|
|
| 560 |
|
|
// reg signed [nb+3:0] s10r,s10i,s10dr,s10di;
|
| 561 |
|
|
always @ (posedge CLK) begin // S10-- result adder
|
| 562 |
|
|
if (ED)
|
| 563 |
|
|
case (ct)
|
| 564 |
|
|
13: begin s10r<=s9d4r +s9r ; // -- Y0
|
| 565 |
|
|
s10i<=s9d4i +s9i ;end //
|
| 566 |
|
|
15: begin
|
| 567 |
|
|
s10r<=s9d3r - s9d1r ; //-- Y3
|
| 568 |
|
|
s10i<=s9d3i - s9d1i ; end
|
| 569 |
|
|
1: begin
|
| 570 |
|
|
s10r<=s9d7r +s9d1r ; //-- Y5
|
| 571 |
|
|
s10i<=s9d7i +s9d1i ; end
|
| 572 |
|
|
3: begin
|
| 573 |
|
|
s10r<=s9d8r - s9d4r ; // -- Y7
|
| 574 |
|
|
s10i<= s9d8i - s9d4i ;end
|
| 575 |
|
|
|
| 576 |
|
|
5:begin s10r<=s9d10r + s9d6r ; //-- Y9
|
| 577 |
|
|
s10i<=s9d10i + s9d6i ; end
|
| 578 |
|
|
7: begin
|
| 579 |
|
|
s10r<=s9d12r - s9d7r ; //-- Y11
|
| 580 |
|
|
s10i<=s9d12i - s9d7i ; end
|
| 581 |
|
|
|
| 582 |
|
|
9: begin
|
| 583 |
|
|
s10r<= s9d12r + s9d10r ; // Y13
|
| 584 |
|
|
s10i<=s9d12i + s9d10i ; end
|
| 585 |
|
|
|
| 586 |
|
|
11: begin
|
| 587 |
|
|
s10r<= s9d13r - s9d12r ; // Y15
|
| 588 |
|
|
s10i<= s9d13i - s9d12i ; end
|
| 589 |
|
|
|
| 590 |
|
|
endcase
|
| 591 |
|
|
s10dr<=s10r; s10di<=s10i;
|
| 592 |
|
|
end
|
| 593 |
|
|
`endif
|
| 594 |
|
|
|
| 595 |
|
|
//wire signed [nb+3:0] s6sr,s6si; //saturation of results
|
| 596 |
|
|
// assign s6sr = (~s6r[nb+4]&&s6r[nb+3])? ((1'b1 <<(nb+3))-1) : s6r[nb+3:0];
|
| 597 |
|
|
// assign s6si = (~s6i[nb+4]&&s6i[nb+3])? ((1'b1<<(nb+3))-1) : s6i[nb+3:0];
|
| 598 |
|
|
//
|
| 599 |
|
|
|
| 600 |
|
|
wire selo;
|
| 601 |
|
|
assign selo = ct-(ct/2)*2;
|
| 602 |
|
|
assign #1 DOR=selo? s10dr:s6r;
|
| 603 |
|
|
assign #1 DOI= selo? s10di:s6i;
|
| 604 |
|
|
|
| 605 |
|
|
endmodule
|
