Subversion Repositories pipelined_fft_256

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////  FFT/IFFT 256 points transform                              ////

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////  Authors: Anatoliy Sergienko, Volodya Lepeha                ////

////  Company: Unicore Systems http://unicore.co.ua              ////

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////  Downloaded from: http://www.opencores.org                  ////

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//// Copyright (C) 2006-2010 Unicore Systems LTD                 ////

//// www.unicore.co.ua                                           ////

//// o.uzenkov@unicore.co.ua                                     ////

////                                                             ////

//// This source file may be used and distributed without        ////

//// restriction provided that this copyright statement is not   ////

//// removed from the file and that any derivative work contains ////

//// the original copyright notice and the associated disclaimer.////

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//// THIS SOFTWARE IS PROVIDED "AS IS"                           ////

//// AND ANY EXPRESSED OR IMPLIED WARRANTIES,                    ////

//// INCLUDING, BUT NOT LIMITED TO, THE IMPLIED                  ////

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//// AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.        ////

//// IN NO EVENT SHALL THE UNICORE SYSTEMS OR ITS                ////

//// CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,            ////

//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL            ////

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//// OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,               ////

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//~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~           

// DESCRIPTION  :        Complex Multiplier by 0.7071

// FUNCTION:               Constant multiplier

// FILES:                        MPU707.v

//  PROPERTIES: 1) Is based on shifts right and add

//                                                      2) for short input bit width 0.7071 is approximated as 10110101                            then rounding        is not used

//                                                      3) for long input bit width 0.7071 is approximated as 10110101000000101        

//                                                  4) hardware is 4 or 5 adders 

//                                                  5) MPYJ switches multiply by j                               

//                                                      6) A complex data is multiplied for 2 cycles

//~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~

`include "FFT256_CONFIG.inc"

module MPUC707 ( CLK,EI ,ED, MPYJ,DR,DI ,DOR ,DOI,  );

        `FFT256paramnb

        input CLK ;

        wire CLK ;

        input EI ;                                      //slowdown

        wire EI ;

        input ED;                                       //data strobe

        input MPYJ ;                            //the result is multiplied by -j

        wire MPYJ ;

        input [nb-1:0] DR ;

        wire signed [nb-1:0] DR ;

        input [nb-1:0] DI ;

        wire signed [nb-1:0] DI ;

        output [nb-1:0] DOR ;

        reg [nb-1:0] DOR ;

        output [nb-1:0] DOI ;

        reg [nb-1:0] DOI ;

        reg signed [nb+1 :0] dx5;

        reg signed      [nb : 0] dt;

        reg signed      [nb-1 : 0] dii;

        wire signed [nb+2 : 0]  dx5p;

        wire  signed  [nb+3 : 0] dot;

        reg edd,edd2, edd3;                     //delayed data enable impulse        

        reg mpyjd,mpyjd2,mpyjd3;

        reg [nb-1:0] doo ;

        reg [nb-1:0] droo ;

        always @(posedge CLK)

                begin

                        if (EI) begin

                                        edd<=ED;

                                        edd2<=edd;

                                        edd3<=edd2;

                                        mpyjd<=MPYJ;

                                        mpyjd2<=mpyjd;

                                        mpyjd3<=mpyjd2;

                                        if (ED)  begin

                                                        dx5<=DR+(DR <<2);        //multiply by 5 

                                                        dt<=DR;

                                                        dii<=DI;

                                                end

                                        else     begin

                                                        dx5<=dii+(dii <<2);      //multiply by 5

                                                        dt<=dii;

                                                end

                                        doo<=(dot >>>4) ;

                                        droo<=doo;

                                        if (edd3)

                                                if (mpyjd3) begin

                                                                DOR<=doo;

                                                        DOI<= - droo; end

                                                else begin

                                                                DOR<=droo;

                                                        DOI<=  doo; end

                                end

                end

        assign  dx5p=(dx5<<1)+(dx5>>>2);                // multiply by 101101                   

        `ifdef FFT256bitwidth_coef_high

        assign   dot=   dx5p+(dt>>>4)+(dx5>>>13);          // multiply by 10110101000000101           

        `else

        assign    dot=          dx5p+(dt>>>4)   ;  // multiply by 10110101         

        `endif

endmodule