Subversion Repositories plb2wbbridge

; Copyright 1991-2009 Mentor Graphics Corporation

;

; All Rights Reserved.

;

; THIS WORK CONTAINS TRADE SECRET AND PROPRIETARY INFORMATION WHICH IS THE PROPERTY OF

; MENTOR GRAPHICS CORPORATION OR ITS LICENSORS AND IS SUBJECT TO LICENSE TERMS.

;

[Library]

others = $MODEL_TECH/../modelsim.ini

;vhdl_psl_checkers = $MODEL_TECH/../vhdl_psl_checkers       // Source files only for this release

;verilog_psl_checkers = $MODEL_TECH/../verilog_psl_checkers // Source files only for this release

;mvc_lib = $MODEL_TECH/../mvc_lib

secureip = c:/compxlib/secureip/

simprim = c:/compxlib/simprim/

simprims_ver = c:/compxlib/simprims_ver/

unisim = c:/compxlib/unisim/

unisims_ver = c:/compxlib/unisims_ver/

xilinxcorelib = c:/compxlib/xilinxcorelib/

xilinxcorelib_ver = c:/compxlib/xilinxcorelib_ver/

microblaze_v7_20_d = /opt/Xilinx/11.1/compxlib/edk/microblaze_v7_20_d/

proc_common_v3_00_a = c:/compxlib/edk/proc_common_v3_00_a/

plb_v46_v1_04_a = c:/compxlib/edk/plb_v46_v1_04_a/

lmb_v10_v1_00_a = /opt/Xilinx/11.1/compxlib/edk/lmb_v10_v1_00_a/

lmb_bram_if_cntlr_v2_10_b = /opt/Xilinx/11.1/compxlib/edk/lmb_bram_if_cntlr_v2_10_b/

lmb_bram_elaborate_v1_00_a = lmb_bram_elaborate_v1_00_a

plbv46_slave_single_v1_01_a = c:/compxlib/edk/plbv46_slave_single_v1_01_a/

interrupt_control_v2_01_a = /opt/Xilinx/11.1/compxlib/edk/interrupt_control_v2_01_a/

xps_gpio_v2_00_a = /opt/Xilinx/11.1/compxlib/edk/xps_gpio_v2_00_a/

xps_timer_v1_01_b = /opt/Xilinx/11.1/compxlib/edk/xps_timer_v1_01_b/

clock_generator_v3_02_a = /opt/Xilinx/11.1/compxlib/edk/clock_generator_v3_02_a/

mdm_v1_00_g = /opt/Xilinx/11.1/compxlib/edk/mdm_v1_00_g/

proc_sys_reset_v2_00_a = /opt/Xilinx/11.1/compxlib/edk/proc_sys_reset_v2_00_a/

xps_intc_v2_00_a = /opt/Xilinx/11.1/compxlib/edk/xps_intc_v2_00_a/

work = work

plbv46_master_bfm_v1_00_a = c:/compxlib/edk/plbv46_master_bfm_v1_00_a/

plbv46_monitor_bfm_v1_00_a = c:/compxlib/edk/plbv46_monitor_bfm_v1_00_a/

plbv46_slave_bfm_v1_00_a = c:/compxlib/edk/plbv46_slave_bfm_v1_00_a/

bfm_synch_v1_00_a = c:/compxlib/edk/bfm_synch_v1_00_a/

plbv46_bfm = c:/compxlib/edk/plbv46_bfm/

plb2wb_bridge_v1_00_a = plb2wb_bridge_v1_00_a

onchip_ram_v1_00_a = onchip_ram_v1_00_a

wb_conbus_v1_00_a = wb_conbus_v1_00_a

[vcom]

; VHDL93 variable selects language version as the default.

; Default is VHDL-2002.

; Value of 0 or 1987 for VHDL-1987.

; Value of 1 or 1993 for VHDL-1993.

; Default or value of 2 or 2002 for VHDL-2002.

; Value of 3 or 2008 for VHDL-2008

VHDL93 = 2002

; Show source line containing error. Default is off.

; Show_source = 1

; Turn off unbound-component warnings. Default is on.

; Show_Warning1 = 0

; Turn off process-without-a-wait-statement warnings. Default is on.

; Show_Warning2 = 0

; Turn off null-range warnings. Default is on.

; Show_Warning3 = 0

; Turn off no-space-in-time-literal warnings. Default is on.

; Show_Warning4 = 0

; Turn off multiple-drivers-on-unresolved-signal warnings. Default is on.

; Show_Warning5 = 0

; Turn off optimization for IEEE std_logic_1164 package. Default is on.

; Optimize_1164 = 0

; Turn on resolving of ambiguous function overloading in favor of the

; "explicit" function declaration (not the one automatically created by

; the compiler for each type declaration). Default is off.

; The .ini file has Explicit enabled so that std_logic_signed/unsigned

; will match the behavior of synthesis tools.

Explicit = 1

; Turn off acceleration of the VITAL packages. Default is to accelerate.

; NoVital = 1

; Turn off VITAL compliance checking. Default is checking on.

; NoVitalCheck = 1

; Ignore VITAL compliance checking errors. Default is to not ignore.

; IgnoreVitalErrors = 1

; Turn off VITAL compliance checking warnings. Default is to show warnings.

; Show_VitalChecksWarnings = 0

; Turn off PSL assertion warning messages. Default is to show warnings.

; Show_PslChecksWarnings = 0

; Enable parsing of embedded PSL assertions. Default is enabled.

; EmbeddedPsl = 0

; Keep silent about case statement static warnings.

; Default is to give a warning.

; NoCaseStaticError = 1

; Keep silent about warnings caused by aggregates that are not locally static.

; Default is to give a warning.

; NoOthersStaticError = 1

; Treat as errors:

;   case statement static warnings

;   warnings caused by aggregates that are not locally static

; Overrides NoCaseStaticError, NoOthersStaticError settings.

; PedanticErrors = 1

; Turn off inclusion of debugging info within design units.

; Default is to include debugging info.

; NoDebug = 1

; Turn off "Loading..." messages. Default is messages on.

; Quiet = 1

; Turn on some limited synthesis rule compliance checking. Checks only:

;    -- signals used (read) by a process must be in the sensitivity list

; CheckSynthesis = 1

; Activate optimizations on expressions that do not involve signals,

; waits, or function/procedure/task invocations. Default is off.

; ScalarOpts = 1

; Turns on lint-style checking.

; Show_Lint = 1

; Require the user to specify a configuration for all bindings,

; and do not generate a compile time default binding for the

; component. This will result in an elaboration error of

; 'component not bound' if the user fails to do so. Avoids the rare

; issue of a false dependency upon the unused default binding.

; RequireConfigForAllDefaultBinding = 1

; Perform default binding at compile time.

; Default is to do default binding at load time.

; BindAtCompile = 1;

; Inhibit range checking on subscripts of arrays. Range checking on

; scalars defined with subtypes is inhibited by default.

; NoIndexCheck = 1

; Inhibit range checks on all (implicit and explicit) assignments to

; scalar objects defined with subtypes.

; NoRangeCheck = 1

; Run the 0-in compiler on the VHDL source files

; Default is off.

; ZeroIn = 1

; Set the options to be passed to the 0-in compiler.

; Default is "".

; ZeroInOptions = ""

; Turn on code coverage in VHDL design units. Default is off.

; Coverage = sbceft

; Turn off code coverage in VHDL subprograms. Default is on.

; CoverageSub = 0

; Automatically exclude VHDL case statement OTHERS choice branches.

; This includes OTHERS choices in selected signal assigment statements.

; Default is to not exclude.

; CoverExcludeDefault = 1

; Control compiler and VOPT optimizations that are allowed when

; code coverage is on.  Refer to the comment for this in the [vlog] area.

; CoverOpt = 3

; Inform code coverage optimizations to respect VHDL 'H' and 'L'

; values on signals in conditions and expressions, and to not automatically

; convert them to '1' and '0'. Default is to not convert.

; CoverRespectHandL = 0

; Increase or decrease the maximum number of rows allowed in a UDP table

; implementing a VHDL condition coverage or expression coverage expression.

; More rows leads to a longer compile time, but more expressions covered.

; CoverMaxUDPRows = 192

; Increase or decrease the maximum number of input patterns that are present

; in FEC table. This leads to a longer compile time with more expressions

; covered with FEC metric.

; CoverMaxFECRows = 192

; Enable or disable Focused Expression Coverage analysis for conditions and

; expressions. Focused Expression Coverage data is provided by default when

; expression and/or condition coverage is active.

; CoverFEC = 0

; Enable or disable short circuit evaluation of conditions and expressions when

; condition or expression coverage is active. Short circuit evaluation is enabled

; by default.

; CoverShortCircuit = 0

; Use this directory for compiler temporary files instead of "work/_temp"

; CompilerTempDir = /tmp

; Set this to cause the compilers to force data to be committed to disk

; when the files are closed.

; SyncCompilerFiles = 1

; Add VHDL-AMS declarations to package STANDARD

; Default is not to add

; AmsStandard = 1

; Range and length checking will be performed on array indices and discrete

; ranges, and when violations are found within subprograms, errors will be

; reported. Default is to issue warnings for violations, because subprograms

; may not be invoked.

; NoDeferSubpgmCheck = 0

; Turn off detection of FSMs having single bit current state variable.

; FsmSingle = 0

; Turn off reset state transitions in FSM.

; FsmResetTrans = 0

; Do not show immediate assertions with constant expressions in

; GUI/report/UCDB etc. By default immediate assertions with constant

; expressions are shown in GUI/report/UCDB etc. This does not affect ;

; evaluation of immediate assertions.

; ShowConstantImmediateAsserts = 0

[vlog]

; Turn off inclusion of debugging info within design units.

; Default is to include debugging info.

; NoDebug = 1

; Turn on `protect compiler directive processing.

; Default is to ignore `protect directives.

; Protect = 1

; Turn off "Loading..." messages. Default is messages on.

; Quiet = 1

; Turn on Verilog hazard checking (order-dependent accessing of global vars).

; Default is off.

; Hazard = 1

; Turn on converting regular Verilog identifiers to uppercase. Allows case

; insensitivity for module names. Default is no conversion.

; UpCase = 1

; Activate optimizations on expressions that do not involve signals,

; waits, or function/procedure/task invocations. Default is off.

; ScalarOpts = 1

; Turns on lint-style checking.

; Show_Lint = 1

; Show source line containing error. Default is off.

; Show_source = 1

; Turn on bad option warning. Default is off.

; Show_BadOptionWarning = 1

; Revert back to IEEE 1364-1995 syntax, default is 0 (off).

; vlog95compat = 1

; Turn off PSL warning messages. Default is to show warnings.

; Show_PslChecksWarnings = 0

; Enable parsing of embedded PSL assertions. Default is enabled.

; EmbeddedPsl = 0

; Set the threshold for automatically identifying sparse Verilog memories.

; A memory with depth equal to or more than the sparse memory threshold gets

; marked as sparse automatically, unless specified otherwise in source code

; or by +nosparse commandline option of vlog or vopt.

; The default is 1M.  (i.e. memories with depth equal

; to or greater than 1M are marked as sparse)

; SparseMemThreshold = 1048576

; Run the 0-in compiler on the Verilog source files

; Default is off.

; ZeroIn = 1

; Set the options to be passed to the 0-in compiler.

; Default is "".

; ZeroInOptions = ""

; Set the option to treat all files specified in a vlog invocation as a

; single compilation unit. The default value is set to 0 which will treat

; each file as a separate compilation unit as specified in the P1800 draft standard.

; MultiFileCompilationUnit = 1

; Turn on code coverage in Verilog design units. Default is off.

; Coverage = sbceft

; Automatically exclude Verilog case statement default branches.

; Default is to not automatically exclude defaults.

; CoverExcludeDefault = 1

; Increase or decrease the maximum number of rows allowed in a UDP table

; implementing a Verilog condition coverage or expression coverage expression.

; More rows leads to a longer compile time, but more expressions covered.

; CoverMaxUDPRows = 192

; Increase or decrease the maximum number of input patterns that are present

; in FEC table. This leads to a longer compile time with more expressions

; covered with FEC metric.

; CoverMaxFECRows = 192

; Enable or disable Focused Expression Coverage analysis for conditions and

; expressions. Focused Expression Coverage data is provided by default when

; expression and/or condition coverage is active.

; CoverFEC = 0

; Enable or disable short circuit evaluation of conditions and expressions when

; condition or expression coverage is active. Short circuit evaluation is enabled

; by default.

; CoverShortCircuit = 0

; Turn on code coverage in VLOG `celldefine modules and modules included

; using vlog -v and -y. Default is off.

; CoverCells = 1

; Control compiler and VOPT optimizations that are allowed when

; code coverage is on. This is a number from 1 to 4, with the following

; meanings (the default is 3):

;    1 -- Turn off all optimizations that affect coverage reports.

;    2 -- Allow optimizations that allow large performance improvements

;         by invoking sequential processes only when the data changes.

;         This may make major reductions in coverage counts.

;    3 -- In addition, allow optimizations that may change expressions or

;         remove some statements. Allow constant propagation. Allow VHDL

;         subprogram inlining and VHDL FF recognition.

;    4 -- In addition, allow optimizations that may remove major regions of

;         code by changing assignments to built-ins or removing unused

;         signals. Change Verilog gates to continuous assignments.

; CoverOpt = 3

; Specify the override for the default value of "cross_num_print_missing"

; option for the Cross in Covergroups. If not specified then LRM default

; value of 0 (zero) is used. This is a compile time option.

; SVCrossNumPrintMissingDefault = 0

; Setting following to 1 would cause creation of variables which

; would represent the value of Coverpoint expressions. This is used

; in conjunction with "SVCoverpointExprVariablePrefix" option

; in the modelsim.ini

; EnableSVCoverpointExprVariable = 0

; Specify the override for the prefix used in forming the variable names

; which represent the Coverpoint expressions. This is used in conjunction with

; "EnableSVCoverpointExprVariable" option of the modelsim.ini

; The default prefix is "expr".

; The variable name is

;    variable name => _

; SVCoverpointExprVariablePrefix = expr

; Override for the default value of the SystemVerilog covergroup,

; coverpoint, and cross option.goal (defined to be 100 in the LRM).

; NOTE: It does not override specific assignments in SystemVerilog

; source code. NOTE: The modelsim.ini variable "SVCovergroupGoal"

; in the [vsim] section can override this value.

; SVCovergroupGoalDefault = 100

; Override for the default value of the SystemVerilog covergroup,

; coverpoint, and cross type_option.goal (defined to be 100 in the LRM)

; NOTE: It does not override specific assignments in SystemVerilog

; source code. NOTE: The modelsim.ini variable "SVCovergroupTypeGoal"

; in the [vsim] section can override this value.

; SVCovergroupTypeGoalDefault = 100

; Specify the override for the default value of "strobe" option for the

; Covergroup Type. This is a compile time option which forces "strobe" to

; a user specified default value and supersedes SystemVerilog specified

; default value of '0'(zero). NOTE: This can be overriden by a runtime

; modelsim.ini variable "SVCovergroupStrobe" in the [vsim] section.

; SVCovergroupStrobeDefault = 0

; Specify the override for the default value of "merge_instances" option for

; the Covergroup Type. This is a compile time option which forces

; "merge_instances" to a user specified default value and supersedes

; SystemVerilog specified default value of '0'(zero).

; SVCovergroupMergeInstancesDefault = 0

; Specify the override for the default value of "per_instance" option for the

; Covergroup variables. This is a compile time option which forces "per_instance"

; to a user specified default value and supersedes SystemVerilog specified

; default value of '0'(zero).

; SVCovergroupPerInstanceDefault = 0

; Specify the override for the default value of "get_inst_coverage" option for the

; Covergroup variables. This is a compile time option which forces

; "get_inst_coverage" to a user specified default value and supersedes

; SystemVerilog specified default value of '0'(zero).

; SVCovergroupGetInstCoverageDefault = 0

;

; A space separated list of resource libraries that contain precompiled

; packages.  The behavior is identical to using the "-L" switch.

;

; LibrarySearchPath =  [ ...]

LibrarySearchPath = mtiAvm mtiOvm mtiUPF

; The behavior is identical to the "-mixedansiports" switch.  Default is off.

; MixedAnsiPorts = 1

; Enable SystemVerilog 3.1a $typeof() function. Default is off.

; EnableTypeOf = 1

; Only allow lower case pragmas. Default is disabled.

; AcceptLowerCasePragmaOnly = 1

; Set the maximum depth permitted for a recursive include file nesting.

; IncludeRecursionDepthMax = 5

; Turn off detection of FSMs having single bit current state variable.

; FsmSingle = 0

; Turn off reset state transitions in FSM.

; FsmResetTrans = 0

; Turn off detections of FSMs having x-assignment.

; FsmXAssign = 0

; List of file suffixes which will be read as SystemVerilog.  White space

; in extensions can be specified with a back-slash: "\ ".  Back-slashes

; can be specified with two consecutive back-slashes: "\\";

; SVFileExtensions = sv svp svh

; This setting is the same as the vlog -sv command line switch.

; Enables SystemVerilog features and keywords when true (1).

; When false (0), the rules of IEEE Std 1364-2001 are followed and

; SystemVerilog keywords are ignored.

; Svlog = 0

; Prints attribute placed upon SV packages during package import

; when true (1).  The attribute will be ignored when this

; entry is false (0). The attribute name is "package_load_message".

; The value of this attribute is a string literal.

; Default is true (1).

; PrintSVPackageLoadingAttribute = 1

; Do not show immediate assertions with constant expressions in

; GUI/reports/UCDB etc. By default immediate assertions with constant

; expressions are shown in GUI/reports/UCDB etc. This does not affect

; evaluation of immediate assertions.

; ShowConstantImmediateAsserts = 0

[sccom]

; Enable use of SCV include files and library.  Default is off.

; UseScv = 1

; Add C++ compiler options to the sccom command line by using this variable.

; CppOptions = -g

; Use custom C++ compiler located at this path rather than the default path.

; The path should point directly at a compiler executable.

; CppPath = /usr/bin/g++

; Enable verbose messages from sccom.  Default is off.

; SccomVerbose = 1

; sccom logfile.  Default is no logfile.

; SccomLogfile = sccom.log

; Enable use of SC_MS include files and library.  Default is off.

; UseScMs = 1

[vopt]

; Turn on code coverage in vopt.  Default is off.

; Coverage = sbceft

; Control compiler optimizations that are allowed when

; code coverage is on.  Refer to the comment for this in the [vlog] area.

; CoverOpt = 3

; Increase or decrease the maximum number of rows allowed in a UDP table

; implementing a vopt condition coverage or expression coverage expression.

; More rows leads to a longer compile time, but more expressions covered.

; CoverMaxUDPRows = 192

; Increase or decrease the maximum number of input patterns that are present

; in FEC table. This leads to a longer compile time with more expressions

; covered with FEC metric.

; CoverMaxFECRows = 192

; Do not show immediate assertions with constant expressions in

; GUI/reports/UCDB etc. By default immediate assertions with constant

; expressions are shown in GUI/reports/UCDB etc. This does not affect

; evaluation of immediate assertions.

; ShowConstantImmediateAsserts = 0

; Set the maximum number of iterations permitted for a generate loop.

; Restricting this permits the implementation to recognize infinite

; generate loops.

; GenerateLoopIterationMax = 100000

; Set the maximum depth permitted for a recursive generate instantiation.

; Restricting this permits the implementation to recognize infinite

; recursions.

; GenerateRecursionDepthMax = 200

[vsim]

; vopt flow

; Set to turn on automatic optimization of a design.

; Default is on

VoptFlow = 1

; vopt automatic SDF

; If automatic design optimization is on, enables automatic compilation

; of SDF files.

; Default is on, uncomment to turn off.

; VoptAutoSDFCompile = 0

; Automatic SDF compilation

; Disables automatic compilation of SDF files in flows that support it.

; Default is on, uncomment to turn off.

; NoAutoSDFCompile = 1

; Simulator resolution

; Set to fs, ps, ns, us, ms, or sec with optional prefix of 1, 10, or 100.

resolution = 1ps

; Disable certain code coverage exclusions automatically.

; Assertions and FSM are exluded from the code coverage by default

; Set AutoExclusionsDisable = fsm to enable code coverage for fsm

; Set AutoExclusionsDisable = assertions to enable code coverage for assertions

; Set AutoExclusionsDisable = all to enable code coverage for all the automatic exclusions

; Or specify comma or space separated list

;AutoExclusionsDisable = fsm,assertions

; User time unit for run commands

; Set to default, fs, ps, ns, us, ms, or sec. The default is to use the

; unit specified for Resolution. For example, if Resolution is 100ps,

; then UserTimeUnit defaults to ps.

; Should generally be set to default.

UserTimeUnit = default

; Default run length

RunLength = 10 sec

; Maximum iterations that can be run without advancing simulation time

IterationLimit = 5000

; Control PSL and Verilog Assume directives during simulation

; Set SimulateAssumeDirectives = 0 to disable assume being simulated as asserts

; Set SimulateAssumeDirectives = 1 to enable assume simulation as asserts

; SimulateAssumeDirectives = 1

; Control the simulation of PSL and SVA

; These switches can be overridden by the vsim command line switches:

;    -psl, -nopsl, -sva, -nosva.

; Set SimulatePSL = 0 to disable PSL simulation

; Set SimulatePSL = 1 to enable PSL simulation (default)

; SimulatePSL = 1

; Set SimulateSVA = 0 to disable SVA simulation

; Set SimulateSVA = 1 to enable concurrent SVA simulation (default)

; SimulateSVA = 1

; Directives to license manager can be set either as single value or as

; space separated multi-values:

; vhdl          Immediately reserve a VHDL license

; vlog          Immediately reserve a Verilog license

; plus          Immediately reserve a VHDL and Verilog license

; nomgc         Do not look for Mentor Graphics Licenses

; nomti         Do not look for Model Technology Licenses

; noqueue       Do not wait in the license queue when a license is not available

; viewsim       Try for viewer license but accept simulator license(s) instead

;               of queuing for viewer license (PE ONLY)

; noviewer      Disable checkout of msimviewer and vsim-viewer license

;               features (PE ONLY)

; noslvhdl      Disable checkout of qhsimvh and vsim license features

; noslvlog      Disable checkout of qhsimvl and vsimvlog license features

; nomix         Disable checkout of msimhdlmix and hdlmix license features

; nolnl         Disable checkout of msimhdlsim and hdlsim license features

; mixedonly     Disable checkout of qhsimvh,qhsimvl,vsim,vsimvlog license

;               features

; lnlonly       Disable checkout of qhsimvh,qhsimvl,vsim,vsimvlog,msimhdlmix,

;               hdlmix license features

; Single value:

; License = plus

; Multi-value:

; License = noqueue plus

; Stop the simulator after a VHDL/Verilog immediate assertion message

; 0 = Note  1 = Warning  2 = Error  3 = Failure  4 = Fatal

BreakOnAssertion = 3

; VHDL assertion Message Format

; %S - Severity Level

; %R - Report Message

; %T - Time of assertion

; %D - Delta

; %I - Instance or Region pathname (if available)

; %i - Instance pathname with process

; %O - Process name

; %K - Kind of object path is to return: Instance, Signal, Process or Unknown

; %P - Instance or Region path without leaf process

; %F - File

; %L - Line number of assertion or, if assertion is in a subprogram, line

;      from which the call is made

; %% - Print '%' character

; If specific format for assertion level is defined, use its format.

; If specific format is not defined for assertion level:

; - and if failure occurs during elaboration, use MessageFormatBreakLine;

; - and if assertion triggers a breakpoint (controlled by BreakOnAssertion

;   level), use MessageFormatBreak;

; - otherwise, use MessageFormat.

; MessageFormatBreakLine = "** %S: %R\n   Time: %T  Iteration: %D  %K: %i File: %F Line: %L\n"

; MessageFormatBreak     = "** %S: %R\n   Time: %T  Iteration: %D  %K: %i File: %F\n"

; MessageFormat          = "** %S: %R\n   Time: %T  Iteration: %D%I\n"

; MessageFormatNote      = "** %S: %R\n   Time: %T  Iteration: %D%I\n"

; MessageFormatWarning   = "** %S: %R\n   Time: %T  Iteration: %D%I\n"

; MessageFormatError     = "** %S: %R\n   Time: %T  Iteration: %D  %K: %i File: %F\n"

; MessageFormatFail      = "** %S: %R\n   Time: %T  Iteration: %D  %K: %i File: %F\n"

; MessageFormatFatal     = "** %S: %R\n   Time: %T  Iteration: %D  %K: %i File: %F\n"

; Error File - alternate file for storing error messages

; ErrorFile = error.log

; Simulation Breakpoint messages

; This flag controls the display of function names when reporting the location

; where the simulator stops do to a breakpoint or fatal error.

; Example w/function name:  # Break in Process ctr at counter.vhd line 44

; Example wo/function name: # Break at counter.vhd line 44

ShowFunctions = 1

; Default radix for all windows and commands.

; Set to symbolic, ascii, binary, octal, decimal, hex, unsigned

DefaultRadix = symbolic

; VSIM Startup command

; Startup = do startup.do

; VSIM Shutdown file

; Filename to save u/i formats and configurations.

; ShutdownFile = restart.do

; To explicitly disable auto save:

; ShutdownFile = --disable-auto-save

; File for saving command transcript

TranscriptFile = transcript

; File for saving command history

; CommandHistory = cmdhist.log

; Specify whether paths in simulator commands should be described

; in VHDL or Verilog format.

; For VHDL, PathSeparator = /

; For Verilog, PathSeparator = .

; Must not be the same character as DatasetSeparator.

PathSeparator = /

; Specify the dataset separator for fully rooted contexts.

; The default is ':'. For example: sim:/top

; Must not be the same character as PathSeparator.

DatasetSeparator = :

; Specify a unique path separator for the Signal Spy set of functions.

; The default will be to use the PathSeparator variable.

; Must not be the same character as DatasetSeparator.

; SignalSpyPathSeparator = /

; Used to control parsing of HDL identifiers input to the tool.

; This includes CLI commands, vsim/vopt/vlog/vcom options,

; string arguments to FLI/VPI/DPI calls, etc.

; If set to 1, accept either Verilog escaped Id syntax or

; VHDL extended id syntax, regardless of source language.

; If set to 0, the syntax of the source language must be used.

; Each identifier in a hierarchical name may need different syntax,

; e.g. "/top/\vhdl*ext*id\/middle/\vlog*ext*id /bottom" or

;       "top.\vhdl*ext*id\.middle.\vlog*ext*id .bottom"

; GenerousIdentifierParsing = 1

; Disable VHDL assertion messages

; IgnoreNote = 1

; IgnoreWarning = 1

; IgnoreError = 1

; IgnoreFailure = 1

; Disable System Verilog assertion messages

; IgnoreSVAInfo = 1

; IgnoreSVAWarning = 1

; IgnoreSVAError = 1

; IgnoreSVAFatal = 1

; Do not print any additional information from Severity System tasks.

; Only the message provided by the user is printed along with severity

; information.

; SVAPrintOnlyUserMessage = 1;

; Default force kind. May be freeze, drive, deposit, or default

; or in other terms, fixed, wired, or charged.

; A value of "default" will use the signal kind to determine the

; force kind, drive for resolved signals, freeze for unresolved signals

; DefaultForceKind = freeze

; Control the iteration of events when a VHDL signal is forced to a value

; This flag can be set to honour the signal update event in next iteration,

; the default is to update and propagate in the same iteration.

; ForceSigNextIter = 1

; If zero, open files when elaborated; otherwise, open files on

; first read or write.  Default is 0.

; DelayFileOpen = 1

; Control VHDL files opened for write.

;   0 = Buffered, 1 = Unbuffered

UnbufferedOutput = 0

; Control the number of VHDL files open concurrently.

; This number should always be less than the current ulimit

; setting for max file descriptors.

;   0 = unlimited

ConcurrentFileLimit = 40

; Control the number of hierarchical regions displayed as

; part of a signal name shown in the Wave window.

; A value of zero tells VSIM to display the full name.

; The default is 0.

; WaveSignalNameWidth = 0

; Turn off warnings when changing VHDL constants and generics

; Default is 1 to generate warning messages

; WarnConstantChange = 0

; Turn off warnings from the std_logic_arith, std_logic_unsigned

; and std_logic_signed packages.

; StdArithNoWarnings = 1

; Turn off warnings from the IEEE numeric_std and numeric_bit packages.

; NumericStdNoWarnings = 1

; Control the format of the (VHDL) FOR generate statement label

; for each iteration.  Do not quote it.

; The format string here must contain the conversion codes %s and %d,

; in that order, and no other conversion codes.  The %s represents

; the generate_label; the %d represents the generate parameter value

; at a particular generate iteration (this is the position number if

; the generate parameter is of an enumeration type).  Embedded whitespace

; is allowed (but discouraged); leading and trailing whitespace is ignored.

; Application of the format must result in a unique scope name over all

; such names in the design so that name lookup can function properly.

; GenerateFormat = %s__%d

; Specify whether checkpoint files should be compressed.

; The default is 1 (compressed).

; CheckpointCompressMode = 0

; Specify whether to enable SystemVerilog DPI "out-of-the-blue" calls.

; The term "out-of-the-blue" refers to SystemVerilog export function calls

; made from C functions that don't have the proper context setup

; (as is the case when running under "DPI-C" import functions).

; When this is enabled, one can call a DPI export function

; (but not task) from any C code.

; the setting of this variable can be one of the following values:

; 0 : dpioutoftheblue call is disabled (default)

; 1 : dpioutoftheblue call is enabled, but export call debug support is not available.

; 2 : dpioutoftheblue call is enabled, and limited export call debug support is available.

; DpiOutOfTheBlue = 1

; Specify whether continuous assignments are run before other normal priority

; processes scheduled in the same iteration. This event ordering minimizes race

; differences between optimized and non-optimized designs, and is the default

; behavior beginning with the 6.5 release. For pre-6.5 event ordering, set

; ImmediateContinuousAssign to 0.

; The default is 1 (enabled).

; ImmediateContinuousAssign = 0

; List of dynamically loaded objects for Verilog PLI applications

; Veriuser = veriuser.sl

; Which default VPI object model should the tool conform to?

; The 1364 modes are Verilog-only, for backwards compatibility with older

; libraries, and SystemVerilog objects are not available in these modes.

;

; In the absence of a user-specified default, the tool default is the

; latest available LRM behavior.

; Options for PliCompatDefault are:

;  VPI_COMPATIBILITY_VERSION_1364v1995

;  VPI_COMPATIBILITY_VERSION_1364v2001

;  VPI_COMPATIBILITY_VERSION_1364v2005

;  VPI_COMPATIBILITY_VERSION_1800v2005

;  VPI_COMPATIBILITY_VERSION_1800v2008

;

; Synonyms for each string are also recognized:

;  VPI_COMPATIBILITY_VERSION_1364v1995 (1995, 95, 1364v1995, 1364V1995, VL1995)

;  VPI_COMPATIBILITY_VERSION_1364v2001 (2001, 01, 1364v2001, 1364V2001, VL2001)

;  VPI_COMPATIBILITY_VERSION_1364v2005 (1364v2005, 1364V2005, VL2005)

;  VPI_COMPATIBILITY_VERSION_1800v2005 (2005, 05, 1800v2005, 1800V2005, SV2005)

;  VPI_COMPATIBILITY_VERSION_1800v2008 (2008, 08, 1800v2008, 1800V2008, SV2008)

; PliCompatDefault = VPI_COMPATIBILITY_VERSION_1800v2005

; Specify default options for the restart command. Options can be one

; or more of: -force -nobreakpoint -nolist -nolog -nowave -noassertions

; DefaultRestartOptions = -force

; Turn on (1) or off (0) WLF file compression.

; The default is 1 (compress WLF file).

; WLFCompress = 0

; Specify whether to save all design hierarchy (1) in the WLF file

; or only regions containing logged signals (0).

; The default is 0 (save only regions with logged signals).

; WLFSaveAllRegions = 1

; WLF file time limit.  Limit WLF file by time, as closely as possible,

; to the specified amount of simulation time.  When the limit is exceeded

; the earliest times get truncated from the file.

; If both time and size limits are specified the most restrictive is used.

; UserTimeUnits are used if time units are not specified.

; The default is 0 (no limit).  Example: WLFTimeLimit = {100 ms}

; WLFTimeLimit = 0

; WLF file size limit.  Limit WLF file size, as closely as possible,

; to the specified number of megabytes.  If both time and size limits

; are specified then the most restrictive is used.

; The default is 0 (no limit).

; WLFSizeLimit = 1000

; Specify whether or not a WLF file should be deleted when the

; simulation ends.  A value of 1 will cause the WLF file to be deleted.

; The default is 0 (do not delete WLF file when simulation ends).

; WLFDeleteOnQuit = 1

; Specify whether or not a WLF file should be indexed during

; simulation.  If set to 0, the WLF file will not be indexed.

; The default is 1, indexed the WLF file.

; WLFIndex = 0

; Specify whether or not a WLF file should be optimized during

; simulation.  If set to 0, the WLF file will not be optimized.

; The default is 1, optimize the WLF file.

; WLFOptimize = 0

; Specify the name of the WLF file.

; The default is vsim.wlf

; WLFFilename = vsim.wlf

; Specify the WLF reader cache size limit for each open WLF file.

; The size is giving in megabytes.  A value of 0 turns off the

; WLF cache.

; WLFSimCacheSize allows a different cache size to be set for

; simulation WLF file independent of post-simulation WLF file

; viewing.  If WLFSimCacheSize is not set it defaults to the

; WLFCacheSize setting.

; The default WLFCacheSize setting is enabled to 256M per open WLF file.

; WLFCacheSize = 2000

; WLFSimCacheSize = 500

; Specify the WLF file event collapse mode.

; 0 = Preserve all events and event order. (same as -wlfnocollapse)

; 1 = Only record values of logged objects at the end of a simulator iteration.

;     (same as -wlfcollapsedelta)

; 2 = Only record values of logged objects at the end of a simulator time step.

;     (same as -wlfcollapsetime)

; The default is 1.

; WLFCollapseMode = 0

; Specify whether WLF file logging can use threads on multi-processor machines

; if 0, no threads will be used, if 1, threads will be used if the system has

; more than one processor

; WLFUseThreads = 1

; Turn on/off undebuggable SystemC type warnings. Default is on.

; ShowUndebuggableScTypeWarning = 0

; Turn on/off unassociated SystemC name warnings. Default is off.

; ShowUnassociatedScNameWarning = 1

; Turn on/off SystemC IEEE 1666 deprecation warnings. Default is off.

; ScShowIeeeDeprecationWarnings = 1

; Turn on/off the check for multiple drivers on a SystemC sc_signal. Default is off.

; ScEnableScSignalWriteCheck = 1

; Set SystemC default time unit.

; Set to fs, ps, ns, us, ms, or sec with optional

; prefix of 1, 10, or 100.  The default is 1 ns.

; The ScTimeUnit value is honored if it is coarser than Resolution.

; If ScTimeUnit is finer than Resolution, it is set to the value

; of Resolution. For example, if Resolution is 100ps and ScTimeUnit is ns,

; then the default time unit will be 1 ns.  However if Resolution

; is 10 ns and ScTimeUnit is ns, then the default time unit will be 10 ns.

ScTimeUnit = ns

; Set SystemC sc_main stack size. The stack size is set as an integer

; number followed by the unit which can be Kb(Kilo-byte), Mb(Mega-byte) or

; Gb(Giga-byte). Default is 10 Mb. The stack size for sc_main depends

; on the amount of data on the sc_main() stack and the memory required

; to succesfully execute the longest function call chain of sc_main().

ScMainStackSize = 10 Mb

; Turn on/off execution of remainder of sc_main upon quitting the current

; simulation session. If the cumulative length of sc_main() in terms of

; simulation time units is less than the length of the current simulation

; run upon quit or restart, sc_main() will be in the middle of execution.

; This switch gives the option to execute the remainder of sc_main upon

; quitting simulation. The drawback of not running sc_main till the end

; is memory leaks for objects created by sc_main. If on, the remainder of

; sc_main will be executed ignoring all delays. This may cause the simulator

; to crash if the code in sc_main is dependent on some simulation state.

; Default is on.

ScMainFinishOnQuit = 1

; Set the SCV relationship name that will be used to identify phase

; relations.  If the name given to a transactor relation matches this

; name, the transactions involved will be treated as phase transactions

ScvPhaseRelationName = mti_phase

; Customize the vsim kernel shutdown behavior at the end of the simulation.

; Some common causes of the end of simulation are $finish (implicit or explicit),

; sc_stop(), tf_dofinish(), and assertion failures.

; This should be set to "ask", "exit", or "stop". The default is "ask".

; "ask"   -- In batch mode, the vsim kernel will abruptly exit.

;            In GUI mode, a dialog box will pop up and ask for user confirmation

;            whether or not to quit the simulation.

; "stop"  -- Cause the simulation to stay loaded in memory. This can make some

;            post-simulation tasks easier.

; "exit"  -- The simulation will abruptly exit without asking for any confirmation.

; "final" -- Run SystemVerilog final blocks then behave as "stop".

; Note: these ini variables can be overriden by the vsim command

;       line switch "-onfinish ".

OnFinish = ask

; Print pending deferred assertion messages.

; Deferred assertion messages may be scheduled after the $finish in the same

; time step. Deferred assertions scheduled to print after the $finish are

; printed before exiting with severity level NOTE since it's not known whether

; the assertion is still valid due to being printed in the active region

; instead of the reactive region where they are normally printed.

; OnFinishPendingAssert = 1;

; Print "simstats" result at the end of simulation before shutdown.

; If this is enabled, the simstats result will be printed out before shutdown.